[llvm] [DAGCombine] Push freeze through sra (PR #208749)
Nikita Popov via llvm-commits
llvm-commits at lists.llvm.org
Wed Aug 19 01:51:17 PDT 2026
https://github.com/nikic updated https://github.com/llvm/llvm-project/pull/208749
>From 74bb749e993d0824ddda884f1bf29e3bccd9a97b Mon Sep 17 00:00:00 2001
From: Nikita Popov <npopov at redhat.com>
Date: Fri, 10 Jul 2026 17:08:18 +0200
Subject: [PATCH] [DAGCombine] Push freeze through sra
This no longer causes regressions (and improves some cases),
so do it.
---
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 6 +-
llvm/test/CodeGen/AMDGPU/srem64.ll | 244 +++++++++---------
llvm/test/CodeGen/X86/freeze-binary.ll | 21 +-
llvm/test/CodeGen/X86/select-constant-xor.ll | 12 +-
4 files changed, 139 insertions(+), 144 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index d60ca57ae5ea8..8101ba511c7b0 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -18491,10 +18491,10 @@ SDValue DAGCombiner::visitFREEZE(SDNode *N) {
return FrozenN0;
}
- // We currently avoid folding freeze over SRA/SRL, due to the problems seen
- // with (freeze (assert ext)) blocking simplifications of SRA/SRL. See for
+ // We currently avoid folding freeze over SRL, due to the problems seen
+ // with (freeze (assert ext)) blocking simplifications of SRL. See for
// example https://reviews.llvm.org/D136529#4120959.
- if (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)
+ if (N0.getOpcode() == ISD::SRL)
return SDValue();
// Fold freeze(op(x, ...)) -> op(freeze(x), ...).
diff --git a/llvm/test/CodeGen/AMDGPU/srem64.ll b/llvm/test/CodeGen/AMDGPU/srem64.ll
index fd713082c1f97..7629363882c37 100644
--- a/llvm/test/CodeGen/AMDGPU/srem64.ll
+++ b/llvm/test/CodeGen/AMDGPU/srem64.ll
@@ -1128,20 +1128,20 @@ define amdgpu_kernel void @s_test_srem32_64(ptr addrspace(1) %out, i64 %x, i64 %
define amdgpu_kernel void @s_test_srem33_64(ptr addrspace(1) %out, i64 %x, i64 %y) {
; GCN-LABEL: s_test_srem33_64:
; GCN: ; %bb.0:
-; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
-; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd
+; GCN-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x9
+; GCN-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0xd
; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: s_ashr_i64 s[6:7], s[2:3], 31
-; GCN-NEXT: s_ashr_i64 s[2:3], s[4:5], 31
-; GCN-NEXT: s_ashr_i32 s4, s3, 31
-; GCN-NEXT: s_add_u32 s2, s2, s4
-; GCN-NEXT: s_mov_b32 s5, s4
-; GCN-NEXT: s_addc_u32 s3, s3, s4
-; GCN-NEXT: s_xor_b64 s[4:5], s[2:3], s[4:5]
+; GCN-NEXT: s_ashr_i64 s[0:1], s[10:11], 31
+; GCN-NEXT: s_ashr_i64 s[4:5], s[2:3], 31
+; GCN-NEXT: s_ashr_i32 s2, s3, 31
+; GCN-NEXT: s_ashr_i32 s3, s5, 31
+; GCN-NEXT: s_add_u32 s4, s4, s2
+; GCN-NEXT: s_addc_u32 s5, s5, s3
+; GCN-NEXT: s_xor_b64 s[4:5], s[4:5], s[2:3]
; GCN-NEXT: v_cvt_f32_u32_e32 v0, s4
; GCN-NEXT: v_cvt_f32_u32_e32 v1, s5
-; GCN-NEXT: s_sub_u32 s8, 0, s4
-; GCN-NEXT: s_subb_u32 s9, 0, s5
+; GCN-NEXT: s_sub_u32 s6, 0, s4
+; GCN-NEXT: s_subb_u32 s7, 0, s5
; GCN-NEXT: s_mov_b32 s3, 0xf000
; GCN-NEXT: v_madmk_f32 v0, v1, 0x4f800000, v0
; GCN-NEXT: v_rcp_f32_e32 v0, v0
@@ -1152,103 +1152,105 @@ define amdgpu_kernel void @s_test_srem33_64(ptr addrspace(1) %out, i64 %x, i64 %
; GCN-NEXT: v_madmk_f32 v0, v1, 0xcf800000, v0
; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GCN-NEXT: v_mul_hi_u32 v2, s8, v0
+; GCN-NEXT: v_mul_hi_u32 v2, s6, v0
; GCN-NEXT: v_readfirstlane_b32 s10, v1
-; GCN-NEXT: v_readfirstlane_b32 s11, v0
-; GCN-NEXT: s_mul_i32 s12, s8, s10
-; GCN-NEXT: v_readfirstlane_b32 s15, v2
-; GCN-NEXT: s_mul_i32 s13, s9, s11
-; GCN-NEXT: s_mul_i32 s14, s8, s11
-; GCN-NEXT: s_add_i32 s12, s15, s12
-; GCN-NEXT: v_mul_hi_u32 v3, v0, s14
-; GCN-NEXT: s_add_i32 s12, s12, s13
-; GCN-NEXT: v_mul_hi_u32 v0, v0, s12
-; GCN-NEXT: v_mul_hi_u32 v4, v1, s14
-; GCN-NEXT: v_readfirstlane_b32 s13, v3
-; GCN-NEXT: s_mul_i32 s15, s11, s12
-; GCN-NEXT: s_add_u32 s13, s13, s15
+; GCN-NEXT: v_readfirstlane_b32 s12, v0
+; GCN-NEXT: s_mul_i32 s13, s6, s10
+; GCN-NEXT: v_readfirstlane_b32 s16, v2
+; GCN-NEXT: s_mul_i32 s14, s7, s12
+; GCN-NEXT: s_mul_i32 s15, s6, s12
+; GCN-NEXT: s_add_i32 s13, s16, s13
+; GCN-NEXT: v_mul_hi_u32 v3, v0, s15
+; GCN-NEXT: s_add_i32 s13, s13, s14
+; GCN-NEXT: v_mul_hi_u32 v0, v0, s13
+; GCN-NEXT: v_mul_hi_u32 v4, v1, s15
+; GCN-NEXT: v_readfirstlane_b32 s14, v3
+; GCN-NEXT: s_mul_i32 s16, s12, s13
+; GCN-NEXT: s_add_u32 s14, s14, s16
+; GCN-NEXT: v_readfirstlane_b32 s16, v0
+; GCN-NEXT: v_mul_hi_u32 v0, v1, s13
+; GCN-NEXT: s_addc_u32 s16, 0, s16
+; GCN-NEXT: s_mul_i32 s15, s10, s15
+; GCN-NEXT: v_readfirstlane_b32 s17, v4
+; GCN-NEXT: s_add_u32 s14, s14, s15
+; GCN-NEXT: s_addc_u32 s14, s16, s17
; GCN-NEXT: v_readfirstlane_b32 s15, v0
-; GCN-NEXT: v_mul_hi_u32 v0, v1, s12
-; GCN-NEXT: s_addc_u32 s15, 0, s15
-; GCN-NEXT: s_mul_i32 s14, s10, s14
-; GCN-NEXT: v_readfirstlane_b32 s16, v4
-; GCN-NEXT: s_add_u32 s13, s13, s14
-; GCN-NEXT: s_addc_u32 s13, s15, s16
-; GCN-NEXT: v_readfirstlane_b32 s14, v0
-; GCN-NEXT: s_addc_u32 s14, s14, 0
-; GCN-NEXT: s_mul_i32 s12, s10, s12
-; GCN-NEXT: s_add_u32 s12, s13, s12
-; GCN-NEXT: s_addc_u32 s13, 0, s14
-; GCN-NEXT: s_add_u32 s11, s11, s12
-; GCN-NEXT: v_mov_b32_e32 v1, s11
-; GCN-NEXT: v_mul_hi_u32 v1, s8, v1
-; GCN-NEXT: s_addc_u32 s10, s10, s13
-; GCN-NEXT: s_mul_i32 s12, s8, s11
-; GCN-NEXT: s_mul_i32 s8, s8, s10
-; GCN-NEXT: v_readfirstlane_b32 s13, v1
-; GCN-NEXT: s_add_i32 s8, s13, s8
-; GCN-NEXT: s_mul_i32 s9, s9, s11
-; GCN-NEXT: v_mov_b32_e32 v0, s12
-; GCN-NEXT: s_add_i32 s8, s8, s9
+; GCN-NEXT: s_addc_u32 s15, s15, 0
+; GCN-NEXT: s_mul_i32 s13, s10, s13
+; GCN-NEXT: s_add_u32 s13, s14, s13
+; GCN-NEXT: s_addc_u32 s14, 0, s15
+; GCN-NEXT: s_add_u32 s12, s12, s13
+; GCN-NEXT: v_mov_b32_e32 v1, s12
+; GCN-NEXT: v_mul_hi_u32 v1, s6, v1
+; GCN-NEXT: s_addc_u32 s10, s10, s14
+; GCN-NEXT: s_mul_i32 s13, s6, s12
+; GCN-NEXT: s_mul_i32 s6, s6, s10
+; GCN-NEXT: v_readfirstlane_b32 s14, v1
+; GCN-NEXT: s_add_i32 s6, s14, s6
+; GCN-NEXT: s_mul_i32 s7, s7, s12
+; GCN-NEXT: v_mov_b32_e32 v0, s13
+; GCN-NEXT: s_add_i32 s6, s6, s7
; GCN-NEXT: v_mul_hi_u32 v2, s10, v0
-; GCN-NEXT: v_mov_b32_e32 v1, s8
-; GCN-NEXT: v_mul_hi_u32 v0, s11, v0
-; GCN-NEXT: v_mul_hi_u32 v3, s11, v1
-; GCN-NEXT: s_mul_i32 s13, s11, s8
-; GCN-NEXT: s_mul_i32 s12, s10, s12
-; GCN-NEXT: v_readfirstlane_b32 s15, v0
+; GCN-NEXT: v_mov_b32_e32 v1, s6
+; GCN-NEXT: v_mul_hi_u32 v0, s12, v0
+; GCN-NEXT: v_mul_hi_u32 v3, s12, v1
+; GCN-NEXT: s_mul_i32 s14, s12, s6
+; GCN-NEXT: s_mul_i32 s13, s10, s13
+; GCN-NEXT: v_readfirstlane_b32 s16, v0
; GCN-NEXT: v_mul_hi_u32 v0, s10, v1
+; GCN-NEXT: v_readfirstlane_b32 s15, v3
+; GCN-NEXT: s_add_u32 s14, s16, s14
+; GCN-NEXT: s_addc_u32 s15, 0, s15
+; GCN-NEXT: v_readfirstlane_b32 s7, v2
+; GCN-NEXT: s_add_u32 s13, s14, s13
+; GCN-NEXT: s_addc_u32 s7, s15, s7
+; GCN-NEXT: v_readfirstlane_b32 s13, v0
+; GCN-NEXT: s_addc_u32 s13, s13, 0
+; GCN-NEXT: s_mul_i32 s6, s10, s6
+; GCN-NEXT: s_add_u32 s6, s7, s6
+; GCN-NEXT: s_addc_u32 s7, 0, s13
+; GCN-NEXT: s_add_u32 s12, s12, s6
+; GCN-NEXT: s_addc_u32 s13, s10, s7
+; GCN-NEXT: s_ashr_i32 s6, s11, 31
+; GCN-NEXT: s_add_u32 s0, s0, s6
+; GCN-NEXT: s_mov_b32 s7, s6
+; GCN-NEXT: s_addc_u32 s1, s1, s6
+; GCN-NEXT: s_xor_b64 s[10:11], s[0:1], s[6:7]
+; GCN-NEXT: v_mov_b32_e32 v0, s13
+; GCN-NEXT: v_mul_hi_u32 v1, s10, v0
+; GCN-NEXT: v_mov_b32_e32 v2, s12
+; GCN-NEXT: v_mul_hi_u32 v3, s10, v2
+; GCN-NEXT: s_mov_b32 s0, s8
+; GCN-NEXT: v_readfirstlane_b32 s8, v1
+; GCN-NEXT: v_mul_hi_u32 v1, s11, v2
+; GCN-NEXT: s_mul_i32 s1, s10, s13
; GCN-NEXT: v_readfirstlane_b32 s14, v3
-; GCN-NEXT: s_add_u32 s13, s15, s13
-; GCN-NEXT: s_addc_u32 s14, 0, s14
-; GCN-NEXT: v_readfirstlane_b32 s9, v2
-; GCN-NEXT: s_add_u32 s12, s13, s12
-; GCN-NEXT: s_addc_u32 s9, s14, s9
-; GCN-NEXT: v_readfirstlane_b32 s12, v0
-; GCN-NEXT: s_addc_u32 s12, s12, 0
-; GCN-NEXT: s_mul_i32 s8, s10, s8
-; GCN-NEXT: s_add_u32 s8, s9, s8
-; GCN-NEXT: s_addc_u32 s9, 0, s12
-; GCN-NEXT: s_add_u32 s11, s11, s8
-; GCN-NEXT: s_addc_u32 s10, s10, s9
-; GCN-NEXT: s_ashr_i32 s8, s7, 31
-; GCN-NEXT: s_add_u32 s6, s6, s8
-; GCN-NEXT: s_mov_b32 s9, s8
-; GCN-NEXT: s_addc_u32 s7, s7, s8
-; GCN-NEXT: s_xor_b64 s[6:7], s[6:7], s[8:9]
-; GCN-NEXT: v_mov_b32_e32 v0, s10
-; GCN-NEXT: v_mul_hi_u32 v1, s6, v0
-; GCN-NEXT: v_mov_b32_e32 v2, s11
-; GCN-NEXT: v_mul_hi_u32 v3, s6, v2
-; GCN-NEXT: s_mul_i32 s12, s6, s10
-; GCN-NEXT: v_readfirstlane_b32 s13, v1
-; GCN-NEXT: v_mul_hi_u32 v1, s7, v2
-; GCN-NEXT: v_readfirstlane_b32 s14, v3
-; GCN-NEXT: v_mul_hi_u32 v0, s7, v0
-; GCN-NEXT: s_add_u32 s12, s14, s12
-; GCN-NEXT: s_addc_u32 s13, 0, s13
-; GCN-NEXT: s_mul_i32 s11, s7, s11
+; GCN-NEXT: v_mul_hi_u32 v0, s11, v0
+; GCN-NEXT: s_add_u32 s1, s14, s1
+; GCN-NEXT: s_addc_u32 s8, 0, s8
+; GCN-NEXT: s_mul_i32 s12, s11, s12
; GCN-NEXT: v_readfirstlane_b32 s14, v1
-; GCN-NEXT: s_add_u32 s11, s12, s11
-; GCN-NEXT: s_addc_u32 s11, s13, s14
-; GCN-NEXT: v_readfirstlane_b32 s12, v0
-; GCN-NEXT: s_addc_u32 s12, s12, 0
-; GCN-NEXT: s_mul_i32 s10, s7, s10
-; GCN-NEXT: s_add_u32 s10, s11, s10
-; GCN-NEXT: v_mov_b32_e32 v0, s10
+; GCN-NEXT: s_add_u32 s1, s1, s12
+; GCN-NEXT: s_addc_u32 s1, s8, s14
+; GCN-NEXT: v_readfirstlane_b32 s8, v0
+; GCN-NEXT: s_addc_u32 s8, s8, 0
+; GCN-NEXT: s_mul_i32 s12, s11, s13
+; GCN-NEXT: s_add_u32 s12, s1, s12
+; GCN-NEXT: v_mov_b32_e32 v0, s12
; GCN-NEXT: v_mul_hi_u32 v0, s4, v0
-; GCN-NEXT: s_addc_u32 s11, 0, s12
-; GCN-NEXT: s_mul_i32 s11, s4, s11
-; GCN-NEXT: v_readfirstlane_b32 s12, v0
-; GCN-NEXT: s_add_i32 s11, s12, s11
-; GCN-NEXT: s_mul_i32 s12, s5, s10
-; GCN-NEXT: s_add_i32 s14, s11, s12
-; GCN-NEXT: s_sub_i32 s12, s7, s14
-; GCN-NEXT: s_mul_i32 s10, s4, s10
-; GCN-NEXT: s_sub_u32 s6, s6, s10
-; GCN-NEXT: s_cselect_b64 s[10:11], -1, 0
-; GCN-NEXT: s_subb_u32 s15, s12, s5
-; GCN-NEXT: s_sub_u32 s16, s6, s4
+; GCN-NEXT: s_addc_u32 s8, 0, s8
+; GCN-NEXT: s_mov_b32 s1, s9
+; GCN-NEXT: s_mul_i32 s8, s4, s8
+; GCN-NEXT: v_readfirstlane_b32 s9, v0
+; GCN-NEXT: s_add_i32 s8, s9, s8
+; GCN-NEXT: s_mul_i32 s9, s5, s12
+; GCN-NEXT: s_add_i32 s14, s8, s9
+; GCN-NEXT: s_sub_i32 s13, s11, s14
+; GCN-NEXT: s_mul_i32 s8, s4, s12
+; GCN-NEXT: s_sub_u32 s10, s10, s8
+; GCN-NEXT: s_cselect_b64 s[8:9], -1, 0
+; GCN-NEXT: s_subb_u32 s15, s13, s5
+; GCN-NEXT: s_sub_u32 s16, s10, s4
; GCN-NEXT: s_cselect_b64 s[12:13], -1, 0
; GCN-NEXT: s_subb_u32 s17, s15, 0
; GCN-NEXT: s_cmp_ge_u32 s17, s5
@@ -1264,20 +1266,20 @@ define amdgpu_kernel void @s_test_srem33_64(ptr addrspace(1) %out, i64 %x, i64 %
; GCN-NEXT: s_cmp_lg_u32 s18, 0
; GCN-NEXT: s_cselect_b32 s13, s13, s16
; GCN-NEXT: s_cselect_b32 s12, s12, s17
-; GCN-NEXT: s_or_b32 s10, s10, s11
-; GCN-NEXT: s_subb_u32 s7, s7, s14
-; GCN-NEXT: s_cmp_ge_u32 s7, s5
-; GCN-NEXT: s_cselect_b32 s10, -1, 0
-; GCN-NEXT: s_cmp_ge_u32 s6, s4
+; GCN-NEXT: s_or_b32 s8, s8, s9
+; GCN-NEXT: s_subb_u32 s8, s11, s14
+; GCN-NEXT: s_cmp_ge_u32 s8, s5
+; GCN-NEXT: s_cselect_b32 s9, -1, 0
+; GCN-NEXT: s_cmp_ge_u32 s10, s4
; GCN-NEXT: s_cselect_b32 s4, -1, 0
-; GCN-NEXT: s_cmp_eq_u32 s7, s5
-; GCN-NEXT: s_cselect_b32 s4, s4, s10
+; GCN-NEXT: s_cmp_eq_u32 s8, s5
+; GCN-NEXT: s_cselect_b32 s4, s4, s9
; GCN-NEXT: s_cmp_lg_u32 s4, 0
-; GCN-NEXT: s_cselect_b32 s5, s12, s7
-; GCN-NEXT: s_cselect_b32 s4, s13, s6
-; GCN-NEXT: s_xor_b64 s[4:5], s[4:5], s[8:9]
-; GCN-NEXT: s_sub_u32 s4, s4, s8
-; GCN-NEXT: s_subb_u32 s5, s5, s8
+; GCN-NEXT: s_cselect_b32 s5, s12, s8
+; GCN-NEXT: s_cselect_b32 s4, s13, s10
+; GCN-NEXT: s_xor_b64 s[4:5], s[4:5], s[6:7]
+; GCN-NEXT: s_sub_u32 s4, s4, s6
+; GCN-NEXT: s_subb_u32 s5, s5, s6
; GCN-NEXT: v_mov_b32_e32 v0, s4
; GCN-NEXT: v_mov_b32_e32 v1, s5
; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
@@ -1286,24 +1288,24 @@ define amdgpu_kernel void @s_test_srem33_64(ptr addrspace(1) %out, i64 %x, i64 %
; GCN-IR-LABEL: s_test_srem33_64:
; GCN-IR: ; %bb.0: ; %_udiv-special-cases
; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
-; GCN-IR-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd
+; GCN-IR-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0xd
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-IR-NEXT: s_ashr_i64 s[2:3], s[2:3], 31
-; GCN-IR-NEXT: s_ashr_i64 s[8:9], s[4:5], 31
; GCN-IR-NEXT: s_ashr_i32 s4, s3, 31
+; GCN-IR-NEXT: s_ashr_i64 s[6:7], s[2:3], 31
; GCN-IR-NEXT: s_mov_b32 s5, s4
-; GCN-IR-NEXT: s_xor_b64 s[2:3], s[2:3], s[4:5]
+; GCN-IR-NEXT: s_ashr_i64 s[10:11], s[8:9], 31
+; GCN-IR-NEXT: s_xor_b64 s[2:3], s[6:7], s[4:5]
; GCN-IR-NEXT: s_sub_u32 s6, s2, s4
; GCN-IR-NEXT: s_subb_u32 s7, s3, s4
; GCN-IR-NEXT: s_ashr_i32 s2, s9, 31
; GCN-IR-NEXT: s_mov_b32 s3, s2
-; GCN-IR-NEXT: s_xor_b64 s[8:9], s[8:9], s[2:3]
+; GCN-IR-NEXT: s_xor_b64 s[8:9], s[10:11], s[2:3]
; GCN-IR-NEXT: s_sub_u32 s8, s8, s2
; GCN-IR-NEXT: s_subb_u32 s9, s9, s2
-; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[10:11], s[6:7], 0
-; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[2:3], s[8:9], 0
+; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[2:3], s[6:7], 0
+; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[10:11], s[8:9], 0
; GCN-IR-NEXT: s_flbit_i32_b64 s12, s[8:9]
-; GCN-IR-NEXT: s_or_b64 s[10:11], s[2:3], s[10:11]
+; GCN-IR-NEXT: s_or_b64 s[10:11], s[10:11], s[2:3]
; GCN-IR-NEXT: s_flbit_i32_b64 s18, s[6:7]
; GCN-IR-NEXT: s_sub_u32 s14, s12, s18
; GCN-IR-NEXT: s_subb_u32 s15, 0, 0
diff --git a/llvm/test/CodeGen/X86/freeze-binary.ll b/llvm/test/CodeGen/X86/freeze-binary.ll
index be4bdfdfeba9a..e4b2dcf0a62dd 100644
--- a/llvm/test/CodeGen/X86/freeze-binary.ll
+++ b/llvm/test/CodeGen/X86/freeze-binary.ll
@@ -452,8 +452,7 @@ define i32 @freeze_ashr(i32 %a0) nounwind {
; X86-LABEL: freeze_ashr:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X86-NEXT: sarl $3, %eax
-; X86-NEXT: sarl $3, %eax
+; X86-NEXT: sarl $6, %eax
; X86-NEXT: retl
;
; X64-LABEL: freeze_ashr:
@@ -471,15 +470,13 @@ define i32 @freeze_ashr_exact(i32 %a0) nounwind {
; X86-LABEL: freeze_ashr_exact:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X86-NEXT: sarl $3, %eax
-; X86-NEXT: sarl $6, %eax
+; X86-NEXT: sarl $9, %eax
; X86-NEXT: retl
;
; X64-LABEL: freeze_ashr_exact:
; X64: # %bb.0:
; X64-NEXT: movl %edi, %eax
-; X64-NEXT: sarl $3, %eax
-; X64-NEXT: sarl $6, %eax
+; X64-NEXT: sarl $9, %eax
; X64-NEXT: retq
%x = ashr exact i32 %a0, 3
%y = freeze i32 %x
@@ -490,20 +487,20 @@ define i32 @freeze_ashr_exact(i32 %a0) nounwind {
define i32 @freeze_ashr_exact_extra_use(i32 %a0, ptr %escape) nounwind {
; X86-LABEL: freeze_ashr_exact_extra_use:
; X86: # %bb.0:
-; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X86-NEXT: sarl $3, %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl %eax, %edx
-; X86-NEXT: sarl $6, %eax
+; X86-NEXT: sarl $3, %edx
+; X86-NEXT: sarl $9, %eax
; X86-NEXT: movl %edx, (%ecx)
; X86-NEXT: retl
;
; X64-LABEL: freeze_ashr_exact_extra_use:
; X64: # %bb.0:
; X64-NEXT: movl %edi, %eax
-; X64-NEXT: sarl $3, %eax
-; X64-NEXT: movl %eax, %ecx
-; X64-NEXT: sarl $6, %eax
+; X64-NEXT: movl %edi, %ecx
+; X64-NEXT: sarl $3, %ecx
+; X64-NEXT: sarl $9, %eax
; X64-NEXT: movl %ecx, (%rsi)
; X64-NEXT: retq
%x = ashr exact i32 %a0, 3
diff --git a/llvm/test/CodeGen/X86/select-constant-xor.ll b/llvm/test/CodeGen/X86/select-constant-xor.ll
index 5d80e04fef38c..efc367d204cf1 100644
--- a/llvm/test/CodeGen/X86/select-constant-xor.ll
+++ b/llvm/test/CodeGen/X86/select-constant-xor.ll
@@ -172,10 +172,8 @@ define i32 @selecti8i32(i8 %a) {
define i32 @icmpasreq(i32 %input, i32 %a, i32 %b) {
; X86-LABEL: icmpasreq:
; X86: # %bb.0:
-; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X86-NEXT: sarl $31, %eax
-; X86-NEXT: cmpl $-1, %eax
-; X86-NEXT: je .LBB8_1
+; X86-NEXT: cmpl $0, {{[0-9]+}}(%esp)
+; X86-NEXT: js .LBB8_1
; X86-NEXT: # %bb.2:
; X86-NEXT: leal {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl (%eax), %eax
@@ -200,10 +198,8 @@ define i32 @icmpasreq(i32 %input, i32 %a, i32 %b) {
define i32 @icmpasrne(i32 %input, i32 %a, i32 %b) {
; X86-LABEL: icmpasrne:
; X86: # %bb.0:
-; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X86-NEXT: sarl $31, %eax
-; X86-NEXT: cmpl $-1, %eax
-; X86-NEXT: jne .LBB9_1
+; X86-NEXT: cmpl $0, {{[0-9]+}}(%esp)
+; X86-NEXT: jns .LBB9_1
; X86-NEXT: # %bb.2:
; X86-NEXT: leal {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl (%eax), %eax
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