[llvm] [AMDGPU] Check hasNoF16PseudoScalarTransInlineConstants in more places (PR #208459)

[Frederik Harwath via llvm-commits]

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@@ -1981,19 +1981,34 @@ class VOP_Pseudo_Scalar<RegisterClass Dst, RegisterOperand SrcOp,
 
 def VOP_Pseudo_Scalar_F32 : VOP_Pseudo_Scalar<SReg_32_XEXEC, SSrc_f32, f32>;
 def VOP_Pseudo_Scalar_F16 : VOP_Pseudo_Scalar<SReg_32_XEXEC, SSrc_f16, f32, f16>;
+def VOP_Pseudo_Scalar_F16_NoInline : VOP_Pseudo_Scalar<SReg_32_XEXEC, SSrc_NoInline_f16, f32, f16>;
+
+// Define regular and "no inline constant" variant of a F16 pseudo
+// scalar transcendental instruction.
+multiclass VOP3PseudoScalarInst_F16<string opName> {
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frederik-h wrote:

But this is very specific to the pseudo-scalar transcendental instructions and for those instructions, the restrictions only applies to F16? Or do you mean that it should be generalized to handle other instructions?

https://github.com/llvm/llvm-project/pull/208459