[llvm] [AMDGPU] Optimize SGPR splat reg sequences for packed 64-bit instructions (PR #217182)

[Tim Gymnich via llvm-commits]

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@@ -2473,10 +2474,86 @@ bool SIFoldOperandsImpl::tryFoldOMod(MachineInstr &MI) {
   return true;
 }
 
+// Try to optimize SGPR reg sequences that are splat <s, s> or <s, s, s, s>
+// where all uses are PackedSingleSGPR64BitInst, replacing with <s, undef, ...>
+bool SIFoldOperandsImpl::tryFoldSGPRSplatRegSequence(MachineInstr &MI) {
+  assert(MI.isRegSequence());
+  Register Reg = MI.getOperand(0).getReg();
+
+  // Only optimize SGPR register sequences
+  if (!TRI->isSGPRClass(MRI->getRegClass(Reg)))
+    return false;
+
+  SmallVector<std::pair<MachineOperand *, unsigned>, 32> Defs;
+  if (!getRegSeqInit(Defs, Reg))
+    return false;
+
+  // Check if this is a splat pattern
+  if (Defs.size() <= 1)
+    return false;
+
+  const auto &[FirstOp, _] = Defs.front();
+  if (!FirstOp->isReg())
+    return false;
+
+  Register FirstReg = FirstOp->getReg();
+  unsigned FirstSubReg = FirstOp->getSubReg();
+
+  if (!TRI->isSGPRClass(MRI->getRegClass(FirstReg)))
+    return false;
+
+  // Check remaining elements match first
+  if (!llvm::all_of(llvm::drop_begin(Defs), [&](const auto &Def) {
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tgymnich wrote:

this should use `llvm::any_of` instead

https://github.com/llvm/llvm-project/pull/217182