[llvm] [BOLT][RISCV] Fix AUIPC/JALR call rewriting (PR #216882)

[Rafael Auler via llvm-commits]

https://github.com/rafaelauler commented:

Regarding the extra stuff being added into the disassembly loop, I want to replicate my comment at #149658:

> On the other hand, I should warn that the kind of stuff you're doing here is what a BOLT target symbolizer would be doing (sanitizing the references based on relocations). Take a look at bolt/lib/Target/X86/X86MCSymbolizer.cpp and bolt/lib/Target/AArch64/AArch64MCSymbolizer.cpp for references on other targets. I noticed RISCV has no symbolizer yet -- the RISCV port probably needs to implement one, otherwise you will be adding a lot of logic to the body of ::disassemble, which was designed to operate with the symbolizer.

I don't know if it's possible to solve the RISCV issues by refactoring logic to live in the symbolizer that works with the disassembler, though, but if it is possible, it's something to consider to make the port more similar to the other two archs (x86 and aarch64).

Regarding unittesting:  try to steer AI away from unittests as we do prefer the LIT ones, if possible. 

https://github.com/llvm/llvm-project/pull/216882