[llvm] [AMDGPU] Improve the sequence for initial unclaused VMEM (PR #216897)

[Stanislav Mekhanoshin via llvm-commits]

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@@ -3709,12 +3709,18 @@ bool SIInsertWaitcnts::run() {
     // Hardware entrypoints must begin with a specific sequence:
     //   S_MOV_B64 S[64:65], 0
     //   V_NOP
+    //   S_SETREG_IMM32_B32 HW_REG_WAVE_MODE.REPLAY_MODE, 1
     //   GLOBAL_PREFETCH_B8 V0, S[64:65] SCOPE:SCOPE_SE TH:TH_LOAD_RT
     MachineBasicBlock::iterator I = EntryBB.begin();
     BuildMI(EntryBB, I, DebugLoc(), TII.get(AMDGPU::S_MOV_B64),
             AMDGPU::SGPR64_SGPR65)
         .addImm(0);
     BuildMI(EntryBB, I, DebugLoc(), TII.get(AMDGPU::V_NOP_e32));
+    unsigned RegEncoding =
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rampitec wrote:

I believe the ticket asks this setreg to be the first instruction in the sequence.

https://github.com/llvm/llvm-project/pull/216897