[llvm] [AMDGPU] Break WAR Hazards Using Scavenged Registers to Assist Load Clustering (PR #216343)
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Tue Aug 18 10:57:11 PDT 2026
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``````````bash
git-clang-format --diff origin/main HEAD --extensions cpp,h -- llvm/lib/Target/AMDGPU/GCNBreakLoadClusterDeps.cpp llvm/lib/Target/AMDGPU/GCNBreakLoadClusterDeps.h llvm/lib/Target/AMDGPU/AMDGPU.h llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp --diff_from_common_commit
``````````
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``````````diff
diff --git a/llvm/lib/Target/AMDGPU/GCNBreakLoadClusterDeps.cpp b/llvm/lib/Target/AMDGPU/GCNBreakLoadClusterDeps.cpp
index ff2f7fd63..ce78ae3b6 100644
--- a/llvm/lib/Target/AMDGPU/GCNBreakLoadClusterDeps.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNBreakLoadClusterDeps.cpp
@@ -162,7 +162,7 @@ Register GCNBreakLoadClusterDepsImpl::renameRegister(Register FromReg,
bool GCNBreakLoadClusterDepsImpl::findReplaceRegisterOperand(
MachineInstr &MI, unsigned OpNum,
const bitset<AMDGPU::NUM_TARGET_REGS> &BannedRegs) {
- MachineBasicBlock& MBB = *MI.getParent();
+ MachineBasicBlock &MBB = *MI.getParent();
MachineInstr *DefToRename = nullptr, *KillerIns = nullptr;
Register OldReg = MI.getOperand(OpNum).getReg();
bitset<AMDGPU::NUM_TARGET_REGS> OldRegClobbers = getVGPR32Lanes(OldReg);
@@ -189,8 +189,9 @@ bool GCNBreakLoadClusterDepsImpl::findReplaceRegisterOperand(
NewKiller = &*It;
ClobberedSubregs |= Subregs.first;
- //Handle promoting OldReg to a super-register of it
- Register NewOldReg = promoteToSuperRegister(*std::prev(It),OldReg,true,false);
+ // Handle promoting OldReg to a super-register of it
+ Register NewOldReg =
+ promoteToSuperRegister(*std::prev(It), OldReg, true, false);
NewOldReg = promoteToSuperRegister(*It, NewOldReg, false, true);
if (NewOldReg != OldReg) {
Changed = true;
@@ -214,7 +215,7 @@ bool GCNBreakLoadClusterDepsImpl::findReplaceRegisterOperand(
}
}
- //Second, go backward from killer to find the def
+ // Second, go backward from killer to find the def
if (KillerIns) {
bitset<AMDGPU::NUM_TARGET_REGS> ClobberedSubregs;
MachineInstr *NewDef = DefToRename ? DefToRename : nullptr;
@@ -249,7 +250,7 @@ bool GCNBreakLoadClusterDepsImpl::findReplaceRegisterOperand(
KillerIns->getReverseIterator();
&*AccumIt != DefToRename; ++AccumIt)
LRU.accumulate(*AccumIt);
-
+
// Iterate over registers in physical register class
const TargetRegisterClass &DefinedRegClass =
*TRI->getPhysRegBaseClass(OldReg);
@@ -266,30 +267,31 @@ bool GCNBreakLoadClusterDepsImpl::findReplaceRegisterOperand(
// Fail if we couldn't find a suitable free register
if (I == DefinedRegClass.getRegisters().size())
return false;
-
+
// Actually rename the register
for (unsigned Op = 0; Op < DefToRename->getNumExplicitOperands(); Op++)
- if (DefToRename->getOperand(Op).isReg() && DefToRename->getOperand(Op).isDef() &&
+ if (DefToRename->getOperand(Op).isReg() &&
+ DefToRename->getOperand(Op).isDef() &&
TRI->regsOverlap(DefToRename->getOperand(Op).getReg(), OldReg))
DefToRename->getOperand(Op).setReg(
- renameRegister(OldReg, DefinedRegClass.getRegisters()[I],
- DefToRename->getOperand(Op).getReg()));
+ renameRegister(OldReg, DefinedRegClass.getRegisters()[I],
+ DefToRename->getOperand(Op).getReg()));
for (MachineBasicBlock::iterator RenameIt =
- std::next(DefToRename->getIterator());
+ std::next(DefToRename->getIterator());
RenameIt != KillerIns; ++RenameIt)
for (unsigned Op = 0; Op < RenameIt->getNumExplicitOperands(); Op++)
if (RenameIt->getOperand(Op).isReg() &&
TRI->regsOverlap(RenameIt->getOperand(Op).getReg(), OldReg))
RenameIt->getOperand(Op).setReg(
- renameRegister(OldReg, DefinedRegClass.getRegisters()[I],
- RenameIt->getOperand(Op).getReg()));
+ renameRegister(OldReg, DefinedRegClass.getRegisters()[I],
+ RenameIt->getOperand(Op).getReg()));
for (unsigned Op = 0; Op < KillerIns->getNumExplicitOperands(); Op++)
if (KillerIns->getOperand(Op).isReg() &&
KillerIns->getOperand(Op).isUse() &&
TRI->regsOverlap(KillerIns->getOperand(Op).getReg(), OldReg))
KillerIns->getOperand(Op).setReg(
- renameRegister(OldReg, DefinedRegClass.getRegisters()[I],
- KillerIns->getOperand(Op).getReg()));
+ renameRegister(OldReg, DefinedRegClass.getRegisters()[I],
+ KillerIns->getOperand(Op).getReg()));
return true;
}
@@ -307,7 +309,7 @@ bool GCNBreakLoadClusterDepsImpl::runOnMachineBasicBlock(
reverse(AllVectorLoads.begin(), AllVectorLoads.end()); // efficiency
bitset<AMDGPU::NUM_TARGET_REGS> UsedLoadSourcePhysregs, UsedLoadDestPhysregs;
- unordered_set<MachineInstr*> ClusterLoads;
+ unordered_set<MachineInstr *> ClusterLoads;
while (!AllVectorLoads.empty()) {
MachineInstr &VecLoadIns = *AllVectorLoads.back();
bitset<AMDGPU::NUM_TARGET_REGS> InsDefs, InsUses;
@@ -329,7 +331,7 @@ bool GCNBreakLoadClusterDepsImpl::runOnMachineBasicBlock(
if (Operand.isReg() && Operand.isUse() &&
TRI->isVGPR(*MRI, Operand.getReg()))
UsedVGPRs |= getVGPR32Lanes(Operand.getReg());
-
+
if ((ClusterRAWHazards & UsedVGPRs).any())
break;
@@ -338,7 +340,7 @@ bool GCNBreakLoadClusterDepsImpl::runOnMachineBasicBlock(
getVGPR32Lanes(ForwardIt->getOperand(0).getReg());
} else
for (MachineOperand &Operand : ForwardIt->defs())
- if (TRI->isVGPR(*MRI,Operand.getReg()))
+ if (TRI->isVGPR(*MRI, Operand.getReg()))
ClusterRAWHazards &= getVGPR32Lanes(Operand.getReg());
}
} else
@@ -347,16 +349,16 @@ bool GCNBreakLoadClusterDepsImpl::runOnMachineBasicBlock(
// If it's used or defined by a load that could be in our cluster, it's
// _NOT_ free.
bitset<AMDGPU::NUM_TARGET_REGS> BannedRegs =
- UsedLoadDestPhysregs | UsedLoadSourcePhysregs;
+ UsedLoadDestPhysregs | UsedLoadSourcePhysregs;
for (MachineInstr *FutureVecLoad : ClusterLoads) {
auto UsesAndDefs = getUsesAndDefsFor(*FutureVecLoad);
BannedRegs |= UsesAndDefs.first;
BannedRegs |= UsesAndDefs.second;
}
-
+
// Check if we have something to rename due to WAR
bitset<AMDGPU::NUM_TARGET_REGS> WarConflicts =
- (InsUses | InsDefs) & (UsedLoadSourcePhysregs | UsedLoadDestPhysregs);
+ (InsUses | InsDefs) & (UsedLoadSourcePhysregs | UsedLoadDestPhysregs);
while (WarConflicts.any()) {
Register OldReg = WarConflicts._Find_first();
unsigned OpNum;
@@ -368,12 +370,12 @@ bool GCNBreakLoadClusterDepsImpl::runOnMachineBasicBlock(
"There should be a conflicting register operand. Where is it?");
if (!findReplaceRegisterOperand(VecLoadIns, OpNum, BannedRegs))
break;
-
+
tie(InsDefs, InsUses) = getUsesAndDefsFor(VecLoadIns);
WarConflicts =
(InsUses | InsDefs) & (UsedLoadSourcePhysregs | UsedLoadDestPhysregs);
}
-
+
// Check if we have something to rename due to WAR
bitset<AMDGPU::NUM_TARGET_REGS> SelfConflicts = InsUses & InsDefs;
while (SelfConflicts.any()) {
@@ -389,11 +391,11 @@ bool GCNBreakLoadClusterDepsImpl::runOnMachineBasicBlock(
bitset<AMDGPU::NUM_TARGET_REGS> SelfBannedRegs = BannedRegs | InsDefs;
if (!findReplaceRegisterOperand(VecLoadIns, OpNum, SelfBannedRegs))
break;
-
+
tie(InsDefs, InsUses) = getUsesAndDefsFor(VecLoadIns);
SelfConflicts = InsUses & InsDefs;
}
-
+
// Coda
UsedLoadDestPhysregs |= InsDefs;
UsedLoadSourcePhysregs |= InsUses;
``````````
</details>
https://github.com/llvm/llvm-project/pull/216343
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