[llvm] [SystemZ] Fix assertion failures during DAG combine (PR #215027)

[Ulrich Weigand via llvm-commits]

uweigand wrote:

Thanks for tracking this down!  I'm not sure introducing machine nodes at this point covers all cases, or is even necessary.  This routine is just an optimization that is likely irrelevant for f16 operations anyway.

Can you try instead simply checking whether the integer type is legal, and simply skipping the optimization if it is not?  I.e. add something like
```
   if (!isTypeLegal(VT))
     break;
```
after the line
```
        EVT VT = MVT::getIntegerVT(Op.getValueSizeInBits());
```
and to be safe also after the subsequent line
```
      EVT VT = MVT::getIntegerVT(ResVT.getSizeInBits());
```

I don't think this should have any adverse effect on generated code here.


https://github.com/llvm/llvm-project/pull/215027