[llvm] [AMDGPU] Check hasNoF16PseudoScalarTransInlineConstants in more places (PR #208459)
Frederik Harwath via llvm-commits
llvm-commits at lists.llvm.org
Tue Aug 18 09:51:36 PDT 2026
https://github.com/frederik-h updated https://github.com/llvm/llvm-project/pull/208459
>From 0bdeb65515f01fb253863104a4c1c47a73c363e0 Mon Sep 17 00:00:00 2001
From: Frederik Harwath <fharwath at amd.com>
Date: Thu, 9 Jul 2026 09:14:46 -0400
Subject: [PATCH 1/8] [AMDGPU] Check hasNoF16PseudoScalarTransInlineConstants
in more places
The isOperandLegal function already rejects inline constants
violating the restriction if the subtarget returns true
for hasNoF16PseudoScalarTransInlineConstants.
Adjust the behavior of the isInlineConstant overload with access to the MI
and reject violations in the machine verifier.
---
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 39 +++++++++++++++++++
llvm/lib/Target/AMDGPU/SIInstrInfo.h | 16 +-------
...ify-f16-pseudo-scalar-trans-inline-imm.mir | 26 +++++++++++++
3 files changed, 66 insertions(+), 15 deletions(-)
create mode 100644 llvm/test/CodeGen/AMDGPU/verify-f16-pseudo-scalar-trans-inline-imm.mir
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index e945db946c158..47c76d80fe11a 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -4735,6 +4735,30 @@ bool SIInstrInfo::isInlineConstant(int64_t Imm, uint8_t OperandType) const {
}
}
+bool SIInstrInfo::isInlineConstant(const MachineInstr &MI, unsigned OpIdx,
+ int64_t ImmVal) const {
+ if (OpIdx >= MI.getDesc().NumOperands)
+ return false;
+
+ if (isCopyInstr(MI)) {
+ unsigned Size = getOpSize(MI, OpIdx);
+ assert(Size == 8 || Size == 4);
+
+ uint8_t OpType = (Size == 8) ? AMDGPU::OPERAND_REG_IMM_INT64
+ : AMDGPU::OPERAND_REG_IMM_INT32;
+ return isInlineConstant(ImmVal, OpType);
+ }
+
+ if (!isInlineConstant(ImmVal, MI.getDesc().operands()[OpIdx].OperandType))
+ return false;
+
+ if (ST.hasNoF16PseudoScalarTransInlineConstants() &&
+ isF16PseudoScalarTrans(MI.getOpcode()))
+ return false;
+
+ return true;
+}
+
static bool compareMachineOp(const MachineOperand &Op0,
const MachineOperand &Op1) {
if (Op0.getType() != Op1.getType())
@@ -5497,6 +5521,21 @@ bool SIInstrInfo::verifyInstruction(const MachineInstr &MI,
}
}
+ if (ST.hasNoF16PseudoScalarTransInlineConstants() &&
+ isF16PseudoScalarTrans(Opcode)) {
+ for (int OpIdx : {Src0Idx, Src1Idx, Src2Idx}) {
+ if (OpIdx == -1)
+ continue;
+ const MachineOperand &MO = MI.getOperand(OpIdx);
+ if (MO.isImm() &&
+ isInlineConstant(MO.getImm(), Desc.operands()[OpIdx].OperandType)) {
+ ErrInfo =
+ "F16 pseudo scalar transcendental instruction uses inline constant";
+ return false;
+ }
+ }
+ }
+
// Special case for writelane - this can break the multiple constant bus rule,
// but still can't use more than one SGPR register
if (Desc.getOpcode() == AMDGPU::V_WRITELANE_B32) {
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
index 8e15b7b45b609..03a647545bc4c 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
@@ -1323,21 +1323,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
}
bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx,
- int64_t ImmVal) const {
- if (OpIdx >= MI.getDesc().NumOperands)
- return false;
-
- if (isCopyInstr(MI)) {
- unsigned Size = getOpSize(MI, OpIdx);
- assert(Size == 8 || Size == 4);
-
- uint8_t OpType = (Size == 8) ?
- AMDGPU::OPERAND_REG_IMM_INT64 : AMDGPU::OPERAND_REG_IMM_INT32;
- return isInlineConstant(ImmVal, OpType);
- }
-
- return isInlineConstant(ImmVal, MI.getDesc().operands()[OpIdx].OperandType);
- }
+ int64_t ImmVal) const;
bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx,
const MachineOperand &MO) const {
diff --git a/llvm/test/CodeGen/AMDGPU/verify-f16-pseudo-scalar-trans-inline-imm.mir b/llvm/test/CodeGen/AMDGPU/verify-f16-pseudo-scalar-trans-inline-imm.mir
new file mode 100644
index 0000000000000..a4528ea77973f
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/verify-f16-pseudo-scalar-trans-inline-imm.mir
@@ -0,0 +1,26 @@
+# RUN: not --crash llc -mtriple=amdgcn -mcpu=gfx1250 -run-pass machineverifier -filetype=null %s 2>&1 | FileCheck -implicit-check-not="Bad machine code" %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx942 -run-pass machineverifier -filetype=null %s
+
+# CHECK: *** Bad machine code: F16 pseudo scalar transcendental instruction uses inline constant ***
+# CHECK: %0:sgpr_32 = V_S_EXP_F16_e64 0, -1, 0, 0, implicit $mode, implicit $exec
+# CHECK: *** Bad machine code: F16 pseudo scalar transcendental instruction uses inline constant ***
+# CHECK: %1:sgpr_32 = V_S_LOG_F16_e64 0, 0, 0, 0, implicit $mode, implicit $exec
+# CHECK: *** Bad machine code: F16 pseudo scalar transcendental instruction uses inline constant ***
+# CHECK: %2:sgpr_32 = V_S_RCP_F16_e64 0, 1, 0, 0, implicit $mode, implicit $exec
+# CHECK: *** Bad machine code: F16 pseudo scalar transcendental instruction uses inline constant ***
+# CHECK: %3:sgpr_32 = V_S_RSQ_F16_e64 0, -16, 0, 0, implicit $mode, implicit $exec
+# CHECK: *** Bad machine code: F16 pseudo scalar transcendental instruction uses inline constant ***
+# CHECK: %4:sgpr_32 = V_S_SQRT_F16_e64 0, 64, 0, 0, implicit $mode, implicit $exec
+---
+name: f16_pseudo_scalar_trans_inline_imm
+tracksRegLiveness: true
+body: |
+ bb.0:
+ %0:sgpr_32 = V_S_EXP_F16_e64 0, -1, 0, 0, implicit $mode, implicit $exec
+ %1:sgpr_32 = V_S_LOG_F16_e64 0, 0, 0, 0, implicit $mode, implicit $exec
+ %2:sgpr_32 = V_S_RCP_F16_e64 0, 1, 0, 0, implicit $mode, implicit $exec
+ %3:sgpr_32 = V_S_RSQ_F16_e64 0, -16, 0, 0, implicit $mode, implicit $exec
+ %4:sgpr_32 = V_S_SQRT_F16_e64 0, 64, 0, 0, implicit $mode, implicit $exec
+ S_ENDPGM 0
+
+...
>From 59bd0af4a967f49aa53018959ca996a5ac229562 Mon Sep 17 00:00:00 2001
From: Frederik Harwath <fharwath at amd.com>
Date: Fri, 14 Aug 2026 03:52:18 -0400
Subject: [PATCH 2/8] Revert "[AMDGPU] Check
hasNoF16PseudoScalarTransInlineConstants in more places"
This reverts commit 0bdeb65515f01fb253863104a4c1c47a73c363e0.
---
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 39 -------------------
llvm/lib/Target/AMDGPU/SIInstrInfo.h | 16 +++++++-
...ify-f16-pseudo-scalar-trans-inline-imm.mir | 26 -------------
3 files changed, 15 insertions(+), 66 deletions(-)
delete mode 100644 llvm/test/CodeGen/AMDGPU/verify-f16-pseudo-scalar-trans-inline-imm.mir
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 47c76d80fe11a..e945db946c158 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -4735,30 +4735,6 @@ bool SIInstrInfo::isInlineConstant(int64_t Imm, uint8_t OperandType) const {
}
}
-bool SIInstrInfo::isInlineConstant(const MachineInstr &MI, unsigned OpIdx,
- int64_t ImmVal) const {
- if (OpIdx >= MI.getDesc().NumOperands)
- return false;
-
- if (isCopyInstr(MI)) {
- unsigned Size = getOpSize(MI, OpIdx);
- assert(Size == 8 || Size == 4);
-
- uint8_t OpType = (Size == 8) ? AMDGPU::OPERAND_REG_IMM_INT64
- : AMDGPU::OPERAND_REG_IMM_INT32;
- return isInlineConstant(ImmVal, OpType);
- }
-
- if (!isInlineConstant(ImmVal, MI.getDesc().operands()[OpIdx].OperandType))
- return false;
-
- if (ST.hasNoF16PseudoScalarTransInlineConstants() &&
- isF16PseudoScalarTrans(MI.getOpcode()))
- return false;
-
- return true;
-}
-
static bool compareMachineOp(const MachineOperand &Op0,
const MachineOperand &Op1) {
if (Op0.getType() != Op1.getType())
@@ -5521,21 +5497,6 @@ bool SIInstrInfo::verifyInstruction(const MachineInstr &MI,
}
}
- if (ST.hasNoF16PseudoScalarTransInlineConstants() &&
- isF16PseudoScalarTrans(Opcode)) {
- for (int OpIdx : {Src0Idx, Src1Idx, Src2Idx}) {
- if (OpIdx == -1)
- continue;
- const MachineOperand &MO = MI.getOperand(OpIdx);
- if (MO.isImm() &&
- isInlineConstant(MO.getImm(), Desc.operands()[OpIdx].OperandType)) {
- ErrInfo =
- "F16 pseudo scalar transcendental instruction uses inline constant";
- return false;
- }
- }
- }
-
// Special case for writelane - this can break the multiple constant bus rule,
// but still can't use more than one SGPR register
if (Desc.getOpcode() == AMDGPU::V_WRITELANE_B32) {
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
index 03a647545bc4c..8e15b7b45b609 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
@@ -1323,7 +1323,21 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
}
bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx,
- int64_t ImmVal) const;
+ int64_t ImmVal) const {
+ if (OpIdx >= MI.getDesc().NumOperands)
+ return false;
+
+ if (isCopyInstr(MI)) {
+ unsigned Size = getOpSize(MI, OpIdx);
+ assert(Size == 8 || Size == 4);
+
+ uint8_t OpType = (Size == 8) ?
+ AMDGPU::OPERAND_REG_IMM_INT64 : AMDGPU::OPERAND_REG_IMM_INT32;
+ return isInlineConstant(ImmVal, OpType);
+ }
+
+ return isInlineConstant(ImmVal, MI.getDesc().operands()[OpIdx].OperandType);
+ }
bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx,
const MachineOperand &MO) const {
diff --git a/llvm/test/CodeGen/AMDGPU/verify-f16-pseudo-scalar-trans-inline-imm.mir b/llvm/test/CodeGen/AMDGPU/verify-f16-pseudo-scalar-trans-inline-imm.mir
deleted file mode 100644
index a4528ea77973f..0000000000000
--- a/llvm/test/CodeGen/AMDGPU/verify-f16-pseudo-scalar-trans-inline-imm.mir
+++ /dev/null
@@ -1,26 +0,0 @@
-# RUN: not --crash llc -mtriple=amdgcn -mcpu=gfx1250 -run-pass machineverifier -filetype=null %s 2>&1 | FileCheck -implicit-check-not="Bad machine code" %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx942 -run-pass machineverifier -filetype=null %s
-
-# CHECK: *** Bad machine code: F16 pseudo scalar transcendental instruction uses inline constant ***
-# CHECK: %0:sgpr_32 = V_S_EXP_F16_e64 0, -1, 0, 0, implicit $mode, implicit $exec
-# CHECK: *** Bad machine code: F16 pseudo scalar transcendental instruction uses inline constant ***
-# CHECK: %1:sgpr_32 = V_S_LOG_F16_e64 0, 0, 0, 0, implicit $mode, implicit $exec
-# CHECK: *** Bad machine code: F16 pseudo scalar transcendental instruction uses inline constant ***
-# CHECK: %2:sgpr_32 = V_S_RCP_F16_e64 0, 1, 0, 0, implicit $mode, implicit $exec
-# CHECK: *** Bad machine code: F16 pseudo scalar transcendental instruction uses inline constant ***
-# CHECK: %3:sgpr_32 = V_S_RSQ_F16_e64 0, -16, 0, 0, implicit $mode, implicit $exec
-# CHECK: *** Bad machine code: F16 pseudo scalar transcendental instruction uses inline constant ***
-# CHECK: %4:sgpr_32 = V_S_SQRT_F16_e64 0, 64, 0, 0, implicit $mode, implicit $exec
----
-name: f16_pseudo_scalar_trans_inline_imm
-tracksRegLiveness: true
-body: |
- bb.0:
- %0:sgpr_32 = V_S_EXP_F16_e64 0, -1, 0, 0, implicit $mode, implicit $exec
- %1:sgpr_32 = V_S_LOG_F16_e64 0, 0, 0, 0, implicit $mode, implicit $exec
- %2:sgpr_32 = V_S_RCP_F16_e64 0, 1, 0, 0, implicit $mode, implicit $exec
- %3:sgpr_32 = V_S_RSQ_F16_e64 0, -16, 0, 0, implicit $mode, implicit $exec
- %4:sgpr_32 = V_S_SQRT_F16_e64 0, 64, 0, 0, implicit $mode, implicit $exec
- S_ENDPGM 0
-
-...
>From a2eed7fabbada1d042169684a03fde1aae429d15 Mon Sep 17 00:00:00 2001
From: Frederik Harwath <fharwath at amd.com>
Date: Fri, 14 Aug 2026 05:39:49 -0400
Subject: [PATCH 3/8] Add gfx1250 run line to pseudo-scalar-transcendental.mir
The "feature" being tested is also enabled for gfx1250
and hence the test should cover it.
---
llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.mir | 2 ++
1 file changed, 2 insertions(+)
diff --git a/llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.mir b/llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.mir
index 19681a4346a13..ba3182e96d45a 100644
--- a/llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.mir
+++ b/llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.mir
@@ -1,6 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1170 -run-pass=si-fold-operands -verify-machineinstrs -o - %s | FileCheck --check-prefixes=GCN %s
# RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 -run-pass=si-fold-operands -verify-machineinstrs -o - %s | FileCheck --check-prefixes=GCN %s
+# RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1250 -run-pass=si-fold-operands -verify-machineinstrs -o - %s | FileCheck --check-prefixes=GCN %s
+
# Do not use inline constants for f16 pseudo scalar transcendentals.
# But allow literal constants.
>From 7b7d3da210ccefa5642c4ce3e340040fe48e07ab Mon Sep 17 00:00:00 2001
From: Frederik Harwath <fharwath at amd.com>
Date: Fri, 14 Aug 2026 05:17:11 -0400
Subject: [PATCH 4/8] Remove hasNoF16PseudoScalarTransInlineConstants use
The use of inline constants should be prevented by using a new operand
type. Remove the current check.
Now the folding happens for inline constants and literals. This is
fine since a follow-up change to the operand type for those
instructions will ensure that the inline constant encoding will not be
emitted even if the fold happens here.
---
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 3 ---
.../AMDGPU/pseudo-scalar-transcendental.mir | 15 +++++----------
2 files changed, 5 insertions(+), 13 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index e945db946c158..801bf3c66882f 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -6482,9 +6482,6 @@ bool SIInstrInfo::isOperandLegal(const MachineInstr &MI, unsigned OpIdx,
if (Op.isFI())
return false;
}
- } else if (IsInlineConst && ST.hasNoF16PseudoScalarTransInlineConstants() &&
- isF16PseudoScalarTrans(MI.getOpcode())) {
- return false;
}
if (MO->isReg()) {
diff --git a/llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.mir b/llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.mir
index ba3182e96d45a..2923065ddaf84 100644
--- a/llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.mir
+++ b/llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.mir
@@ -13,8 +13,7 @@ tracksRegLiveness: true
body: |
bb.0:
; GCN-LABEL: name: exp_f16_imm
- ; GCN: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 15360
- ; GCN-NEXT: [[V_S_EXP_F16_e64_:%[0-9]+]]:sgpr_32 = V_S_EXP_F16_e64 1, [[S_MOV_B32_]], 0, 0, implicit $mode, implicit $exec
+ ; GCN: [[V_S_EXP_F16_e64_:%[0-9]+]]:sgpr_32 = V_S_EXP_F16_e64 1, 15360, 0, 0, implicit $mode, implicit $exec
%0:sgpr_32 = S_MOV_B32 15360
%1:sgpr_32 = V_S_EXP_F16_e64 1, %0:sgpr_32, 0, 0, implicit $mode, implicit $exec
...
@@ -36,8 +35,7 @@ tracksRegLiveness: true
body: |
bb.0:
; GCN-LABEL: name: log_f16_imm
- ; GCN: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 15360
- ; GCN-NEXT: [[V_S_LOG_F16_e64_:%[0-9]+]]:sgpr_32 = V_S_LOG_F16_e64 1, [[S_MOV_B32_]], 0, 0, implicit $mode, implicit $exec
+ ; GCN: [[V_S_LOG_F16_e64_:%[0-9]+]]:sgpr_32 = V_S_LOG_F16_e64 1, 15360, 0, 0, implicit $mode, implicit $exec
%0:sgpr_32 = S_MOV_B32 15360
%1:sgpr_32 = V_S_LOG_F16_e64 1, %0:sgpr_32, 0, 0, implicit $mode, implicit $exec
...
@@ -59,8 +57,7 @@ tracksRegLiveness: true
body: |
bb.0:
; GCN-LABEL: name: rcp_f16_imm
- ; GCN: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 15360
- ; GCN-NEXT: [[V_S_RCP_F16_e64_:%[0-9]+]]:sgpr_32 = V_S_RCP_F16_e64 1, [[S_MOV_B32_]], 0, 0, implicit $mode, implicit $exec
+ ; GCN: [[V_S_RCP_F16_e64_:%[0-9]+]]:sgpr_32 = V_S_RCP_F16_e64 1, 15360, 0, 0, implicit $mode, implicit $exec
%0:sgpr_32 = S_MOV_B32 15360
%1:sgpr_32 = V_S_RCP_F16_e64 1, %0:sgpr_32, 0, 0, implicit $mode, implicit $exec
...
@@ -82,8 +79,7 @@ tracksRegLiveness: true
body: |
bb.0:
; GCN-LABEL: name: rsq_f16_imm
- ; GCN: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 15360
- ; GCN-NEXT: [[V_S_RSQ_F16_e64_:%[0-9]+]]:sgpr_32 = V_S_RSQ_F16_e64 1, [[S_MOV_B32_]], 0, 0, implicit $mode, implicit $exec
+ ; GCN: [[V_S_RSQ_F16_e64_:%[0-9]+]]:sgpr_32 = V_S_RSQ_F16_e64 1, 15360, 0, 0, implicit $mode, implicit $exec
%0:sgpr_32 = S_MOV_B32 15360
%1:sgpr_32 = V_S_RSQ_F16_e64 1, %0:sgpr_32, 0, 0, implicit $mode, implicit $exec
...
@@ -105,8 +101,7 @@ tracksRegLiveness: true
body: |
bb.0:
; GCN-LABEL: name: sqrt_f16_imm
- ; GCN: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 15360
- ; GCN-NEXT: [[V_S_SQRT_F16_e64_:%[0-9]+]]:sgpr_32 = V_S_SQRT_F16_e64 1, [[S_MOV_B32_]], 0, 0, implicit $mode, implicit $exec
+ ; GCN: [[V_S_SQRT_F16_e64_:%[0-9]+]]:sgpr_32 = V_S_SQRT_F16_e64 1, 15360, 0, 0, implicit $mode, implicit $exec
%0:sgpr_32 = S_MOV_B32 15360
%1:sgpr_32 = V_S_SQRT_F16_e64 1, %0:sgpr_32, 0, 0, implicit $mode, implicit $exec
...
>From 367d24acf6d22d2d0aa1486e0b948ae0c0a89b53 Mon Sep 17 00:00:00 2001
From: Frederik Harwath <fharwath at amd.com>
Date: Fri, 14 Aug 2026 07:14:04 -0400
Subject: [PATCH 5/8] Change pseudo-scalar-transcendental.mir to compile to
assembly
The existing test did only test that the FOLDING for inline constants
was prevented by checking the MIR after si-fold-operands. Completely
preventing the folding is not necessary. We aim to allow the
folding (current state after removing the check that prevented it),
but make sure that the instruction will be emitted without using the
literal encoding. This cannot be verified at the MIR level.
Remove the gfx1170 run line since the compilation crashes in
getInstSizeInBytes. The instructions are not properly defined for
gfx1170 and it seems questionable that they should be (follow-up issue).
---
.../AMDGPU/pseudo-scalar-transcendental.mir | 243 ++++++++++++++++--
1 file changed, 218 insertions(+), 25 deletions(-)
diff --git a/llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.mir b/llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.mir
index 2923065ddaf84..90adf3f95a379 100644
--- a/llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.mir
+++ b/llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.mir
@@ -1,21 +1,214 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
-# RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1170 -run-pass=si-fold-operands -verify-machineinstrs -o - %s | FileCheck --check-prefixes=GCN %s
-# RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 -run-pass=si-fold-operands -verify-machineinstrs -o - %s | FileCheck --check-prefixes=GCN %s
-# RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1250 -run-pass=si-fold-operands -verify-machineinstrs -o - %s | FileCheck --check-prefixes=GCN %s
-
+# NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -mtriple=amdgpu12.00-amd-amdpal -x mir --show-mc-encoding < %s | FileCheck --check-prefixes=GFX12 %s
+# RUN: llc -mtriple=amdgpu12.50-amd-amdpal -x mir --show-mc-encoding < %s | FileCheck --check-prefixes=GFX1250 %s
# Do not use inline constants for f16 pseudo scalar transcendentals.
# But allow literal constants.
+# FIXME: Inline constants are used on the _imm test cases (see shorter encoding with 0xf2 in byte 4)
+
+--- |
+ define void @exp_f16_imm() {
+ ; GFX12-LABEL: exp_f16_imm:
+ ; GFX12: ; %bb.0:
+ ; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 ; encoding: [0x00,0x00,0xc8,0xbf]
+ ; GFX12-NEXT: s_wait_expcnt 0x0 ; encoding: [0x00,0x00,0xc4,0xbf]
+ ; GFX12-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
+ ; GFX12-NEXT: s_wait_bvhcnt 0x0 ; encoding: [0x00,0x00,0xc3,0xbf]
+ ; GFX12-NEXT: s_wait_kmcnt 0x0 ; encoding: [0x00,0x00,0xc7,0xbf]
+ ; GFX12-NEXT: v_s_exp_f16 s0, neg(1.0) ; encoding: [0x00,0x00,0x81,0xd6,0xf2,0x00,0x01,0x22]
+ ; GFX12-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
+ ;
+ ; GFX1250-LABEL: exp_f16_imm:
+ ; GFX1250: ; %bb.0:
+ ; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 ; encoding: [0x00,0x00,0xc8,0xbf]
+ ; GFX1250-NEXT: s_wait_kmcnt 0x0 ; encoding: [0x00,0x00,0xc7,0xbf]
+ ; GFX1250-NEXT: v_s_exp_f16 s0, neg(1.0) ; encoding: [0x00,0x00,0x81,0xd6,0xf2,0x00,0x01,0x22]
+ ; GFX1250-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
+ ret void
+ }
+ define void @exp_f16_literal() {
+ ; GFX12-LABEL: exp_f16_literal:
+ ; GFX12: ; %bb.0:
+ ; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 ; encoding: [0x00,0x00,0xc8,0xbf]
+ ; GFX12-NEXT: s_wait_expcnt 0x0 ; encoding: [0x00,0x00,0xc4,0xbf]
+ ; GFX12-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
+ ; GFX12-NEXT: s_wait_bvhcnt 0x0 ; encoding: [0x00,0x00,0xc3,0xbf]
+ ; GFX12-NEXT: s_wait_kmcnt 0x0 ; encoding: [0x00,0x00,0xc7,0xbf]
+ ; GFX12-NEXT: v_s_exp_f16 s0, neg(0x4240) ; encoding: [0x00,0x00,0x81,0xd6,0xff,0x00,0x01,0x22,0x40,0x42,0x00,0x00]
+ ; GFX12-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
+ ;
+ ; GFX1250-LABEL: exp_f16_literal:
+ ; GFX1250: ; %bb.0:
+ ; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 ; encoding: [0x00,0x00,0xc8,0xbf]
+ ; GFX1250-NEXT: s_wait_kmcnt 0x0 ; encoding: [0x00,0x00,0xc7,0xbf]
+ ; GFX1250-NEXT: v_s_exp_f16 s0, neg(0x4240) ; encoding: [0x00,0x00,0x81,0xd6,0xff,0x00,0x01,0x22,0x40,0x42,0x00,0x00]
+ ; GFX1250-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
+ ret void
+ }
+ define void @log_f16_imm() {
+ ; GFX12-LABEL: log_f16_imm:
+ ; GFX12: ; %bb.0:
+ ; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 ; encoding: [0x00,0x00,0xc8,0xbf]
+ ; GFX12-NEXT: s_wait_expcnt 0x0 ; encoding: [0x00,0x00,0xc4,0xbf]
+ ; GFX12-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
+ ; GFX12-NEXT: s_wait_bvhcnt 0x0 ; encoding: [0x00,0x00,0xc3,0xbf]
+ ; GFX12-NEXT: s_wait_kmcnt 0x0 ; encoding: [0x00,0x00,0xc7,0xbf]
+ ; GFX12-NEXT: v_s_log_f16 s0, neg(1.0) ; encoding: [0x00,0x00,0x83,0xd6,0xf2,0x00,0x01,0x22]
+ ; GFX12-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
+ ;
+ ; GFX1250-LABEL: log_f16_imm:
+ ; GFX1250: ; %bb.0:
+ ; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 ; encoding: [0x00,0x00,0xc8,0xbf]
+ ; GFX1250-NEXT: s_wait_kmcnt 0x0 ; encoding: [0x00,0x00,0xc7,0xbf]
+ ; GFX1250-NEXT: v_s_log_f16 s0, neg(1.0) ; encoding: [0x00,0x00,0x83,0xd6,0xf2,0x00,0x01,0x22]
+ ; GFX1250-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
+ ret void
+ }
+ define void @log_f16_literal() {
+ ; GFX12-LABEL: log_f16_literal:
+ ; GFX12: ; %bb.0:
+ ; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 ; encoding: [0x00,0x00,0xc8,0xbf]
+ ; GFX12-NEXT: s_wait_expcnt 0x0 ; encoding: [0x00,0x00,0xc4,0xbf]
+ ; GFX12-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
+ ; GFX12-NEXT: s_wait_bvhcnt 0x0 ; encoding: [0x00,0x00,0xc3,0xbf]
+ ; GFX12-NEXT: s_wait_kmcnt 0x0 ; encoding: [0x00,0x00,0xc7,0xbf]
+ ; GFX12-NEXT: v_s_log_f16 s0, neg(0x4240) ; encoding: [0x00,0x00,0x83,0xd6,0xff,0x00,0x01,0x22,0x40,0x42,0x00,0x00]
+ ; GFX12-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
+ ;
+ ; GFX1250-LABEL: log_f16_literal:
+ ; GFX1250: ; %bb.0:
+ ; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 ; encoding: [0x00,0x00,0xc8,0xbf]
+ ; GFX1250-NEXT: s_wait_kmcnt 0x0 ; encoding: [0x00,0x00,0xc7,0xbf]
+ ; GFX1250-NEXT: v_s_log_f16 s0, neg(0x4240) ; encoding: [0x00,0x00,0x83,0xd6,0xff,0x00,0x01,0x22,0x40,0x42,0x00,0x00]
+ ; GFX1250-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
+ ret void
+ }
+ define void @rcp_f16_imm() {
+ ; GFX12-LABEL: rcp_f16_imm:
+ ; GFX12: ; %bb.0:
+ ; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 ; encoding: [0x00,0x00,0xc8,0xbf]
+ ; GFX12-NEXT: s_wait_expcnt 0x0 ; encoding: [0x00,0x00,0xc4,0xbf]
+ ; GFX12-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
+ ; GFX12-NEXT: s_wait_bvhcnt 0x0 ; encoding: [0x00,0x00,0xc3,0xbf]
+ ; GFX12-NEXT: s_wait_kmcnt 0x0 ; encoding: [0x00,0x00,0xc7,0xbf]
+ ; GFX12-NEXT: v_s_rcp_f16 s0, neg(1.0) ; encoding: [0x00,0x00,0x85,0xd6,0xf2,0x00,0x01,0x22]
+ ; GFX12-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
+ ;
+ ; GFX1250-LABEL: rcp_f16_imm:
+ ; GFX1250: ; %bb.0:
+ ; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 ; encoding: [0x00,0x00,0xc8,0xbf]
+ ; GFX1250-NEXT: s_wait_kmcnt 0x0 ; encoding: [0x00,0x00,0xc7,0xbf]
+ ; GFX1250-NEXT: v_s_rcp_f16 s0, neg(1.0) ; encoding: [0x00,0x00,0x85,0xd6,0xf2,0x00,0x01,0x22]
+ ; GFX1250-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
+ ret void
+ }
+ define void @rcp_f16_literal() {
+ ; GFX12-LABEL: rcp_f16_literal:
+ ; GFX12: ; %bb.0:
+ ; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 ; encoding: [0x00,0x00,0xc8,0xbf]
+ ; GFX12-NEXT: s_wait_expcnt 0x0 ; encoding: [0x00,0x00,0xc4,0xbf]
+ ; GFX12-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
+ ; GFX12-NEXT: s_wait_bvhcnt 0x0 ; encoding: [0x00,0x00,0xc3,0xbf]
+ ; GFX12-NEXT: s_wait_kmcnt 0x0 ; encoding: [0x00,0x00,0xc7,0xbf]
+ ; GFX12-NEXT: v_s_rcp_f16 s0, neg(0x4240) ; encoding: [0x00,0x00,0x85,0xd6,0xff,0x00,0x01,0x22,0x40,0x42,0x00,0x00]
+ ; GFX12-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
+ ;
+ ; GFX1250-LABEL: rcp_f16_literal:
+ ; GFX1250: ; %bb.0:
+ ; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 ; encoding: [0x00,0x00,0xc8,0xbf]
+ ; GFX1250-NEXT: s_wait_kmcnt 0x0 ; encoding: [0x00,0x00,0xc7,0xbf]
+ ; GFX1250-NEXT: v_s_rcp_f16 s0, neg(0x4240) ; encoding: [0x00,0x00,0x85,0xd6,0xff,0x00,0x01,0x22,0x40,0x42,0x00,0x00]
+ ; GFX1250-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
+ ret void
+ }
+ define void @rsq_f16_imm() {
+ ; GFX12-LABEL: rsq_f16_imm:
+ ; GFX12: ; %bb.0:
+ ; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 ; encoding: [0x00,0x00,0xc8,0xbf]
+ ; GFX12-NEXT: s_wait_expcnt 0x0 ; encoding: [0x00,0x00,0xc4,0xbf]
+ ; GFX12-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
+ ; GFX12-NEXT: s_wait_bvhcnt 0x0 ; encoding: [0x00,0x00,0xc3,0xbf]
+ ; GFX12-NEXT: s_wait_kmcnt 0x0 ; encoding: [0x00,0x00,0xc7,0xbf]
+ ; GFX12-NEXT: v_s_rsq_f16 s0, neg(1.0) ; encoding: [0x00,0x00,0x87,0xd6,0xf2,0x00,0x01,0x22]
+ ; GFX12-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
+ ;
+ ; GFX1250-LABEL: rsq_f16_imm:
+ ; GFX1250: ; %bb.0:
+ ; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 ; encoding: [0x00,0x00,0xc8,0xbf]
+ ; GFX1250-NEXT: s_wait_kmcnt 0x0 ; encoding: [0x00,0x00,0xc7,0xbf]
+ ; GFX1250-NEXT: v_s_rsq_f16 s0, neg(1.0) ; encoding: [0x00,0x00,0x87,0xd6,0xf2,0x00,0x01,0x22]
+ ; GFX1250-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
+ ret void
+ }
+ define void @rsq_f16_literal() {
+ ; GFX12-LABEL: rsq_f16_literal:
+ ; GFX12: ; %bb.0:
+ ; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 ; encoding: [0x00,0x00,0xc8,0xbf]
+ ; GFX12-NEXT: s_wait_expcnt 0x0 ; encoding: [0x00,0x00,0xc4,0xbf]
+ ; GFX12-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
+ ; GFX12-NEXT: s_wait_bvhcnt 0x0 ; encoding: [0x00,0x00,0xc3,0xbf]
+ ; GFX12-NEXT: s_wait_kmcnt 0x0 ; encoding: [0x00,0x00,0xc7,0xbf]
+ ; GFX12-NEXT: v_s_rsq_f16 s0, neg(0x4240) ; encoding: [0x00,0x00,0x87,0xd6,0xff,0x00,0x01,0x22,0x40,0x42,0x00,0x00]
+ ; GFX12-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
+ ;
+ ; GFX1250-LABEL: rsq_f16_literal:
+ ; GFX1250: ; %bb.0:
+ ; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 ; encoding: [0x00,0x00,0xc8,0xbf]
+ ; GFX1250-NEXT: s_wait_kmcnt 0x0 ; encoding: [0x00,0x00,0xc7,0xbf]
+ ; GFX1250-NEXT: v_s_rsq_f16 s0, neg(0x4240) ; encoding: [0x00,0x00,0x87,0xd6,0xff,0x00,0x01,0x22,0x40,0x42,0x00,0x00]
+ ; GFX1250-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
+ ret void
+ }
+ define void @sqrt_f16_imm() {
+ ; GFX12-LABEL: sqrt_f16_imm:
+ ; GFX12: ; %bb.0:
+ ; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 ; encoding: [0x00,0x00,0xc8,0xbf]
+ ; GFX12-NEXT: s_wait_expcnt 0x0 ; encoding: [0x00,0x00,0xc4,0xbf]
+ ; GFX12-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
+ ; GFX12-NEXT: s_wait_bvhcnt 0x0 ; encoding: [0x00,0x00,0xc3,0xbf]
+ ; GFX12-NEXT: s_wait_kmcnt 0x0 ; encoding: [0x00,0x00,0xc7,0xbf]
+ ; GFX12-NEXT: v_s_sqrt_f16 s0, neg(1.0) ; encoding: [0x00,0x00,0x89,0xd6,0xf2,0x00,0x01,0x22]
+ ; GFX12-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
+ ;
+ ; GFX1250-LABEL: sqrt_f16_imm:
+ ; GFX1250: ; %bb.0:
+ ; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 ; encoding: [0x00,0x00,0xc8,0xbf]
+ ; GFX1250-NEXT: s_wait_kmcnt 0x0 ; encoding: [0x00,0x00,0xc7,0xbf]
+ ; GFX1250-NEXT: v_s_sqrt_f16 s0, neg(1.0) ; encoding: [0x00,0x00,0x89,0xd6,0xf2,0x00,0x01,0x22]
+ ; GFX1250-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
+ ret void
+ }
+ define void @sqrt_f16_literal() {
+ ; GFX12-LABEL: sqrt_f16_literal:
+ ; GFX12: ; %bb.0:
+ ; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 ; encoding: [0x00,0x00,0xc8,0xbf]
+ ; GFX12-NEXT: s_wait_expcnt 0x0 ; encoding: [0x00,0x00,0xc4,0xbf]
+ ; GFX12-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
+ ; GFX12-NEXT: s_wait_bvhcnt 0x0 ; encoding: [0x00,0x00,0xc3,0xbf]
+ ; GFX12-NEXT: s_wait_kmcnt 0x0 ; encoding: [0x00,0x00,0xc7,0xbf]
+ ; GFX12-NEXT: v_s_sqrt_f16 s0, neg(0x4240) ; encoding: [0x00,0x00,0x89,0xd6,0xff,0x00,0x01,0x22,0x40,0x42,0x00,0x00]
+ ; GFX12-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
+ ;
+ ; GFX1250-LABEL: sqrt_f16_literal:
+ ; GFX1250: ; %bb.0:
+ ; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 ; encoding: [0x00,0x00,0xc8,0xbf]
+ ; GFX1250-NEXT: s_wait_kmcnt 0x0 ; encoding: [0x00,0x00,0xc7,0xbf]
+ ; GFX1250-NEXT: v_s_sqrt_f16 s0, neg(0x4240) ; encoding: [0x00,0x00,0x89,0xd6,0xff,0x00,0x01,0x22,0x40,0x42,0x00,0x00]
+ ; GFX1250-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
+ ret void
+ }
+...
+
---
name: exp_f16_imm
tracksRegLiveness: true
body: |
bb.0:
- ; GCN-LABEL: name: exp_f16_imm
- ; GCN: [[V_S_EXP_F16_e64_:%[0-9]+]]:sgpr_32 = V_S_EXP_F16_e64 1, 15360, 0, 0, implicit $mode, implicit $exec
%0:sgpr_32 = S_MOV_B32 15360
%1:sgpr_32 = V_S_EXP_F16_e64 1, %0:sgpr_32, 0, 0, implicit $mode, implicit $exec
+ $sgpr0 = COPY %1
+ S_ENDPGM 0, implicit $sgpr0
...
---
@@ -23,10 +216,10 @@ name: exp_f16_literal
tracksRegLiveness: true
body: |
bb.0:
- ; GCN-LABEL: name: exp_f16_literal
- ; GCN: [[V_S_EXP_F16_e64_:%[0-9]+]]:sgpr_32 = V_S_EXP_F16_e64 1, 16960, 0, 0, implicit $mode, implicit $exec
%0:sgpr_32 = S_MOV_B32 16960
%1:sgpr_32 = V_S_EXP_F16_e64 1, %0:sgpr_32, 0, 0, implicit $mode, implicit $exec
+ $sgpr0 = COPY %1
+ S_ENDPGM 0, implicit $sgpr0
...
---
@@ -34,10 +227,10 @@ name: log_f16_imm
tracksRegLiveness: true
body: |
bb.0:
- ; GCN-LABEL: name: log_f16_imm
- ; GCN: [[V_S_LOG_F16_e64_:%[0-9]+]]:sgpr_32 = V_S_LOG_F16_e64 1, 15360, 0, 0, implicit $mode, implicit $exec
%0:sgpr_32 = S_MOV_B32 15360
%1:sgpr_32 = V_S_LOG_F16_e64 1, %0:sgpr_32, 0, 0, implicit $mode, implicit $exec
+ $sgpr0 = COPY %1
+ S_ENDPGM 0, implicit $sgpr0
...
---
@@ -45,10 +238,10 @@ name: log_f16_literal
tracksRegLiveness: true
body: |
bb.0:
- ; GCN-LABEL: name: log_f16_literal
- ; GCN: [[V_S_LOG_F16_e64_:%[0-9]+]]:sgpr_32 = V_S_LOG_F16_e64 1, 16960, 0, 0, implicit $mode, implicit $exec
%0:sgpr_32 = S_MOV_B32 16960
%1:sgpr_32 = V_S_LOG_F16_e64 1, %0:sgpr_32, 0, 0, implicit $mode, implicit $exec
+ $sgpr0 = COPY %1
+ S_ENDPGM 0, implicit $sgpr0
...
---
@@ -56,10 +249,10 @@ name: rcp_f16_imm
tracksRegLiveness: true
body: |
bb.0:
- ; GCN-LABEL: name: rcp_f16_imm
- ; GCN: [[V_S_RCP_F16_e64_:%[0-9]+]]:sgpr_32 = V_S_RCP_F16_e64 1, 15360, 0, 0, implicit $mode, implicit $exec
%0:sgpr_32 = S_MOV_B32 15360
%1:sgpr_32 = V_S_RCP_F16_e64 1, %0:sgpr_32, 0, 0, implicit $mode, implicit $exec
+ $sgpr0 = COPY %1
+ S_ENDPGM 0, implicit $sgpr0
...
---
@@ -67,10 +260,10 @@ name: rcp_f16_literal
tracksRegLiveness: true
body: |
bb.0:
- ; GCN-LABEL: name: rcp_f16_literal
- ; GCN: [[V_S_RCP_F16_e64_:%[0-9]+]]:sgpr_32 = V_S_RCP_F16_e64 1, 16960, 0, 0, implicit $mode, implicit $exec
%0:sgpr_32 = S_MOV_B32 16960
%1:sgpr_32 = V_S_RCP_F16_e64 1, %0:sgpr_32, 0, 0, implicit $mode, implicit $exec
+ $sgpr0 = COPY %1
+ S_ENDPGM 0, implicit $sgpr0
...
---
@@ -78,10 +271,10 @@ name: rsq_f16_imm
tracksRegLiveness: true
body: |
bb.0:
- ; GCN-LABEL: name: rsq_f16_imm
- ; GCN: [[V_S_RSQ_F16_e64_:%[0-9]+]]:sgpr_32 = V_S_RSQ_F16_e64 1, 15360, 0, 0, implicit $mode, implicit $exec
%0:sgpr_32 = S_MOV_B32 15360
%1:sgpr_32 = V_S_RSQ_F16_e64 1, %0:sgpr_32, 0, 0, implicit $mode, implicit $exec
+ $sgpr0 = COPY %1
+ S_ENDPGM 0, implicit $sgpr0
...
---
@@ -89,10 +282,10 @@ name: rsq_f16_literal
tracksRegLiveness: true
body: |
bb.0:
- ; GCN-LABEL: name: rsq_f16_literal
- ; GCN: [[V_S_RSQ_F16_e64_:%[0-9]+]]:sgpr_32 = V_S_RSQ_F16_e64 1, 16960, 0, 0, implicit $mode, implicit $exec
%0:sgpr_32 = S_MOV_B32 16960
%1:sgpr_32 = V_S_RSQ_F16_e64 1, %0:sgpr_32, 0, 0, implicit $mode, implicit $exec
+ $sgpr0 = COPY %1
+ S_ENDPGM 0, implicit $sgpr0
...
---
@@ -100,10 +293,10 @@ name: sqrt_f16_imm
tracksRegLiveness: true
body: |
bb.0:
- ; GCN-LABEL: name: sqrt_f16_imm
- ; GCN: [[V_S_SQRT_F16_e64_:%[0-9]+]]:sgpr_32 = V_S_SQRT_F16_e64 1, 15360, 0, 0, implicit $mode, implicit $exec
%0:sgpr_32 = S_MOV_B32 15360
%1:sgpr_32 = V_S_SQRT_F16_e64 1, %0:sgpr_32, 0, 0, implicit $mode, implicit $exec
+ $sgpr0 = COPY %1
+ S_ENDPGM 0, implicit $sgpr0
...
---
@@ -111,8 +304,8 @@ name: sqrt_f16_literal
tracksRegLiveness: true
body: |
bb.0:
- ; GCN-LABEL: name: sqrt_f16_literal
- ; GCN: [[V_S_SQRT_F16_e64_:%[0-9]+]]:sgpr_32 = V_S_SQRT_F16_e64 1, 16960, 0, 0, implicit $mode, implicit $exec
%0:sgpr_32 = S_MOV_B32 16960
%1:sgpr_32 = V_S_SQRT_F16_e64 1, %0:sgpr_32, 0, 0, implicit $mode, implicit $exec
+ $sgpr0 = COPY %1
+ S_ENDPGM 0, implicit $sgpr0
...
>From f549b331d0cfac03793bc8b4d00ed8a21a91c23c Mon Sep 17 00:00:00 2001
From: Frederik Harwath <fharwath at amd.com>
Date: Fri, 14 Aug 2026 03:42:54 -0400
Subject: [PATCH 6/8] [AMDGPU] Use new operand type to prevent inline constants
on gfx12 F16 pseudo scalar trans instructions
---
llvm/lib/Target/AMDGPU/AMDGPU.td | 5 ++-
.../AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 8 +++-
.../Disassembler/AMDGPUDisassembler.cpp | 6 +++
.../AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp | 1 +
.../MCTargetDesc/AMDGPUMCCodeEmitter.cpp | 3 ++
llvm/lib/Target/AMDGPU/SIDefines.h | 1 +
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 4 +-
llvm/lib/Target/AMDGPU/SIInstrInfo.h | 8 ----
llvm/lib/Target/AMDGPU/SIRegisterInfo.td | 1 +
.../Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp | 2 +
llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h | 1 +
llvm/lib/Target/AMDGPU/VOP3Instructions.td | 45 ++++++++++++++-----
.../AMDGPU/pseudo-scalar-transcendental.mir | 24 +++++-----
llvm/test/MC/AMDGPU/gfx12_asm_vop3-fake16.s | 20 ++++-----
llvm/test/MC/AMDGPU/gfx12_asm_vop3.s | 20 ++++-----
.../Disassembler/AMDGPU/gfx12_dasm_vop3.txt | 20 ++++-----
16 files changed, 104 insertions(+), 65 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.td b/llvm/lib/Target/AMDGPU/AMDGPU.td
index a1298e5969ea0..d5e71db74a736 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.td
@@ -1140,9 +1140,12 @@ defm PseudoScalarTrans : AMDGPUSubtargetFeature<"pseudo-scalar-trans",
defm NoF16PseudoScalarTransInlineConstants : AMDGPUSubtargetFeature<"no-f16-pseudo-scalar-trans-inline-constants",
"Inline constants are not supported for F16 pseudo scalar transcendentals",
- /*GenPredicate=*/0
+ /*GenPredicate=*/1
>;
+def HasF16PseudoScalarTransWithInlineConstants :
+ Predicate<"Subtarget->hasPseudoScalarTrans() && !Subtarget->hasNoF16PseudoScalarTransInlineConstants()">;
+
defm RestrictedSOffset : AMDGPUSubtargetFeature<"restricted-soffset",
"Has restricted SOffset (immediate not supported)."
>;
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index 9c0a5f2ec2773..7b6ffc94431bd 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -499,6 +499,8 @@ class AMDGPUOperand : public MCParsedAsmOperand {
bool isSSrc_f16() const { return isSCSrcB16() || isLiteralImm(MVT::f16); }
+ bool isSSrc_NoInline_f16() const { return isSSrc_f16(); }
+
bool isSSrcV2F16() const {
llvm_unreachable("cannot happen");
return isSSrc_f16();
@@ -2095,6 +2097,7 @@ static const fltSemantics *getOpFltSemantics(uint8_t OperandType) {
case AMDGPU::OPERAND_KIMM64:
return &APFloat::IEEEdouble();
case AMDGPU::OPERAND_REG_IMM_FP16:
+ case AMDGPU::OPERAND_REG_IMM_NOINLINE_FP16:
case AMDGPU::OPERAND_REG_INLINE_C_FP16:
case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:
case AMDGPU::OPERAND_REG_IMM_V2FP16:
@@ -2489,6 +2492,7 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyMo
case AMDGPU::OPERAND_REG_INLINE_AC_FP32:
case AMDGPU::OPERAND_REG_IMM_INT16:
case AMDGPU::OPERAND_REG_IMM_FP16:
+ case AMDGPU::OPERAND_REG_IMM_NOINLINE_FP16:
case AMDGPU::OPERAND_REG_INLINE_C_INT16:
case AMDGPU::OPERAND_REG_INLINE_C_FP16:
case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:
@@ -2596,6 +2600,7 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyMo
case AMDGPU::OPERAND_REG_INLINE_C_INT16:
case AMDGPU::OPERAND_REG_INLINE_C_FP16:
case AMDGPU::OPERAND_REG_IMM_FP16:
+ case AMDGPU::OPERAND_REG_IMM_NOINLINE_FP16:
case AMDGPU::OPERAND_REG_IMM_BF16:
case AMDGPU::OPERAND_REG_INLINE_C_BF16:
case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:
@@ -3828,7 +3833,8 @@ bool AMDGPUAsmParser::isInlineConstant(const MCInst &Inst,
OperandType == AMDGPU::OPERAND_REG_INLINE_C_BF16)
return AMDGPU::isInlinableLiteralBF16(Val, hasInv2PiInlineImm());
- if (OperandType == AMDGPU::OPERAND_REG_IMM_NOINLINE_V2FP16)
+ if (OperandType == AMDGPU::OPERAND_REG_IMM_NOINLINE_V2FP16 ||
+ OperandType == AMDGPU::OPERAND_REG_IMM_NOINLINE_FP16)
return false;
llvm_unreachable("invalid operand type");
diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
index 1322aac689800..36f4f01545d28 100644
--- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
+++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
@@ -573,6 +573,11 @@ void AMDGPUDisassembler::decodeImmOperands(MCInst &MI,
if (AMDGPU::EncValues::INLINE_FLOATING_C_MIN <= Imm &&
Imm <= AMDGPU::EncValues::INLINE_FLOATING_C_MAX) {
switch (OpDesc.OperandType) {
+ case AMDGPU::OPERAND_REG_IMM_NOINLINE_FP16:
+ case AMDGPU::OPERAND_REG_IMM_NOINLINE_V2FP16:
+ // Inline constant encodings are not allowed for NOINLINE operand types.
+ // Keep the raw encoding value.
+ continue;
case AMDGPU::OPERAND_REG_IMM_BF16:
case AMDGPU::OPERAND_REG_IMM_V2BF16:
case AMDGPU::OPERAND_REG_INLINE_C_BF16:
@@ -1703,6 +1708,7 @@ AMDGPUDisassembler::decodeLiteralConstant(const MCInstrDesc &Desc,
case AMDGPU::OPERAND_REG_IMM_V2FP16_SPLAT:
UseLit = AMDGPU::isPKFMACF16InlineConstant(Val, isGFX11Plus());
break;
+ case AMDGPU::OPERAND_REG_IMM_NOINLINE_FP16:
case AMDGPU::OPERAND_REG_IMM_NOINLINE_V2FP16:
break;
case AMDGPU::OPERAND_REG_IMM_INT16:
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
index 9687f31b298ad..e21dfbc421e34 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
@@ -887,6 +887,7 @@ void AMDGPUInstPrinter::printRegularOperand(const MCInst *MI, unsigned OpNo,
break;
case AMDGPU::OPERAND_REG_INLINE_C_FP16:
case AMDGPU::OPERAND_REG_IMM_FP16:
+ case AMDGPU::OPERAND_REG_IMM_NOINLINE_FP16:
printImmediateF16(Op.getImm(), STI, O);
break;
case AMDGPU::OPERAND_REG_INLINE_C_BF16:
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
index b3fdf38b9a688..83f0f340c25a0 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
@@ -337,6 +337,9 @@ std::optional<uint64_t> AMDGPUMCCodeEmitter::getLitEncoding(
// which does not have f16 support?
return getLit16Encoding(static_cast<uint16_t>(Imm), STI);
+ case AMDGPU::OPERAND_REG_IMM_NOINLINE_FP16:
+ return 255;
+
case AMDGPU::OPERAND_REG_IMM_BF16:
case AMDGPU::OPERAND_REG_INLINE_C_BF16:
// We don't actually need to check Inv2Pi here because BF16 instructions can
diff --git a/llvm/lib/Target/AMDGPU/SIDefines.h b/llvm/lib/Target/AMDGPU/SIDefines.h
index ffaf9fb9e573a..07db806690d04 100644
--- a/llvm/lib/Target/AMDGPU/SIDefines.h
+++ b/llvm/lib/Target/AMDGPU/SIDefines.h
@@ -422,6 +422,7 @@ enum OperandType : unsigned {
OPERAND_REG_IMM_FP64,
OPERAND_REG_IMM_BF16,
OPERAND_REG_IMM_FP16,
+ OPERAND_REG_IMM_NOINLINE_FP16,
OPERAND_REG_IMM_V2BF16,
OPERAND_REG_IMM_V2FP16,
OPERAND_REG_IMM_V2FP16_SPLAT,
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 801bf3c66882f..4f888f1982049 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -4712,6 +4712,7 @@ bool SIInstrInfo::isInlineConstant(int64_t Imm, uint8_t OperandType) const {
case AMDGPU::OPERAND_KIMM32:
case AMDGPU::OPERAND_KIMM16:
case AMDGPU::OPERAND_KIMM64:
+ case AMDGPU::OPERAND_REG_IMM_NOINLINE_FP16:
return false;
case AMDGPU::OPERAND_INLINE_C_AV64_PSEUDO:
return isLegalAV64PseudoImm(Imm);
@@ -5156,10 +5157,9 @@ bool SIInstrInfo::verifyInstruction(const MachineInstr &MI,
case AMDGPU::OPERAND_REG_IMM_V2BF16:
case AMDGPU::OPERAND_REG_IMM_V2FP64:
case AMDGPU::OPERAND_REG_IMM_V2INT64:
- break;
+ case AMDGPU::OPERAND_REG_IMM_NOINLINE_FP16:
case AMDGPU::OPERAND_REG_IMM_NOINLINE_V2FP16:
break;
- break;
case AMDGPU::OPERAND_REG_INLINE_C_INT16:
case AMDGPU::OPERAND_REG_INLINE_C_INT32:
case AMDGPU::OPERAND_REG_INLINE_C_INT64:
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
index 8e15b7b45b609..54028740cdd3f 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
@@ -1169,14 +1169,6 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
Opc == AMDGPU::GLOBAL_WBINV;
}
- static bool isF16PseudoScalarTrans(unsigned Opcode) {
- return Opcode == AMDGPU::V_S_EXP_F16_e64 ||
- Opcode == AMDGPU::V_S_LOG_F16_e64 ||
- Opcode == AMDGPU::V_S_RCP_F16_e64 ||
- Opcode == AMDGPU::V_S_RSQ_F16_e64 ||
- Opcode == AMDGPU::V_S_SQRT_F16_e64;
- }
-
static bool doesNotReadTiedSource(const MachineInstr &MI) {
return SIInstrFlags::isTiedSourceNotRead(MI);
}
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.td b/llvm/lib/Target/AMDGPU/SIRegisterInfo.td
index 31f927709e682..21d8bceebbf2e 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.td
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.td
@@ -1394,6 +1394,7 @@ class SrcRegOrImm9_t16<string operandType, RegisterClass regClass = VS_16>
def SSrc_b16 : SrcRegOrImm9 <SReg_32, "OPERAND_REG_IMM_INT16">;
def SSrc_bf16 : SrcRegOrImm9 <SReg_32, "OPERAND_REG_IMM_BF16">;
def SSrc_f16 : SrcRegOrImm9 <SReg_32, "OPERAND_REG_IMM_FP16">;
+def SSrc_NoInline_f16 : SrcRegOrImm9 <SReg_32, "OPERAND_REG_IMM_NOINLINE_FP16">;
def SSrc_b32 : SrcRegOrImm9 <SReg_32, "OPERAND_REG_IMM_INT32">;
def SSrc_f32 : SrcRegOrImm9 <SReg_32, "OPERAND_REG_IMM_FP32">;
def SSrc_b64 : SrcRegOrImm9 <SReg_64_Encodable, "OPERAND_REG_IMM_INT64">;
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
index 71d95a23e30d3..699cbe335df0f 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
@@ -2838,6 +2838,7 @@ bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo) {
case AMDGPU::OPERAND_REG_IMM_FP32:
case AMDGPU::OPERAND_REG_IMM_FP64:
case AMDGPU::OPERAND_REG_IMM_FP16:
+ case AMDGPU::OPERAND_REG_IMM_NOINLINE_FP16:
case AMDGPU::OPERAND_REG_IMM_V2FP16:
case AMDGPU::OPERAND_REG_IMM_V2FP16_SPLAT:
case AMDGPU::OPERAND_REG_IMM_NOINLINE_V2FP16:
@@ -3284,6 +3285,7 @@ int64_t encode32BitLiteral(int64_t Imm, OperandType Type, bool IsLit) {
break;
case OPERAND_REG_IMM_BF16:
case OPERAND_REG_IMM_FP16:
+ case OPERAND_REG_IMM_NOINLINE_FP16:
case OPERAND_REG_INLINE_C_BF16:
case OPERAND_REG_INLINE_C_FP16:
return Imm & 0xffff;
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
index 4b08c08c5a60d..6a4007fcd93ae 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
@@ -1610,6 +1610,7 @@ inline unsigned getOperandSize(const MCOperandInfo &OpInfo) {
case AMDGPU::OPERAND_REG_IMM_INT16:
case AMDGPU::OPERAND_REG_IMM_BF16:
case AMDGPU::OPERAND_REG_IMM_FP16:
+ case AMDGPU::OPERAND_REG_IMM_NOINLINE_FP16:
case AMDGPU::OPERAND_REG_INLINE_C_INT16:
case AMDGPU::OPERAND_REG_INLINE_C_BF16:
case AMDGPU::OPERAND_REG_INLINE_C_FP16:
diff --git a/llvm/lib/Target/AMDGPU/VOP3Instructions.td b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
index f2a2f2b3a2499..6740a9046f09b 100644
--- a/llvm/lib/Target/AMDGPU/VOP3Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
@@ -1995,19 +1995,36 @@ class VOP_Pseudo_Scalar<RegisterClass Dst, RegisterOperand SrcOp,
def VOP_Pseudo_Scalar_F32 : VOP_Pseudo_Scalar<SReg_32_XEXEC, SSrc_f32, f32>;
def VOP_Pseudo_Scalar_F16 : VOP_Pseudo_Scalar<SReg_32_XEXEC, SSrc_f16, f32, f16>;
+def VOP_Pseudo_Scalar_F16_NoInline : VOP_Pseudo_Scalar<SReg_32_XEXEC, SSrc_NoInline_f16, f32, f16>;
+
+// Define regular and "no inline constant" variant of a F16 pseudo
+// scalar transcendental instruction.
+multiclass VOP3PseudoScalarInst_F16<string opName> {
+ let SubtargetPredicate = HasF16PseudoScalarTransWithInlineConstants,
+ AssemblerPredicate = HasF16PseudoScalarTransWithInlineConstants,
+ TRANS = 1, isReMaterializable = 1, SchedRW = [WritePseudoScalarTrans] in {
+ defm NAME : VOP3PseudoScalarInst<opName, VOP_Pseudo_Scalar_F16>;
+ }
+
+ let SubtargetPredicate = HasNoF16PseudoScalarTransInlineConstants,
+ AssemblerPredicate = HasNoF16PseudoScalarTransInlineConstants,
+ TRANS = 1, isReMaterializable = 1, SchedRW = [WritePseudoScalarTrans] in {
+ defm !strconcat(NAME, "_noinline") : VOP3PseudoScalarInst<opName, VOP_Pseudo_Scalar_F16_NoInline>;
+ }
+}
let SubtargetPredicate = HasPseudoScalarTrans, TRANS = 1,
isReMaterializable = 1, SchedRW = [WritePseudoScalarTrans] in {
defm V_S_EXP_F32 : VOP3PseudoScalarInst<"v_s_exp_f32", VOP_Pseudo_Scalar_F32, AMDGPUexp>;
- defm V_S_EXP_F16 : VOP3PseudoScalarInst<"v_s_exp_f16", VOP_Pseudo_Scalar_F16>;
+ defm V_S_EXP_F16 : VOP3PseudoScalarInst_F16<"v_s_exp_f16">;
defm V_S_LOG_F32 : VOP3PseudoScalarInst<"v_s_log_f32", VOP_Pseudo_Scalar_F32, AMDGPUlog>;
- defm V_S_LOG_F16 : VOP3PseudoScalarInst<"v_s_log_f16", VOP_Pseudo_Scalar_F16>;
+ defm V_S_LOG_F16 : VOP3PseudoScalarInst_F16<"v_s_log_f16">;
defm V_S_RCP_F32 : VOP3PseudoScalarInst<"v_s_rcp_f32", VOP_Pseudo_Scalar_F32, AMDGPUrcp>;
- defm V_S_RCP_F16 : VOP3PseudoScalarInst<"v_s_rcp_f16", VOP_Pseudo_Scalar_F16>;
+ defm V_S_RCP_F16 : VOP3PseudoScalarInst_F16<"v_s_rcp_f16">;
defm V_S_RSQ_F32 : VOP3PseudoScalarInst<"v_s_rsq_f32", VOP_Pseudo_Scalar_F32, AMDGPUrsq>;
- defm V_S_RSQ_F16 : VOP3PseudoScalarInst<"v_s_rsq_f16", VOP_Pseudo_Scalar_F16>;
+ defm V_S_RSQ_F16 : VOP3PseudoScalarInst_F16<"v_s_rsq_f16">;
defm V_S_SQRT_F32 : VOP3PseudoScalarInst<"v_s_sqrt_f32", VOP_Pseudo_Scalar_F32, any_amdgcn_sqrt>;
- defm V_S_SQRT_F16 : VOP3PseudoScalarInst<"v_s_sqrt_f16", VOP_Pseudo_Scalar_F16>;
+ defm V_S_SQRT_F16 : VOP3PseudoScalarInst_F16<"v_s_sqrt_f16">;
}
class PseudoScalarPatF16<SDPatternOperator node, VOP3_Pseudo inst> : GCNPat <
@@ -2152,16 +2169,24 @@ defm V_MINMAX_NUM_F32 : VOP3_Realtriple_with_name_gfx12_gfx13<0x268,0x268, "
defm V_MAXMIN_NUM_F32 : VOP3_Realtriple_with_name_gfx12_gfx13<0x269, 0x269, "V_MAXMIN_F32", "v_maxmin_num_f32">;
defm V_MINMAX_NUM_F16 : VOP3_Realtriple_t16_and_fake16_gfx12_gfx13<0x26a, 0x26a, "v_minmax_num_f16", "V_MINMAX_F16", "v_minmax_f16">;
defm V_MAXMIN_NUM_F16 : VOP3_Realtriple_t16_and_fake16_gfx12_gfx13<0x26b, 0x26b, "v_maxmin_num_f16", "V_MAXMIN_F16", "v_maxmin_f16">;
+
+// Define regular and "no inline constant" variant (for gfx12) of a
+// F16 pseudo-scalar transcendental instruction.
+multiclass VOP3Only_Real_F16_PseudoScalarTrans<bits<10> op> {
+ defm NAME : VOP3_Real_Base<GFX13Gen, op, NAME, 1>;
+ defm !strconcat(NAME, "_noinline") : VOP3_Real_Base<GFX12Gen, op, !strconcat(NAME, "_noinline"), 1>;
+}
+
defm V_S_EXP_F32 : VOP3Only_Real_Base_gfx12_gfx13<0x280>;
-defm V_S_EXP_F16 : VOP3Only_Real_Base_gfx12_gfx13<0x281>;
+defm V_S_EXP_F16 : VOP3Only_Real_F16_PseudoScalarTrans<0x281>;
defm V_S_LOG_F32 : VOP3Only_Real_Base_gfx12_gfx13<0x282>;
-defm V_S_LOG_F16 : VOP3Only_Real_Base_gfx12_gfx13<0x283>;
+defm V_S_LOG_F16 : VOP3Only_Real_F16_PseudoScalarTrans<0x283>;
defm V_S_RCP_F32 : VOP3Only_Real_Base_gfx12_gfx13<0x284>;
-defm V_S_RCP_F16 : VOP3Only_Real_Base_gfx12_gfx13<0x285>;
+defm V_S_RCP_F16 : VOP3Only_Real_F16_PseudoScalarTrans<0x285>;
defm V_S_RSQ_F32 : VOP3Only_Real_Base_gfx12_gfx13<0x286>;
-defm V_S_RSQ_F16 : VOP3Only_Real_Base_gfx12_gfx13<0x287>;
+defm V_S_RSQ_F16 : VOP3Only_Real_F16_PseudoScalarTrans<0x287>;
defm V_S_SQRT_F32 : VOP3Only_Real_Base_gfx12_gfx13<0x288>;
-defm V_S_SQRT_F16 : VOP3Only_Real_Base_gfx12_gfx13<0x289>;
+defm V_S_SQRT_F16 : VOP3Only_Real_F16_PseudoScalarTrans<0x289>;
defm V_MAD_CO_U64_U32 : VOP3be_Real_with_name_gfx12_NO_DPP_gfx13<0x2fe, 0x2f8, "V_MAD_U64_U32", "v_mad_co_u64_u32">;
defm V_MAD_CO_I64_I32 : VOP3be_Real_with_name_gfx12_NO_DPP_gfx13<0x2ff, 0x2f9, "V_MAD_I64_I32", "v_mad_co_i64_i32">;
diff --git a/llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.mir b/llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.mir
index 90adf3f95a379..a59add37d5435 100644
--- a/llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.mir
+++ b/llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.mir
@@ -3,9 +3,7 @@
# RUN: llc -mtriple=amdgpu12.50-amd-amdpal -x mir --show-mc-encoding < %s | FileCheck --check-prefixes=GFX1250 %s
# Do not use inline constants for f16 pseudo scalar transcendentals.
-# But allow literal constants.
-
-# FIXME: Inline constants are used on the _imm test cases (see shorter encoding with 0xf2 in byte 4)
+# Use literal encoding instead (0xff marker + 4-byte literal).
--- |
define void @exp_f16_imm() {
@@ -16,14 +14,14 @@
; GFX12-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
; GFX12-NEXT: s_wait_bvhcnt 0x0 ; encoding: [0x00,0x00,0xc3,0xbf]
; GFX12-NEXT: s_wait_kmcnt 0x0 ; encoding: [0x00,0x00,0xc7,0xbf]
- ; GFX12-NEXT: v_s_exp_f16 s0, neg(1.0) ; encoding: [0x00,0x00,0x81,0xd6,0xf2,0x00,0x01,0x22]
+ ; GFX12-NEXT: v_s_exp_f16 s0, neg(1.0) ; encoding: [0x00,0x00,0x81,0xd6,0xff,0x00,0x01,0x22,0x00,0x3c,0x00,0x00]
; GFX12-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
;
; GFX1250-LABEL: exp_f16_imm:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 ; encoding: [0x00,0x00,0xc8,0xbf]
; GFX1250-NEXT: s_wait_kmcnt 0x0 ; encoding: [0x00,0x00,0xc7,0xbf]
- ; GFX1250-NEXT: v_s_exp_f16 s0, neg(1.0) ; encoding: [0x00,0x00,0x81,0xd6,0xf2,0x00,0x01,0x22]
+ ; GFX1250-NEXT: v_s_exp_f16 s0, neg(1.0) ; encoding: [0x00,0x00,0x81,0xd6,0xff,0x00,0x01,0x22,0x00,0x3c,0x00,0x00]
; GFX1250-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
ret void
}
@@ -54,14 +52,14 @@
; GFX12-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
; GFX12-NEXT: s_wait_bvhcnt 0x0 ; encoding: [0x00,0x00,0xc3,0xbf]
; GFX12-NEXT: s_wait_kmcnt 0x0 ; encoding: [0x00,0x00,0xc7,0xbf]
- ; GFX12-NEXT: v_s_log_f16 s0, neg(1.0) ; encoding: [0x00,0x00,0x83,0xd6,0xf2,0x00,0x01,0x22]
+ ; GFX12-NEXT: v_s_log_f16 s0, neg(1.0) ; encoding: [0x00,0x00,0x83,0xd6,0xff,0x00,0x01,0x22,0x00,0x3c,0x00,0x00]
; GFX12-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
;
; GFX1250-LABEL: log_f16_imm:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 ; encoding: [0x00,0x00,0xc8,0xbf]
; GFX1250-NEXT: s_wait_kmcnt 0x0 ; encoding: [0x00,0x00,0xc7,0xbf]
- ; GFX1250-NEXT: v_s_log_f16 s0, neg(1.0) ; encoding: [0x00,0x00,0x83,0xd6,0xf2,0x00,0x01,0x22]
+ ; GFX1250-NEXT: v_s_log_f16 s0, neg(1.0) ; encoding: [0x00,0x00,0x83,0xd6,0xff,0x00,0x01,0x22,0x00,0x3c,0x00,0x00]
; GFX1250-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
ret void
}
@@ -92,14 +90,14 @@
; GFX12-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
; GFX12-NEXT: s_wait_bvhcnt 0x0 ; encoding: [0x00,0x00,0xc3,0xbf]
; GFX12-NEXT: s_wait_kmcnt 0x0 ; encoding: [0x00,0x00,0xc7,0xbf]
- ; GFX12-NEXT: v_s_rcp_f16 s0, neg(1.0) ; encoding: [0x00,0x00,0x85,0xd6,0xf2,0x00,0x01,0x22]
+ ; GFX12-NEXT: v_s_rcp_f16 s0, neg(1.0) ; encoding: [0x00,0x00,0x85,0xd6,0xff,0x00,0x01,0x22,0x00,0x3c,0x00,0x00]
; GFX12-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
;
; GFX1250-LABEL: rcp_f16_imm:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 ; encoding: [0x00,0x00,0xc8,0xbf]
; GFX1250-NEXT: s_wait_kmcnt 0x0 ; encoding: [0x00,0x00,0xc7,0xbf]
- ; GFX1250-NEXT: v_s_rcp_f16 s0, neg(1.0) ; encoding: [0x00,0x00,0x85,0xd6,0xf2,0x00,0x01,0x22]
+ ; GFX1250-NEXT: v_s_rcp_f16 s0, neg(1.0) ; encoding: [0x00,0x00,0x85,0xd6,0xff,0x00,0x01,0x22,0x00,0x3c,0x00,0x00]
; GFX1250-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
ret void
}
@@ -130,14 +128,14 @@
; GFX12-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
; GFX12-NEXT: s_wait_bvhcnt 0x0 ; encoding: [0x00,0x00,0xc3,0xbf]
; GFX12-NEXT: s_wait_kmcnt 0x0 ; encoding: [0x00,0x00,0xc7,0xbf]
- ; GFX12-NEXT: v_s_rsq_f16 s0, neg(1.0) ; encoding: [0x00,0x00,0x87,0xd6,0xf2,0x00,0x01,0x22]
+ ; GFX12-NEXT: v_s_rsq_f16 s0, neg(1.0) ; encoding: [0x00,0x00,0x87,0xd6,0xff,0x00,0x01,0x22,0x00,0x3c,0x00,0x00]
; GFX12-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
;
; GFX1250-LABEL: rsq_f16_imm:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 ; encoding: [0x00,0x00,0xc8,0xbf]
; GFX1250-NEXT: s_wait_kmcnt 0x0 ; encoding: [0x00,0x00,0xc7,0xbf]
- ; GFX1250-NEXT: v_s_rsq_f16 s0, neg(1.0) ; encoding: [0x00,0x00,0x87,0xd6,0xf2,0x00,0x01,0x22]
+ ; GFX1250-NEXT: v_s_rsq_f16 s0, neg(1.0) ; encoding: [0x00,0x00,0x87,0xd6,0xff,0x00,0x01,0x22,0x00,0x3c,0x00,0x00]
; GFX1250-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
ret void
}
@@ -168,14 +166,14 @@
; GFX12-NEXT: s_wait_samplecnt 0x0 ; encoding: [0x00,0x00,0xc2,0xbf]
; GFX12-NEXT: s_wait_bvhcnt 0x0 ; encoding: [0x00,0x00,0xc3,0xbf]
; GFX12-NEXT: s_wait_kmcnt 0x0 ; encoding: [0x00,0x00,0xc7,0xbf]
- ; GFX12-NEXT: v_s_sqrt_f16 s0, neg(1.0) ; encoding: [0x00,0x00,0x89,0xd6,0xf2,0x00,0x01,0x22]
+ ; GFX12-NEXT: v_s_sqrt_f16 s0, neg(1.0) ; encoding: [0x00,0x00,0x89,0xd6,0xff,0x00,0x01,0x22,0x00,0x3c,0x00,0x00]
; GFX12-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
;
; GFX1250-LABEL: sqrt_f16_imm:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 ; encoding: [0x00,0x00,0xc8,0xbf]
; GFX1250-NEXT: s_wait_kmcnt 0x0 ; encoding: [0x00,0x00,0xc7,0xbf]
- ; GFX1250-NEXT: v_s_sqrt_f16 s0, neg(1.0) ; encoding: [0x00,0x00,0x89,0xd6,0xf2,0x00,0x01,0x22]
+ ; GFX1250-NEXT: v_s_sqrt_f16 s0, neg(1.0) ; encoding: [0x00,0x00,0x89,0xd6,0xff,0x00,0x01,0x22,0x00,0x3c,0x00,0x00]
; GFX1250-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
ret void
}
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop3-fake16.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop3-fake16.s
index 3eaace04b7279..efdeda678ad15 100644
--- a/llvm/test/MC/AMDGPU/gfx12_asm_vop3-fake16.s
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop3-fake16.s
@@ -6809,10 +6809,10 @@ v_s_exp_f16 s5, null
// GFX12: v_s_exp_f16 s5, null ; encoding: [0x05,0x00,0x81,0xd6,0x7c,0x00,0x01,0x02]
v_s_exp_f16 s5, -1
-// GFX12: v_s_exp_f16 s5, -1 ; encoding: [0x05,0x00,0x81,0xd6,0xc1,0x00,0x01,0x02]
+// GFX12: v_s_exp_f16 s5, -1 ; encoding: [0x05,0x00,0x81,0xd6,0xff,0x00,0x01,0x02,0xff,0xff,0x00,0x00]
v_s_exp_f16 s5, 0.5
-// GFX12: v_s_exp_f16 s5, 0.5 ; encoding: [0x05,0x00,0x81,0xd6,0xf0,0x00,0x01,0x02]
+// GFX12: v_s_exp_f16 s5, 0.5 ; encoding: [0x05,0x00,0x81,0xd6,0xff,0x00,0x01,0x02,0x00,0x38,0x00,0x00]
v_s_exp_f16 s5, src_scc
// GFX12: v_s_exp_f16 s5, src_scc ; encoding: [0x05,0x00,0x81,0xd6,0xfd,0x00,0x01,0x02]
@@ -6923,10 +6923,10 @@ v_s_log_f16 s5, null
// GFX12: v_s_log_f16 s5, null ; encoding: [0x05,0x00,0x83,0xd6,0x7c,0x00,0x01,0x02]
v_s_log_f16 s5, -1
-// GFX12: v_s_log_f16 s5, -1 ; encoding: [0x05,0x00,0x83,0xd6,0xc1,0x00,0x01,0x02]
+// GFX12: v_s_log_f16 s5, -1 ; encoding: [0x05,0x00,0x83,0xd6,0xff,0x00,0x01,0x02,0xff,0xff,0x00,0x00]
v_s_log_f16 s5, 0.5
-// GFX12: v_s_log_f16 s5, 0.5 ; encoding: [0x05,0x00,0x83,0xd6,0xf0,0x00,0x01,0x02]
+// GFX12: v_s_log_f16 s5, 0.5 ; encoding: [0x05,0x00,0x83,0xd6,0xff,0x00,0x01,0x02,0x00,0x38,0x00,0x00]
v_s_log_f16 s5, src_scc
// GFX12: v_s_log_f16 s5, src_scc ; encoding: [0x05,0x00,0x83,0xd6,0xfd,0x00,0x01,0x02]
@@ -7037,10 +7037,10 @@ v_s_rcp_f16 s5, null
// GFX12: v_s_rcp_f16 s5, null ; encoding: [0x05,0x00,0x85,0xd6,0x7c,0x00,0x01,0x02]
v_s_rcp_f16 s5, -1
-// GFX12: v_s_rcp_f16 s5, -1 ; encoding: [0x05,0x00,0x85,0xd6,0xc1,0x00,0x01,0x02]
+// GFX12: v_s_rcp_f16 s5, -1 ; encoding: [0x05,0x00,0x85,0xd6,0xff,0x00,0x01,0x02,0xff,0xff,0x00,0x00]
v_s_rcp_f16 s5, 0.5
-// GFX12: v_s_rcp_f16 s5, 0.5 ; encoding: [0x05,0x00,0x85,0xd6,0xf0,0x00,0x01,0x02]
+// GFX12: v_s_rcp_f16 s5, 0.5 ; encoding: [0x05,0x00,0x85,0xd6,0xff,0x00,0x01,0x02,0x00,0x38,0x00,0x00]
v_s_rcp_f16 s5, src_scc
// GFX12: v_s_rcp_f16 s5, src_scc ; encoding: [0x05,0x00,0x85,0xd6,0xfd,0x00,0x01,0x02]
@@ -7151,10 +7151,10 @@ v_s_rsq_f16 s5, null
// GFX12: v_s_rsq_f16 s5, null ; encoding: [0x05,0x00,0x87,0xd6,0x7c,0x00,0x01,0x02]
v_s_rsq_f16 s5, -1
-// GFX12: v_s_rsq_f16 s5, -1 ; encoding: [0x05,0x00,0x87,0xd6,0xc1,0x00,0x01,0x02]
+// GFX12: v_s_rsq_f16 s5, -1 ; encoding: [0x05,0x00,0x87,0xd6,0xff,0x00,0x01,0x02,0xff,0xff,0x00,0x00]
v_s_rsq_f16 s5, 0.5
-// GFX12: v_s_rsq_f16 s5, 0.5 ; encoding: [0x05,0x00,0x87,0xd6,0xf0,0x00,0x01,0x02]
+// GFX12: v_s_rsq_f16 s5, 0.5 ; encoding: [0x05,0x00,0x87,0xd6,0xff,0x00,0x01,0x02,0x00,0x38,0x00,0x00]
v_s_rsq_f16 s5, src_scc
// GFX12: v_s_rsq_f16 s5, src_scc ; encoding: [0x05,0x00,0x87,0xd6,0xfd,0x00,0x01,0x02]
@@ -7265,10 +7265,10 @@ v_s_sqrt_f16 s5, null
// GFX12: v_s_sqrt_f16 s5, null ; encoding: [0x05,0x00,0x89,0xd6,0x7c,0x00,0x01,0x02]
v_s_sqrt_f16 s5, -1
-// GFX12: v_s_sqrt_f16 s5, -1 ; encoding: [0x05,0x00,0x89,0xd6,0xc1,0x00,0x01,0x02]
+// GFX12: v_s_sqrt_f16 s5, -1 ; encoding: [0x05,0x00,0x89,0xd6,0xff,0x00,0x01,0x02,0xff,0xff,0x00,0x00]
v_s_sqrt_f16 s5, 0.5
-// GFX12: v_s_sqrt_f16 s5, 0.5 ; encoding: [0x05,0x00,0x89,0xd6,0xf0,0x00,0x01,0x02]
+// GFX12: v_s_sqrt_f16 s5, 0.5 ; encoding: [0x05,0x00,0x89,0xd6,0xff,0x00,0x01,0x02,0x00,0x38,0x00,0x00]
v_s_sqrt_f16 s5, src_scc
// GFX12: v_s_sqrt_f16 s5, src_scc ; encoding: [0x05,0x00,0x89,0xd6,0xfd,0x00,0x01,0x02]
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop3.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop3.s
index 78e4f70bbe4bb..2cb5fb861cc61 100644
--- a/llvm/test/MC/AMDGPU/gfx12_asm_vop3.s
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop3.s
@@ -7178,10 +7178,10 @@ v_s_exp_f16 s5, null
// GFX12: v_s_exp_f16 s5, null ; encoding: [0x05,0x00,0x81,0xd6,0x7c,0x00,0x01,0x02]
v_s_exp_f16 s5, -1
-// GFX12: v_s_exp_f16 s5, -1 ; encoding: [0x05,0x00,0x81,0xd6,0xc1,0x00,0x01,0x02]
+// GFX12: v_s_exp_f16 s5, -1 ; encoding: [0x05,0x00,0x81,0xd6,0xff,0x00,0x01,0x02,0xff,0xff,0x00,0x00]
v_s_exp_f16 s5, 0.5
-// GFX12: v_s_exp_f16 s5, 0.5 ; encoding: [0x05,0x00,0x81,0xd6,0xf0,0x00,0x01,0x02]
+// GFX12: v_s_exp_f16 s5, 0.5 ; encoding: [0x05,0x00,0x81,0xd6,0xff,0x00,0x01,0x02,0x00,0x38,0x00,0x00]
v_s_exp_f16 s5, src_scc
// GFX12: v_s_exp_f16 s5, src_scc ; encoding: [0x05,0x00,0x81,0xd6,0xfd,0x00,0x01,0x02]
@@ -7292,10 +7292,10 @@ v_s_log_f16 s5, null
// GFX12: v_s_log_f16 s5, null ; encoding: [0x05,0x00,0x83,0xd6,0x7c,0x00,0x01,0x02]
v_s_log_f16 s5, -1
-// GFX12: v_s_log_f16 s5, -1 ; encoding: [0x05,0x00,0x83,0xd6,0xc1,0x00,0x01,0x02]
+// GFX12: v_s_log_f16 s5, -1 ; encoding: [0x05,0x00,0x83,0xd6,0xff,0x00,0x01,0x02,0xff,0xff,0x00,0x00]
v_s_log_f16 s5, 0.5
-// GFX12: v_s_log_f16 s5, 0.5 ; encoding: [0x05,0x00,0x83,0xd6,0xf0,0x00,0x01,0x02]
+// GFX12: v_s_log_f16 s5, 0.5 ; encoding: [0x05,0x00,0x83,0xd6,0xff,0x00,0x01,0x02,0x00,0x38,0x00,0x00]
v_s_log_f16 s5, src_scc
// GFX12: v_s_log_f16 s5, src_scc ; encoding: [0x05,0x00,0x83,0xd6,0xfd,0x00,0x01,0x02]
@@ -7406,10 +7406,10 @@ v_s_rcp_f16 s5, null
// GFX12: v_s_rcp_f16 s5, null ; encoding: [0x05,0x00,0x85,0xd6,0x7c,0x00,0x01,0x02]
v_s_rcp_f16 s5, -1
-// GFX12: v_s_rcp_f16 s5, -1 ; encoding: [0x05,0x00,0x85,0xd6,0xc1,0x00,0x01,0x02]
+// GFX12: v_s_rcp_f16 s5, -1 ; encoding: [0x05,0x00,0x85,0xd6,0xff,0x00,0x01,0x02,0xff,0xff,0x00,0x00]
v_s_rcp_f16 s5, 0.5
-// GFX12: v_s_rcp_f16 s5, 0.5 ; encoding: [0x05,0x00,0x85,0xd6,0xf0,0x00,0x01,0x02]
+// GFX12: v_s_rcp_f16 s5, 0.5 ; encoding: [0x05,0x00,0x85,0xd6,0xff,0x00,0x01,0x02,0x00,0x38,0x00,0x00]
v_s_rcp_f16 s5, src_scc
// GFX12: v_s_rcp_f16 s5, src_scc ; encoding: [0x05,0x00,0x85,0xd6,0xfd,0x00,0x01,0x02]
@@ -7520,10 +7520,10 @@ v_s_rsq_f16 s5, null
// GFX12: v_s_rsq_f16 s5, null ; encoding: [0x05,0x00,0x87,0xd6,0x7c,0x00,0x01,0x02]
v_s_rsq_f16 s5, -1
-// GFX12: v_s_rsq_f16 s5, -1 ; encoding: [0x05,0x00,0x87,0xd6,0xc1,0x00,0x01,0x02]
+// GFX12: v_s_rsq_f16 s5, -1 ; encoding: [0x05,0x00,0x87,0xd6,0xff,0x00,0x01,0x02,0xff,0xff,0x00,0x00]
v_s_rsq_f16 s5, 0.5
-// GFX12: v_s_rsq_f16 s5, 0.5 ; encoding: [0x05,0x00,0x87,0xd6,0xf0,0x00,0x01,0x02]
+// GFX12: v_s_rsq_f16 s5, 0.5 ; encoding: [0x05,0x00,0x87,0xd6,0xff,0x00,0x01,0x02,0x00,0x38,0x00,0x00]
v_s_rsq_f16 s5, src_scc
// GFX12: v_s_rsq_f16 s5, src_scc ; encoding: [0x05,0x00,0x87,0xd6,0xfd,0x00,0x01,0x02]
@@ -7634,10 +7634,10 @@ v_s_sqrt_f16 s5, null
// GFX12: v_s_sqrt_f16 s5, null ; encoding: [0x05,0x00,0x89,0xd6,0x7c,0x00,0x01,0x02]
v_s_sqrt_f16 s5, -1
-// GFX12: v_s_sqrt_f16 s5, -1 ; encoding: [0x05,0x00,0x89,0xd6,0xc1,0x00,0x01,0x02]
+// GFX12: v_s_sqrt_f16 s5, -1 ; encoding: [0x05,0x00,0x89,0xd6,0xff,0x00,0x01,0x02,0xff,0xff,0x00,0x00]
v_s_sqrt_f16 s5, 0.5
-// GFX12: v_s_sqrt_f16 s5, 0.5 ; encoding: [0x05,0x00,0x89,0xd6,0xf0,0x00,0x01,0x02]
+// GFX12: v_s_sqrt_f16 s5, 0.5 ; encoding: [0x05,0x00,0x89,0xd6,0xff,0x00,0x01,0x02,0x00,0x38,0x00,0x00]
v_s_sqrt_f16 s5, src_scc
// GFX12: v_s_sqrt_f16 s5, src_scc ; encoding: [0x05,0x00,0x89,0xd6,0xfd,0x00,0x01,0x02]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3.txt
index 5f92dfcd9e9b8..ed7292198f6a4 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3.txt
@@ -9039,10 +9039,10 @@
# GFX12: v_s_exp_f16 s5, null ; encoding: [0x05,0x00,0x81,0xd6,0x7c,0x00,0x01,0x02]
0x05,0x00,0x81,0xd6,0xc1,0x00,0x00,0x00
-# GFX12: v_s_exp_f16 s5, -1 ; encoding: [0x05,0x00,0x81,0xd6,0xc1,0x00,0x01,0x02]
+# GFX12: v_s_exp_f16 s5, -1 ; encoding: [0x05,0x00,0x81,0xd6,0xff,0x00,0x01,0x02,0xff,0xff,0x00,0x00]
0x05,0x00,0x81,0xd6,0xf0,0x00,0x00,0x00
-# GFX12: v_s_exp_f16 s5, 0.5 ; encoding: [0x05,0x00,0x81,0xd6,0xf0,0x00,0x01,0x02]
+# GFX12: v_s_exp_f16 s5, 0xf0 ; encoding: [0x05,0x00,0x81,0xd6,0xff,0x00,0x01,0x02,0xf0,0x00,0x00,0x00]
0x05,0x00,0x81,0xd6,0xfd,0x00,0x00,0x00
# GFX12: v_s_exp_f16 s5, src_scc ; encoding: [0x05,0x00,0x81,0xd6,0xfd,0x00,0x01,0x02]
@@ -9153,10 +9153,10 @@
# GFX12: v_s_log_f16 s5, null ; encoding: [0x05,0x00,0x83,0xd6,0x7c,0x00,0x01,0x02]
0x05,0x00,0x83,0xd6,0xc1,0x00,0x00,0x00
-# GFX12: v_s_log_f16 s5, -1 ; encoding: [0x05,0x00,0x83,0xd6,0xc1,0x00,0x01,0x02]
+# GFX12: v_s_log_f16 s5, -1 ; encoding: [0x05,0x00,0x83,0xd6,0xff,0x00,0x01,0x02,0xff,0xff,0x00,0x00]
0x05,0x00,0x83,0xd6,0xf0,0x00,0x00,0x00
-# GFX12: v_s_log_f16 s5, 0.5 ; encoding: [0x05,0x00,0x83,0xd6,0xf0,0x00,0x01,0x02]
+# GFX12: v_s_log_f16 s5, 0xf0 ; encoding: [0x05,0x00,0x83,0xd6,0xff,0x00,0x01,0x02,0xf0,0x00,0x00,0x00]
0x05,0x00,0x83,0xd6,0xfd,0x00,0x00,0x00
# GFX12: v_s_log_f16 s5, src_scc ; encoding: [0x05,0x00,0x83,0xd6,0xfd,0x00,0x01,0x02]
@@ -9267,10 +9267,10 @@
# GFX12: v_s_rcp_f16 s5, null ; encoding: [0x05,0x00,0x85,0xd6,0x7c,0x00,0x01,0x02]
0x05,0x00,0x85,0xd6,0xc1,0x00,0x00,0x00
-# GFX12: v_s_rcp_f16 s5, -1 ; encoding: [0x05,0x00,0x85,0xd6,0xc1,0x00,0x01,0x02]
+# GFX12: v_s_rcp_f16 s5, -1 ; encoding: [0x05,0x00,0x85,0xd6,0xff,0x00,0x01,0x02,0xff,0xff,0x00,0x00]
0x05,0x00,0x85,0xd6,0xf0,0x00,0x00,0x00
-# GFX12: v_s_rcp_f16 s5, 0.5 ; encoding: [0x05,0x00,0x85,0xd6,0xf0,0x00,0x01,0x02]
+# GFX12: v_s_rcp_f16 s5, 0xf0 ; encoding: [0x05,0x00,0x85,0xd6,0xff,0x00,0x01,0x02,0xf0,0x00,0x00,0x00]
0x05,0x00,0x85,0xd6,0xfd,0x00,0x00,0x00
# GFX12: v_s_rcp_f16 s5, src_scc ; encoding: [0x05,0x00,0x85,0xd6,0xfd,0x00,0x01,0x02]
@@ -9381,10 +9381,10 @@
# GFX12: v_s_rsq_f16 s5, null ; encoding: [0x05,0x00,0x87,0xd6,0x7c,0x00,0x01,0x02]
0x05,0x00,0x87,0xd6,0xc1,0x00,0x00,0x00
-# GFX12: v_s_rsq_f16 s5, -1 ; encoding: [0x05,0x00,0x87,0xd6,0xc1,0x00,0x01,0x02]
+# GFX12: v_s_rsq_f16 s5, -1 ; encoding: [0x05,0x00,0x87,0xd6,0xff,0x00,0x01,0x02,0xff,0xff,0x00,0x00]
0x05,0x00,0x87,0xd6,0xf0,0x00,0x00,0x00
-# GFX12: v_s_rsq_f16 s5, 0.5 ; encoding: [0x05,0x00,0x87,0xd6,0xf0,0x00,0x01,0x02]
+# GFX12: v_s_rsq_f16 s5, 0xf0 ; encoding: [0x05,0x00,0x87,0xd6,0xff,0x00,0x01,0x02,0xf0,0x00,0x00,0x00]
0x05,0x00,0x87,0xd6,0xfd,0x00,0x00,0x00
# GFX12: v_s_rsq_f16 s5, src_scc ; encoding: [0x05,0x00,0x87,0xd6,0xfd,0x00,0x01,0x02]
@@ -9495,10 +9495,10 @@
# GFX12: v_s_sqrt_f16 s5, null ; encoding: [0x05,0x00,0x89,0xd6,0x7c,0x00,0x01,0x02]
0x05,0x00,0x89,0xd6,0xc1,0x00,0x00,0x00
-# GFX12: v_s_sqrt_f16 s5, -1 ; encoding: [0x05,0x00,0x89,0xd6,0xc1,0x00,0x01,0x02]
+# GFX12: v_s_sqrt_f16 s5, -1 ; encoding: [0x05,0x00,0x89,0xd6,0xff,0x00,0x01,0x02,0xff,0xff,0x00,0x00]
0x05,0x00,0x89,0xd6,0xf0,0x00,0x00,0x00
-# GFX12: v_s_sqrt_f16 s5, 0.5 ; encoding: [0x05,0x00,0x89,0xd6,0xf0,0x00,0x01,0x02]
+# GFX12: v_s_sqrt_f16 s5, 0xf0 ; encoding: [0x05,0x00,0x89,0xd6,0xff,0x00,0x01,0x02,0xf0,0x00,0x00,0x00]
0x05,0x00,0x89,0xd6,0xfd,0x00,0x00,0x00
# GFX12: v_s_sqrt_f16 s5, src_scc ; encoding: [0x05,0x00,0x89,0xd6,0xfd,0x00,0x01,0x02]
>From 9be8e33a5fa6f51da0ce62cda2c9a21e0b365498 Mon Sep 17 00:00:00 2001
From: Frederik Harwath <fharwath at amd.com>
Date: Tue, 18 Aug 2026 11:17:30 -0400
Subject: [PATCH 7/8] Adjust test
---
.../AMDGPU/pseudo-scalar-transcendental.mir | 20 +++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.mir b/llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.mir
index a59add37d5435..92de0c8bff9a3 100644
--- a/llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.mir
+++ b/llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.mir
@@ -201,6 +201,8 @@
---
name: exp_f16_imm
tracksRegLiveness: true
+machineFunctionInfo:
+ stackPtrOffsetReg: '$sgpr32'
body: |
bb.0:
%0:sgpr_32 = S_MOV_B32 15360
@@ -212,6 +214,8 @@ body: |
---
name: exp_f16_literal
tracksRegLiveness: true
+machineFunctionInfo:
+ stackPtrOffsetReg: '$sgpr32'
body: |
bb.0:
%0:sgpr_32 = S_MOV_B32 16960
@@ -223,6 +227,8 @@ body: |
---
name: log_f16_imm
tracksRegLiveness: true
+machineFunctionInfo:
+ stackPtrOffsetReg: '$sgpr32'
body: |
bb.0:
%0:sgpr_32 = S_MOV_B32 15360
@@ -234,6 +240,8 @@ body: |
---
name: log_f16_literal
tracksRegLiveness: true
+machineFunctionInfo:
+ stackPtrOffsetReg: '$sgpr32'
body: |
bb.0:
%0:sgpr_32 = S_MOV_B32 16960
@@ -245,6 +253,8 @@ body: |
---
name: rcp_f16_imm
tracksRegLiveness: true
+machineFunctionInfo:
+ stackPtrOffsetReg: '$sgpr32'
body: |
bb.0:
%0:sgpr_32 = S_MOV_B32 15360
@@ -256,6 +266,8 @@ body: |
---
name: rcp_f16_literal
tracksRegLiveness: true
+machineFunctionInfo:
+ stackPtrOffsetReg: '$sgpr32'
body: |
bb.0:
%0:sgpr_32 = S_MOV_B32 16960
@@ -267,6 +279,8 @@ body: |
---
name: rsq_f16_imm
tracksRegLiveness: true
+machineFunctionInfo:
+ stackPtrOffsetReg: '$sgpr32'
body: |
bb.0:
%0:sgpr_32 = S_MOV_B32 15360
@@ -278,6 +292,8 @@ body: |
---
name: rsq_f16_literal
tracksRegLiveness: true
+machineFunctionInfo:
+ stackPtrOffsetReg: '$sgpr32'
body: |
bb.0:
%0:sgpr_32 = S_MOV_B32 16960
@@ -289,6 +305,8 @@ body: |
---
name: sqrt_f16_imm
tracksRegLiveness: true
+machineFunctionInfo:
+ stackPtrOffsetReg: '$sgpr32'
body: |
bb.0:
%0:sgpr_32 = S_MOV_B32 15360
@@ -300,6 +318,8 @@ body: |
---
name: sqrt_f16_literal
tracksRegLiveness: true
+machineFunctionInfo:
+ stackPtrOffsetReg: '$sgpr32'
body: |
bb.0:
%0:sgpr_32 = S_MOV_B32 16960
>From c6443cf6a086d08fde81587410939aed9c022606 Mon Sep 17 00:00:00 2001
From: Frederik Harwath <fharwath at amd.com>
Date: Tue, 18 Aug 2026 12:50:29 -0400
Subject: [PATCH 8/8] Add AssemblerPredicate in tablegen
---
llvm/lib/Target/AMDGPU/AMDGPU.td | 3 ++-
llvm/lib/Target/AMDGPU/VOP3Instructions.td | 16 +++++++---------
2 files changed, 9 insertions(+), 10 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.td b/llvm/lib/Target/AMDGPU/AMDGPU.td
index db6825580882b..a54fc0ee99a5c 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.td
@@ -1236,7 +1236,8 @@ defm NoF16PseudoScalarTransInlineConstants : AMDGPUSubtargetFeature<"no-f16-pseu
>;
def HasF16PseudoScalarTransWithInlineConstants :
- Predicate<"Subtarget->hasPseudoScalarTrans() && !Subtarget->hasNoF16PseudoScalarTransInlineConstants()">;
+ Predicate<"Subtarget->hasPseudoScalarTrans() && !Subtarget->hasNoF16PseudoScalarTransInlineConstants()">,
+ AssemblerPredicate<(all_of FeaturePseudoScalarTrans, (not FeatureNoF16PseudoScalarTransInlineConstants))>;
defm RestrictedSOffset : AMDGPUSubtargetFeature<"restricted-soffset",
"Has restricted SOffset (immediate not supported)."
diff --git a/llvm/lib/Target/AMDGPU/VOP3Instructions.td b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
index c3202cff3e8a4..0617511c0df70 100644
--- a/llvm/lib/Target/AMDGPU/VOP3Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
@@ -1986,16 +1986,14 @@ def VOP_Pseudo_Scalar_F16_NoInline : VOP_Pseudo_Scalar<SReg_32_XEXEC, SSrc_NoInl
// Define regular and "no inline constant" variant of a F16 pseudo
// scalar transcendental instruction.
multiclass VOP3PseudoScalarInst_F16<string opName> {
- let SubtargetPredicate = HasF16PseudoScalarTransWithInlineConstants,
- AssemblerPredicate = HasF16PseudoScalarTransWithInlineConstants,
- TRANS = 1, isReMaterializable = 1, SchedRW = [WritePseudoScalarTrans] in {
- defm NAME : VOP3PseudoScalarInst<opName, VOP_Pseudo_Scalar_F16>;
- }
+ let TRANS = 1, isReMaterializable = 1, SchedRW = [WritePseudoScalarTrans] in {
+ let SubtargetPredicate = HasF16PseudoScalarTransWithInlineConstants in {
+ defm NAME : VOP3PseudoScalarInst<opName, VOP_Pseudo_Scalar_F16>;
+ }
- let SubtargetPredicate = HasNoF16PseudoScalarTransInlineConstants,
- AssemblerPredicate = HasNoF16PseudoScalarTransInlineConstants,
- TRANS = 1, isReMaterializable = 1, SchedRW = [WritePseudoScalarTrans] in {
- defm !strconcat(NAME, "_noinline") : VOP3PseudoScalarInst<opName, VOP_Pseudo_Scalar_F16_NoInline>;
+ let SubtargetPredicate = HasNoF16PseudoScalarTransInlineConstants in {
+ defm !strconcat(NAME, "_noinline") : VOP3PseudoScalarInst<opName, VOP_Pseudo_Scalar_F16_NoInline>;
+ }
}
}
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