[llvm] [LV] Add cross-part load overlap heuristic for interleaving (PR #214500)

[Sergey Shcherbinin via llvm-commits]

SergeyShch01 wrote:

@fhahn,

> From the description, it is not clear if we already get the downstream CSE benefits? IIUC this would require more additional work to get benefits from the patch?

Thanks for pointing this out. 

This is the first patch in the series which is described in the RFC and reproduced below. It addresses only the simplest case:
detecting load redundancy that becomes explicit after interleaving and using it to guide the IC=1 to IC=2 decision. Existing downstream passes may remove the exposed redundancy, but this patch does not guarantee that they will do so (it depends on the GEP structure which can compliate redundancy recognition downstream).

Guaranteed elimination is provided by the final explicit post-unroll apply patch, which is step 6 in the plan below.

Patch plan:
1. Add a minimal IC=1 to IC=2 heuristic for a single block, exact part-aware
   SCEV load equality and no writes between provider and redundant load.
2. Support same-block writes when AA/SCEV proves that they do not clobber the
   load.
3. Support multi-block CFGs with dominance, bounded reachability and
   cross-block clobber proofs.
4. Add generic and induction congruence together with complete supported load
   shapes and shared/single-position unroll semantics.
5. Add affine propagation and secondary load discovery.
6. Add explicit post-unroll load apply both when cross-part CSE selects IC=2
   and when IC=2 was selected earlier by another heuristic or by the user.

I will also clarify the PR description so that downstream CSE does not imply that this first patch already guarantees elimination.

https://github.com/llvm/llvm-project/pull/214500