[llvm] [AMDGPU][GlobalISel] Fix denormal handling in legalizeFlogUnsafe (PR #217008)
Arseniy Obolenskiy via llvm-commits
llvm-commits at lists.llvm.org
Tue Aug 18 05:19:15 PDT 2026
https://github.com/aobolensk created https://github.com/llvm/llvm-project/pull/217008
The scaled input was computed but never used, so the ldexp scaling was dead and denormals produced -inf
>From ff982ee09b44afd06d40cb8dea42202f52e99ffc Mon Sep 17 00:00:00 2001
From: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: Tue, 18 Aug 2026 14:16:37 +0200
Subject: [PATCH] [AMDGPU][GlobalISel] Fix denormal handling in
legalizeFlogUnsafe
The scaled input was computed but never used, so the ldexp scaling was dead and denormals produced -inf
---
.../lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 2 +-
llvm/test/CodeGen/AMDGPU/llvm.log.ll | 185 ++++++++++++------
llvm/test/CodeGen/AMDGPU/llvm.log10.ll | 185 ++++++++++++------
3 files changed, 241 insertions(+), 131 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index 38b88d87051c6..42048a9bb3105 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -3852,7 +3852,7 @@ bool AMDGPULegalizerInfo::legalizeFlogUnsafe(MachineIRBuilder &B, Register Dst,
auto [ScaledInput, IsScaled] = getScaledLogInput(B, Src, Flags);
if (ScaledInput) {
auto LogSrc = B.buildIntrinsic(Intrinsic::amdgcn_log, {Ty})
- .addUse(Src)
+ .addUse(ScaledInput)
.setMIFlags(Flags);
auto ScaledResultOffset = B.buildFConstant(Ty, -32.0 * Log2BaseInverted);
auto Zero = B.buildFConstant(Ty, 0.0);
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.log.ll b/llvm/test/CodeGen/AMDGPU/llvm.log.ll
index ee51803a1df50..0b8c2a75d6806 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.log.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.log.ll
@@ -3627,13 +3627,16 @@ define float @v_log_f32_fast(float %in) {
; SI-GISEL-LABEL: v_log_f32_fast:
; SI-GISEL: ; %bb.0:
; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-GISEL-NEXT: v_log_f32_e32 v2, v0
; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
-; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0xc1b17218
; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
-; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3f317218
-; SI-GISEL-NEXT: v_fma_f32 v0, v2, v1, v0
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc1b17218
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x3f317218
+; SI-GISEL-NEXT: v_fma_f32 v0, v0, v2, v1
; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; VI-SDAG-LABEL: v_log_f32_fast:
@@ -3653,13 +3656,16 @@ define float @v_log_f32_fast(float %in) {
; VI-GISEL-LABEL: v_log_f32_fast:
; VI-GISEL: ; %bb.0:
; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-GISEL-NEXT: v_log_f32_e32 v2, v0
; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0xc1b17218
; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
-; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317218, v2
-; VI-GISEL-NEXT: v_add_f32_e32 v0, v1, v0
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc1b17218
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0
+; VI-GISEL-NEXT: v_add_f32_e32 v0, v0, v1
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_log_f32_fast:
@@ -3679,13 +3685,16 @@ define float @v_log_f32_fast(float %in) {
; GFX900-GISEL-LABEL: v_log_f32_fast:
; GFX900-GISEL: ; %bb.0:
; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-GISEL-NEXT: v_log_f32_e32 v2, v0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0xc1b17218
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3f317218
-; GFX900-GISEL-NEXT: v_fma_f32 v0, v2, v1, v0
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0xc1b17218
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x3f317218
+; GFX900-GISEL-NEXT: v_fma_f32 v0, v0, v2, v1
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-SDAG-LABEL: v_log_f32_fast:
@@ -3704,8 +3713,13 @@ define float @v_log_f32_fast(float %in) {
; GFX1100-GISEL-LABEL: v_log_f32_fast:
; GFX1100-GISEL: ; %bb.0:
; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-GISEL-NEXT: v_log_f32_e32 v1, v0
; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v1, v0
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 0xc1b17218, vcc_lo
; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v0, 0x3f317218, v1
@@ -3942,13 +3956,16 @@ define float @v_log_f32_afn(float %in) {
; SI-GISEL-LABEL: v_log_f32_afn:
; SI-GISEL: ; %bb.0:
; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-GISEL-NEXT: v_log_f32_e32 v2, v0
; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
-; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0xc1b17218
; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
-; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3f317218
-; SI-GISEL-NEXT: v_fma_f32 v0, v2, v1, v0
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc1b17218
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x3f317218
+; SI-GISEL-NEXT: v_fma_f32 v0, v0, v2, v1
; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; VI-SDAG-LABEL: v_log_f32_afn:
@@ -3968,13 +3985,16 @@ define float @v_log_f32_afn(float %in) {
; VI-GISEL-LABEL: v_log_f32_afn:
; VI-GISEL: ; %bb.0:
; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-GISEL-NEXT: v_log_f32_e32 v2, v0
; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0xc1b17218
; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
-; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317218, v2
-; VI-GISEL-NEXT: v_add_f32_e32 v0, v1, v0
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc1b17218
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0
+; VI-GISEL-NEXT: v_add_f32_e32 v0, v0, v1
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_log_f32_afn:
@@ -3994,13 +4014,16 @@ define float @v_log_f32_afn(float %in) {
; GFX900-GISEL-LABEL: v_log_f32_afn:
; GFX900-GISEL: ; %bb.0:
; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-GISEL-NEXT: v_log_f32_e32 v2, v0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0xc1b17218
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3f317218
-; GFX900-GISEL-NEXT: v_fma_f32 v0, v2, v1, v0
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0xc1b17218
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x3f317218
+; GFX900-GISEL-NEXT: v_fma_f32 v0, v0, v2, v1
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-SDAG-LABEL: v_log_f32_afn:
@@ -4019,8 +4042,13 @@ define float @v_log_f32_afn(float %in) {
; GFX1100-GISEL-LABEL: v_log_f32_afn:
; GFX1100-GISEL: ; %bb.0:
; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-GISEL-NEXT: v_log_f32_e32 v1, v0
; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v1, v0
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 0xc1b17218, vcc_lo
; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v0, 0x3f317218, v1
@@ -4086,13 +4114,16 @@ define float @v_log_f32_afn_dynamic(float %in) #1 {
; SI-GISEL-LABEL: v_log_f32_afn_dynamic:
; SI-GISEL: ; %bb.0:
; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-GISEL-NEXT: v_log_f32_e32 v2, v0
; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
-; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0xc1b17218
; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
-; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3f317218
-; SI-GISEL-NEXT: v_fma_f32 v0, v2, v1, v0
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc1b17218
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x3f317218
+; SI-GISEL-NEXT: v_fma_f32 v0, v0, v2, v1
; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; VI-SDAG-LABEL: v_log_f32_afn_dynamic:
@@ -4112,13 +4143,16 @@ define float @v_log_f32_afn_dynamic(float %in) #1 {
; VI-GISEL-LABEL: v_log_f32_afn_dynamic:
; VI-GISEL: ; %bb.0:
; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-GISEL-NEXT: v_log_f32_e32 v2, v0
; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0xc1b17218
; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
-; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317218, v2
-; VI-GISEL-NEXT: v_add_f32_e32 v0, v1, v0
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc1b17218
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0
+; VI-GISEL-NEXT: v_add_f32_e32 v0, v0, v1
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_log_f32_afn_dynamic:
@@ -4138,13 +4172,16 @@ define float @v_log_f32_afn_dynamic(float %in) #1 {
; GFX900-GISEL-LABEL: v_log_f32_afn_dynamic:
; GFX900-GISEL: ; %bb.0:
; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-GISEL-NEXT: v_log_f32_e32 v2, v0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0xc1b17218
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3f317218
-; GFX900-GISEL-NEXT: v_fma_f32 v0, v2, v1, v0
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0xc1b17218
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x3f317218
+; GFX900-GISEL-NEXT: v_fma_f32 v0, v0, v2, v1
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-SDAG-LABEL: v_log_f32_afn_dynamic:
@@ -4163,8 +4200,13 @@ define float @v_log_f32_afn_dynamic(float %in) #1 {
; GFX1100-GISEL-LABEL: v_log_f32_afn_dynamic:
; GFX1100-GISEL: ; %bb.0:
; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-GISEL-NEXT: v_log_f32_e32 v1, v0
; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v1, v0
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 0xc1b17218, vcc_lo
; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v0, 0x3f317218, v1
@@ -4201,13 +4243,16 @@ define float @v_fabs_log_f32_afn(float %in) {
; SI-GISEL-LABEL: v_fabs_log_f32_afn:
; SI-GISEL: ; %bb.0:
; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-GISEL-NEXT: v_log_f32_e64 v2, |v0|
; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
-; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0xc1b17218
; SI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
-; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3f317218
-; SI-GISEL-NEXT: v_fma_f32 v0, v2, v1, v0
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; SI-GISEL-NEXT: v_ldexp_f32_e64 v0, |v0|, v1
+; SI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc1b17218
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x3f317218
+; SI-GISEL-NEXT: v_fma_f32 v0, v0, v2, v1
; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; VI-SDAG-LABEL: v_fabs_log_f32_afn:
@@ -4227,13 +4272,16 @@ define float @v_fabs_log_f32_afn(float %in) {
; VI-GISEL-LABEL: v_fabs_log_f32_afn:
; VI-GISEL: ; %bb.0:
; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-GISEL-NEXT: v_log_f32_e64 v2, |v0|
; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0xc1b17218
; VI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
-; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317218, v2
-; VI-GISEL-NEXT: v_add_f32_e32 v0, v1, v0
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; VI-GISEL-NEXT: v_ldexp_f32 v0, |v0|, v1
+; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc1b17218
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3f317218, v0
+; VI-GISEL-NEXT: v_add_f32_e32 v0, v0, v1
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_fabs_log_f32_afn:
@@ -4253,13 +4301,16 @@ define float @v_fabs_log_f32_afn(float %in) {
; GFX900-GISEL-LABEL: v_fabs_log_f32_afn:
; GFX900-GISEL: ; %bb.0:
; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-GISEL-NEXT: v_log_f32_e64 v2, |v0|
; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0xc1b17218
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3f317218
-; GFX900-GISEL-NEXT: v_fma_f32 v0, v2, v1, v0
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, |v0|, v1
+; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0xc1b17218
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x3f317218
+; GFX900-GISEL-NEXT: v_fma_f32 v0, v0, v2, v1
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-SDAG-LABEL: v_fabs_log_f32_afn:
@@ -4279,9 +4330,13 @@ define float @v_fabs_log_f32_afn(float %in) {
; GFX1100-GISEL-LABEL: v_fabs_log_f32_afn:
; GFX1100-GISEL: ; %bb.0:
; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-GISEL-NEXT: v_log_f32_e64 v1, |v0|
; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0
+; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, |v0|, v1
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v1, v0
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 0xc1b17218, s0
; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v0, 0x3f317218, v1
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.log10.ll b/llvm/test/CodeGen/AMDGPU/llvm.log10.ll
index 81e165d0e5972..8fcc16c2e6f56 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.log10.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.log10.ll
@@ -3627,13 +3627,16 @@ define float @v_log10_f32_fast(float %in) {
; SI-GISEL-LABEL: v_log10_f32_fast:
; SI-GISEL: ; %bb.0:
; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-GISEL-NEXT: v_log_f32_e32 v2, v0
; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
-; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0xc11a209b
; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
-; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3e9a209b
-; SI-GISEL-NEXT: v_fma_f32 v0, v2, v1, v0
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc11a209b
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x3e9a209b
+; SI-GISEL-NEXT: v_fma_f32 v0, v0, v2, v1
; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; VI-SDAG-LABEL: v_log10_f32_fast:
@@ -3653,13 +3656,16 @@ define float @v_log10_f32_fast(float %in) {
; VI-GISEL-LABEL: v_log10_f32_fast:
; VI-GISEL: ; %bb.0:
; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-GISEL-NEXT: v_log_f32_e32 v2, v0
; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0xc11a209b
; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
-; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209b, v2
-; VI-GISEL-NEXT: v_add_f32_e32 v0, v1, v0
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc11a209b
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0
+; VI-GISEL-NEXT: v_add_f32_e32 v0, v0, v1
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_log10_f32_fast:
@@ -3679,13 +3685,16 @@ define float @v_log10_f32_fast(float %in) {
; GFX900-GISEL-LABEL: v_log10_f32_fast:
; GFX900-GISEL: ; %bb.0:
; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-GISEL-NEXT: v_log_f32_e32 v2, v0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0xc11a209b
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3e9a209b
-; GFX900-GISEL-NEXT: v_fma_f32 v0, v2, v1, v0
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0xc11a209b
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x3e9a209b
+; GFX900-GISEL-NEXT: v_fma_f32 v0, v0, v2, v1
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-SDAG-LABEL: v_log10_f32_fast:
@@ -3704,8 +3713,13 @@ define float @v_log10_f32_fast(float %in) {
; GFX1100-GISEL-LABEL: v_log10_f32_fast:
; GFX1100-GISEL: ; %bb.0:
; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-GISEL-NEXT: v_log_f32_e32 v1, v0
; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v1, v0
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 0xc11a209b, vcc_lo
; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v0, 0x3e9a209b, v1
@@ -3942,13 +3956,16 @@ define float @v_log10_f32_afn(float %in) {
; SI-GISEL-LABEL: v_log10_f32_afn:
; SI-GISEL: ; %bb.0:
; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-GISEL-NEXT: v_log_f32_e32 v2, v0
; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
-; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0xc11a209b
; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
-; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3e9a209b
-; SI-GISEL-NEXT: v_fma_f32 v0, v2, v1, v0
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc11a209b
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x3e9a209b
+; SI-GISEL-NEXT: v_fma_f32 v0, v0, v2, v1
; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; VI-SDAG-LABEL: v_log10_f32_afn:
@@ -3968,13 +3985,16 @@ define float @v_log10_f32_afn(float %in) {
; VI-GISEL-LABEL: v_log10_f32_afn:
; VI-GISEL: ; %bb.0:
; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-GISEL-NEXT: v_log_f32_e32 v2, v0
; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0xc11a209b
; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
-; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209b, v2
-; VI-GISEL-NEXT: v_add_f32_e32 v0, v1, v0
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc11a209b
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0
+; VI-GISEL-NEXT: v_add_f32_e32 v0, v0, v1
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_log10_f32_afn:
@@ -3994,13 +4014,16 @@ define float @v_log10_f32_afn(float %in) {
; GFX900-GISEL-LABEL: v_log10_f32_afn:
; GFX900-GISEL: ; %bb.0:
; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-GISEL-NEXT: v_log_f32_e32 v2, v0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0xc11a209b
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3e9a209b
-; GFX900-GISEL-NEXT: v_fma_f32 v0, v2, v1, v0
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0xc11a209b
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x3e9a209b
+; GFX900-GISEL-NEXT: v_fma_f32 v0, v0, v2, v1
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-SDAG-LABEL: v_log10_f32_afn:
@@ -4019,8 +4042,13 @@ define float @v_log10_f32_afn(float %in) {
; GFX1100-GISEL-LABEL: v_log10_f32_afn:
; GFX1100-GISEL: ; %bb.0:
; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-GISEL-NEXT: v_log_f32_e32 v1, v0
; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v1, v0
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 0xc11a209b, vcc_lo
; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v0, 0x3e9a209b, v1
@@ -4086,13 +4114,16 @@ define float @v_log10_f32_afn_dynamic(float %in) #1 {
; SI-GISEL-LABEL: v_log10_f32_afn_dynamic:
; SI-GISEL: ; %bb.0:
; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-GISEL-NEXT: v_log_f32_e32 v2, v0
; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
-; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0xc11a209b
; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
-; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3e9a209b
-; SI-GISEL-NEXT: v_fma_f32 v0, v2, v1, v0
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc11a209b
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x3e9a209b
+; SI-GISEL-NEXT: v_fma_f32 v0, v0, v2, v1
; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; VI-SDAG-LABEL: v_log10_f32_afn_dynamic:
@@ -4112,13 +4143,16 @@ define float @v_log10_f32_afn_dynamic(float %in) #1 {
; VI-GISEL-LABEL: v_log10_f32_afn_dynamic:
; VI-GISEL: ; %bb.0:
; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-GISEL-NEXT: v_log_f32_e32 v2, v0
; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0xc11a209b
; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
-; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209b, v2
-; VI-GISEL-NEXT: v_add_f32_e32 v0, v1, v0
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc11a209b
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0
+; VI-GISEL-NEXT: v_add_f32_e32 v0, v0, v1
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_log10_f32_afn_dynamic:
@@ -4138,13 +4172,16 @@ define float @v_log10_f32_afn_dynamic(float %in) #1 {
; GFX900-GISEL-LABEL: v_log10_f32_afn_dynamic:
; GFX900-GISEL: ; %bb.0:
; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-GISEL-NEXT: v_log_f32_e32 v2, v0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0xc11a209b
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3e9a209b
-; GFX900-GISEL-NEXT: v_fma_f32 v0, v2, v1, v0
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0xc11a209b
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x3e9a209b
+; GFX900-GISEL-NEXT: v_fma_f32 v0, v0, v2, v1
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-SDAG-LABEL: v_log10_f32_afn_dynamic:
@@ -4163,8 +4200,13 @@ define float @v_log10_f32_afn_dynamic(float %in) #1 {
; GFX1100-GISEL-LABEL: v_log10_f32_afn_dynamic:
; GFX1100-GISEL: ; %bb.0:
; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-GISEL-NEXT: v_log_f32_e32 v1, v0
; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v1, v0
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 0xc11a209b, vcc_lo
; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v0, 0x3e9a209b, v1
@@ -4201,13 +4243,16 @@ define float @v_fabs_log10_f32_afn(float %in) {
; SI-GISEL-LABEL: v_fabs_log10_f32_afn:
; SI-GISEL: ; %bb.0:
; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-GISEL-NEXT: v_log_f32_e64 v2, |v0|
; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
-; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0xc11a209b
; SI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
-; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3e9a209b
-; SI-GISEL-NEXT: v_fma_f32 v0, v2, v1, v0
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; SI-GISEL-NEXT: v_ldexp_f32_e64 v0, |v0|, v1
+; SI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc11a209b
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x3e9a209b
+; SI-GISEL-NEXT: v_fma_f32 v0, v0, v2, v1
; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; VI-SDAG-LABEL: v_fabs_log10_f32_afn:
@@ -4227,13 +4272,16 @@ define float @v_fabs_log10_f32_afn(float %in) {
; VI-GISEL-LABEL: v_fabs_log10_f32_afn:
; VI-GISEL: ; %bb.0:
; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-GISEL-NEXT: v_log_f32_e64 v2, |v0|
; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
-; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0xc11a209b
; VI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
-; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209b, v2
-; VI-GISEL-NEXT: v_add_f32_e32 v0, v1, v0
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; VI-GISEL-NEXT: v_ldexp_f32 v0, |v0|, v1
+; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc11a209b
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3e9a209b, v0
+; VI-GISEL-NEXT: v_add_f32_e32 v0, v0, v1
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_fabs_log10_f32_afn:
@@ -4253,13 +4301,16 @@ define float @v_fabs_log10_f32_afn(float %in) {
; GFX900-GISEL-LABEL: v_fabs_log10_f32_afn:
; GFX900-GISEL: ; %bb.0:
; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-GISEL-NEXT: v_log_f32_e64 v2, |v0|
; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0xc11a209b
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3e9a209b
-; GFX900-GISEL-NEXT: v_fma_f32 v0, v2, v1, v0
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, |v0|, v1
+; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0xc11a209b
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x3e9a209b
+; GFX900-GISEL-NEXT: v_fma_f32 v0, v0, v2, v1
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX1100-SDAG-LABEL: v_fabs_log10_f32_afn:
@@ -4279,9 +4330,13 @@ define float @v_fabs_log10_f32_afn(float %in) {
; GFX1100-GISEL-LABEL: v_fabs_log10_f32_afn:
; GFX1100-GISEL: ; %bb.0:
; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-GISEL-NEXT: v_log_f32_e64 v1, |v0|
; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0
+; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, |v0|, v1
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v1, v0
; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 0xc11a209b, s0
; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v0, 0x3e9a209b, v1
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