[llvm] [AArch64][SVE] Lower extended v2i8 loads using SVE. (PR #217006)

Tue Aug 18 05:15:05 PDT 2026

llvmorg-github-actions[bot] wrote:




@llvm/pr-subscribers-backend-aarch64

Author: Sander de Smalen (sdesmalen-arm)

<details>
<summary>Changes</summary>

Loads of v2i8 are promoted to v2i32, which requires two extend operations; v2i8 -> v2i16, then v2i16 -> v2i32. This comes largely for free when using SVE's extending loads.

---
Full diff: https://github.com/llvm/llvm-project/pull/217006.diff


5 Files Affected:

- (modified) llvm/lib/Target/AArch64/AArch64ISelLowering.cpp (+8-3) 
- (modified) llvm/test/CodeGen/AArch64/neon-extadd-extract.ll (+4-5) 
- (modified) llvm/test/CodeGen/AArch64/sve-fixed-length-masked-gather.ll (+5-7) 
- (modified) llvm/test/CodeGen/AArch64/sve-fixed-length-masked-scatter.ll (+2-3) 
- (modified) llvm/test/CodeGen/AArch64/sve-insert-vector-to-predicate-load.ll (+2-4) 


``````````diff

diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 89a9249d11412..d707f9d061de3 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -8911,11 +8911,16 @@ SDValue AArch64TargetLowering::LowerOperation(SDValue Op,
     return LowerTRUNCATE(Op, DAG);
   case ISD::MLOAD:
     return LowerMLOAD(Op, DAG);
-  case ISD::LOAD:
-    if (useSVEForFixedLengthVectorVT(Op.getValueType(),
-                                     !Subtarget->isNeonAvailable()))
+  case ISD::LOAD: {
+    // Extending loads of v2i8 -> v2i32 are bettered lowered using SVE's
+    // extending load instructions as they otherwise require 2 instructions to
+    // promote to v2i32.
+    bool OverrideNeon = !Subtarget->isNeonAvailable() ||
+                        cast<LoadSDNode>(Op)->getMemoryVT() == MVT::v2i8;
+    if (useSVEForFixedLengthVectorVT(Op.getValueType(), OverrideNeon))
       return LowerFixedLengthVectorLoadToSVE(Op, DAG);
     return LowerLOAD(Op, DAG);
+  }
   case ISD::ADD:
   case ISD::AND:
   case ISD::SUB:
diff --git a/llvm/test/CodeGen/AArch64/neon-extadd-extract.ll b/llvm/test/CodeGen/AArch64/neon-extadd-extract.ll
index b35511dd4ab69..1fd0728108d92 100644
--- a/llvm/test/CodeGen/AArch64/neon-extadd-extract.ll
+++ b/llvm/test/CodeGen/AArch64/neon-extadd-extract.ll
@@ -775,12 +775,11 @@ entry:
 define <2 x i8> @extract_scalable_vec() vscale_range(1,16) "target-features"="+sve" {
 ; CHECK-SD-LABEL: extract_scalable_vec:
 ; CHECK-SD:       // %bb.0: // %entry
+; CHECK-SD-NEXT:    ptrue p0.s, vl2
 ; CHECK-SD-NEXT:    mov x8, xzr
-; CHECK-SD-NEXT:    index z1.s, #2, #3
-; CHECK-SD-NEXT:    ldr h0, [x8]
-; CHECK-SD-NEXT:    ushll v0.8h, v0.8b, #0
-; CHECK-SD-NEXT:    ushll v0.4s, v0.4h, #0
-; CHECK-SD-NEXT:    mul v0.2s, v0.2s, v1.2s
+; CHECK-SD-NEXT:    index z0.s, #2, #3
+; CHECK-SD-NEXT:    ld1b { z1.s }, p0/z, [x8]
+; CHECK-SD-NEXT:    mul v0.2s, v1.2s, v0.2s
 ; CHECK-SD-NEXT:    ret
 ;
 ; CHECK-GI-LABEL: extract_scalable_vec:
diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-masked-gather.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-masked-gather.ll
index eb938224b5375..1830f046308b6 100644
--- a/llvm/test/CodeGen/AArch64/sve-fixed-length-masked-gather.ll
+++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-masked-gather.ll
@@ -12,16 +12,14 @@ target triple = "aarch64-unknown-linux-gnu"
 define void @masked_gather_v2i8(ptr %a, ptr %b) vscale_range(2,0) #0 {
 ; CHECK-LABEL: masked_gather_v2i8:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    ldr h0, [x0]
-; CHECK-NEXT:    ptrue p0.d, vl2
-; CHECK-NEXT:    ushll v0.8h, v0.8b, #0
-; CHECK-NEXT:    ushll v0.4s, v0.4h, #0
+; CHECK-NEXT:    ptrue p0.s, vl2
+; CHECK-NEXT:    ptrue p1.d, vl2
+; CHECK-NEXT:    ld1b { z0.s }, p0/z, [x0]
 ; CHECK-NEXT:    cmeq v0.2s, v0.2s, #0
 ; CHECK-NEXT:    sshll v0.2d, v0.2s, #0
-; CHECK-NEXT:    cmpne p1.d, p0/z, z0.d, #0
+; CHECK-NEXT:    cmpne p2.d, p1/z, z0.d, #0
 ; CHECK-NEXT:    ldr q0, [x1]
-; CHECK-NEXT:    ptrue p0.s, vl2
-; CHECK-NEXT:    ld1b { z0.d }, p1/z, [z0.d]
+; CHECK-NEXT:    ld1b { z0.d }, p2/z, [z0.d]
 ; CHECK-NEXT:    xtn v0.2s, v0.2d
 ; CHECK-NEXT:    st1b { z0.s }, p0, [x0]
 ; CHECK-NEXT:    ret
diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-masked-scatter.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-masked-scatter.ll
index 07239f3c52204..3666496a1eacb 100644
--- a/llvm/test/CodeGen/AArch64/sve-fixed-length-masked-scatter.ll
+++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-masked-scatter.ll
@@ -12,10 +12,9 @@ target triple = "aarch64-unknown-linux-gnu"
 define void @masked_scatter_v2i8(ptr %a, ptr %b) vscale_range(2,0) #0 {
 ; CHECK-LABEL: masked_scatter_v2i8:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    ldr h0, [x0]
+; CHECK-NEXT:    ptrue p0.s, vl2
+; CHECK-NEXT:    ld1b { z0.s }, p0/z, [x0]
 ; CHECK-NEXT:    ptrue p0.d, vl2
-; CHECK-NEXT:    ushll v0.8h, v0.8b, #0
-; CHECK-NEXT:    ushll v0.4s, v0.4h, #0
 ; CHECK-NEXT:    cmeq v1.2s, v0.2s, #0
 ; CHECK-NEXT:    ushll v0.2d, v0.2s, #0
 ; CHECK-NEXT:    sshll v1.2d, v1.2s, #0
diff --git a/llvm/test/CodeGen/AArch64/sve-insert-vector-to-predicate-load.ll b/llvm/test/CodeGen/AArch64/sve-insert-vector-to-predicate-load.ll
index ddf502e5eb91a..a04fe01fa5843 100644
--- a/llvm/test/CodeGen/AArch64/sve-insert-vector-to-predicate-load.ll
+++ b/llvm/test/CodeGen/AArch64/sve-insert-vector-to-predicate-load.ll
@@ -172,11 +172,9 @@ define <vscale x 16 x i1> @pred_load_neg5(ptr %addr, <vscale x 2 x i8> %passthru
 define <vscale x 16 x i1> @pred_load_v2i8_multiuse(ptr %addr) #0 {
 ; CHECK-LABEL: pred_load_v2i8_multiuse:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    ldr h0, [x0]
+; CHECK-NEXT:    ptrue p0.d
+; CHECK-NEXT:    ld1b { z0.d }, p0/z, [x0]
 ; CHECK-NEXT:    ldr p0, [x0]
-; CHECK-NEXT:    ushll v0.8h, v0.8b, #0
-; CHECK-NEXT:    ushll v0.4s, v0.4h, #0
-; CHECK-NEXT:    ushll v0.2d, v0.2s, #0
 ; CHECK-NEXT:    // fake_use: $z0
 ; CHECK-NEXT:    ret
   %load = load <2 x i8>, ptr %addr, align 4

``````````

</details>


https://github.com/llvm/llvm-project/pull/217006
