[llvm] [X86] Add test coverage for #215069 (PR #216982)

[Simon Pilgrim via llvm-commits]

https://github.com/RKSimon created https://github.com/llvm/llvm-project/pull/216982

None

>From dac7b2178e39b9274ef734c97add951d19b6a468 Mon Sep 17 00:00:00 2001
From: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: Tue, 18 Aug 2026 11:39:31 +0100
Subject: [PATCH] [X86] Add test coverage for #215069

---
 llvm/test/CodeGen/X86/vector-reduce-xor.ll | 63 +++++++++-------------
 1 file changed, 26 insertions(+), 37 deletions(-)

diff --git a/llvm/test/CodeGen/X86/vector-reduce-xor.ll b/llvm/test/CodeGen/X86/vector-reduce-xor.ll
index b8009e5b3daed..6122c6ea2104c 100644
--- a/llvm/test/CodeGen/X86/vector-reduce-xor.ll
+++ b/llvm/test/CodeGen/X86/vector-reduce-xor.ll
@@ -1,17 +1,17 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=i686--   -mattr=+sse2     | FileCheck %s --check-prefixes=SSE,X86-SSE,SSE2,X86-SSE2
-; RUN: llc < %s -mtriple=x86_64-- -mattr=+sse2     | FileCheck %s --check-prefixes=SSE,X64-SSE,SSE2,X64-SSE2
-; RUN: llc < %s -mtriple=i686--   -mattr=+sse4.1   | FileCheck %s --check-prefixes=SSE,X86-SSE,SSE4,X86-SSE4
-; RUN: llc < %s -mtriple=x86_64-- -mattr=+sse4.1   | FileCheck %s --check-prefixes=SSE,X64-SSE,SSE4,X64-SSE4
-; RUN: llc < %s -mtriple=i686--   -mattr=+sse4.2   | FileCheck %s --check-prefixes=SSE,X86-SSE,SSE4,X86-SSE4
-; RUN: llc < %s -mtriple=x86_64-- -mattr=+sse4.2   | FileCheck %s --check-prefixes=SSE,X64-SSE,SSE4,X64-SSE4
-; RUN: llc < %s -mtriple=i686--   -mattr=+avx      | FileCheck %s --check-prefixes=AVX,AVX1OR2,AVX1,X86-AVX1
-; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx      | FileCheck %s --check-prefixes=AVX,AVX1OR2,AVX1,X64-AVX1
-; RUN: llc < %s -mtriple=i686--   -mattr=+avx2     | FileCheck %s --check-prefixes=AVX,AVX1OR2,AVX2,X86-AVX2
-; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx2     | FileCheck %s --check-prefixes=AVX,AVX1OR2,AVX2,X64-AVX2
-; RUN: llc < %s -mtriple=x86_64-  -mattr=+avx512f  | FileCheck %s --check-prefixes=AVX,AVX512,AVX512F
-; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx512f,+avx512bw | FileCheck %s --check-prefixes=AVX,AVX512,AVX512BW
-; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx512f,+avx512bw,+avx512dq,+avx512vl | FileCheck %s --check-prefixes=AVX,AVX512,AVX512VL
+; RUN: llc < %s -mtriple=i686--   -mattr=+sse2     | FileCheck %s --check-prefixes=CHECK,SSE,X86-SSE,SSE2,X86-SSE2
+; RUN: llc < %s -mtriple=x86_64-- -mattr=+sse2     | FileCheck %s --check-prefixes=CHECK,SSE,X64-SSE,SSE2,X64-SSE2
+; RUN: llc < %s -mtriple=i686--   -mattr=+sse4.1   | FileCheck %s --check-prefixes=CHECK,SSE,X86-SSE,SSE4,X86-SSE4
+; RUN: llc < %s -mtriple=x86_64-- -mattr=+sse4.1   | FileCheck %s --check-prefixes=CHECK,SSE,X64-SSE,SSE4,X64-SSE4
+; RUN: llc < %s -mtriple=i686--   -mattr=+sse4.2   | FileCheck %s --check-prefixes=CHECK,SSE,X86-SSE,SSE4,X86-SSE4
+; RUN: llc < %s -mtriple=x86_64-- -mattr=+sse4.2   | FileCheck %s --check-prefixes=CHECK,SSE,X64-SSE,SSE4,X64-SSE4
+; RUN: llc < %s -mtriple=i686--   -mattr=+avx      | FileCheck %s --check-prefixes=CHECK,AVX,AVX1OR2,AVX1,X86-AVX1
+; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx      | FileCheck %s --check-prefixes=CHECK,AVX,AVX1OR2,AVX1,X64-AVX1
+; RUN: llc < %s -mtriple=i686--   -mattr=+avx2     | FileCheck %s --check-prefixes=CHECK,AVX,AVX1OR2,AVX2,X86-AVX2
+; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx2     | FileCheck %s --check-prefixes=CHECK,AVX,AVX1OR2,AVX2,X64-AVX2
+; RUN: llc < %s -mtriple=x86_64-  -mattr=+avx512f  | FileCheck %s --check-prefixes=CHECK,AVX,AVX512,AVX512F
+; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx512f,+avx512bw | FileCheck %s --check-prefixes=CHECK,AVX,AVX512,AVX512BW
+; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx512f,+avx512bw,+avx512dq,+avx512vl | FileCheck %s --check-prefixes=CHECK,AVX,AVX512,AVX512VL
 
 ;
 ; vXi64
@@ -1557,31 +1557,20 @@ define i8 @test_v128i8(<128 x i8> %a0) nounwind {
   ret i8 %1
 }
 
-declare i64 @llvm.vector.reduce.xor.v2i64(<2 x i64>)
-declare i64 @llvm.vector.reduce.xor.v4i64(<4 x i64>)
-declare i64 @llvm.vector.reduce.xor.v8i64(<8 x i64>)
-declare i64 @llvm.vector.reduce.xor.v16i64(<16 x i64>)
-
-declare i32 @llvm.vector.reduce.xor.v2i32(<2 x i32>)
-declare i32 @llvm.vector.reduce.xor.v4i32(<4 x i32>)
-declare i32 @llvm.vector.reduce.xor.v8i32(<8 x i32>)
-declare i32 @llvm.vector.reduce.xor.v16i32(<16 x i32>)
-declare i32 @llvm.vector.reduce.xor.v32i32(<32 x i32>)
-
-declare i16 @llvm.vector.reduce.xor.v2i16(<2 x i16>)
-declare i16 @llvm.vector.reduce.xor.v4i16(<4 x i16>)
-declare i16 @llvm.vector.reduce.xor.v8i16(<8 x i16>)
-declare i16 @llvm.vector.reduce.xor.v16i16(<16 x i16>)
-declare i16 @llvm.vector.reduce.xor.v32i16(<32 x i16>)
-declare i16 @llvm.vector.reduce.xor.v64i16(<64 x i16>)
+define i32 @PR215069() {
+; CHECK-LABEL: PR215069:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movb $7, %cl
+; CHECK-NEXT:    xorl %eax, %eax
+; CHECK-NEXT:    testb %cl, %cl
+; CHECK-NEXT:    setnp %al
+; CHECK-NEXT:    ret{{[l|q]}}
+  %i0 = insertelement <4 x i32> zeroinitializer, i32 0, i64 0
+  %i1 = xor <4 x i32> %i0, <i32 -1, i32 -1, i32 -1, i32 0>
+  %i2 = call i32 @llvm.vector.reduce.xor.v4i32(<4 x i32> %i1)
+  ret i32 %i2
+}
 
-declare i8 @llvm.vector.reduce.xor.v2i8(<2 x i8>)
-declare i8 @llvm.vector.reduce.xor.v4i8(<4 x i8>)
-declare i8 @llvm.vector.reduce.xor.v8i8(<8 x i8>)
-declare i8 @llvm.vector.reduce.xor.v16i8(<16 x i8>)
-declare i8 @llvm.vector.reduce.xor.v32i8(<32 x i8>)
-declare i8 @llvm.vector.reduce.xor.v64i8(<64 x i8>)
-declare i8 @llvm.vector.reduce.xor.v128i8(<128 x i8>)
 ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
 ; AVX1OR2: {{.*}}
 ; AVX512BW: {{.*}}