[llvm] 99cc412 - [AArch64] Combine shift and truncate into deinterleave. (#216060)
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Tue Aug 18 03:29:05 PDT 2026
Author: Sander de Smalen
Date: 2026-08-18T11:29:01+01:00
New Revision: 99cc412512f33bac30966e5f23cf40336c7c7916
URL: https://github.com/llvm/llvm-project/commit/99cc412512f33bac30966e5f23cf40336c7c7916
DIFF: https://github.com/llvm/llvm-project/commit/99cc412512f33bac30966e5f23cf40336c7c7916.diff
LOG: [AArch64] Combine shift and truncate into deinterleave. (#216060)
This is an alternative approach to #213252, from which I've taken some
of the tests.
Co-authored-by: Jacob Crawley <jacob.crawley at arm.com>
Added:
llvm/test/CodeGen/AArch64/sve-shift-trunc-combine.ll
Modified:
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 89a9249d11412..c3ac44aeedf92 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -26676,6 +26676,27 @@ static SDValue performUzpCombine(SDNode *N, SelectionDAG &DAG,
}
}
+ // uzp1(nvcast(x >> k), nvcast(y >> k)) -> uzp2(nvcast(x), nvcast(y))
+ // where 'k' is 'sizeof(eltty(x))/2'.
+ if (SDValue PreCastOp0 = isNVCastToHalfWidthElements(Op0)) {
+ if (SDValue PreCastOp1 = isNVCastToHalfWidthElements(Op1)) {
+ if (PreCastOp0.getOpcode() == ISD::SRL &&
+ PreCastOp1.getOpcode() == ISD::SRL &&
+ PreCastOp0.getOperand(1) == PreCastOp1.getOperand(1)) {
+ ConstantSDNode *ShiftAmount =
+ isConstOrConstSplat(PreCastOp0.getOperand(1), /*AllowUndef=*/false,
+ /*AllowTruncate=*/true);
+ if (ShiftAmount &&
+ ShiftAmount->getAsZExtVal() == ResVT.getScalarSizeInBits())
+ return DAG.getNode(AArch64ISD::UZP2, DL, ResVT,
+ DAG.getNode(AArch64ISD::NVCAST, DL, ResVT,
+ PreCastOp0.getOperand(0)),
+ DAG.getNode(AArch64ISD::NVCAST, DL, ResVT,
+ PreCastOp1.getOperand(0)));
+ }
+ }
+ }
+
// These optimizations only work on little endian.
if (!DAG.getDataLayout().isLittleEndian())
return SDValue();
diff --git a/llvm/test/CodeGen/AArch64/sve-shift-trunc-combine.ll b/llvm/test/CodeGen/AArch64/sve-shift-trunc-combine.ll
new file mode 100644
index 0000000000000..28e3840fbc96c
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/sve-shift-trunc-combine.ll
@@ -0,0 +1,162 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=aarch64 -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64_be -mattr=+sve -verify-machineinstrs < %s | FileCheck %s --check-prefix=BE
+
+; Test the following DAG combine:
+; uzp1(nvcast(x >> k), nvcast(y >> k)) -> uzp2(nvcast(x), nvcast(y))
+; (where k = sizeof(x)/2)
+
+define void @lshr_trunc_i16_load_scalable(ptr %src, ptr %dst) #0 {
+; CHECK-LABEL: lshr_trunc_i16_load_scalable:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr z0, [x0, #1, mul vl]
+; CHECK-NEXT: ldr z1, [x0]
+; CHECK-NEXT: uzp2 z0.b, z1.b, z0.b
+; CHECK-NEXT: str z0, [x1]
+; CHECK-NEXT: ret
+;
+; BE-LABEL: lshr_trunc_i16_load_scalable:
+; BE: // %bb.0:
+; BE-NEXT: ptrue p0.h
+; BE-NEXT: ld1h { z0.h }, p0/z, [x0, #1, mul vl]
+; BE-NEXT: ld1h { z1.h }, p0/z, [x0]
+; BE-NEXT: ptrue p0.b
+; BE-NEXT: uzp2 z0.b, z1.b, z0.b
+; BE-NEXT: st1b { z0.b }, p0, [x1]
+; BE-NEXT: ret
+ %x = load <vscale x 16 x i16>, ptr %src, align 2
+ %shift = lshr <vscale x 16 x i16> %x, splat (i16 8)
+ %result = trunc <vscale x 16 x i16> %shift to <vscale x 16 x i8>
+ store <vscale x 16 x i8> %result, ptr %dst, align 1
+ ret void
+}
+
+define void @lshr_trunc_i16_load_fixed_length(ptr %src, ptr %dst) #0 {
+; CHECK-LABEL: lshr_trunc_i16_load_fixed_length:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldp q1, q0, [x0]
+; CHECK-NEXT: uzp2 v0.16b, v1.16b, v0.16b
+; CHECK-NEXT: str q0, [x1]
+; CHECK-NEXT: ret
+;
+; BE-LABEL: lshr_trunc_i16_load_fixed_length:
+; BE: // %bb.0:
+; BE-NEXT: add x8, x0, #16
+; BE-NEXT: ld1 { v0.8h }, [x0]
+; BE-NEXT: ld1 { v1.8h }, [x8]
+; BE-NEXT: uzp2 v0.16b, v0.16b, v1.16b
+; BE-NEXT: st1 { v0.16b }, [x1]
+; BE-NEXT: ret
+ %x = load < 16 x i16>, ptr %src, align 2
+ %shift = lshr < 16 x i16> %x, splat (i16 8)
+ %result = trunc < 16 x i16> %shift to < 16 x i8>
+ store < 16 x i8> %result, ptr %dst, align 1
+ ret void
+}
+
+define void @ashr_trunc_i16_load(ptr %src, ptr %dst)#0 {
+; CHECK-LABEL: ashr_trunc_i16_load:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr z0, [x0, #1, mul vl]
+; CHECK-NEXT: ldr z1, [x0]
+; CHECK-NEXT: uzp2 z0.b, z1.b, z0.b
+; CHECK-NEXT: str z0, [x1]
+; CHECK-NEXT: ret
+;
+; BE-LABEL: ashr_trunc_i16_load:
+; BE: // %bb.0:
+; BE-NEXT: ptrue p0.h
+; BE-NEXT: ld1h { z0.h }, p0/z, [x0, #1, mul vl]
+; BE-NEXT: ld1h { z1.h }, p0/z, [x0]
+; BE-NEXT: ptrue p0.b
+; BE-NEXT: uzp2 z0.b, z1.b, z0.b
+; BE-NEXT: st1b { z0.b }, p0, [x1]
+; BE-NEXT: ret
+ %x = load <vscale x 16 x i16>, ptr %src, align 2
+ %shift = ashr <vscale x 16 x i16> %x, splat (i16 8)
+ %result = trunc <vscale x 16 x i16> %shift to <vscale x 16 x i8>
+ store <vscale x 16 x i8> %result, ptr %dst, align 1
+ ret void
+}
+
+define void @lshr_trunc_i32_load(ptr %src, ptr %dst) #0 {
+; CHECK-LABEL: lshr_trunc_i32_load:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr z0, [x0, #1, mul vl]
+; CHECK-NEXT: ldr z1, [x0]
+; CHECK-NEXT: uzp2 z0.h, z1.h, z0.h
+; CHECK-NEXT: str z0, [x1]
+; CHECK-NEXT: ret
+;
+; BE-LABEL: lshr_trunc_i32_load:
+; BE: // %bb.0:
+; BE-NEXT: ptrue p0.s
+; BE-NEXT: ld1w { z0.s }, p0/z, [x0, #1, mul vl]
+; BE-NEXT: ld1w { z1.s }, p0/z, [x0]
+; BE-NEXT: ptrue p0.h
+; BE-NEXT: uzp2 z0.h, z1.h, z0.h
+; BE-NEXT: st1h { z0.h }, p0, [x1]
+; BE-NEXT: ret
+ %x = load <vscale x 8 x i32>, ptr %src, align 2
+ %shift = lshr <vscale x 8 x i32> %x, splat (i32 16)
+ %result = trunc <vscale x 8 x i32> %shift to <vscale x 8 x i16>
+ store <vscale x 8 x i16> %result, ptr %dst, align 1
+ ret void
+}
+
+define void @lshr_trunc_i64_load(ptr %src, ptr %dst) #0 {
+; CHECK-LABEL: lshr_trunc_i64_load:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr z0, [x0, #1, mul vl]
+; CHECK-NEXT: ldr z1, [x0]
+; CHECK-NEXT: uzp2 z0.s, z1.s, z0.s
+; CHECK-NEXT: str z0, [x1]
+; CHECK-NEXT: ret
+;
+; BE-LABEL: lshr_trunc_i64_load:
+; BE: // %bb.0:
+; BE-NEXT: ptrue p0.d
+; BE-NEXT: ld1d { z0.d }, p0/z, [x0, #1, mul vl]
+; BE-NEXT: ld1d { z1.d }, p0/z, [x0]
+; BE-NEXT: ptrue p0.s
+; BE-NEXT: uzp2 z0.s, z1.s, z0.s
+; BE-NEXT: st1w { z0.s }, p0, [x1]
+; BE-NEXT: ret
+ %x = load <vscale x 4 x i64>, ptr %src, align 2
+ %shift = lshr <vscale x 4 x i64> %x, splat (i64 32)
+ %result = trunc <vscale x 4 x i64> %shift to <vscale x 4 x i32>
+ store <vscale x 4 x i32> %result, ptr %dst, align 1
+ ret void
+}
+
+; Negative test: the shift amount must be equal to the destination width.
+define void @lshr_trunc_wrong_amount(ptr %src, ptr %dst) #0 {
+; CHECK-LABEL: lshr_trunc_wrong_amount:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ldr z0, [x0]
+; CHECK-NEXT: ldr z1, [x0, #1, mul vl]
+; CHECK-NEXT: lsr z1.h, z1.h, #7
+; CHECK-NEXT: lsr z0.h, z0.h, #7
+; CHECK-NEXT: uzp1 z0.b, z0.b, z1.b
+; CHECK-NEXT: str z0, [x1]
+; CHECK-NEXT: ret
+;
+; BE-LABEL: lshr_trunc_wrong_amount:
+; BE: // %bb.0:
+; BE-NEXT: ptrue p0.h
+; BE-NEXT: ld1h { z0.h }, p0/z, [x0]
+; BE-NEXT: ld1h { z1.h }, p0/z, [x0, #1, mul vl]
+; BE-NEXT: ptrue p0.b
+; BE-NEXT: lsr z1.h, z1.h, #7
+; BE-NEXT: lsr z0.h, z0.h, #7
+; BE-NEXT: uzp1 z0.b, z0.b, z1.b
+; BE-NEXT: st1b { z0.b }, p0, [x1]
+; BE-NEXT: ret
+ %x = load <vscale x 16 x i16>, ptr %src, align 2
+ %shift = lshr <vscale x 16 x i16> %x, splat (i16 7)
+ %result = trunc <vscale x 16 x i16> %shift to <vscale x 16 x i8>
+ store <vscale x 16 x i8> %result, ptr %dst, align 1
+ ret void
+}
+
+attributes #0 = { "target-features"="+sve" }
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