[llvm] [AArch64][NeoverseV1] Model multi-cycle micro-ops correctly (NumMicro… (PR #216656)

[David Green via llvm-commits]

davemgreen wrote:

> many micro-ops for a single instruction like ST4 (27 micro-ops)

A ST4 _will_ be split into multiple micro-ops. 27 is a bit high - someone was likely trying to make the numbers fit the SWOG where the real bottleneck is probably in decode. I would expect it to be 2 or 4 stores + some number of shuffles, maybe 4 maybe 8. Plus store-data and the postinc if present. The really slow part on some cpus is getting through decode, there is a section in the SWOG about it.

Another example, chosen randomly, is that I would expect a tbx3 is a tbx2+tbx1, and a tbx2=tbx1+tbx1. So a tbx3 is 3 microops, not a single microop that holds the pipeline for 3 cycles.

Some others might hold a pipeline for multiple cycles, I'm not sure. The divides do and maybe some of the reductions.

https://github.com/llvm/llvm-project/pull/216656