[flang] [llvm] [flang][PPC] Implement ieee_set_status and ieee_get_status for AIX (PR #215618)

[Eugene Epshteyn via llvm-commits]

================
@@ -5210,11 +5210,80 @@ template <bool isGet, bool isModes>
 void IntrinsicLibrary::genIeeeGetOrSetModesOrStatus(
     llvm::ArrayRef<fir::ExtendedValue> args) {
   assert(args.size() == 1);
+  if constexpr (!isModes) {
+    llvm::Triple triple = fir::getTargetTriple(builder.getModule());
+    mlir::Type i32Ty = builder.getIntegerType(32);
+    mlir::Type i32PtrTy = builder.getRefType(i32Ty);
+    if (triple.isOSAIX()) {
+      // On AIX, fegetenv/fesetenv does not round-trip the FPSCR trap-enable
+      // bits [7:3].
+      //
+      // ieee_status_type.__data layout:
+      //   bytes  [0, 20) - fenv_t saved by fegetenv / restored by fesetenv
+      //   bytes [20, 28) - raw FPSCR double from mffs (trap-enable bits [7:3])
+      static constexpr int kAIXFenvTSize = 20; // sizeof(fenv_t) on AIX
----------------
eugeneepshteyn wrote:

(This comment was generated by AI.)

The branch keys on `triple.isOSAIX()` generally, so 32-bit `powerpc-ibm-aix` takes this same offset-20 path (the emitted IR is identical to the 64-bit case), but the lit test only covers `powerpc64-ibm-aix`. Can you confirm `sizeof(fenv_t) == 20` on 32-bit AIX as well, and make the constant per-arch if not? Adding a `powerpc-ibm-aix` RUN line to the test would pin the branch selection, but the native size evidence is the load-bearing part.

https://github.com/llvm/llvm-project/pull/215618