[llvm] [AMDGPU] Fix BFMPatterns mutliclass operand type for i64 (PR #216690)
Madhur Kumar via llvm-commits
llvm-commits at lists.llvm.org
Mon Aug 17 11:58:10 PDT 2026
https://github.com/MadhurKumar004 updated https://github.com/llvm/llvm-project/pull/216690
>From 1f5046545046fe239e72b4a552da4c2786df10c1 Mon Sep 17 00:00:00 2001
From: Madhur Kumar <madhurkumar004 at gmail.com>
Date: Mon, 17 Aug 2026 15:29:20 +0530
Subject: [PATCH 1/2] Pre-commit test
---
llvm/test/CodeGen/AMDGPU/bfm.ll | 200 ++++++++++++++++++++++++++++++++
1 file changed, 200 insertions(+)
diff --git a/llvm/test/CodeGen/AMDGPU/bfm.ll b/llvm/test/CodeGen/AMDGPU/bfm.ll
index 1db9f9344f8ca..257d783b7b038 100644
--- a/llvm/test/CodeGen/AMDGPU/bfm.ll
+++ b/llvm/test/CodeGen/AMDGPU/bfm.ll
@@ -89,6 +89,47 @@ define void @v_bfm_pattern(ptr addrspace(1) %out, i32 %x, i32 %y) #0 {
ret void
}
+define amdgpu_ps i64 @s_bfm64_pattern(i64 inreg %x, i64 inreg %y) {
+; SI-LABEL: s_bfm64_pattern:
+; SI: ; %bb.0:
+; SI-NEXT: s_lshl_b64 s[0:1], 1, s0
+; SI-NEXT: s_add_u32 s0, s0, -1
+; SI-NEXT: s_addc_u32 s1, s1, -1
+; SI-NEXT: s_lshl_b64 s[0:1], s[0:1], s2
+; SI-NEXT: ; return to shader part epilog
+;
+; VI-LABEL: s_bfm64_pattern:
+; VI: ; %bb.0:
+; VI-NEXT: s_lshl_b64 s[0:1], 1, s0
+; VI-NEXT: s_add_u32 s0, s0, -1
+; VI-NEXT: s_addc_u32 s1, s1, -1
+; VI-NEXT: s_lshl_b64 s[0:1], s[0:1], s2
+; VI-NEXT: ; return to shader part epilog
+ %a = shl i64 1, %x
+ %b = sub i64 %a, 1
+ %c = shl i64 %b, %y
+ ret i64 %c
+}
+
+define amdgpu_ps i64 @s_bfm64_pattern_simple(i64 inreg %x) {
+; SI-LABEL: s_bfm64_pattern_simple:
+; SI: ; %bb.0:
+; SI-NEXT: s_lshl_b64 s[0:1], 1, s0
+; SI-NEXT: s_add_u32 s0, s0, -1
+; SI-NEXT: s_addc_u32 s1, s1, -1
+; SI-NEXT: ; return to shader part epilog
+;
+; VI-LABEL: s_bfm64_pattern_simple:
+; VI: ; %bb.0:
+; VI-NEXT: s_lshl_b64 s[0:1], 1, s0
+; VI-NEXT: s_add_u32 s0, s0, -1
+; VI-NEXT: s_addc_u32 s1, s1, -1
+; VI-NEXT: ; return to shader part epilog
+ %a = shl i64 1, %x
+ %b = sub i64 %a, 1
+ ret i64 %b
+}
+
define void @v_bfm_pattern_simple(ptr addrspace(1) %out, i32 %x) #0 {
; SI-LABEL: v_bfm_pattern_simple:
; SI: ; %bb.0:
@@ -115,4 +156,163 @@ define void @v_bfm_pattern_simple(ptr addrspace(1) %out, i32 %x) #0 {
ret void
}
+define amdgpu_ps <2 x i64> @s_bfm64_v2i64_pattern(<2 x i64> inreg %x, <2 x i64> inreg %y) {
+; SI-LABEL: s_bfm64_v2i64_pattern:
+; SI: ; %bb.0:
+; SI-NEXT: s_lshl_b64 s[2:3], 1, s2
+; SI-NEXT: s_lshl_b64 s[0:1], 1, s0
+; SI-NEXT: s_add_u32 s0, s0, -1
+; SI-NEXT: s_addc_u32 s1, s1, -1
+; SI-NEXT: s_add_u32 s2, s2, -1
+; SI-NEXT: s_addc_u32 s3, s3, -1
+; SI-NEXT: s_lshl_b64 s[2:3], s[2:3], s6
+; SI-NEXT: s_lshl_b64 s[0:1], s[0:1], s4
+; SI-NEXT: ; return to shader part epilog
+;
+; VI-LABEL: s_bfm64_v2i64_pattern:
+; VI: ; %bb.0:
+; VI-NEXT: s_lshl_b64 s[2:3], 1, s2
+; VI-NEXT: s_lshl_b64 s[0:1], 1, s0
+; VI-NEXT: s_add_u32 s0, s0, -1
+; VI-NEXT: s_addc_u32 s1, s1, -1
+; VI-NEXT: s_add_u32 s2, s2, -1
+; VI-NEXT: s_addc_u32 s3, s3, -1
+; VI-NEXT: s_lshl_b64 s[2:3], s[2:3], s6
+; VI-NEXT: s_lshl_b64 s[0:1], s[0:1], s4
+; VI-NEXT: ; return to shader part epilog
+ %a = shl <2 x i64> splat (i64 1), %x
+ %b = sub <2 x i64> %a, splat (i64 1)
+ %c = shl <2 x i64> %b, %y
+ ret <2 x i64> %c
+}
+
+define amdgpu_ps <2 x i64> @s_bfm64_v2i64_pattern_simple(<2 x i64> inreg %x) {
+; SI-LABEL: s_bfm64_v2i64_pattern_simple:
+; SI: ; %bb.0:
+; SI-NEXT: s_lshl_b64 s[0:1], 1, s0
+; SI-NEXT: s_lshl_b64 s[2:3], 1, s2
+; SI-NEXT: s_add_u32 s2, s2, -1
+; SI-NEXT: s_addc_u32 s3, s3, -1
+; SI-NEXT: s_add_u32 s0, s0, -1
+; SI-NEXT: s_addc_u32 s1, s1, -1
+; SI-NEXT: ; return to shader part epilog
+;
+; VI-LABEL: s_bfm64_v2i64_pattern_simple:
+; VI: ; %bb.0:
+; VI-NEXT: s_lshl_b64 s[0:1], 1, s0
+; VI-NEXT: s_lshl_b64 s[2:3], 1, s2
+; VI-NEXT: s_add_u32 s2, s2, -1
+; VI-NEXT: s_addc_u32 s3, s3, -1
+; VI-NEXT: s_add_u32 s0, s0, -1
+; VI-NEXT: s_addc_u32 s1, s1, -1
+; VI-NEXT: ; return to shader part epilog
+ %a = shl <2 x i64> splat (i64 1), %x
+ %b = sub <2 x i64> %a, splat (i64 1)
+ ret <2 x i64> %b
+}
+
+define i64 @v_bfm64_pattern(i64 %x, i64 %y) {
+; SI-LABEL: v_bfm64_pattern:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_lshl_b64 v[0:1], 1, v0
+; SI-NEXT: v_add_i32_e32 v0, vcc, -1, v0
+; SI-NEXT: v_addc_u32_e32 v1, vcc, -1, v1, vcc
+; SI-NEXT: v_lshl_b64 v[0:1], v[0:1], v2
+; SI-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-LABEL: v_bfm64_pattern:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_lshlrev_b64 v[0:1], v0, 1
+; VI-NEXT: v_add_u32_e32 v0, vcc, -1, v0
+; VI-NEXT: v_addc_u32_e32 v1, vcc, -1, v1, vcc
+; VI-NEXT: v_lshlrev_b64 v[0:1], v2, v[0:1]
+; VI-NEXT: s_setpc_b64 s[30:31]
+ %a = shl i64 1, %x
+ %b = sub i64 %a, 1
+ %c = shl i64 %b, %y
+ ret i64 %c
+}
+
+define i64 @v_bfm64_pattern_simple(i64 %x) {
+; SI-LABEL: v_bfm64_pattern_simple:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_lshl_b64 v[0:1], 1, v0
+; SI-NEXT: v_add_i32_e32 v0, vcc, -1, v0
+; SI-NEXT: v_addc_u32_e32 v1, vcc, -1, v1, vcc
+; SI-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-LABEL: v_bfm64_pattern_simple:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_lshlrev_b64 v[0:1], v0, 1
+; VI-NEXT: v_add_u32_e32 v0, vcc, -1, v0
+; VI-NEXT: v_addc_u32_e32 v1, vcc, -1, v1, vcc
+; VI-NEXT: s_setpc_b64 s[30:31]
+ %a = shl i64 1, %x
+ %b = sub i64 %a, 1
+ ret i64 %b
+}
+
+define <2 x i64> @v_bfm64_v2i64_pattern(<2 x i64> %x, <2 x i64> %y) {
+; SI-LABEL: v_bfm64_v2i64_pattern:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_lshl_b64 v[2:3], 1, v2
+; SI-NEXT: v_lshl_b64 v[0:1], 1, v0
+; SI-NEXT: v_add_i32_e32 v2, vcc, -1, v2
+; SI-NEXT: v_addc_u32_e32 v3, vcc, -1, v3, vcc
+; SI-NEXT: v_add_i32_e32 v0, vcc, -1, v0
+; SI-NEXT: v_addc_u32_e32 v1, vcc, -1, v1, vcc
+; SI-NEXT: v_lshl_b64 v[0:1], v[0:1], v4
+; SI-NEXT: v_lshl_b64 v[2:3], v[2:3], v6
+; SI-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-LABEL: v_bfm64_v2i64_pattern:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_lshlrev_b64 v[2:3], v2, 1
+; VI-NEXT: v_lshlrev_b64 v[0:1], v0, 1
+; VI-NEXT: v_add_u32_e32 v2, vcc, -1, v2
+; VI-NEXT: v_addc_u32_e32 v3, vcc, -1, v3, vcc
+; VI-NEXT: v_add_u32_e32 v0, vcc, -1, v0
+; VI-NEXT: v_addc_u32_e32 v1, vcc, -1, v1, vcc
+; VI-NEXT: v_lshlrev_b64 v[0:1], v4, v[0:1]
+; VI-NEXT: v_lshlrev_b64 v[2:3], v6, v[2:3]
+; VI-NEXT: s_setpc_b64 s[30:31]
+ %a = shl <2 x i64> splat (i64 1), %x
+ %b = sub <2 x i64> %a, splat (i64 1)
+ %c = shl <2 x i64> %b, %y
+ ret <2 x i64> %c
+}
+
+define <2 x i64> @v_bfm64_v2i64_pattern_simple(<2 x i64> %x) {
+; SI-LABEL: v_bfm64_v2i64_pattern_simple:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_lshl_b64 v[0:1], 1, v0
+; SI-NEXT: v_lshl_b64 v[2:3], 1, v2
+; SI-NEXT: v_add_i32_e32 v0, vcc, -1, v0
+; SI-NEXT: v_addc_u32_e32 v1, vcc, -1, v1, vcc
+; SI-NEXT: v_add_i32_e32 v2, vcc, -1, v2
+; SI-NEXT: v_addc_u32_e32 v3, vcc, -1, v3, vcc
+; SI-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-LABEL: v_bfm64_v2i64_pattern_simple:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_lshlrev_b64 v[0:1], v0, 1
+; VI-NEXT: v_lshlrev_b64 v[2:3], v2, 1
+; VI-NEXT: v_add_u32_e32 v0, vcc, -1, v0
+; VI-NEXT: v_addc_u32_e32 v1, vcc, -1, v1, vcc
+; VI-NEXT: v_add_u32_e32 v2, vcc, -1, v2
+; VI-NEXT: v_addc_u32_e32 v3, vcc, -1, v3, vcc
+; VI-NEXT: s_setpc_b64 s[30:31]
+ %a = shl <2 x i64> splat (i64 1), %x
+ %b = sub <2 x i64> %a, splat (i64 1)
+ ret <2 x i64> %b
+}
+
attributes #0 = { nounwind }
>From 38ae2a26b7268a48f0525dcaba84dfd678b6e2a8 Mon Sep 17 00:00:00 2001
From: Madhur Kumar <madhurkumar004 at gmail.com>
Date: Tue, 18 Aug 2026 00:23:11 +0530
Subject: [PATCH 2/2] [AMDGPU] Fix BFMPatterns mutliclass operand type for i64
---
llvm/lib/Target/AMDGPU/SIInstructions.td | 6 +--
llvm/test/CodeGen/AMDGPU/bfm.ll | 54 ++++++------------------
2 files changed, 15 insertions(+), 45 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
index 36cacfd47f62c..5fce07e2ac262 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -4385,18 +4385,18 @@ def : GCNPat<
multiclass BFMPatterns <ValueType vt, PatFrag SHL, PatFrag ADD, InstSI BFM> {
def : GCNPat <
- (vt (SHL (vt (add (vt (shl 1, vt:$a)), -1)), vt:$b)),
+ (vt (SHL (vt (add (vt (shl 1, i32:$a)), -1)), i32:$b)),
(BFM $a, $b)
>;
def : GCNPat <
- (vt (ADD (vt (shl 1, vt:$a)), -1)),
+ (vt (ADD (vt (shl 1, i32:$a)), -1)),
(BFM $a, (i32 0))
>;
}
defm : BFMPatterns <i32, UniformBinFrag<shl>, UniformBinFrag<add>, S_BFM_B32>;
-// FIXME: defm : BFMPatterns <i64, UniformBinFrag<shl>, UniformBinFrag<add>, S_BFM_B64>;
+defm : BFMPatterns <i64, UniformBinFrag<shl>, UniformBinFrag<add>, S_BFM_B64>;
defm : BFMPatterns <i32, DivergentBinFrag<shl>, DivergentBinFrag<add>, V_BFM_B32_e64>;
// Bitfield extract patterns
diff --git a/llvm/test/CodeGen/AMDGPU/bfm.ll b/llvm/test/CodeGen/AMDGPU/bfm.ll
index 257d783b7b038..0e2663f38e783 100644
--- a/llvm/test/CodeGen/AMDGPU/bfm.ll
+++ b/llvm/test/CodeGen/AMDGPU/bfm.ll
@@ -92,18 +92,12 @@ define void @v_bfm_pattern(ptr addrspace(1) %out, i32 %x, i32 %y) #0 {
define amdgpu_ps i64 @s_bfm64_pattern(i64 inreg %x, i64 inreg %y) {
; SI-LABEL: s_bfm64_pattern:
; SI: ; %bb.0:
-; SI-NEXT: s_lshl_b64 s[0:1], 1, s0
-; SI-NEXT: s_add_u32 s0, s0, -1
-; SI-NEXT: s_addc_u32 s1, s1, -1
-; SI-NEXT: s_lshl_b64 s[0:1], s[0:1], s2
+; SI-NEXT: s_bfm_b64 s[0:1], s0, s2
; SI-NEXT: ; return to shader part epilog
;
; VI-LABEL: s_bfm64_pattern:
; VI: ; %bb.0:
-; VI-NEXT: s_lshl_b64 s[0:1], 1, s0
-; VI-NEXT: s_add_u32 s0, s0, -1
-; VI-NEXT: s_addc_u32 s1, s1, -1
-; VI-NEXT: s_lshl_b64 s[0:1], s[0:1], s2
+; VI-NEXT: s_bfm_b64 s[0:1], s0, s2
; VI-NEXT: ; return to shader part epilog
%a = shl i64 1, %x
%b = sub i64 %a, 1
@@ -114,16 +108,12 @@ define amdgpu_ps i64 @s_bfm64_pattern(i64 inreg %x, i64 inreg %y) {
define amdgpu_ps i64 @s_bfm64_pattern_simple(i64 inreg %x) {
; SI-LABEL: s_bfm64_pattern_simple:
; SI: ; %bb.0:
-; SI-NEXT: s_lshl_b64 s[0:1], 1, s0
-; SI-NEXT: s_add_u32 s0, s0, -1
-; SI-NEXT: s_addc_u32 s1, s1, -1
+; SI-NEXT: s_bfm_b64 s[0:1], s0, 0
; SI-NEXT: ; return to shader part epilog
;
; VI-LABEL: s_bfm64_pattern_simple:
; VI: ; %bb.0:
-; VI-NEXT: s_lshl_b64 s[0:1], 1, s0
-; VI-NEXT: s_add_u32 s0, s0, -1
-; VI-NEXT: s_addc_u32 s1, s1, -1
+; VI-NEXT: s_bfm_b64 s[0:1], s0, 0
; VI-NEXT: ; return to shader part epilog
%a = shl i64 1, %x
%b = sub i64 %a, 1
@@ -159,26 +149,14 @@ define void @v_bfm_pattern_simple(ptr addrspace(1) %out, i32 %x) #0 {
define amdgpu_ps <2 x i64> @s_bfm64_v2i64_pattern(<2 x i64> inreg %x, <2 x i64> inreg %y) {
; SI-LABEL: s_bfm64_v2i64_pattern:
; SI: ; %bb.0:
-; SI-NEXT: s_lshl_b64 s[2:3], 1, s2
-; SI-NEXT: s_lshl_b64 s[0:1], 1, s0
-; SI-NEXT: s_add_u32 s0, s0, -1
-; SI-NEXT: s_addc_u32 s1, s1, -1
-; SI-NEXT: s_add_u32 s2, s2, -1
-; SI-NEXT: s_addc_u32 s3, s3, -1
-; SI-NEXT: s_lshl_b64 s[2:3], s[2:3], s6
-; SI-NEXT: s_lshl_b64 s[0:1], s[0:1], s4
+; SI-NEXT: s_bfm_b64 s[2:3], s2, s6
+; SI-NEXT: s_bfm_b64 s[0:1], s0, s4
; SI-NEXT: ; return to shader part epilog
;
; VI-LABEL: s_bfm64_v2i64_pattern:
; VI: ; %bb.0:
-; VI-NEXT: s_lshl_b64 s[2:3], 1, s2
-; VI-NEXT: s_lshl_b64 s[0:1], 1, s0
-; VI-NEXT: s_add_u32 s0, s0, -1
-; VI-NEXT: s_addc_u32 s1, s1, -1
-; VI-NEXT: s_add_u32 s2, s2, -1
-; VI-NEXT: s_addc_u32 s3, s3, -1
-; VI-NEXT: s_lshl_b64 s[2:3], s[2:3], s6
-; VI-NEXT: s_lshl_b64 s[0:1], s[0:1], s4
+; VI-NEXT: s_bfm_b64 s[2:3], s2, s6
+; VI-NEXT: s_bfm_b64 s[0:1], s0, s4
; VI-NEXT: ; return to shader part epilog
%a = shl <2 x i64> splat (i64 1), %x
%b = sub <2 x i64> %a, splat (i64 1)
@@ -189,22 +167,14 @@ define amdgpu_ps <2 x i64> @s_bfm64_v2i64_pattern(<2 x i64> inreg %x, <2 x i64>
define amdgpu_ps <2 x i64> @s_bfm64_v2i64_pattern_simple(<2 x i64> inreg %x) {
; SI-LABEL: s_bfm64_v2i64_pattern_simple:
; SI: ; %bb.0:
-; SI-NEXT: s_lshl_b64 s[0:1], 1, s0
-; SI-NEXT: s_lshl_b64 s[2:3], 1, s2
-; SI-NEXT: s_add_u32 s2, s2, -1
-; SI-NEXT: s_addc_u32 s3, s3, -1
-; SI-NEXT: s_add_u32 s0, s0, -1
-; SI-NEXT: s_addc_u32 s1, s1, -1
+; SI-NEXT: s_bfm_b64 s[2:3], s2, 0
+; SI-NEXT: s_bfm_b64 s[0:1], s0, 0
; SI-NEXT: ; return to shader part epilog
;
; VI-LABEL: s_bfm64_v2i64_pattern_simple:
; VI: ; %bb.0:
-; VI-NEXT: s_lshl_b64 s[0:1], 1, s0
-; VI-NEXT: s_lshl_b64 s[2:3], 1, s2
-; VI-NEXT: s_add_u32 s2, s2, -1
-; VI-NEXT: s_addc_u32 s3, s3, -1
-; VI-NEXT: s_add_u32 s0, s0, -1
-; VI-NEXT: s_addc_u32 s1, s1, -1
+; VI-NEXT: s_bfm_b64 s[2:3], s2, 0
+; VI-NEXT: s_bfm_b64 s[0:1], s0, 0
; VI-NEXT: ; return to shader part epilog
%a = shl <2 x i64> splat (i64 1), %x
%b = sub <2 x i64> %a, splat (i64 1)
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