[llvm] [CodeGen][Hexagon] Pass the shared RegisterClassInfo object to Hexagon frame lowering (PR #216752)
Nikhil Kotikalapudi via llvm-commits
llvm-commits at lists.llvm.org
Mon Aug 17 10:30:55 PDT 2026
https://github.com/nkotikal updated https://github.com/llvm/llvm-project/pull/216752
>From 38afc0928685cac14e0842d52a710eb101a1fd9c Mon Sep 17 00:00:00 2001
From: nkotikal <nak00001 at outlook.com>
Date: Sun, 16 Aug 2026 13:27:15 -0400
Subject: [PATCH 1/4] restored hexagon rci from #216510
---
.../lib/Target/Hexagon/HexagonFrameLowering.cpp | 17 ++++++++++-------
llvm/lib/Target/Hexagon/HexagonFrameLowering.h | 8 +++++---
2 files changed, 15 insertions(+), 10 deletions(-)
diff --git a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
index b665ef98c5e44..57e611db15ca0 100644
--- a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
@@ -38,6 +38,7 @@
#include "llvm/CodeGen/MachinePostDominators.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/PseudoSourceValue.h"
+#include "llvm/CodeGen/RegisterClassInfo.h"
#include "llvm/CodeGen/RegisterScavenging.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/IR/Attributes.h"
@@ -2415,11 +2416,11 @@ void HexagonFrameLowering::determineCalleeSaves(MachineFunction &MF,
TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
}
-Register HexagonFrameLowering::findPhysReg(MachineFunction &MF,
- HexagonBlockRanges::IndexRange &FIR,
- HexagonBlockRanges::InstrIndexMap &IndexMap,
- HexagonBlockRanges::RegToRangeMap &DeadMap,
- const TargetRegisterClass *RC) const {
+Register HexagonFrameLowering::findPhysReg(
+ MachineFunction &MF, HexagonBlockRanges::IndexRange &FIR,
+ HexagonBlockRanges::InstrIndexMap &IndexMap,
+ HexagonBlockRanges::RegToRangeMap &DeadMap, const TargetRegisterClass *RC,
+ const RegisterClassInfo &RCI) const {
auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
auto &MRI = MF.getRegInfo();
@@ -2433,7 +2434,7 @@ Register HexagonFrameLowering::findPhysReg(MachineFunction &MF,
return false;
};
- for (Register Reg : HRI.getRawAllocationOrder(*RC, MF)) {
+ for (Register Reg : RCI.getOrder(RC)) {
bool Dead = true;
for (auto R : HexagonBlockRanges::expandToSubRegs({Reg,0}, MRI, HRI)) {
if (isDead(R.Reg))
@@ -2453,6 +2454,8 @@ void HexagonFrameLowering::optimizeSpillSlots(MachineFunction &MF,
auto &HII = *HST.getInstrInfo();
auto &HRI = *HST.getRegisterInfo();
auto &MRI = MF.getRegInfo();
+ RegisterClassInfo RCI;
+ RCI.runOnMachineFunction(MF);
HexagonBlockRanges HBR(MF);
using BlockIndexMap =
@@ -2700,7 +2703,7 @@ void HexagonFrameLowering::optimizeSpillSlots(MachineFunction &MF,
SrcOp.getSubReg() };
auto *RC = HII.getRegClass(SI.getDesc(), 2);
// The this-> is needed to unconfuse MSVC.
- Register FoundR = this->findPhysReg(MF, Range, IM, DM, RC);
+ Register FoundR = this->findPhysReg(MF, Range, IM, DM, RC, RCI);
LLVM_DEBUG(dbgs() << "Replacement reg:" << printReg(FoundR, &HRI)
<< '\n');
if (FoundR == 0)
diff --git a/llvm/lib/Target/Hexagon/HexagonFrameLowering.h b/llvm/lib/Target/Hexagon/HexagonFrameLowering.h
index 0b93795f2b912..bdb7b50791468 100644
--- a/llvm/lib/Target/Hexagon/HexagonFrameLowering.h
+++ b/llvm/lib/Target/Hexagon/HexagonFrameLowering.h
@@ -26,6 +26,7 @@ class HexagonRegisterInfo;
class MachineFunction;
class MachineInstr;
class MachineRegisterInfo;
+class RegisterClassInfo;
class MCRegisterClass;
using TargetRegisterClass = MCRegisterClass;
@@ -171,9 +172,10 @@ class HexagonFrameLowering : public TargetFrameLowering {
SmallVectorImpl<Register> &NewRegs) const;
Register findPhysReg(MachineFunction &MF, HexagonBlockRanges::IndexRange &FIR,
- HexagonBlockRanges::InstrIndexMap &IndexMap,
- HexagonBlockRanges::RegToRangeMap &DeadMap,
- const TargetRegisterClass *RC) const;
+ HexagonBlockRanges::InstrIndexMap &IndexMap,
+ HexagonBlockRanges::RegToRangeMap &DeadMap,
+ const TargetRegisterClass *RC,
+ const RegisterClassInfo &RCI) const;
void optimizeSpillSlots(MachineFunction &MF,
SmallVectorImpl<Register> &VRegs) const;
>From 213846e93c36e1aa2032fedfd31a7222a4eb9923 Mon Sep 17 00:00:00 2001
From: nkotikal <nak00001 at outlook.com>
Date: Sun, 16 Aug 2026 23:34:32 -0400
Subject: [PATCH 2/4] Hexagon TargetFrameLowering RCI order to prevent checking
reserved regs
---
.../llvm/CodeGen/TargetFrameLowering.h | 8 +++
llvm/lib/CodeGen/PrologEpilogInserter.cpp | 15 ++++--
llvm/lib/CodeGen/RegisterScavenging.cpp | 4 ++
llvm/lib/CodeGen/ShrinkWrap.cpp | 1 +
.../Target/Hexagon/HexagonFrameLowering.cpp | 53 ++++++++++---------
.../lib/Target/Hexagon/HexagonFrameLowering.h | 5 +-
6 files changed, 58 insertions(+), 28 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/TargetFrameLowering.h b/llvm/include/llvm/CodeGen/TargetFrameLowering.h
index 77a1b709d9e17..aa9deced5db79 100644
--- a/llvm/include/llvm/CodeGen/TargetFrameLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetFrameLowering.h
@@ -25,6 +25,7 @@ namespace llvm {
class BitVector;
class CalleeSavedInfo;
class MachineFunction;
+ class RegisterClassInfo;
class RegScavenger;
namespace TargetStackID {
@@ -400,6 +401,13 @@ class LLVM_ABI TargetFrameLowering {
virtual void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs,
RegScavenger *RS = nullptr) const;
+ /// Called immediately before determineCalleeSaves with the shared
+ /// RegisterClassInfo from the pass manager. Default is a no-op.
+ /// Required since adding to determineCalleeSaves would require modifying every target override.
+ virtual void processFunctionBeforeCalleeSaves(
+ MachineFunction &MF, RegScavenger *RS = nullptr,
+ const RegisterClassInfo *RCI = nullptr) const {}
+
/// processFunctionBeforeFrameFinalized - This method is called immediately
/// before the specified function's frame layout (MF.getFrameInfo()) is
/// finalized. Once the frame is finalized, MO_FrameIndex operands are
diff --git a/llvm/lib/CodeGen/PrologEpilogInserter.cpp b/llvm/lib/CodeGen/PrologEpilogInserter.cpp
index 4cfce20465e21..eb272b2792a73 100644
--- a/llvm/lib/CodeGen/PrologEpilogInserter.cpp
+++ b/llvm/lib/CodeGen/PrologEpilogInserter.cpp
@@ -97,6 +97,7 @@ class PEIImpl {
// Emit remarks.
MachineOptimizationRemarkEmitter *ORE = nullptr;
+ const RegisterClassInfo *RCI = nullptr;
void calculateCallFrameInfo(MachineFunction &MF);
void calculateSaveRestoreBlocks(MachineFunction &MF);
@@ -121,7 +122,8 @@ class PEIImpl {
void insertZeroCallUsedRegs(MachineFunction &MF);
public:
- PEIImpl(MachineOptimizationRemarkEmitter *ORE) : ORE(ORE) {}
+ PEIImpl(MachineOptimizationRemarkEmitter *ORE, const RegisterClassInfo *RCI)
+ : ORE(ORE), RCI(RCI) {}
bool run(MachineFunction &MF);
};
@@ -149,6 +151,7 @@ INITIALIZE_PASS_BEGIN(PEILegacy, DEBUG_TYPE, "Prologue/Epilogue Insertion",
INITIALIZE_PASS_DEPENDENCY(MachineLoopInfoWrapperPass)
INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass)
INITIALIZE_PASS_DEPENDENCY(MachineOptimizationRemarkEmitterPass)
+INITIALIZE_PASS_DEPENDENCY(MachineRegisterClassInfoWrapperPass)
INITIALIZE_PASS_END(PEILegacy, DEBUG_TYPE,
"Prologue/Epilogue Insertion & Frame Finalization", false,
false)
@@ -163,6 +166,7 @@ STATISTIC(NumBytesStackSpace,
void PEILegacy::getAnalysisUsage(AnalysisUsage &AU) const {
AU.setPreservesCFG();
AU.addRequired<MachineOptimizationRemarkEmitterPass>();
+ AU.addRequired<MachineRegisterClassInfoWrapperPass>();
MachineFunctionPass::getAnalysisUsage(AU);
}
@@ -353,7 +357,9 @@ bool PEIImpl::run(MachineFunction &MF) {
bool PEILegacy::runOnMachineFunction(MachineFunction &MF) {
MachineOptimizationRemarkEmitter *ORE =
&getAnalysis<MachineOptimizationRemarkEmitterPass>().getORE();
- return PEIImpl(ORE).run(MF);
+ const RegisterClassInfo *RCI =
+ &getAnalysis<MachineRegisterClassInfoWrapperPass>().getRCI();
+ return PEIImpl(ORE, RCI).run(MF);
}
PreservedAnalyses
@@ -361,7 +367,9 @@ PrologEpilogInserterPass::run(MachineFunction &MF,
MachineFunctionAnalysisManager &MFAM) {
MachineOptimizationRemarkEmitter &ORE =
MFAM.getResult<MachineOptimizationRemarkEmitterAnalysis>(MF);
- if (!PEIImpl(&ORE).run(MF))
+ const RegisterClassInfo &RCI =
+ MFAM.getResult<MachineRegisterClassAnalysis>(MF);
+ if (!PEIImpl(&ORE, &RCI).run(MF))
return PreservedAnalyses::all();
return getMachineFunctionPassPreservedAnalyses().preserveSet<CFGAnalyses>();
@@ -665,6 +673,7 @@ void PEIImpl::spillCalleeSavedRegs(MachineFunction &MF) {
// Determine which of the registers in the callee save list should be saved.
BitVector SavedRegs;
+ TFI->processFunctionBeforeCalleeSaves(MF, RS, RCI);
TFI->determineCalleeSaves(MF, SavedRegs, RS);
// Assign stack slots for any callee-saved registers that must be spilled.
diff --git a/llvm/lib/CodeGen/RegisterScavenging.cpp b/llvm/lib/CodeGen/RegisterScavenging.cpp
index 8ef8906ef8086..c710d6b59bb6a 100644
--- a/llvm/lib/CodeGen/RegisterScavenging.cpp
+++ b/llvm/lib/CodeGen/RegisterScavenging.cpp
@@ -27,6 +27,7 @@
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/RegisterClassInfo.h"
#include "llvm/CodeGen/TargetFrameLowering.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
@@ -520,7 +521,10 @@ class ScavengerTest : public MachineFunctionPass {
// Let's hope that calling those outside of PrologEpilogueInserter works
// well enough to initialize the scavenger with some emergency spillslots
// for the target.
+ RegisterClassInfo RCI;
+ RCI.runOnMachineFunction(MF);
BitVector SavedRegs;
+ TFL.processFunctionBeforeCalleeSaves(MF, &RS, &RCI);
TFL.determineCalleeSaves(MF, SavedRegs, &RS);
TFL.processFunctionBeforeFrameFinalized(MF, &RS);
diff --git a/llvm/lib/CodeGen/ShrinkWrap.cpp b/llvm/lib/CodeGen/ShrinkWrap.cpp
index 32cae27489c39..67c6d964ce784 100644
--- a/llvm/lib/CodeGen/ShrinkWrap.cpp
+++ b/llvm/lib/CodeGen/ShrinkWrap.cpp
@@ -180,6 +180,7 @@ class ShrinkWrapImpl {
const TargetFrameLowering *TFI =
MachineFunc->getSubtarget().getFrameLowering();
+ TFI->processFunctionBeforeCalleeSaves(*MachineFunc, RS, RCI);
TFI->determineCalleeSaves(*MachineFunc, SavedRegs, RS);
for (int Reg = SavedRegs.find_first(); Reg != -1;
diff --git a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
index 57e611db15ca0..58dc8ba5b50bd 100644
--- a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
@@ -2360,31 +2360,24 @@ bool HexagonFrameLowering::expandSpillMacros(MachineFunction &MF,
return Changed;
}
-void HexagonFrameLowering::determineCalleeSaves(MachineFunction &MF,
- BitVector &SavedRegs,
- RegScavenger *RS) const {
+void HexagonFrameLowering::processFunctionBeforeCalleeSaves(
+ MachineFunction &MF, RegScavenger *RS, const RegisterClassInfo *RCI) const {
auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
- SavedRegs.resize(HRI.getNumRegs());
-
- // If we have a function containing __builtin_eh_return we want to spill and
- // restore all callee saved registers. Pretend that they are used.
- if (MF.getInfo<HexagonMachineFunctionInfo>()->hasEHReturn())
- for (const MCPhysReg *R = HRI.getCalleeSavedRegs(&MF); *R; ++R)
- SavedRegs.set(*R);
-
// Replace predicate register pseudo spill code.
- SmallVector<Register,8> NewRegs;
+ SmallVector<Register, 8> NewRegs;
expandSpillMacros(MF, NewRegs);
- if (OptimizeSpillSlots && !isOptNone(MF))
- optimizeSpillSlots(MF, NewRegs);
+ if (OptimizeSpillSlots && !isOptNone(MF)) {
+ assert(RCI && "RegisterClassInfo required to optimize spill slots");
+ optimizeSpillSlots(MF, NewRegs, *RCI);
+ }
// We need to reserve a spill slot if scavenging could potentially require
// spilling a scavenged register.
if (!NewRegs.empty() || mayOverflowFrameOffset(MF)) {
MachineFrameInfo &MFI = MF.getFrameInfo();
MachineRegisterInfo &MRI = MF.getRegInfo();
- SetVector<const TargetRegisterClass*> SpillRCs;
+ SetVector<const TargetRegisterClass *> SpillRCs;
// Reserve an int register in any case, because it could be used to hold
// the stack offset in case it does not fit into a spill instruction.
SpillRCs.insert(&Hexagon::IntRegsRegClass);
@@ -2397,12 +2390,12 @@ void HexagonFrameLowering::determineCalleeSaves(MachineFunction &MF,
continue;
unsigned Num = 1;
switch (RC->getID()) {
- case Hexagon::IntRegsRegClassID:
- Num = NumberScavengerSlots;
- break;
- case Hexagon::HvxQRRegClassID:
- Num = 2; // Vector predicate spills also need a vector register.
- break;
+ case Hexagon::IntRegsRegClassID:
+ Num = NumberScavengerSlots;
+ break;
+ case Hexagon::HvxQRRegClassID:
+ Num = 2; // Vector predicate spills also need a vector register.
+ break;
}
unsigned S = HRI.getSpillSize(*RC);
Align A = HRI.getSpillAlign(*RC);
@@ -2412,6 +2405,20 @@ void HexagonFrameLowering::determineCalleeSaves(MachineFunction &MF,
}
}
}
+}
+
+void HexagonFrameLowering::determineCalleeSaves(MachineFunction &MF,
+ BitVector &SavedRegs,
+ RegScavenger *RS) const {
+ auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
+
+ SavedRegs.resize(HRI.getNumRegs());
+
+ // If we have a function containing __builtin_eh_return we want to spill and
+ // restore all callee saved registers. Pretend that they are used.
+ if (MF.getInfo<HexagonMachineFunctionInfo>()->hasEHReturn())
+ for (const MCPhysReg *R = HRI.getCalleeSavedRegs(&MF); *R; ++R)
+ SavedRegs.set(*R);
TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
}
@@ -2449,13 +2456,11 @@ Register HexagonFrameLowering::findPhysReg(
}
void HexagonFrameLowering::optimizeSpillSlots(MachineFunction &MF,
- SmallVectorImpl<Register> &VRegs) const {
+ SmallVectorImpl<Register> &VRegs, const RegisterClassInfo &RCI) const {
auto &HST = MF.getSubtarget<HexagonSubtarget>();
auto &HII = *HST.getInstrInfo();
auto &HRI = *HST.getRegisterInfo();
auto &MRI = MF.getRegInfo();
- RegisterClassInfo RCI;
- RCI.runOnMachineFunction(MF);
HexagonBlockRanges HBR(MF);
using BlockIndexMap =
diff --git a/llvm/lib/Target/Hexagon/HexagonFrameLowering.h b/llvm/lib/Target/Hexagon/HexagonFrameLowering.h
index bdb7b50791468..f4f505d358023 100644
--- a/llvm/lib/Target/Hexagon/HexagonFrameLowering.h
+++ b/llvm/lib/Target/Hexagon/HexagonFrameLowering.h
@@ -82,6 +82,9 @@ class HexagonFrameLowering : public TargetFrameLowering {
MachineBasicBlock::iterator I) const override;
void processFunctionBeforeFrameFinalized(MachineFunction &MF,
RegScavenger *RS = nullptr) const override;
+ void processFunctionBeforeCalleeSaves(
+ MachineFunction &MF, RegScavenger *RS = nullptr,
+ const RegisterClassInfo *RCI = nullptr) const override;
void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs,
RegScavenger *RS) const override;
@@ -177,7 +180,7 @@ class HexagonFrameLowering : public TargetFrameLowering {
const TargetRegisterClass *RC,
const RegisterClassInfo &RCI) const;
void optimizeSpillSlots(MachineFunction &MF,
- SmallVectorImpl<Register> &VRegs) const;
+ SmallVectorImpl<Register> &VRegs, const RegisterClassInfo &RCI) const;
void findShrunkPrologEpilog(MachineFunction &MF, MachineBasicBlock *&PrologB,
MachineBasicBlock *&EpilogB) const;
>From 0a798a91a4f9bcd619f0a8dca1398f88372585c7 Mon Sep 17 00:00:00 2001
From: nkotikal <nak00001 at outlook.com>
Date: Sun, 16 Aug 2026 23:56:17 -0400
Subject: [PATCH 3/4] clang format
---
llvm/include/llvm/CodeGen/TargetFrameLowering.h | 3 ++-
llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp | 5 +++--
llvm/lib/Target/Hexagon/HexagonFrameLowering.h | 4 ++--
3 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/TargetFrameLowering.h b/llvm/include/llvm/CodeGen/TargetFrameLowering.h
index aa9deced5db79..f1364b89d763a 100644
--- a/llvm/include/llvm/CodeGen/TargetFrameLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetFrameLowering.h
@@ -403,7 +403,8 @@ class LLVM_ABI TargetFrameLowering {
/// Called immediately before determineCalleeSaves with the shared
/// RegisterClassInfo from the pass manager. Default is a no-op.
- /// Required since adding to determineCalleeSaves would require modifying every target override.
+ /// Required since adding to determineCalleeSaves would require modifying
+ /// every target override.
virtual void processFunctionBeforeCalleeSaves(
MachineFunction &MF, RegScavenger *RS = nullptr,
const RegisterClassInfo *RCI = nullptr) const {}
diff --git a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
index 58dc8ba5b50bd..4528a9c37e175 100644
--- a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
@@ -2455,8 +2455,9 @@ Register HexagonFrameLowering::findPhysReg(
return 0;
}
-void HexagonFrameLowering::optimizeSpillSlots(MachineFunction &MF,
- SmallVectorImpl<Register> &VRegs, const RegisterClassInfo &RCI) const {
+void HexagonFrameLowering::optimizeSpillSlots(
+ MachineFunction &MF, SmallVectorImpl<Register> &VRegs,
+ const RegisterClassInfo &RCI) const {
auto &HST = MF.getSubtarget<HexagonSubtarget>();
auto &HII = *HST.getInstrInfo();
auto &HRI = *HST.getRegisterInfo();
diff --git a/llvm/lib/Target/Hexagon/HexagonFrameLowering.h b/llvm/lib/Target/Hexagon/HexagonFrameLowering.h
index f4f505d358023..7eaf94cc5f42f 100644
--- a/llvm/lib/Target/Hexagon/HexagonFrameLowering.h
+++ b/llvm/lib/Target/Hexagon/HexagonFrameLowering.h
@@ -179,8 +179,8 @@ class HexagonFrameLowering : public TargetFrameLowering {
HexagonBlockRanges::RegToRangeMap &DeadMap,
const TargetRegisterClass *RC,
const RegisterClassInfo &RCI) const;
- void optimizeSpillSlots(MachineFunction &MF,
- SmallVectorImpl<Register> &VRegs, const RegisterClassInfo &RCI) const;
+ void optimizeSpillSlots(MachineFunction &MF, SmallVectorImpl<Register> &VRegs,
+ const RegisterClassInfo &RCI) const;
void findShrunkPrologEpilog(MachineFunction &MF, MachineBasicBlock *&PrologB,
MachineBasicBlock *&EpilogB) const;
>From 701efcd76c1e0be19322ff1da94c0d2a2f077cf7 Mon Sep 17 00:00:00 2001
From: nkotikal <nak00001 at outlook.com>
Date: Mon, 17 Aug 2026 12:13:32 -0400
Subject: [PATCH 4/4] fixed pipeline tests
---
llvm/test/CodeGen/AArch64/O0-pipeline.ll | 1 +
llvm/test/CodeGen/LoongArch/O0-pipeline.ll | 1 +
llvm/test/CodeGen/PowerPC/O0-pipeline.ll | 1 +
llvm/test/CodeGen/RISCV/O0-pipeline.ll | 1 +
llvm/test/CodeGen/SPIRV/llc-pipeline.ll | 1 +
llvm/test/CodeGen/X86/O0-pipeline.ll | 1 +
6 files changed, 6 insertions(+)
diff --git a/llvm/test/CodeGen/AArch64/O0-pipeline.ll b/llvm/test/CodeGen/AArch64/O0-pipeline.ll
index b363e11f62811..400f7a2764101 100644
--- a/llvm/test/CodeGen/AArch64/O0-pipeline.ll
+++ b/llvm/test/CodeGen/AArch64/O0-pipeline.ll
@@ -59,6 +59,7 @@
; CHECK-NEXT: Fixup Statepoint Caller Saved
; CHECK-NEXT: Lazy Machine Block Frequency Analysis
; CHECK-NEXT: Machine Optimization Remark Emitter
+; CHECK-NEXT: Machine Register Class Info Analysis
; CHECK-NEXT: Prologue/Epilogue Insertion & Frame Finalization
; CHECK-NEXT: Post-RA pseudo instruction expansion pass
; CHECK-NEXT: AArch64 pseudo instruction expansion pass
diff --git a/llvm/test/CodeGen/LoongArch/O0-pipeline.ll b/llvm/test/CodeGen/LoongArch/O0-pipeline.ll
index bf519342fa4cc..8239636cfcdda 100644
--- a/llvm/test/CodeGen/LoongArch/O0-pipeline.ll
+++ b/llvm/test/CodeGen/LoongArch/O0-pipeline.ll
@@ -47,6 +47,7 @@
; CHECK-NEXT: Fixup Statepoint Caller Saved
; CHECK-NEXT: Lazy Machine Block Frequency Analysis
; CHECK-NEXT: Machine Optimization Remark Emitter
+; CHECK-NEXT: Machine Register Class Info Analysis
; CHECK-NEXT: Prologue/Epilogue Insertion & Frame Finalization
; CHECK-NEXT: Post-RA pseudo instruction expansion pass
; CHECK-NEXT: Analyze Machine Code For Garbage Collection
diff --git a/llvm/test/CodeGen/PowerPC/O0-pipeline.ll b/llvm/test/CodeGen/PowerPC/O0-pipeline.ll
index b0ba623edfb0a..94f6b8ffe49e3 100644
--- a/llvm/test/CodeGen/PowerPC/O0-pipeline.ll
+++ b/llvm/test/CodeGen/PowerPC/O0-pipeline.ll
@@ -53,6 +53,7 @@
; CHECK-NEXT: Fixup Statepoint Caller Saved
; CHECK-NEXT: Lazy Machine Block Frequency Analysis
; CHECK-NEXT: Machine Optimization Remark Emitter
+; CHECK-NEXT: Machine Register Class Info Analysis
; CHECK-NEXT: Prologue/Epilogue Insertion & Frame Finalization
; CHECK-NEXT: Post-RA pseudo instruction expansion pass
; CHECK-NEXT: Analyze Machine Code For Garbage Collection
diff --git a/llvm/test/CodeGen/RISCV/O0-pipeline.ll b/llvm/test/CodeGen/RISCV/O0-pipeline.ll
index 847a8bd96c6d6..900ad1a0fd320 100644
--- a/llvm/test/CodeGen/RISCV/O0-pipeline.ll
+++ b/llvm/test/CodeGen/RISCV/O0-pipeline.ll
@@ -55,6 +55,7 @@
; CHECK-NEXT: Fixup Statepoint Caller Saved
; CHECK-NEXT: Lazy Machine Block Frequency Analysis
; CHECK-NEXT: Machine Optimization Remark Emitter
+; CHECK-NEXT: Machine Register Class Info Analysis
; CHECK-NEXT: Prologue/Epilogue Insertion & Frame Finalization
; CHECK-NEXT: Post-RA pseudo instruction expansion pass
; CHECK-NEXT: RISC-V post-regalloc pseudo instruction expansion pass
diff --git a/llvm/test/CodeGen/SPIRV/llc-pipeline.ll b/llvm/test/CodeGen/SPIRV/llc-pipeline.ll
index c57945255a1f6..f55748a57ba80 100644
--- a/llvm/test/CodeGen/SPIRV/llc-pipeline.ll
+++ b/llvm/test/CodeGen/SPIRV/llc-pipeline.ll
@@ -75,6 +75,7 @@
; SPIRV-O0-NEXT: Fixup Statepoint Caller Saved
; SPIRV-O0-NEXT: Lazy Machine Block Frequency Analysis
; SPIRV-O0-NEXT: Machine Optimization Remark Emitter
+; SPIRV-O0-NEXT: Machine Register Class Info Analysis
; SPIRV-O0-NEXT: Prologue/Epilogue Insertion & Frame Finalization
; SPIRV-O0-NEXT: Post-RA pseudo instruction expansion pass
; SPIRV-O0-NEXT: Analyze Machine Code For Garbage Collection
diff --git a/llvm/test/CodeGen/X86/O0-pipeline.ll b/llvm/test/CodeGen/X86/O0-pipeline.ll
index e8a3084563573..372c2a476113c 100644
--- a/llvm/test/CodeGen/X86/O0-pipeline.ll
+++ b/llvm/test/CodeGen/X86/O0-pipeline.ll
@@ -58,6 +58,7 @@
; CHECK-NEXT: Fixup Statepoint Caller Saved
; CHECK-NEXT: Lazy Machine Block Frequency Analysis
; CHECK-NEXT: Machine Optimization Remark Emitter
+; CHECK-NEXT: Machine Register Class Info Analysis
; CHECK-NEXT: Prologue/Epilogue Insertion & Frame Finalization
; CHECK-NEXT: Post-RA pseudo instruction expansion pass
; CHECK-NEXT: X86 pseudo instruction expansion pass
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