[llvm] [AMDGPU][GlobalISel] Scale M0/GPR indirect index by element size (PR #216698)
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llvm-commits at lists.llvm.org
Mon Aug 17 04:27:11 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-llvm-globalisel
Author: Arseniy Obolenskiy (aobolensk)
<details>
<summary>Changes</summary>
M0/GPR-index addressing counts 32 bit registers, not bytes, so extracting/inserting elements wider than 32 bits needs the index scaled by `element size/4` before use
---
Patch is 36.70 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/216698.diff
4 Files Affected:
- (modified) llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp (+21-3)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll (+46-44)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-extract-vector-elt.mir (+28-14)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-insert-vector-elt.mir (+16-8)
``````````diff
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
index 0a5dbca02fea2..56647c382065e 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
@@ -3411,6 +3411,23 @@ computeIndirectRegIndex(MachineRegisterInfo &MRI, const SIRegisterInfo &TRI,
return std::pair(IdxBaseReg, SubRegs[Offset]);
}
+/// M0/GPR-index addressing counts 32-bit registers, not EltSize-byte elements.
+static Register scaleIndirectIdxReg(MachineRegisterInfo &MRI,
+ const SIInstrInfo &TII,
+ MachineBasicBlock &BB, MachineInstr &I,
+ const DebugLoc &DL, Register IdxReg,
+ unsigned EltSize) {
+ if (EltSize <= 4)
+ return IdxReg;
+
+ assert(isPowerOf2_32(EltSize) && "cannot scale index by a shift");
+ Register ScaledIdxReg = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
+ BuildMI(BB, I, DL, TII.get(AMDGPU::S_LSHL_B32), ScaledIdxReg)
+ .addReg(IdxReg)
+ .addImm(Log2_32(EltSize / 4));
+ return ScaledIdxReg;
+}
+
bool AMDGPUInstructionSelector::selectG_EXTRACT_VECTOR_ELT(
MachineInstr &MI) const {
Register DstReg = MI.getOperand(0).getReg();
@@ -3452,6 +3469,9 @@ bool AMDGPUInstructionSelector::selectG_EXTRACT_VECTOR_ELT(
if (DstTy.getSizeInBits() != 32 && !Is64)
return false;
+ IdxReg = scaleIndirectIdxReg(*MRI, TII, *BB, MI, DL, IdxReg,
+ DstTy.getSizeInBits() / 8);
+
BuildMI(*BB, &MI, DL, TII.get(AMDGPU::COPY), AMDGPU::M0)
.addReg(IdxReg);
@@ -3463,9 +3483,6 @@ bool AMDGPUInstructionSelector::selectG_EXTRACT_VECTOR_ELT(
return true;
}
- if (SrcRB->getID() != AMDGPU::VGPRRegBankID || DstTy.getSizeInBits() != 32)
- return false;
-
if (!STI.useVGPRIndexMode()) {
BuildMI(*BB, &MI, DL, TII.get(AMDGPU::COPY), AMDGPU::M0)
.addReg(IdxReg);
@@ -3534,6 +3551,7 @@ bool AMDGPUInstructionSelector::selectG_INSERT_VECTOR_ELT(
MachineBasicBlock *BB = MI.getParent();
const DebugLoc &DL = MI.getDebugLoc();
+ IdxReg = scaleIndirectIdxReg(*MRI, TII, *BB, MI, DL, IdxReg, ValSize / 8);
if (!IndexMode) {
BuildMI(*BB, &MI, DL, TII.get(AMDGPU::COPY), AMDGPU::M0)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
index bff28f14bbfa5..381c02754cf68 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
@@ -288,7 +288,7 @@ define amdgpu_ps void @dyn_extract_v8i64_const_s_s(i32 inreg %sel) {
; GPRIDX-LABEL: dyn_extract_v8i64_const_s_s:
; GPRIDX: ; %bb.0: ; %entry
; GPRIDX-NEXT: s_mov_b64 s[4:5], 1
-; GPRIDX-NEXT: s_mov_b32 m0, s2
+; GPRIDX-NEXT: s_lshl_b32 m0, s2, 1
; GPRIDX-NEXT: s_mov_b64 s[18:19], 8
; GPRIDX-NEXT: s_mov_b64 s[16:17], 7
; GPRIDX-NEXT: s_mov_b64 s[14:15], 6
@@ -305,7 +305,7 @@ define amdgpu_ps void @dyn_extract_v8i64_const_s_s(i32 inreg %sel) {
; MOVREL-LABEL: dyn_extract_v8i64_const_s_s:
; MOVREL: ; %bb.0: ; %entry
; MOVREL-NEXT: s_mov_b64 s[4:5], 1
-; MOVREL-NEXT: s_mov_b32 m0, s2
+; MOVREL-NEXT: s_lshl_b32 m0, s2, 1
; MOVREL-NEXT: s_mov_b64 s[18:19], 8
; MOVREL-NEXT: s_mov_b64 s[16:17], 7
; MOVREL-NEXT: s_mov_b64 s[14:15], 6
@@ -322,7 +322,7 @@ define amdgpu_ps void @dyn_extract_v8i64_const_s_s(i32 inreg %sel) {
; GFX10-LABEL: dyn_extract_v8i64_const_s_s:
; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: s_mov_b64 s[4:5], 1
-; GFX10-NEXT: s_mov_b32 m0, s2
+; GFX10-NEXT: s_lshl_b32 m0, s2, 1
; GFX10-NEXT: s_mov_b64 s[18:19], 8
; GFX10-NEXT: s_mov_b64 s[16:17], 7
; GFX10-NEXT: s_mov_b64 s[14:15], 6
@@ -339,7 +339,7 @@ define amdgpu_ps void @dyn_extract_v8i64_const_s_s(i32 inreg %sel) {
; GFX11-LABEL: dyn_extract_v8i64_const_s_s:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_mov_b64 s[4:5], 1
-; GFX11-NEXT: s_mov_b32 m0, s2
+; GFX11-NEXT: s_lshl_b32 m0, s2, 1
; GFX11-NEXT: s_mov_b64 s[18:19], 8
; GFX11-NEXT: s_mov_b64 s[16:17], 7
; GFX11-NEXT: s_mov_b64 s[14:15], 6
@@ -623,7 +623,7 @@ define amdgpu_ps void @dyn_extract_v8i64_s_s(<8 x i64> inreg %vec, i32 inreg %se
; GPRIDX: ; %bb.0: ; %entry
; GPRIDX-NEXT: s_mov_b32 s0, s2
; GPRIDX-NEXT: s_mov_b32 s1, s3
-; GPRIDX-NEXT: s_mov_b32 m0, s18
+; GPRIDX-NEXT: s_lshl_b32 m0, s18, 1
; GPRIDX-NEXT: s_mov_b32 s2, s4
; GPRIDX-NEXT: s_mov_b32 s3, s5
; GPRIDX-NEXT: s_mov_b32 s4, s6
@@ -648,7 +648,7 @@ define amdgpu_ps void @dyn_extract_v8i64_s_s(<8 x i64> inreg %vec, i32 inreg %se
; MOVREL: ; %bb.0: ; %entry
; MOVREL-NEXT: s_mov_b32 s0, s2
; MOVREL-NEXT: s_mov_b32 s1, s3
-; MOVREL-NEXT: s_mov_b32 m0, s18
+; MOVREL-NEXT: s_lshl_b32 m0, s18, 1
; MOVREL-NEXT: s_mov_b32 s2, s4
; MOVREL-NEXT: s_mov_b32 s3, s5
; MOVREL-NEXT: s_mov_b32 s4, s6
@@ -673,7 +673,7 @@ define amdgpu_ps void @dyn_extract_v8i64_s_s(<8 x i64> inreg %vec, i32 inreg %se
; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: s_mov_b32 s0, s2
; GFX10-NEXT: s_mov_b32 s1, s3
-; GFX10-NEXT: s_mov_b32 m0, s18
+; GFX10-NEXT: s_lshl_b32 m0, s18, 1
; GFX10-NEXT: s_mov_b32 s2, s4
; GFX10-NEXT: s_mov_b32 s3, s5
; GFX10-NEXT: s_mov_b32 s4, s6
@@ -698,7 +698,7 @@ define amdgpu_ps void @dyn_extract_v8i64_s_s(<8 x i64> inreg %vec, i32 inreg %se
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_mov_b32 s0, s2
; GFX11-NEXT: s_mov_b32 s1, s3
-; GFX11-NEXT: s_mov_b32 m0, s18
+; GFX11-NEXT: s_lshl_b32 m0, s18, 1
; GFX11-NEXT: s_mov_b32 s2, s4
; GFX11-NEXT: s_mov_b32 s3, s5
; GFX11-NEXT: s_mov_b32 s4, s6
@@ -832,7 +832,7 @@ define amdgpu_ps double @dyn_extract_v8f64_s_s_offset1(<8 x double> inreg %vec,
; GCN-NEXT: s_mov_b32 s1, s3
; GCN-NEXT: s_mov_b32 s2, s4
; GCN-NEXT: s_mov_b32 s3, s5
-; GCN-NEXT: s_mov_b32 m0, s18
+; GCN-NEXT: s_lshl_b32 m0, s18, 1
; GCN-NEXT: s_mov_b32 s4, s6
; GCN-NEXT: s_mov_b32 s5, s7
; GCN-NEXT: s_mov_b32 s6, s8
@@ -854,7 +854,7 @@ define amdgpu_ps double @dyn_extract_v8f64_s_s_offset1(<8 x double> inreg %vec,
; GFX10PLUS-NEXT: s_mov_b32 s1, s3
; GFX10PLUS-NEXT: s_mov_b32 s2, s4
; GFX10PLUS-NEXT: s_mov_b32 s3, s5
-; GFX10PLUS-NEXT: s_mov_b32 m0, s18
+; GFX10PLUS-NEXT: s_lshl_b32 m0, s18, 1
; GFX10PLUS-NEXT: s_mov_b32 s4, s6
; GFX10PLUS-NEXT: s_mov_b32 s5, s7
; GFX10PLUS-NEXT: s_mov_b32 s6, s8
@@ -884,7 +884,7 @@ define amdgpu_ps double @dyn_extract_v8f64_s_s_offset2(<8 x double> inreg %vec,
; GCN-NEXT: s_mov_b32 s3, s5
; GCN-NEXT: s_mov_b32 s4, s6
; GCN-NEXT: s_mov_b32 s5, s7
-; GCN-NEXT: s_mov_b32 m0, s18
+; GCN-NEXT: s_lshl_b32 m0, s18, 1
; GCN-NEXT: s_mov_b32 s6, s8
; GCN-NEXT: s_mov_b32 s7, s9
; GCN-NEXT: s_mov_b32 s8, s10
@@ -906,7 +906,7 @@ define amdgpu_ps double @dyn_extract_v8f64_s_s_offset2(<8 x double> inreg %vec,
; GFX10PLUS-NEXT: s_mov_b32 s3, s5
; GFX10PLUS-NEXT: s_mov_b32 s4, s6
; GFX10PLUS-NEXT: s_mov_b32 s5, s7
-; GFX10PLUS-NEXT: s_mov_b32 m0, s18
+; GFX10PLUS-NEXT: s_lshl_b32 m0, s18, 1
; GFX10PLUS-NEXT: s_mov_b32 s6, s8
; GFX10PLUS-NEXT: s_mov_b32 s7, s9
; GFX10PLUS-NEXT: s_mov_b32 s8, s10
@@ -936,7 +936,7 @@ define amdgpu_ps double @dyn_extract_v8f64_s_s_offset3(<8 x double> inreg %vec,
; GCN-NEXT: s_mov_b32 s5, s7
; GCN-NEXT: s_mov_b32 s6, s8
; GCN-NEXT: s_mov_b32 s7, s9
-; GCN-NEXT: s_mov_b32 m0, s18
+; GCN-NEXT: s_lshl_b32 m0, s18, 1
; GCN-NEXT: s_mov_b32 s8, s10
; GCN-NEXT: s_mov_b32 s9, s11
; GCN-NEXT: s_mov_b32 s10, s12
@@ -958,7 +958,7 @@ define amdgpu_ps double @dyn_extract_v8f64_s_s_offset3(<8 x double> inreg %vec,
; GFX10PLUS-NEXT: s_mov_b32 s5, s7
; GFX10PLUS-NEXT: s_mov_b32 s6, s8
; GFX10PLUS-NEXT: s_mov_b32 s7, s9
-; GFX10PLUS-NEXT: s_mov_b32 m0, s18
+; GFX10PLUS-NEXT: s_lshl_b32 m0, s18, 1
; GFX10PLUS-NEXT: s_mov_b32 s8, s10
; GFX10PLUS-NEXT: s_mov_b32 s9, s11
; GFX10PLUS-NEXT: s_mov_b32 s10, s12
@@ -988,7 +988,7 @@ define amdgpu_ps double @dyn_extract_v8f64_s_s_offset4(<8 x double> inreg %vec,
; GCN-NEXT: s_mov_b32 s7, s9
; GCN-NEXT: s_mov_b32 s8, s10
; GCN-NEXT: s_mov_b32 s9, s11
-; GCN-NEXT: s_mov_b32 m0, s18
+; GCN-NEXT: s_lshl_b32 m0, s18, 1
; GCN-NEXT: s_mov_b32 s10, s12
; GCN-NEXT: s_mov_b32 s11, s13
; GCN-NEXT: s_mov_b32 s12, s14
@@ -1010,7 +1010,7 @@ define amdgpu_ps double @dyn_extract_v8f64_s_s_offset4(<8 x double> inreg %vec,
; GFX10PLUS-NEXT: s_mov_b32 s7, s9
; GFX10PLUS-NEXT: s_mov_b32 s8, s10
; GFX10PLUS-NEXT: s_mov_b32 s9, s11
-; GFX10PLUS-NEXT: s_mov_b32 m0, s18
+; GFX10PLUS-NEXT: s_lshl_b32 m0, s18, 1
; GFX10PLUS-NEXT: s_mov_b32 s10, s12
; GFX10PLUS-NEXT: s_mov_b32 s11, s13
; GFX10PLUS-NEXT: s_mov_b32 s12, s14
@@ -1040,7 +1040,7 @@ define amdgpu_ps double @dyn_extract_v8f64_s_s_offset5(<8 x double> inreg %vec,
; GCN-NEXT: s_mov_b32 s9, s11
; GCN-NEXT: s_mov_b32 s10, s12
; GCN-NEXT: s_mov_b32 s11, s13
-; GCN-NEXT: s_mov_b32 m0, s18
+; GCN-NEXT: s_lshl_b32 m0, s18, 1
; GCN-NEXT: s_mov_b32 s12, s14
; GCN-NEXT: s_mov_b32 s13, s15
; GCN-NEXT: s_mov_b32 s14, s16
@@ -1062,7 +1062,7 @@ define amdgpu_ps double @dyn_extract_v8f64_s_s_offset5(<8 x double> inreg %vec,
; GFX10PLUS-NEXT: s_mov_b32 s9, s11
; GFX10PLUS-NEXT: s_mov_b32 s10, s12
; GFX10PLUS-NEXT: s_mov_b32 s11, s13
-; GFX10PLUS-NEXT: s_mov_b32 m0, s18
+; GFX10PLUS-NEXT: s_lshl_b32 m0, s18, 1
; GFX10PLUS-NEXT: s_mov_b32 s12, s14
; GFX10PLUS-NEXT: s_mov_b32 s13, s15
; GFX10PLUS-NEXT: s_mov_b32 s14, s16
@@ -1092,7 +1092,7 @@ define amdgpu_ps double @dyn_extract_v8f64_s_s_offset6(<8 x double> inreg %vec,
; GCN-NEXT: s_mov_b32 s11, s13
; GCN-NEXT: s_mov_b32 s12, s14
; GCN-NEXT: s_mov_b32 s13, s15
-; GCN-NEXT: s_mov_b32 m0, s18
+; GCN-NEXT: s_lshl_b32 m0, s18, 1
; GCN-NEXT: s_mov_b32 s14, s16
; GCN-NEXT: s_mov_b32 s15, s17
; GCN-NEXT: s_movrels_b64 s[0:1], s[12:13]
@@ -1114,7 +1114,7 @@ define amdgpu_ps double @dyn_extract_v8f64_s_s_offset6(<8 x double> inreg %vec,
; GFX10PLUS-NEXT: s_mov_b32 s11, s13
; GFX10PLUS-NEXT: s_mov_b32 s12, s14
; GFX10PLUS-NEXT: s_mov_b32 s13, s15
-; GFX10PLUS-NEXT: s_mov_b32 m0, s18
+; GFX10PLUS-NEXT: s_lshl_b32 m0, s18, 1
; GFX10PLUS-NEXT: s_mov_b32 s14, s16
; GFX10PLUS-NEXT: s_mov_b32 s15, s17
; GFX10PLUS-NEXT: s_movrels_b64 s[0:1], s[12:13]
@@ -1144,7 +1144,7 @@ define amdgpu_ps double @dyn_extract_v8f64_s_s_offset7(<8 x double> inreg %vec,
; GPRIDX-NEXT: s_mov_b32 s13, s15
; GPRIDX-NEXT: s_mov_b32 s14, s16
; GPRIDX-NEXT: s_mov_b32 s15, s17
-; GPRIDX-NEXT: s_mov_b32 m0, s18
+; GPRIDX-NEXT: s_lshl_b32 m0, s18, 1
; GPRIDX-NEXT: s_nop 0
; GPRIDX-NEXT: s_movrels_b64 s[0:1], s[14:15]
; GPRIDX-NEXT: ; return to shader part epilog
@@ -1167,7 +1167,7 @@ define amdgpu_ps double @dyn_extract_v8f64_s_s_offset7(<8 x double> inreg %vec,
; MOVREL-NEXT: s_mov_b32 s13, s15
; MOVREL-NEXT: s_mov_b32 s14, s16
; MOVREL-NEXT: s_mov_b32 s15, s17
-; MOVREL-NEXT: s_mov_b32 m0, s18
+; MOVREL-NEXT: s_lshl_b32 m0, s18, 1
; MOVREL-NEXT: s_movrels_b64 s[0:1], s[14:15]
; MOVREL-NEXT: ; return to shader part epilog
;
@@ -1189,7 +1189,7 @@ define amdgpu_ps double @dyn_extract_v8f64_s_s_offset7(<8 x double> inreg %vec,
; GFX10PLUS-NEXT: s_mov_b32 s13, s15
; GFX10PLUS-NEXT: s_mov_b32 s14, s16
; GFX10PLUS-NEXT: s_mov_b32 s15, s17
-; GFX10PLUS-NEXT: s_mov_b32 m0, s18
+; GFX10PLUS-NEXT: s_lshl_b32 m0, s18, 1
; GFX10PLUS-NEXT: s_movrels_b64 s[0:1], s[14:15]
; GFX10PLUS-NEXT: ; return to shader part epilog
entry:
@@ -1201,9 +1201,10 @@ entry:
define amdgpu_ps double @dyn_extract_v8f64_s_s_offsetm1(<8 x double> inreg %vec, i32 inreg %sel) {
; GCN-LABEL: dyn_extract_v8f64_s_s_offsetm1:
; GCN: ; %bb.0: ; %entry
+; GCN-NEXT: s_add_i32 s18, s18, -1
; GCN-NEXT: s_mov_b32 s0, s2
; GCN-NEXT: s_mov_b32 s1, s3
-; GCN-NEXT: s_add_i32 m0, s18, -1
+; GCN-NEXT: s_lshl_b32 m0, s18, 1
; GCN-NEXT: s_mov_b32 s2, s4
; GCN-NEXT: s_mov_b32 s3, s5
; GCN-NEXT: s_mov_b32 s4, s6
@@ -1223,9 +1224,10 @@ define amdgpu_ps double @dyn_extract_v8f64_s_s_offsetm1(<8 x double> inreg %vec,
;
; GFX10PLUS-LABEL: dyn_extract_v8f64_s_s_offsetm1:
; GFX10PLUS: ; %bb.0: ; %entry
+; GFX10PLUS-NEXT: s_add_i32 s18, s18, -1
; GFX10PLUS-NEXT: s_mov_b32 s0, s2
; GFX10PLUS-NEXT: s_mov_b32 s1, s3
-; GFX10PLUS-NEXT: s_add_i32 m0, s18, -1
+; GFX10PLUS-NEXT: s_lshl_b32 m0, s18, 1
; GFX10PLUS-NEXT: s_mov_b32 s2, s4
; GFX10PLUS-NEXT: s_mov_b32 s3, s5
; GFX10PLUS-NEXT: s_mov_b32 s4, s6
@@ -1550,7 +1552,7 @@ define amdgpu_ps void @dyn_extract_v8p1_s_s(<8 x ptr addrspace(1)> inreg %vec, i
; GPRIDX: ; %bb.0: ; %entry
; GPRIDX-NEXT: s_mov_b32 s0, s2
; GPRIDX-NEXT: s_mov_b32 s1, s3
-; GPRIDX-NEXT: s_mov_b32 m0, s18
+; GPRIDX-NEXT: s_lshl_b32 m0, s18, 1
; GPRIDX-NEXT: s_mov_b32 s2, s4
; GPRIDX-NEXT: s_mov_b32 s3, s5
; GPRIDX-NEXT: s_mov_b32 s4, s6
@@ -1575,7 +1577,7 @@ define amdgpu_ps void @dyn_extract_v8p1_s_s(<8 x ptr addrspace(1)> inreg %vec, i
; MOVREL: ; %bb.0: ; %entry
; MOVREL-NEXT: s_mov_b32 s0, s2
; MOVREL-NEXT: s_mov_b32 s1, s3
-; MOVREL-NEXT: s_mov_b32 m0, s18
+; MOVREL-NEXT: s_lshl_b32 m0, s18, 1
; MOVREL-NEXT: s_mov_b32 s2, s4
; MOVREL-NEXT: s_mov_b32 s3, s5
; MOVREL-NEXT: s_mov_b32 s4, s6
@@ -1600,7 +1602,7 @@ define amdgpu_ps void @dyn_extract_v8p1_s_s(<8 x ptr addrspace(1)> inreg %vec, i
; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: s_mov_b32 s0, s2
; GFX10-NEXT: s_mov_b32 s1, s3
-; GFX10-NEXT: s_mov_b32 m0, s18
+; GFX10-NEXT: s_lshl_b32 m0, s18, 1
; GFX10-NEXT: s_mov_b32 s2, s4
; GFX10-NEXT: s_mov_b32 s3, s5
; GFX10-NEXT: s_mov_b32 s4, s6
@@ -1625,7 +1627,7 @@ define amdgpu_ps void @dyn_extract_v8p1_s_s(<8 x ptr addrspace(1)> inreg %vec, i
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_mov_b32 s0, s2
; GFX11-NEXT: s_mov_b32 s1, s3
-; GFX11-NEXT: s_mov_b32 m0, s18
+; GFX11-NEXT: s_lshl_b32 m0, s18, 1
; GFX11-NEXT: s_mov_b32 s2, s4
; GFX11-NEXT: s_mov_b32 s3, s5
; GFX11-NEXT: s_mov_b32 s4, s6
@@ -1870,7 +1872,7 @@ define amdgpu_ps double @dyn_extract_v16f64_s_s(i32 inreg %sel) {
; GCN-LABEL: dyn_extract_v16f64_s_s:
; GCN: ; %bb.0: ; %entry
; GCN-NEXT: s_mov_b64 s[36:37], 1.0
-; GCN-NEXT: s_mov_b32 m0, s2
+; GCN-NEXT: s_lshl_b32 m0, s2, 1
; GCN-NEXT: s_mov_b32 s66, 0
; GCN-NEXT: s_mov_b32 s67, 0x40300000
; GCN-NEXT: s_mov_b32 s64, 0
@@ -1905,7 +1907,7 @@ define amdgpu_ps double @dyn_extract_v16f64_s_s(i32 inreg %sel) {
; GFX10PLUS-LABEL: dyn_extract_v16f64_s_s:
; GFX10PLUS: ; %bb.0: ; %entry
; GFX10PLUS-NEXT: s_mov_b64 s[36:37], 1.0
-; GFX10PLUS-NEXT: s_mov_b32 m0, s2
+; GFX10PLUS-NEXT: s_lshl_b32 m0, s2, 1
; GFX10PLUS-NEXT: s_mov_b32 s66, 0
; GFX10PLUS-NEXT: s_mov_b32 s67, 0x40300000
; GFX10PLUS-NEXT: s_mov_b32 s64, 0
@@ -2394,7 +2396,7 @@ define amdgpu_ps double @dyn_extract_v6f64_s_s(<6 x double> inreg %vec, i32 inre
; GCN: ; %bb.0: ; %entry
; GCN-NEXT: s_mov_b32 s0, s2
; GCN-NEXT: s_mov_b32 s1, s3
-; GCN-NEXT: s_mov_b32 m0, s14
+; GCN-NEXT: s_lshl_b32 m0, s14, 1
; GCN-NEXT: s_mov_b32 s2, s4
; GCN-NEXT: s_mov_b32 s3, s5
; GCN-NEXT: s_mov_b32 s4, s6
@@ -2412,7 +2414,7 @@ define amdgpu_ps double @dyn_extract_v6f64_s_s(<6 x double> inreg %vec, i32 inre
; GFX10PLUS: ; %bb.0: ; %entry
; GFX10PLUS-NEXT: s_mov_b32 s0, s2
; GFX10PLUS-NEXT: s_mov_b32 s1, s3
-; GFX10PLUS-NEXT: s_mov_b32 m0, s14
+; GFX10PLUS-NEXT: s_lshl_b32 m0, s14, 1
; GFX10PLUS-NEXT: s_mov_b32 s2, s4
; GFX10PLUS-NEXT: s_mov_b32 s3, s5
; GFX10PLUS-NEXT: s_mov_b32 s4, s6
@@ -2780,7 +2782,7 @@ define amdgpu_ps double @dyn_extract_v7f64_s_s(<7 x double> inreg %vec, i32 inre
; GCN: ; %bb.0: ; %entry
; GCN-NEXT: s_mov_b32 s0, s2
; GCN-NEXT: s_mov_b32 s1, s3
-; GCN-NEXT: s_mov_b32 m0, s16
+; GCN-NEXT: s_lshl_b32 m0, s16, 1
; GCN-NEXT: s_mov_b32 s2, s4
; GCN-NEXT: s_mov_b32 s3, s5
; GCN-NEXT: s_mov_b32 s4, s6
@@ -2800,7 +2802,7 @@ define amdgpu_ps double @dyn_extract_v7f64_s_s(<7 x double> inreg %vec, i32 inre
; GFX10PLUS: ; %bb.0: ; %entry
; GFX10PLUS-NEXT: s_mov_b32 s0, s2
; GFX10PLUS-NEXT: s_mov_b32 s1, s3
-; GFX10PLUS-NEXT: s_mov_b32 m0, s16
+; GFX10PLUS-NEXT: s_lshl_b32 m0, s16, 1
; GFX10PLUS-NEXT: s_mov_b32 s2, s4
; GFX10PLUS-NEXT: s_mov_b32 s3, s5
; GFX10PLUS-NEXT: s_mov_b32 s4, s6
@@ -2898,7 +2900,7 @@ define amdgpu_kernel void @dyn_extract_v5f64_s_s(ptr addrspace(1) %out, i32 %sel
; GPRIDX-NEXT: s_mov_b32 s13, 0x40140000
; GPRIDX-NEXT: s_mov_b64 s[10:11], 4.0
; GPRIDX-NEXT: s_waitcnt lgkmcnt(0)
-; GPRIDX-NEXT: s_mov_b32 m0, s2
+; GPRIDX-NEXT: s_lshl_b32 m0, s2, 1
; GPRIDX-NEXT: s_mov_b32 s8, 0
; GPRIDX-NEXT: s_mov_b32 s9, 0x40080000
; GPRIDX-NEXT: s_mov_b64 s[6:7], 2.0
@@ -2986,7 +2988,7 @@ define amdgpu_kernel void @dyn_extract_v5f64_s_s(ptr addrspace(1) %out, i32 %sel
; MOVREL-NEXT: s_mov_b32 flat_scratch_lo, s13
; MOVREL-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; MOVREL-NEXT: s_waitcnt lgkmcnt(0)
-; MOVREL-NEXT: s_mov_b32 m0, s2
+; MOVREL-NEXT: s_lshl_b32 m0, s2, 1
; MOVREL-NEXT: s_mov_b32 s12, 0
; MOVREL-NEXT: s_mov_b32 s13, 0x40140000
; MOVREL-NEXT: s_mov_b64 s[10:11], 4.0
@@ -3083,7 +3085,7 @@ define amdgpu_kernel void @dyn_extract_v5f64_s_s(ptr addrspace(1) %out, i32 %sel
; GFX10-NEXT: s_mov_b64 s[2:3], 2.0
; GFX10-NEXT: v_mov_b32_e32 v2, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-NEXT: s_mov_b32 m0, s12
+; GFX10-NEXT: s_lshl_b32 m0, s12, 1
; GFX10-NEXT: s_movrels_b64 s[0:1], s[0:1]
; GFX10-NEXT: v_mov_b32_e32 v0, s0
; GFX10-NEXT: v_mov_b32_e32 v1, s1
@@ -3172,7 +3174,7 @@ define amdgpu_kernel void @dyn_extract_v5f64_s_s(ptr addrspace(1) %out, i32 %sel
; GFX11-NEXT: s_mov_b64 s[2:3], 2.0
; GFX11-NEXT: v_mov_b32_e32 v2, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: s_mov_b32 m0, s12
+; GFX11-NEXT: s_lshl_b32 m0, s12, 1
; GFX11-NEXT: s_movrels_b64 s[0:1], s[0:1]
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX11-NEXT: global_store_b64 v2, v[0:1], s[10:11]
@@ -4252,7 +4254,7 @@ define amdgpu_kernel void @dyn_extract_v4f64_s_s_s(ptr addrspace(1) %out, i32 %s
; GPRIDX-NEXT: s_mov_b32 s4, 0
; GPRIDX-NEXT: s_mov_b32 s5, 0x40080000
; GPRIDX-NEXT: s_waitcnt lgkmcnt(0)
-; GPRIDX-NEXT: s_mov_b32 m0, s12
+; GPRIDX-NEXT: s_lshl_b32 m0, s12, 1
; GPRIDX-NEXT: s_mov_b64 s[2:3], 2.0
; GPRIDX-NEXT: s_movrels_b64 s[0:1], s[0:1]
; GPRIDX-NEXT: v_mov_b32_e32 v0, s0
@@ -4333,12 +4335,12 @@ define amdgpu_kernel void @dyn_extract_v4f64_s_s_s(ptr addrspace(1) %out, i32 %s
; MOVREL-NEXT: ; %bb.0: ; %entry
; MOVREL-NEXT: s_load_dwordx2 s[10:11], s[8:9], 0x0
; MOVREL-NEXT: s_load_dword s8, s[8:9], 0x8
-; MOVREL-NEXT: s_mov_b64 s[0:1], 1.0
; MOVREL-NEXT: s_add_i32 s12, s12, s17
+; MOVREL-NEXT: s_mov_b64 s[0:1], 1.0
; MOVREL-NEXT: s_mov_b64 s[6:7], 4.0
; MOVREL-NEXT: s_mov_b32 s4, 0
; MOVREL-NEXT: s_waitcnt lgkmcnt(0)
-; MOVREL-NEXT: s_mov_b32 m0, s8
+; MOVREL-NEXT: s_lshl_b32 m0, s8, 1
; MOVREL-NEXT: s_mov_b32 s5, 0x40080000
; MOVREL-NEXT: s_mov_b64 s[2:3], 2.0
; MOVREL-NEXT: s_movrels_b64 s[0:1], s[0:1]
@@ -4431,7 +4433,7 @@ define amdgpu_kernel void @dyn_extract_v4f64_s_s_s(ptr addrspace(1) %out, i32 %s
; GFX10-NEXT: s_mov_b64 s[2:3], 2.0
; GFX10-NEXT: v_mov_b32_e32 v2, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-NEXT: s_mov_b32 m0, s12
+; GFX10-NEXT: s_lshl_b32 m0, s12, 1
; GFX10-NEXT: s_movrels_b64 s[0:1], s[0:1]
; GFX10-NEXT: v_mov_b32_e32 v0, s0
; GFX10-NEXT: v_mov_b32_e32 v1, s1
@@ -4518,7 +4520,7 @@ define amdgpu_kernel void @dyn_extract_v4f64_s_s_s(ptr addrspace(1) %out, i32 %s
; GFX11-NEXT: s_mov_b64 s[2:3], 2.0
; GFX11-NEXT: v_mov_b32_e32 v2, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: s_mov_b32 m0, s10
+; GFX11-NEXT: s_lshl_b32 m0, s10, 1
; GFX11-NEXT: ...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/216698
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