[llvm] [AMDGPU] Fix BFMPatterns mutliclass operand type for i64 (PR #216690)
Madhur Kumar via llvm-commits
llvm-commits at lists.llvm.org
Mon Aug 17 03:33:16 PDT 2026
https://github.com/MadhurKumar004 created https://github.com/llvm/llvm-project/pull/216690
The operands ($a, $b) were typed with vt, making them i64 when instantiated with BFMPatterns<i64,...>. This conflicts with the instruction's i32 operands (SSrc_b32), causing tablegen to fail with "Type set is empty". Type them as i32 explicitly, since all BFM instructions use 32-bit count operands regardless of result type.
>From e3aa83f220b4a12c69e0778faf8092d08a5253fd Mon Sep 17 00:00:00 2001
From: Madhur Kumar <madhurkumar004 at gmail.com>
Date: Mon, 17 Aug 2026 15:29:20 +0530
Subject: [PATCH 1/2] Pre-commit test
---
llvm/test/CodeGen/AMDGPU/bfm.ll | 79 +++++++++++++++++++++++++++++++++
1 file changed, 79 insertions(+)
diff --git a/llvm/test/CodeGen/AMDGPU/bfm.ll b/llvm/test/CodeGen/AMDGPU/bfm.ll
index 1db9f9344f8ca..2b18face3691f 100644
--- a/llvm/test/CodeGen/AMDGPU/bfm.ll
+++ b/llvm/test/CodeGen/AMDGPU/bfm.ll
@@ -89,6 +89,85 @@ define void @v_bfm_pattern(ptr addrspace(1) %out, i32 %x, i32 %y) #0 {
ret void
}
+define amdgpu_kernel void @s_bfm64_pattern(ptr addrspace(1) %out, i64 %x, i64 %y) #0 {
+; SI-LABEL: s_bfm64_pattern:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_load_dword s3, s[4:5], 0xd
+; SI-NEXT: s_mov_b32 s7, 0xf000
+; SI-NEXT: s_mov_b32 s6, -1
+; SI-NEXT: s_mov_b32 s4, s0
+; SI-NEXT: s_mov_b32 s5, s1
+; SI-NEXT: s_lshl_b64 s[0:1], 1, s2
+; SI-NEXT: s_add_u32 s0, s0, -1
+; SI-NEXT: s_addc_u32 s1, s1, -1
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_lshl_b64 s[0:1], s[0:1], s3
+; SI-NEXT: v_mov_b32_e32 v0, s0
+; SI-NEXT: v_mov_b32_e32 v1, s1
+; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: s_bfm64_pattern:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_load_dword s3, s[4:5], 0x34
+; VI-NEXT: v_mov_b32_e32 v0, s0
+; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: s_lshl_b64 s[0:1], 1, s2
+; VI-NEXT: s_add_u32 s0, s0, -1
+; VI-NEXT: s_addc_u32 s1, s1, -1
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_lshl_b64 s[0:1], s[0:1], s3
+; VI-NEXT: v_mov_b32_e32 v3, s1
+; VI-NEXT: v_mov_b32_e32 v2, s0
+; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
+; VI-NEXT: s_endpgm
+ %a = shl i64 1, %x
+ %b = sub i64 %a, 1
+ %c = shl i64 %b, %y
+ store i64 %c, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_kernel void @s_bfm64_pattern_simple(ptr addrspace(1) %out, i64 %x) #0 {
+; SI-LABEL: s_bfm64_pattern_simple:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; SI-NEXT: s_mov_b32 s7, 0xf000
+; SI-NEXT: s_mov_b32 s6, -1
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_mov_b32 s4, s0
+; SI-NEXT: s_mov_b32 s5, s1
+; SI-NEXT: s_lshl_b64 s[0:1], 1, s2
+; SI-NEXT: s_add_u32 s0, s0, -1
+; SI-NEXT: s_addc_u32 s1, s1, -1
+; SI-NEXT: v_mov_b32_e32 v0, s0
+; SI-NEXT: v_mov_b32_e32 v1, s1
+; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: s_bfm64_pattern_simple:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v0, s0
+; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: s_lshl_b64 s[0:1], 1, s2
+; VI-NEXT: s_add_u32 s0, s0, -1
+; VI-NEXT: s_addc_u32 s1, s1, -1
+; VI-NEXT: v_mov_b32_e32 v3, s1
+; VI-NEXT: v_mov_b32_e32 v2, s0
+; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
+; VI-NEXT: s_endpgm
+ %a = shl i64 1, %x
+ %b = sub i64 %a, 1
+ store i64 %b, ptr addrspace(1) %out
+ ret void
+}
+
define void @v_bfm_pattern_simple(ptr addrspace(1) %out, i32 %x) #0 {
; SI-LABEL: v_bfm_pattern_simple:
; SI: ; %bb.0:
>From 9d7937b9426534150b61e9a69fcc673e4fe663f9 Mon Sep 17 00:00:00 2001
From: Madhur Kumar <madhurkumar004 at gmail.com>
Date: Mon, 17 Aug 2026 15:34:10 +0530
Subject: [PATCH 2/2] [AMDGPU] Fix BFMPatterns mutliclass operand type for i64
---
llvm/lib/Target/AMDGPU/SIInstructions.td | 6 +++---
llvm/test/CodeGen/AMDGPU/bfm.ll | 18 ++++--------------
2 files changed, 7 insertions(+), 17 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
index 36cacfd47f62c..5fce07e2ac262 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -4385,18 +4385,18 @@ def : GCNPat<
multiclass BFMPatterns <ValueType vt, PatFrag SHL, PatFrag ADD, InstSI BFM> {
def : GCNPat <
- (vt (SHL (vt (add (vt (shl 1, vt:$a)), -1)), vt:$b)),
+ (vt (SHL (vt (add (vt (shl 1, i32:$a)), -1)), i32:$b)),
(BFM $a, $b)
>;
def : GCNPat <
- (vt (ADD (vt (shl 1, vt:$a)), -1)),
+ (vt (ADD (vt (shl 1, i32:$a)), -1)),
(BFM $a, (i32 0))
>;
}
defm : BFMPatterns <i32, UniformBinFrag<shl>, UniformBinFrag<add>, S_BFM_B32>;
-// FIXME: defm : BFMPatterns <i64, UniformBinFrag<shl>, UniformBinFrag<add>, S_BFM_B64>;
+defm : BFMPatterns <i64, UniformBinFrag<shl>, UniformBinFrag<add>, S_BFM_B64>;
defm : BFMPatterns <i32, DivergentBinFrag<shl>, DivergentBinFrag<add>, V_BFM_B32_e64>;
// Bitfield extract patterns
diff --git a/llvm/test/CodeGen/AMDGPU/bfm.ll b/llvm/test/CodeGen/AMDGPU/bfm.ll
index 2b18face3691f..f866a68ccc1d8 100644
--- a/llvm/test/CodeGen/AMDGPU/bfm.ll
+++ b/llvm/test/CodeGen/AMDGPU/bfm.ll
@@ -99,11 +99,8 @@ define amdgpu_kernel void @s_bfm64_pattern(ptr addrspace(1) %out, i64 %x, i64 %y
; SI-NEXT: s_mov_b32 s6, -1
; SI-NEXT: s_mov_b32 s4, s0
; SI-NEXT: s_mov_b32 s5, s1
-; SI-NEXT: s_lshl_b64 s[0:1], 1, s2
-; SI-NEXT: s_add_u32 s0, s0, -1
-; SI-NEXT: s_addc_u32 s1, s1, -1
; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: s_lshl_b64 s[0:1], s[0:1], s3
+; SI-NEXT: s_bfm_b64 s[0:1], s2, s3
; SI-NEXT: v_mov_b32_e32 v0, s0
; SI-NEXT: v_mov_b32_e32 v1, s1
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
@@ -116,11 +113,8 @@ define amdgpu_kernel void @s_bfm64_pattern(ptr addrspace(1) %out, i64 %x, i64 %y
; VI-NEXT: s_load_dword s3, s[4:5], 0x34
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
-; VI-NEXT: s_lshl_b64 s[0:1], 1, s2
-; VI-NEXT: s_add_u32 s0, s0, -1
-; VI-NEXT: s_addc_u32 s1, s1, -1
; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: s_lshl_b64 s[0:1], s[0:1], s3
+; VI-NEXT: s_bfm_b64 s[0:1], s2, s3
; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_mov_b32_e32 v2, s0
; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
@@ -141,9 +135,7 @@ define amdgpu_kernel void @s_bfm64_pattern_simple(ptr addrspace(1) %out, i64 %x)
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_mov_b32 s4, s0
; SI-NEXT: s_mov_b32 s5, s1
-; SI-NEXT: s_lshl_b64 s[0:1], 1, s2
-; SI-NEXT: s_add_u32 s0, s0, -1
-; SI-NEXT: s_addc_u32 s1, s1, -1
+; SI-NEXT: s_bfm_b64 s[0:1], s2, 0
; SI-NEXT: v_mov_b32_e32 v0, s0
; SI-NEXT: v_mov_b32_e32 v1, s1
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
@@ -155,9 +147,7 @@ define amdgpu_kernel void @s_bfm64_pattern_simple(ptr addrspace(1) %out, i64 %x)
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
-; VI-NEXT: s_lshl_b64 s[0:1], 1, s2
-; VI-NEXT: s_add_u32 s0, s0, -1
-; VI-NEXT: s_addc_u32 s1, s1, -1
+; VI-NEXT: s_bfm_b64 s[0:1], s2, 0
; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_mov_b32_e32 v2, s0
; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
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