[llvm] 83fc40a - AArch64: Fix optimizeCondBranch crash on an undef register (#216593)

[via llvm-commits]

Author: Matt Arsenault
Date: 2026-08-17T10:07:32+02:00
New Revision: 83fc40a59dd97fcde13c18aa08b9ef940b97a22e

URL: https://github.com/llvm/llvm-project/commit/83fc40a59dd97fcde13c18aa08b9ef940b97a22e
DIFF: https://github.com/llvm/llvm-project/commit/83fc40a59dd97fcde13c18aa08b9ef940b97a22e.diff

LOG: AArch64: Fix optimizeCondBranch crash on an undef register (#216593)

Found by AI while working on something else.

Co-authored-by: Claude (Opus 4.8) <noreply at anthropic.com>

Added: 
    llvm/test/CodeGen/AArch64/optimize-cond-branch-undef.mir

Modified: 
    llvm/lib/Target/AArch64/AArch64InstrInfo.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
index 2f31686b4f19b..bd4cacc737fd7 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -10090,6 +10090,8 @@ bool AArch64InstrInfo::optimizeCondBranch(MachineInstr &MI) const {
     return false;
 
   MachineInstr *DefMI = MRI->getVRegDef(VReg);
+  if (!DefMI)
+    return false;
 
   // Look through COPY instructions to find definition.
   while (DefMI->isCopy()) {

diff  --git a/llvm/test/CodeGen/AArch64/optimize-cond-branch-undef.mir b/llvm/test/CodeGen/AArch64/optimize-cond-branch-undef.mir
new file mode 100644
index 0000000000000..7a4d9b98ca1a1
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/optimize-cond-branch-undef.mir
@@ -0,0 +1,32 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -mtriple=aarch64-- -run-pass=peephole-opt -o - %s | FileCheck %s
+# A conditional branch on an undef register with no def must not crash the
+# peephole optimizer while it looks through the copy chain for the definition.
+
+---
+name: cbz_undef
+tracksRegLiveness: true
+body: |
+  ; CHECK-LABEL: name: cbz_undef
+  ; CHECK: bb.0:
+  ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   CBZW undef %0:gpr32, %bb.2
+  ; CHECK-NEXT:   B %bb.1
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1:
+  ; CHECK-NEXT:   RET_ReallyLR
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.2:
+  ; CHECK-NEXT:   RET_ReallyLR
+  bb.0:
+    successors: %bb.1, %bb.2
+    CBZW undef %0:gpr32, %bb.2
+    B %bb.1
+
+  bb.1:
+    RET_ReallyLR
+
+  bb.2:
+    RET_ReallyLR
+...