[llvm] [AArch64] Fold vector select with power-of-2 bit-test to CMTST+BSP (PR #209100)
Mugundan S via llvm-commits
llvm-commits at lists.llvm.org
Sun Aug 16 23:42:20 PDT 2026
https://github.com/MGN-GIT updated https://github.com/llvm/llvm-project/pull/209100
>From 0866f720b432bdd8ba1dc45939f45250102d158d Mon Sep 17 00:00:00 2001
From: Greenie0701 <smugundan12a at gmail.com>
Date: Mon, 13 Jul 2026 12:52:50 +0530
Subject: [PATCH 1/6] [AArch64] Fold vector select with power-of-2 bit-test to
CMTST+BSP
---
.../Target/AArch64/AArch64ISelLowering.cpp | 59 +++++++++++++++++++
llvm/lib/Target/AArch64/AArch64InstrInfo.td | 10 +++-
.../CodeGen/AArch64/cmtst-select-pow2-mask.ll | 55 +++++++++++++++++
3 files changed, 121 insertions(+), 3 deletions(-)
create mode 100644 llvm/test/CodeGen/AArch64/cmtst-select-pow2-mask.ll
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 46ffc9287dc62..8e6e2a0746254 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -16757,6 +16757,28 @@ static SDValue tryLowerToBSL(SDValue N, SelectionDAG &DAG) {
N0->getOperand(1 - i), N1->getOperand(1 - j));
}
+ // Fold: or(and(xor(AArch64ISD::CMTST(X,M), allones), A),
+ // and(AArch64ISD::CMTST(X,M), B)) --> BSP(CMTST(X,M), A, B)
+ // This absorbs the NOT produced by performSETCCCombine when it folds
+ // setcc(and(X,Mask), 0, seteq) --> NOT(CMTST(X,Mask)).
+ for (int i = 1; i >= 0; --i)
+ for (int j = 1; j >= 0; --j) {
+ SDValue NotCMTST = N0->getOperand(i);
+ SDValue A = N0->getOperand(1 - i);
+ SDValue CMTST = N1->getOperand(j);
+ SDValue B = N1->getOperand(1 - j);
+
+ if (NotCMTST.getOpcode() != ISD::XOR ||
+ !ISD::isBuildVectorAllOnes(NotCMTST.getOperand(1).getNode()))
+ continue;
+ if (NotCMTST.getOperand(0) != CMTST)
+ continue;
+ if (CMTST.getOpcode() != AArch64ISD::CMTST)
+ continue;
+
+ return DAG.getNode(AArch64ISD::BSP, DL, VT, CMTST, A, B);
+ }
+
return SDValue();
}
@@ -29261,6 +29283,43 @@ static SDValue performSETCCCombine(SDNode *N,
SplatLHSVal.isOne())
return DAG.getSetCC(DL, VT, DAG.getConstant(0, DL, CmpVT), RHS, ISD::SETGE);
+ // Fold setcc(and(X, Mask), Mask/0, eq/ne) --> [not] AArch64ISD::CMTST(X,
+ // Mask) for a power of 2 splat Mask, replacing AND+CMEQ with a single CMTST.
+ // Any NOT folds away when the result feeds a BSL/BIF/BIT select.
+ if (!DCI.isBeforeLegalize() && CmpVT.isFixedLengthVector() &&
+ (Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
+ LHS.getOpcode() == ISD::AND) {
+ APInt SplatVal;
+ SDValue X, MaskOp;
+ if (ISD::isConstantSplatVector(LHS.getOperand(1).getNode(), SplatVal) &&
+ SplatVal.isPowerOf2()) {
+ X = LHS.getOperand(0);
+ MaskOp = LHS.getOperand(1);
+ } else if (ISD::isConstantSplatVector(LHS.getOperand(0).getNode(),
+ SplatVal) &&
+ SplatVal.isPowerOf2()) {
+ X = LHS.getOperand(1);
+ MaskOp = LHS.getOperand(0);
+ }
+ if (X.getNode()) {
+ bool RHSIsZero = ISD::isBuildVectorAllZeros(RHS.getNode());
+ APInt RHSSplat;
+ bool RHSIsMask = !RHSIsZero &&
+ ISD::isConstantSplatVector(RHS.getNode(), RHSSplat) &&
+ RHSSplat == SplatVal;
+ if (RHSIsZero || RHSIsMask) {
+ SDValue CMTSTNode =
+ DAG.getNode(AArch64ISD::CMTST, DL, CmpVT, X, MaskOp);
+ // CMTST gives all-ones where (X & Mask) != 0, i.e. SETNE(AND, 0).
+ // Invert when the original condition is the opposite sense.
+ bool Invert = (Cond == ISD::SETEQ) ? RHSIsZero : RHSIsMask;
+ if (Invert)
+ return DAG.getNOT(DL, CMTSTNode, CmpVT);
+ return CMTSTNode;
+ }
+ }
+ }
+
return SDValue();
}
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index e59428f0ea33c..789a8aecbd886 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -953,6 +953,9 @@ def AArch64vsri : SDNode<"AArch64ISD::VSRI", SDT_AArch64vshiftinsert>;
// element must be identical.
def AArch64bsp: SDNode<"AArch64ISD::BSP", SDT_AArch64trivec>;
+// AArch64ISD::CMTST node: result is all-ones per lane where (X & Y) != 0.
+def AArch64cmtst: SDNode<"AArch64ISD::CMTST", SDT_AArch64Zip>;
+
def AArch64cmeq : PatFrag<(ops node:$lhs, node:$rhs),
(setcc node:$lhs, node:$rhs, SETEQ)>;
def AArch64cmge : PatFrag<(ops node:$lhs, node:$rhs),
@@ -981,7 +984,7 @@ def AArch64cmlez : PatFrag<(ops node:$lhs),
def AArch64cmltz : PatFrag<(ops node:$lhs),
(setcc immAllZerosV, node:$lhs, SETGT)>;
-def AArch64cmtst : PatFrag<(ops node:$LHS, node:$RHS),
+def AArch64cmtst_frag : PatFrag<(ops node:$LHS, node:$RHS),
(vnot (AArch64cmeqz (and node:$LHS, node:$RHS)))>;
def AArch64fcmeqz : PatFrag<(ops node:$lhs),
@@ -6161,9 +6164,10 @@ defm CMGE : SIMDThreeSameVector<0, 0b00111, "cmge", AArch64cmge>;
defm CMGT : SIMDThreeSameVector<0, 0b00110, "cmgt", AArch64cmgt>;
defm CMHI : SIMDThreeSameVector<1, 0b00110, "cmhi", AArch64cmhi>;
defm CMHS : SIMDThreeSameVector<1, 0b00111, "cmhs", AArch64cmhs>;
-defm CMTST : SIMDThreeSameVector<0, 0b10001, "cmtst", AArch64cmtst>;
+defm CMTST : SIMDThreeSameVector<0, 0b10001, "cmtst", AArch64cmtst_frag>;
foreach VT = [ v8i8, v16i8, v4i16, v8i16, v2i32, v4i32, v2i64 ] in {
def : Pat<(VT (vnot (AArch64cmeqz VT:$Rn))), (!cast<Instruction>("CMTST"#VT) VT:$Rn, VT:$Rn)>;
+def : Pat<(VT (AArch64cmtst VT:$Rn, VT:$Rm)), (!cast<Instruction>("CMTST"#VT) VT:$Rn, VT:$Rm)>;
}
defm FABD : SIMDThreeSameVectorFP<1,1,0b010,"fabd", int_aarch64_neon_fabd>;
let Predicates = [HasNEON] in {
@@ -6605,7 +6609,7 @@ defm CMGE : SIMDThreeScalarD<0, 0b00111, "cmge", AArch64cmge>;
defm CMGT : SIMDThreeScalarD<0, 0b00110, "cmgt", AArch64cmgt>;
defm CMHI : SIMDThreeScalarD<1, 0b00110, "cmhi", AArch64cmhi>;
defm CMHS : SIMDThreeScalarD<1, 0b00111, "cmhs", AArch64cmhs>;
-defm CMTST : SIMDThreeScalarD<0, 0b10001, "cmtst", AArch64cmtst>;
+defm CMTST : SIMDThreeScalarD<0, 0b10001, "cmtst", AArch64cmtst_frag>;
defm FABD : SIMDFPThreeScalar<1, 1, 0b010, "fabd", int_aarch64_sisd_fabd>;
def : Pat<(v1f64 (int_aarch64_neon_fabd (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
(FABD64 FPR64:$Rn, FPR64:$Rm)>;
diff --git a/llvm/test/CodeGen/AArch64/cmtst-select-pow2-mask.ll b/llvm/test/CodeGen/AArch64/cmtst-select-pow2-mask.ll
new file mode 100644
index 0000000000000..60c837be638be
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/cmtst-select-pow2-mask.ll
@@ -0,0 +1,55 @@
+; Test: (X & Mask) == Mask, for a power-of-2 Mask, folds to CMTST
+; instead of AND+CMEQ when used as a select condition inside a BSL/BSP fold.
+; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+
+define <16 x i8> @cmtst_select_v16i8_pow2(<16 x i8> %x, <16 x i8> %y) {
+; CHECK-LABEL: cmtst_select_v16i8_pow2:
+; CHECK: movi v2.16b, #2
+; CHECK-NEXT: cmtst v2.16b, v0.16b, v2.16b
+; CHECK-NEXT: bif v0.16b, v1.16b, v2.16b
+; CHECK-NEXT: ret
+ %mask = and <16 x i8> %x, splat(i8 2)
+ %cmp = icmp eq <16 x i8> %mask, splat(i8 2)
+ %sel = select <16 x i1> %cmp, <16 x i8> %x, <16 x i8> %y
+ ret <16 x i8> %sel
+}
+
+define <8 x i16> @cmtst_select_v8i16_pow2(<8 x i16> %x, <8 x i16> %y) {
+; CHECK-LABEL: cmtst_select_v8i16_pow2:
+; CHECK: movi v2.8h, #4
+; CHECK-NEXT: cmtst v2.8h, v0.8h, v2.8h
+; CHECK-NEXT: bif v0.16b, v1.16b, v2.16b
+; CHECK-NEXT: ret
+ %mask = and <8 x i16> %x, splat(i16 4)
+ %cmp = icmp eq <8 x i16> %mask, splat(i16 4)
+ %sel = select <8 x i1> %cmp, <8 x i16> %x, <8 x i16> %y
+ ret <8 x i16> %sel
+}
+
+define <4 x i32> @cmtst_select_v4i32_pow2(<4 x i32> %x, <4 x i32> %y) {
+; CHECK-LABEL: cmtst_select_v4i32_pow2:
+; CHECK: movi v2.4s, #8
+; CHECK-NEXT: cmtst v2.4s, v0.4s, v2.4s
+; CHECK-NEXT: bif v0.16b, v1.16b, v2.16b
+; CHECK-NEXT: ret
+ %mask = and <4 x i32> %x, splat(i32 8)
+ %cmp = icmp eq <4 x i32> %mask, splat(i32 8)
+ %sel = select <4 x i1> %cmp, <4 x i32> %x, <4 x i32> %y
+ ret <4 x i32> %sel
+}
+
+; Negative test - non-power-of-2 mask must NOT use CMTST; must fall back to
+; AND+CMEQ.
+define <16 x i8> @no_cmtst_non_pow2(<16 x i8> %x, <16 x i8> %y) {
+; CHECK-LABEL: no_cmtst_non_pow2:
+; CHECK: movi v2.16b, #3
+; CHECK-NEXT: and v3.16b, v0.16b, v2.16b
+; CHECK-NEXT: cmeq v2.16b, v3.16b, v2.16b
+; CHECK-NEXT: bif v0.16b, v1.16b, v2.16b
+; CHECK-NEXT: ret
+ %mask = and <16 x i8> %x, splat(i8 3)
+ %cmp = icmp eq <16 x i8> %mask, splat(i8 3)
+ %sel = select <16 x i1> %cmp, <16 x i8> %x, <16 x i8> %y
+ ret <16 x i8> %sel
+}
>From 0c38c847be88430ba92d434fb64ac53d24f98ba2 Mon Sep 17 00:00:00 2001
From: Mugundan S <137760120+MGN-GIT at users.noreply.github.com>
Date: Mon, 3 Aug 2026 09:19:10 +0530
Subject: [PATCH 2/6] [AArch64] Fold vector select with power-of-2 bit-test to
CMTST+BSP
---
.../Target/AArch64/AArch64ISelLowering.cpp | 44 ++++---------------
1 file changed, 9 insertions(+), 35 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 8e6e2a0746254..b873b33ab3328 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -29283,41 +29283,15 @@ static SDValue performSETCCCombine(SDNode *N,
SplatLHSVal.isOne())
return DAG.getSetCC(DL, VT, DAG.getConstant(0, DL, CmpVT), RHS, ISD::SETGE);
- // Fold setcc(and(X, Mask), Mask/0, eq/ne) --> [not] AArch64ISD::CMTST(X,
- // Mask) for a power of 2 splat Mask, replacing AND+CMEQ with a single CMTST.
- // Any NOT folds away when the result feeds a BSL/BIF/BIT select.
- if (!DCI.isBeforeLegalize() && CmpVT.isFixedLengthVector() &&
- (Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
- LHS.getOpcode() == ISD::AND) {
- APInt SplatVal;
- SDValue X, MaskOp;
- if (ISD::isConstantSplatVector(LHS.getOperand(1).getNode(), SplatVal) &&
- SplatVal.isPowerOf2()) {
- X = LHS.getOperand(0);
- MaskOp = LHS.getOperand(1);
- } else if (ISD::isConstantSplatVector(LHS.getOperand(0).getNode(),
- SplatVal) &&
- SplatVal.isPowerOf2()) {
- X = LHS.getOperand(1);
- MaskOp = LHS.getOperand(0);
- }
- if (X.getNode()) {
- bool RHSIsZero = ISD::isBuildVectorAllZeros(RHS.getNode());
- APInt RHSSplat;
- bool RHSIsMask = !RHSIsZero &&
- ISD::isConstantSplatVector(RHS.getNode(), RHSSplat) &&
- RHSSplat == SplatVal;
- if (RHSIsZero || RHSIsMask) {
- SDValue CMTSTNode =
- DAG.getNode(AArch64ISD::CMTST, DL, CmpVT, X, MaskOp);
- // CMTST gives all-ones where (X & Mask) != 0, i.e. SETNE(AND, 0).
- // Invert when the original condition is the opposite sense.
- bool Invert = (Cond == ISD::SETEQ) ? RHSIsZero : RHSIsMask;
- if (Invert)
- return DAG.getNOT(DL, CMTSTNode, CmpVT);
- return CMTSTNode;
- }
- }
+ // Fold setcc(and(X, Y), 0, seteq) --> NOT(AArch64ISD::CMTST(X, Y))
+ // after DAG legalization. SETNE will have been legalized to SETEQ by now.
+ // The NOT folds away when the result feeds a BSP.
+ if (DCI.isAfterLegalizeDAG() && CmpVT.isFixedLengthVector() &&
+ Cond == ISD::SETEQ && LHS.getOpcode() == ISD::AND &&
+ ISD::isConstantSplatVectorAllZeros(RHS.getNode())) {
+ SDValue CMTSTNode = DAG.getNode(AArch64ISD::CMTST, DL, CmpVT,
+ LHS.getOperand(0), LHS.getOperand(1));
+ return DAG.getNOT(DL, CMTSTNode, CmpVT);
}
return SDValue();
>From fb7cad6ea9630736f6b66906b53d3223010be598 Mon Sep 17 00:00:00 2001
From: Mugundan <smugundan12a at gmail.com>
Date: Sat, 15 Aug 2026 12:42:21 +0530
Subject: [PATCH 3/6] [AArch64] Fold vector select with power-of-2 bit-test to
CMTST+BSP
---
.../Target/AArch64/AArch64ISelLowering.cpp | 28 ++-----------------
llvm/lib/Target/AArch64/AArch64InstrInfo.td | 7 ++---
2 files changed, 6 insertions(+), 29 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index b873b33ab3328..f4d3fd35174b7 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -16757,28 +16757,6 @@ static SDValue tryLowerToBSL(SDValue N, SelectionDAG &DAG) {
N0->getOperand(1 - i), N1->getOperand(1 - j));
}
- // Fold: or(and(xor(AArch64ISD::CMTST(X,M), allones), A),
- // and(AArch64ISD::CMTST(X,M), B)) --> BSP(CMTST(X,M), A, B)
- // This absorbs the NOT produced by performSETCCCombine when it folds
- // setcc(and(X,Mask), 0, seteq) --> NOT(CMTST(X,Mask)).
- for (int i = 1; i >= 0; --i)
- for (int j = 1; j >= 0; --j) {
- SDValue NotCMTST = N0->getOperand(i);
- SDValue A = N0->getOperand(1 - i);
- SDValue CMTST = N1->getOperand(j);
- SDValue B = N1->getOperand(1 - j);
-
- if (NotCMTST.getOpcode() != ISD::XOR ||
- !ISD::isBuildVectorAllOnes(NotCMTST.getOperand(1).getNode()))
- continue;
- if (NotCMTST.getOperand(0) != CMTST)
- continue;
- if (CMTST.getOpcode() != AArch64ISD::CMTST)
- continue;
-
- return DAG.getNode(AArch64ISD::BSP, DL, VT, CMTST, A, B);
- }
-
return SDValue();
}
@@ -29283,12 +29261,12 @@ static SDValue performSETCCCombine(SDNode *N,
SplatLHSVal.isOne())
return DAG.getSetCC(DL, VT, DAG.getConstant(0, DL, CmpVT), RHS, ISD::SETGE);
- // Fold setcc(and(X, Y), 0, seteq) --> NOT(AArch64ISD::CMTST(X, Y))
- // after DAG legalization. SETNE will have been legalized to SETEQ by now.
+ // Fold setcc(and(X, Y), 0, seteq) --> NOT(AArch64ISD::CMTST(X, Y)).
+ // SETNE will have been legalized to SETEQ by this point.
// The NOT folds away when the result feeds a BSP.
if (DCI.isAfterLegalizeDAG() && CmpVT.isFixedLengthVector() &&
Cond == ISD::SETEQ && LHS.getOpcode() == ISD::AND &&
- ISD::isConstantSplatVectorAllZeros(RHS.getNode())) {
+ isZerosVector(RHS.getNode())) {
SDValue CMTSTNode = DAG.getNode(AArch64ISD::CMTST, DL, CmpVT,
LHS.getOperand(0), LHS.getOperand(1));
return DAG.getNOT(DL, CMTSTNode, CmpVT);
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index 789a8aecbd886..154920523b16c 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -984,7 +984,7 @@ def AArch64cmlez : PatFrag<(ops node:$lhs),
def AArch64cmltz : PatFrag<(ops node:$lhs),
(setcc immAllZerosV, node:$lhs, SETGT)>;
-def AArch64cmtst_frag : PatFrag<(ops node:$LHS, node:$RHS),
+def AArch64cmtst : PatFrag<(ops node:$LHS, node:$RHS),
(vnot (AArch64cmeqz (and node:$LHS, node:$RHS)))>;
def AArch64fcmeqz : PatFrag<(ops node:$lhs),
@@ -6164,10 +6164,9 @@ defm CMGE : SIMDThreeSameVector<0, 0b00111, "cmge", AArch64cmge>;
defm CMGT : SIMDThreeSameVector<0, 0b00110, "cmgt", AArch64cmgt>;
defm CMHI : SIMDThreeSameVector<1, 0b00110, "cmhi", AArch64cmhi>;
defm CMHS : SIMDThreeSameVector<1, 0b00111, "cmhs", AArch64cmhs>;
-defm CMTST : SIMDThreeSameVector<0, 0b10001, "cmtst", AArch64cmtst_frag>;
+defm CMTST : SIMDThreeSameVector<0, 0b10001, "cmtst", AArch64cmtst>;
foreach VT = [ v8i8, v16i8, v4i16, v8i16, v2i32, v4i32, v2i64 ] in {
def : Pat<(VT (vnot (AArch64cmeqz VT:$Rn))), (!cast<Instruction>("CMTST"#VT) VT:$Rn, VT:$Rn)>;
-def : Pat<(VT (AArch64cmtst VT:$Rn, VT:$Rm)), (!cast<Instruction>("CMTST"#VT) VT:$Rn, VT:$Rm)>;
}
defm FABD : SIMDThreeSameVectorFP<1,1,0b010,"fabd", int_aarch64_neon_fabd>;
let Predicates = [HasNEON] in {
@@ -6609,7 +6608,7 @@ defm CMGE : SIMDThreeScalarD<0, 0b00111, "cmge", AArch64cmge>;
defm CMGT : SIMDThreeScalarD<0, 0b00110, "cmgt", AArch64cmgt>;
defm CMHI : SIMDThreeScalarD<1, 0b00110, "cmhi", AArch64cmhi>;
defm CMHS : SIMDThreeScalarD<1, 0b00111, "cmhs", AArch64cmhs>;
-defm CMTST : SIMDThreeScalarD<0, 0b10001, "cmtst", AArch64cmtst_frag>;
+defm CMTST : SIMDThreeScalarD<0, 0b10001, "cmtst", AArch64cmtst>;
defm FABD : SIMDFPThreeScalar<1, 1, 0b010, "fabd", int_aarch64_sisd_fabd>;
def : Pat<(v1f64 (int_aarch64_neon_fabd (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
(FABD64 FPR64:$Rn, FPR64:$Rm)>;
>From 91f709aca546d6f976a69783dbe6eac5bda5bb39 Mon Sep 17 00:00:00 2001
From: Mugundan S <137760120+MGN-GIT at users.noreply.github.com>
Date: Sun, 16 Aug 2026 11:01:52 +0530
Subject: [PATCH 4/6] [AArch64] Fold vector select with power-of-2 bit-test to
CMTST+BSP
---
llvm/lib/Target/AArch64/AArch64InstrInfo.td | 3 ---
1 file changed, 3 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index 154920523b16c..da6b90e9636f8 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -984,9 +984,6 @@ def AArch64cmlez : PatFrag<(ops node:$lhs),
def AArch64cmltz : PatFrag<(ops node:$lhs),
(setcc immAllZerosV, node:$lhs, SETGT)>;
-def AArch64cmtst : PatFrag<(ops node:$LHS, node:$RHS),
- (vnot (AArch64cmeqz (and node:$LHS, node:$RHS)))>;
-
def AArch64fcmeqz : PatFrag<(ops node:$lhs),
(AArch64fcmeq node:$lhs, immAllZerosV)>;
>From fad760f673fc589f94686d08de9c2d0d626d520e Mon Sep 17 00:00:00 2001
From: Mugundan <smugundan12a at gmail.com>
Date: Mon, 17 Aug 2026 10:41:38 +0530
Subject: [PATCH 5/6] Fix test failures on AArch64
---
llvm/test/CodeGen/AArch64/combine-mul.ll | 5 +-
...st-and-by-const-from-lshr-in-eqcmp-zero.ll | 47 +-
...ist-and-by-const-from-shl-in-eqcmp-zero.ll | 86 +-
.../AArch64/neon-bitwise-instructions.ll | 32 +-
llvm/test/CodeGen/AArch64/select-bitcast.ll | 887 ++++++++----------
.../CodeGen/AArch64/urem-seteq-vec-splat.ll | 5 +-
.../AArch64/vec-combine-compare-to-bitmask.ll | 11 +-
.../AArch64/vector-popcnt-128-ult-ugt.ll | 254 ++---
8 files changed, 662 insertions(+), 665 deletions(-)
diff --git a/llvm/test/CodeGen/AArch64/combine-mul.ll b/llvm/test/CodeGen/AArch64/combine-mul.ll
index ff6d1a571a084..c49e5ae6620a9 100644
--- a/llvm/test/CodeGen/AArch64/combine-mul.ll
+++ b/llvm/test/CodeGen/AArch64/combine-mul.ll
@@ -28,7 +28,10 @@ define <4 x i1> @PR48683_vec(<4 x i32> %x) {
define <4 x i1> @PR48683_vec_undef(<4 x i32> %x) {
; CHECK-LABEL: PR48683_vec_undef:
; CHECK: // %bb.0:
-; CHECK-NEXT: movi v0.2d, #0000000000000000
+; CHECK-NEXT: movi v1.4s, #2
+; CHECK-NEXT: mul v0.4s, v0.4s, v0.4s
+; CHECK-NEXT: cmtst v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: xtn v0.4h, v0.4s
; CHECK-NEXT: ret
%a = mul <4 x i32> %x, %x
%b = and <4 x i32> %a, <i32 2, i32 2, i32 2, i32 undef>
diff --git a/llvm/test/CodeGen/AArch64/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll b/llvm/test/CodeGen/AArch64/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
index e662a2a59ed75..7d8ff9ac11e30 100644
--- a/llvm/test/CodeGen/AArch64/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
+++ b/llvm/test/CodeGen/AArch64/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
@@ -286,8 +286,8 @@ define <4 x i1> @vec_4xi32_splat_eq(<4 x i32> %x, <4 x i32> %y) nounwind {
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: movi v2.4s, #1
; CHECK-SD-NEXT: ushl v0.4s, v0.4s, v1.4s
-; CHECK-SD-NEXT: and v0.16b, v0.16b, v2.16b
-; CHECK-SD-NEXT: cmeq v0.4s, v0.4s, #0
+; CHECK-SD-NEXT: cmtst v0.4s, v0.4s, v2.4s
+; CHECK-SD-NEXT: mvn v0.16b, v0.16b
; CHECK-SD-NEXT: xtn v0.4h, v0.4s
; CHECK-SD-NEXT: ret
;
@@ -307,16 +307,27 @@ define <4 x i1> @vec_4xi32_splat_eq(<4 x i32> %x, <4 x i32> %y) nounwind {
}
define <4 x i1> @vec_4xi32_nonsplat_eq(<4 x i32> %x, <4 x i32> %y) nounwind {
-; CHECK-LABEL: vec_4xi32_nonsplat_eq:
-; CHECK: // %bb.0:
-; CHECK-NEXT: adrp x8, .LCPI13_0
-; CHECK-NEXT: neg v1.4s, v1.4s
-; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI13_0]
-; CHECK-NEXT: ushl v1.4s, v2.4s, v1.4s
-; CHECK-NEXT: and v0.16b, v1.16b, v0.16b
-; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
-; CHECK-NEXT: xtn v0.4h, v0.4s
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: vec_4xi32_nonsplat_eq:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: adrp x8, .LCPI13_0
+; CHECK-SD-NEXT: neg v1.4s, v1.4s
+; CHECK-SD-NEXT: ldr q2, [x8, :lo12:.LCPI13_0]
+; CHECK-SD-NEXT: ushl v1.4s, v2.4s, v1.4s
+; CHECK-SD-NEXT: cmtst v0.4s, v1.4s, v0.4s
+; CHECK-SD-NEXT: mvn v0.16b, v0.16b
+; CHECK-SD-NEXT: xtn v0.4h, v0.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: vec_4xi32_nonsplat_eq:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: adrp x8, .LCPI13_0
+; CHECK-GI-NEXT: neg v1.4s, v1.4s
+; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI13_0]
+; CHECK-GI-NEXT: ushl v1.4s, v2.4s, v1.4s
+; CHECK-GI-NEXT: and v0.16b, v1.16b, v0.16b
+; CHECK-GI-NEXT: cmeq v0.4s, v0.4s, #0
+; CHECK-GI-NEXT: xtn v0.4h, v0.4s
+; CHECK-GI-NEXT: ret
%t0 = lshr <4 x i32> <i32 0, i32 1, i32 16776960, i32 2147483648>, %y
%t1 = and <4 x i32> %t0, %x
%res = icmp eq <4 x i32> %t1, <i32 0, i32 0, i32 0, i32 0>
@@ -328,8 +339,8 @@ define <4 x i1> @vec_4xi32_nonsplat_undef0_eq(<4 x i32> %x, <4 x i32> %y) nounwi
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: movi v2.4s, #1
; CHECK-SD-NEXT: ushl v0.4s, v0.4s, v1.4s
-; CHECK-SD-NEXT: and v0.16b, v0.16b, v2.16b
-; CHECK-SD-NEXT: cmeq v0.4s, v0.4s, #0
+; CHECK-SD-NEXT: cmtst v0.4s, v0.4s, v2.4s
+; CHECK-SD-NEXT: mvn v0.16b, v0.16b
; CHECK-SD-NEXT: xtn v0.4h, v0.4s
; CHECK-SD-NEXT: ret
;
@@ -353,8 +364,8 @@ define <4 x i1> @vec_4xi32_nonsplat_undef1_eq(<4 x i32> %x, <4 x i32> %y) nounwi
; CHECK-SD-NEXT: movi v2.4s, #1
; CHECK-SD-NEXT: neg v1.4s, v1.4s
; CHECK-SD-NEXT: ushl v1.4s, v2.4s, v1.4s
-; CHECK-SD-NEXT: and v0.16b, v1.16b, v0.16b
-; CHECK-SD-NEXT: cmeq v0.4s, v0.4s, #0
+; CHECK-SD-NEXT: cmtst v0.4s, v1.4s, v0.4s
+; CHECK-SD-NEXT: mvn v0.16b, v0.16b
; CHECK-SD-NEXT: xtn v0.4h, v0.4s
; CHECK-SD-NEXT: ret
;
@@ -379,8 +390,8 @@ define <4 x i1> @vec_4xi32_nonsplat_undef2_eq(<4 x i32> %x, <4 x i32> %y) nounwi
; CHECK-SD-NEXT: movi v2.4s, #1
; CHECK-SD-NEXT: neg v1.4s, v1.4s
; CHECK-SD-NEXT: ushl v1.4s, v2.4s, v1.4s
-; CHECK-SD-NEXT: and v0.16b, v1.16b, v0.16b
-; CHECK-SD-NEXT: cmeq v0.4s, v0.4s, #0
+; CHECK-SD-NEXT: cmtst v0.4s, v1.4s, v0.4s
+; CHECK-SD-NEXT: mvn v0.16b, v0.16b
; CHECK-SD-NEXT: xtn v0.4h, v0.4s
; CHECK-SD-NEXT: ret
;
diff --git a/llvm/test/CodeGen/AArch64/hoist-and-by-const-from-shl-in-eqcmp-zero.ll b/llvm/test/CodeGen/AArch64/hoist-and-by-const-from-shl-in-eqcmp-zero.ll
index e1d5da3d37922..f61e4303ca2be 100644
--- a/llvm/test/CodeGen/AArch64/hoist-and-by-const-from-shl-in-eqcmp-zero.ll
+++ b/llvm/test/CodeGen/AArch64/hoist-and-by-const-from-shl-in-eqcmp-zero.ll
@@ -294,14 +294,23 @@ define i1 @scalar_i64_bitsinmiddle_eq(i64 %x, i64 %y) nounwind {
;------------------------------------------------------------------------------;
define <4 x i1> @vec_4xi32_splat_eq(<4 x i32> %x, <4 x i32> %y) nounwind {
-; CHECK-LABEL: vec_4xi32_splat_eq:
-; CHECK: // %bb.0:
-; CHECK-NEXT: movi v2.4s, #1
-; CHECK-NEXT: ushl v1.4s, v2.4s, v1.4s
-; CHECK-NEXT: and v0.16b, v1.16b, v0.16b
-; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
-; CHECK-NEXT: xtn v0.4h, v0.4s
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: vec_4xi32_splat_eq:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: movi v2.4s, #1
+; CHECK-SD-NEXT: ushl v1.4s, v2.4s, v1.4s
+; CHECK-SD-NEXT: cmtst v0.4s, v1.4s, v0.4s
+; CHECK-SD-NEXT: mvn v0.16b, v0.16b
+; CHECK-SD-NEXT: xtn v0.4h, v0.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: vec_4xi32_splat_eq:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v2.4s, #1
+; CHECK-GI-NEXT: ushl v1.4s, v2.4s, v1.4s
+; CHECK-GI-NEXT: and v0.16b, v1.16b, v0.16b
+; CHECK-GI-NEXT: cmeq v0.4s, v0.4s, #0
+; CHECK-GI-NEXT: xtn v0.4h, v0.4s
+; CHECK-GI-NEXT: ret
%t0 = shl <4 x i32> <i32 1, i32 1, i32 1, i32 1>, %y
%t1 = and <4 x i32> %t0, %x
%res = icmp eq <4 x i32> %t1, <i32 0, i32 0, i32 0, i32 0>
@@ -309,15 +318,25 @@ define <4 x i1> @vec_4xi32_splat_eq(<4 x i32> %x, <4 x i32> %y) nounwind {
}
define <4 x i1> @vec_4xi32_nonsplat_eq(<4 x i32> %x, <4 x i32> %y) nounwind {
-; CHECK-LABEL: vec_4xi32_nonsplat_eq:
-; CHECK: // %bb.0:
-; CHECK-NEXT: adrp x8, .LCPI13_0
-; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI13_0]
-; CHECK-NEXT: ushl v1.4s, v2.4s, v1.4s
-; CHECK-NEXT: and v0.16b, v1.16b, v0.16b
-; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
-; CHECK-NEXT: xtn v0.4h, v0.4s
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: vec_4xi32_nonsplat_eq:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: adrp x8, .LCPI13_0
+; CHECK-SD-NEXT: ldr q2, [x8, :lo12:.LCPI13_0]
+; CHECK-SD-NEXT: ushl v1.4s, v2.4s, v1.4s
+; CHECK-SD-NEXT: cmtst v0.4s, v1.4s, v0.4s
+; CHECK-SD-NEXT: mvn v0.16b, v0.16b
+; CHECK-SD-NEXT: xtn v0.4h, v0.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: vec_4xi32_nonsplat_eq:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: adrp x8, .LCPI13_0
+; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI13_0]
+; CHECK-GI-NEXT: ushl v1.4s, v2.4s, v1.4s
+; CHECK-GI-NEXT: and v0.16b, v1.16b, v0.16b
+; CHECK-GI-NEXT: cmeq v0.4s, v0.4s, #0
+; CHECK-GI-NEXT: xtn v0.4h, v0.4s
+; CHECK-GI-NEXT: ret
%t0 = shl <4 x i32> <i32 0, i32 1, i32 16776960, i32 2147483648>, %y
%t1 = and <4 x i32> %t0, %x
%res = icmp eq <4 x i32> %t1, <i32 0, i32 0, i32 0, i32 0>
@@ -325,14 +344,23 @@ define <4 x i1> @vec_4xi32_nonsplat_eq(<4 x i32> %x, <4 x i32> %y) nounwind {
}
define <4 x i1> @vec_4xi32_nonsplat_undef0_eq(<4 x i32> %x, <4 x i32> %y) nounwind {
-; CHECK-LABEL: vec_4xi32_nonsplat_undef0_eq:
-; CHECK: // %bb.0:
-; CHECK-NEXT: movi v2.4s, #1
-; CHECK-NEXT: ushl v1.4s, v2.4s, v1.4s
-; CHECK-NEXT: and v0.16b, v1.16b, v0.16b
-; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
-; CHECK-NEXT: xtn v0.4h, v0.4s
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: vec_4xi32_nonsplat_undef0_eq:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: movi v2.4s, #1
+; CHECK-SD-NEXT: ushl v1.4s, v2.4s, v1.4s
+; CHECK-SD-NEXT: cmtst v0.4s, v1.4s, v0.4s
+; CHECK-SD-NEXT: mvn v0.16b, v0.16b
+; CHECK-SD-NEXT: xtn v0.4h, v0.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: vec_4xi32_nonsplat_undef0_eq:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v2.4s, #1
+; CHECK-GI-NEXT: ushl v1.4s, v2.4s, v1.4s
+; CHECK-GI-NEXT: and v0.16b, v1.16b, v0.16b
+; CHECK-GI-NEXT: cmeq v0.4s, v0.4s, #0
+; CHECK-GI-NEXT: xtn v0.4h, v0.4s
+; CHECK-GI-NEXT: ret
%t0 = shl <4 x i32> <i32 1, i32 1, i32 undef, i32 1>, %y
%t1 = and <4 x i32> %t0, %x
%res = icmp eq <4 x i32> %t1, <i32 0, i32 0, i32 0, i32 0>
@@ -343,8 +371,8 @@ define <4 x i1> @vec_4xi32_nonsplat_undef1_eq(<4 x i32> %x, <4 x i32> %y) nounwi
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: movi v2.4s, #1
; CHECK-SD-NEXT: ushl v1.4s, v2.4s, v1.4s
-; CHECK-SD-NEXT: and v0.16b, v1.16b, v0.16b
-; CHECK-SD-NEXT: cmeq v0.4s, v0.4s, #0
+; CHECK-SD-NEXT: cmtst v0.4s, v1.4s, v0.4s
+; CHECK-SD-NEXT: mvn v0.16b, v0.16b
; CHECK-SD-NEXT: xtn v0.4h, v0.4s
; CHECK-SD-NEXT: ret
;
@@ -367,8 +395,8 @@ define <4 x i1> @vec_4xi32_nonsplat_undef2_eq(<4 x i32> %x, <4 x i32> %y) nounwi
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: movi v2.4s, #1
; CHECK-SD-NEXT: ushl v1.4s, v2.4s, v1.4s
-; CHECK-SD-NEXT: and v0.16b, v1.16b, v0.16b
-; CHECK-SD-NEXT: cmeq v0.4s, v0.4s, #0
+; CHECK-SD-NEXT: cmtst v0.4s, v1.4s, v0.4s
+; CHECK-SD-NEXT: mvn v0.16b, v0.16b
; CHECK-SD-NEXT: xtn v0.4h, v0.4s
; CHECK-SD-NEXT: ret
;
diff --git a/llvm/test/CodeGen/AArch64/neon-bitwise-instructions.ll b/llvm/test/CodeGen/AArch64/neon-bitwise-instructions.ll
index 1f761139a7fe2..1e34880be237f 100644
--- a/llvm/test/CodeGen/AArch64/neon-bitwise-instructions.ll
+++ b/llvm/test/CodeGen/AArch64/neon-bitwise-instructions.ll
@@ -1507,12 +1507,18 @@ define <8 x i8> @vselect_cmpz_eq(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) {
}
define <8 x i8> @vselect_tst(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) {
-; CHECK-LABEL: vselect_tst:
-; CHECK: // %bb.0:
-; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
-; CHECK-NEXT: cmeq v0.8b, v0.8b, #0
-; CHECK-NEXT: bsl v0.8b, v2.8b, v1.8b
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: vselect_tst:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmtst v0.8b, v0.8b, v1.8b
+; CHECK-SD-NEXT: bsl v0.8b, v1.8b, v2.8b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: vselect_tst:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
+; CHECK-GI-NEXT: cmeq v0.8b, v0.8b, #0
+; CHECK-GI-NEXT: bsl v0.8b, v2.8b, v1.8b
+; CHECK-GI-NEXT: ret
%tmp3 = and <8 x i8> %a, %b
%tmp4 = icmp eq <8 x i8> %tmp3, zeroinitializer
%d = select <8 x i1> %tmp4, <8 x i8> %c, <8 x i8> %b
@@ -1520,10 +1526,16 @@ define <8 x i8> @vselect_tst(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) {
}
define <8 x i8> @sext_tst(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) {
-; CHECK-LABEL: sext_tst:
-; CHECK: // %bb.0:
-; CHECK-NEXT: cmtst v0.8b, v0.8b, v1.8b
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: sext_tst:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: cmtst v0.8b, v0.8b, v1.8b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: sext_tst:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
+; CHECK-GI-NEXT: cmtst v0.8b, v0.8b, v0.8b
+; CHECK-GI-NEXT: ret
%tmp3 = and <8 x i8> %a, %b
%tmp4 = icmp ne <8 x i8> %tmp3, zeroinitializer
%d = sext <8 x i1> %tmp4 to <8 x i8>
diff --git a/llvm/test/CodeGen/AArch64/select-bitcast.ll b/llvm/test/CodeGen/AArch64/select-bitcast.ll
index 8a79182182ab4..458fd5ccf2c8b 100644
--- a/llvm/test/CodeGen/AArch64/select-bitcast.ll
+++ b/llvm/test/CodeGen/AArch64/select-bitcast.ll
@@ -11,13 +11,11 @@ define void @if_then_else8(ptr %out, i8 %mask, ptr %if_true, ptr %if_false) {
; CHECK-LE-NEXT: adrp x8, .LCPI0_0
; CHECK-LE-NEXT: ldr q2, [x8, :lo12:.LCPI0_0]
; CHECK-LE-NEXT: ldp q4, q3, [x2]
-; CHECK-LE-NEXT: and v1.16b, v0.16b, v1.16b
-; CHECK-LE-NEXT: and v0.16b, v0.16b, v2.16b
+; CHECK-LE-NEXT: cmtst v1.4s, v0.4s, v1.4s
+; CHECK-LE-NEXT: cmtst v0.4s, v0.4s, v2.4s
; CHECK-LE-NEXT: ldp q5, q2, [x3]
-; CHECK-LE-NEXT: cmeq v1.4s, v1.4s, #0
-; CHECK-LE-NEXT: cmeq v0.4s, v0.4s, #0
-; CHECK-LE-NEXT: bsl v1.16b, v2.16b, v3.16b
-; CHECK-LE-NEXT: bsl v0.16b, v5.16b, v4.16b
+; CHECK-LE-NEXT: bsl v1.16b, v3.16b, v2.16b
+; CHECK-LE-NEXT: bsl v0.16b, v4.16b, v5.16b
; CHECK-LE-NEXT: stp q0, q1, [x0]
; CHECK-LE-NEXT: ret
;
@@ -32,17 +30,15 @@ define void @if_then_else8(ptr %out, i8 %mask, ptr %if_true, ptr %if_false) {
; CHECK-BE-NEXT: ld1 { v2.4s }, [x8]
; CHECK-BE-NEXT: add x8, x2, #16
; CHECK-BE-NEXT: add x9, x3, #16
-; CHECK-BE-NEXT: ld1 { v3.4s }, [x9]
-; CHECK-BE-NEXT: ld1 { v4.4s }, [x2]
+; CHECK-BE-NEXT: ld1 { v3.4s }, [x8]
+; CHECK-BE-NEXT: ld1 { v4.4s }, [x9]
; CHECK-BE-NEXT: ld1 { v5.4s }, [x3]
-; CHECK-BE-NEXT: and v1.16b, v0.16b, v1.16b
-; CHECK-BE-NEXT: and v0.16b, v0.16b, v2.16b
-; CHECK-BE-NEXT: ld1 { v2.4s }, [x8]
+; CHECK-BE-NEXT: cmtst v1.4s, v0.4s, v1.4s
; CHECK-BE-NEXT: add x8, x0, #16
-; CHECK-BE-NEXT: cmeq v1.4s, v1.4s, #0
-; CHECK-BE-NEXT: cmeq v0.4s, v0.4s, #0
-; CHECK-BE-NEXT: bsl v1.16b, v3.16b, v2.16b
-; CHECK-BE-NEXT: bsl v0.16b, v5.16b, v4.16b
+; CHECK-BE-NEXT: cmtst v0.4s, v0.4s, v2.4s
+; CHECK-BE-NEXT: ld1 { v2.4s }, [x2]
+; CHECK-BE-NEXT: bsl v1.16b, v3.16b, v4.16b
+; CHECK-BE-NEXT: bsl v0.16b, v2.16b, v5.16b
; CHECK-BE-NEXT: st1 { v1.4s }, [x8]
; CHECK-BE-NEXT: st1 { v0.4s }, [x0]
; CHECK-BE-NEXT: ret
@@ -66,76 +62,67 @@ define void @if_then_else16(ptr %out, i16 %mask, ptr %if_true, ptr %if_false) {
; CHECK-LE-NEXT: adrp x8, .LCPI1_1
; CHECK-LE-NEXT: ldr q3, [x8, :lo12:.LCPI1_1]
; CHECK-LE-NEXT: adrp x8, .LCPI1_0
-; CHECK-LE-NEXT: and v1.16b, v0.16b, v1.16b
+; CHECK-LE-NEXT: cmtst v1.4s, v0.4s, v1.4s
; CHECK-LE-NEXT: ldr q4, [x8, :lo12:.LCPI1_0]
-; CHECK-LE-NEXT: and v2.16b, v0.16b, v2.16b
-; CHECK-LE-NEXT: and v3.16b, v0.16b, v3.16b
-; CHECK-LE-NEXT: ldp q6, q7, [x3, #32]
-; CHECK-LE-NEXT: and v0.16b, v0.16b, v4.16b
-; CHECK-LE-NEXT: cmeq v1.4s, v1.4s, #0
-; CHECK-LE-NEXT: ldp q4, q5, [x2, #32]
-; CHECK-LE-NEXT: cmeq v2.4s, v2.4s, #0
-; CHECK-LE-NEXT: ldp q16, q17, [x3]
-; CHECK-LE-NEXT: cmeq v3.4s, v3.4s, #0
-; CHECK-LE-NEXT: cmeq v0.4s, v0.4s, #0
-; CHECK-LE-NEXT: bsl v1.16b, v6.16b, v4.16b
-; CHECK-LE-NEXT: ldp q4, q6, [x2]
-; CHECK-LE-NEXT: bsl v2.16b, v7.16b, v5.16b
-; CHECK-LE-NEXT: bsl v3.16b, v16.16b, v4.16b
-; CHECK-LE-NEXT: bsl v0.16b, v17.16b, v6.16b
+; CHECK-LE-NEXT: ldp q5, q16, [x3, #32]
+; CHECK-LE-NEXT: ldp q6, q7, [x2, #32]
+; CHECK-LE-NEXT: cmtst v2.4s, v0.4s, v2.4s
+; CHECK-LE-NEXT: cmtst v3.4s, v0.4s, v3.4s
+; CHECK-LE-NEXT: cmtst v0.4s, v0.4s, v4.4s
+; CHECK-LE-NEXT: ldp q4, q17, [x3]
+; CHECK-LE-NEXT: bsl v1.16b, v6.16b, v5.16b
+; CHECK-LE-NEXT: ldp q5, q6, [x2]
+; CHECK-LE-NEXT: bsl v2.16b, v7.16b, v16.16b
+; CHECK-LE-NEXT: bsl v3.16b, v5.16b, v4.16b
+; CHECK-LE-NEXT: bsl v0.16b, v6.16b, v17.16b
; CHECK-LE-NEXT: stp q1, q2, [x0, #32]
; CHECK-LE-NEXT: stp q3, q0, [x0]
; CHECK-LE-NEXT: ret
;
; CHECK-BE-LABEL: if_then_else16:
; CHECK-BE: // %bb.0: // %start
-; CHECK-BE-NEXT: adrp x9, .LCPI1_3
-; CHECK-BE-NEXT: add x9, x9, :lo12:.LCPI1_3
+; CHECK-BE-NEXT: add x9, x2, #48
+; CHECK-BE-NEXT: dup v3.4s, w1
; CHECK-BE-NEXT: add x8, x2, #32
; CHECK-BE-NEXT: ld1 { v2.4s }, [x9]
+; CHECK-BE-NEXT: adrp x9, .LCPI1_3
+; CHECK-BE-NEXT: add x9, x9, :lo12:.LCPI1_3
+; CHECK-BE-NEXT: ld1 { v4.4s }, [x9]
; CHECK-BE-NEXT: adrp x9, .LCPI1_2
; CHECK-BE-NEXT: add x9, x9, :lo12:.LCPI1_2
-; CHECK-BE-NEXT: ld1 { v3.4s }, [x9]
-; CHECK-BE-NEXT: adrp x9, .LCPI1_1
-; CHECK-BE-NEXT: add x9, x9, :lo12:.LCPI1_1
-; CHECK-BE-NEXT: dup v0.4s, w1
-; CHECK-BE-NEXT: ld1 { v5.4s }, [x9]
-; CHECK-BE-NEXT: ld1 { v1.4s }, [x8]
-; CHECK-BE-NEXT: add x8, x2, #48
-; CHECK-BE-NEXT: add x9, x3, #48
-; CHECK-BE-NEXT: ld1 { v7.4s }, [x2]
-; CHECK-BE-NEXT: ld1 { v4.4s }, [x8]
+; CHECK-BE-NEXT: ld1 { v0.4s }, [x8]
; CHECK-BE-NEXT: adrp x8, .LCPI1_0
; CHECK-BE-NEXT: add x8, x8, :lo12:.LCPI1_0
-; CHECK-BE-NEXT: and v2.16b, v0.16b, v2.16b
-; CHECK-BE-NEXT: ld1 { v6.4s }, [x8]
-; CHECK-BE-NEXT: and v3.16b, v0.16b, v3.16b
-; CHECK-BE-NEXT: and v5.16b, v0.16b, v5.16b
-; CHECK-BE-NEXT: add x8, x3, #32
-; CHECK-BE-NEXT: ld1 { v17.4s }, [x3]
-; CHECK-BE-NEXT: ld1 { v16.4s }, [x8]
-; CHECK-BE-NEXT: add x8, x2, #16
-; CHECK-BE-NEXT: cmeq v2.4s, v2.4s, #0
-; CHECK-BE-NEXT: and v0.16b, v0.16b, v6.16b
+; CHECK-BE-NEXT: ld1 { v5.4s }, [x9]
+; CHECK-BE-NEXT: adrp x9, .LCPI1_1
+; CHECK-BE-NEXT: add x9, x9, :lo12:.LCPI1_1
; CHECK-BE-NEXT: ld1 { v6.4s }, [x9]
-; CHECK-BE-NEXT: cmeq v3.4s, v3.4s, #0
-; CHECK-BE-NEXT: cmeq v5.4s, v5.4s, #0
-; CHECK-BE-NEXT: add x9, x3, #16
-; CHECK-BE-NEXT: bit v1.16b, v16.16b, v2.16b
-; CHECK-BE-NEXT: ld1 { v2.4s }, [x8]
+; CHECK-BE-NEXT: add x9, x3, #32
+; CHECK-BE-NEXT: ld1 { v7.4s }, [x8]
+; CHECK-BE-NEXT: cmtst v4.4s, v3.4s, v4.4s
; CHECK-BE-NEXT: ld1 { v16.4s }, [x9]
-; CHECK-BE-NEXT: cmeq v0.4s, v0.4s, #0
-; CHECK-BE-NEXT: bsl v3.16b, v6.16b, v4.16b
-; CHECK-BE-NEXT: mov v4.16b, v5.16b
+; CHECK-BE-NEXT: add x8, x3, #48
+; CHECK-BE-NEXT: cmtst v5.4s, v3.4s, v5.4s
+; CHECK-BE-NEXT: add x9, x2, #16
+; CHECK-BE-NEXT: ld1 { v17.4s }, [x8]
+; CHECK-BE-NEXT: cmtst v6.4s, v3.4s, v6.4s
+; CHECK-BE-NEXT: cmtst v3.4s, v3.4s, v7.4s
+; CHECK-BE-NEXT: add x8, x3, #16
+; CHECK-BE-NEXT: ld1 { v1.4s }, [x2]
+; CHECK-BE-NEXT: ld1 { v7.4s }, [x3]
+; CHECK-BE-NEXT: bif v0.16b, v16.16b, v4.16b
+; CHECK-BE-NEXT: ld1 { v4.4s }, [x9]
+; CHECK-BE-NEXT: ld1 { v16.4s }, [x8]
+; CHECK-BE-NEXT: bif v2.16b, v17.16b, v5.16b
; CHECK-BE-NEXT: add x8, x0, #32
-; CHECK-BE-NEXT: bsl v4.16b, v17.16b, v7.16b
-; CHECK-BE-NEXT: bsl v0.16b, v16.16b, v2.16b
-; CHECK-BE-NEXT: st1 { v1.4s }, [x8]
+; CHECK-BE-NEXT: bif v1.16b, v7.16b, v6.16b
+; CHECK-BE-NEXT: bsl v3.16b, v4.16b, v16.16b
+; CHECK-BE-NEXT: st1 { v0.4s }, [x8]
; CHECK-BE-NEXT: add x8, x0, #48
-; CHECK-BE-NEXT: st1 { v3.4s }, [x8]
+; CHECK-BE-NEXT: st1 { v2.4s }, [x8]
; CHECK-BE-NEXT: add x8, x0, #16
-; CHECK-BE-NEXT: st1 { v4.4s }, [x0]
-; CHECK-BE-NEXT: st1 { v0.4s }, [x8]
+; CHECK-BE-NEXT: st1 { v1.4s }, [x0]
+; CHECK-BE-NEXT: st1 { v3.4s }, [x8]
; CHECK-BE-NEXT: ret
start:
%t = load <16 x i32>, ptr %if_true, align 4
@@ -149,158 +136,142 @@ start:
define void @if_then_else32(ptr %out, i32 %mask, ptr %if_true, ptr %if_false) {
; CHECK-LE-LABEL: if_then_else32:
; CHECK-LE: // %bb.0: // %start
-; CHECK-LE-NEXT: adrp x8, .LCPI2_0
-; CHECK-LE-NEXT: dup v7.4s, w1
-; CHECK-LE-NEXT: ldr q5, [x8, :lo12:.LCPI2_0]
-; CHECK-LE-NEXT: adrp x8, .LCPI2_1
-; CHECK-LE-NEXT: ldr q16, [x8, :lo12:.LCPI2_1]
-; CHECK-LE-NEXT: adrp x8, .LCPI2_6
-; CHECK-LE-NEXT: ldr q19, [x8, :lo12:.LCPI2_6]
+; CHECK-LE-NEXT: dup v6.4s, w1
+; CHECK-LE-NEXT: adrp x8, .LCPI2_5
+; CHECK-LE-NEXT: adrp x9, .LCPI2_6
+; CHECK-LE-NEXT: ldr q17, [x8, :lo12:.LCPI2_5]
; CHECK-LE-NEXT: adrp x8, .LCPI2_7
-; CHECK-LE-NEXT: and v5.16b, v7.16b, v5.16b
+; CHECK-LE-NEXT: ldr q23, [x9, :lo12:.LCPI2_6]
; CHECK-LE-NEXT: ldr q20, [x8, :lo12:.LCPI2_7]
-; CHECK-LE-NEXT: adrp x8, .LCPI2_2
-; CHECK-LE-NEXT: and v16.16b, v7.16b, v16.16b
-; CHECK-LE-NEXT: ldr q21, [x8, :lo12:.LCPI2_2]
-; CHECK-LE-NEXT: adrp x8, .LCPI2_5
-; CHECK-LE-NEXT: and v19.16b, v7.16b, v19.16b
-; CHECK-LE-NEXT: ldr q22, [x8, :lo12:.LCPI2_5]
-; CHECK-LE-NEXT: adrp x8, .LCPI2_4
-; CHECK-LE-NEXT: and v20.16b, v7.16b, v20.16b
-; CHECK-LE-NEXT: ldr q23, [x8, :lo12:.LCPI2_4]
-; CHECK-LE-NEXT: ldp q4, q6, [x2, #96]
-; CHECK-LE-NEXT: ldp q17, q18, [x3, #96]
-; CHECK-LE-NEXT: and v22.16b, v7.16b, v22.16b
-; CHECK-LE-NEXT: cmeq v19.4s, v19.4s, #0
-; CHECK-LE-NEXT: and v23.16b, v7.16b, v23.16b
-; CHECK-LE-NEXT: cmeq v20.4s, v20.4s, #0
-; CHECK-LE-NEXT: ldp q3, q2, [x2, #64]
-; CHECK-LE-NEXT: adrp x8, .LCPI2_3
-; CHECK-LE-NEXT: cmeq v22.4s, v22.4s, #0
-; CHECK-LE-NEXT: ldr q24, [x8, :lo12:.LCPI2_3]
-; CHECK-LE-NEXT: and v21.16b, v7.16b, v21.16b
-; CHECK-LE-NEXT: bit v6.16b, v18.16b, v19.16b
-; CHECK-LE-NEXT: ldp q18, q19, [x3, #64]
-; CHECK-LE-NEXT: cmeq v23.4s, v23.4s, #0
-; CHECK-LE-NEXT: bit v4.16b, v17.16b, v20.16b
-; CHECK-LE-NEXT: and v7.16b, v7.16b, v24.16b
-; CHECK-LE-NEXT: cmeq v16.4s, v16.4s, #0
-; CHECK-LE-NEXT: cmeq v5.4s, v5.4s, #0
-; CHECK-LE-NEXT: cmeq v21.4s, v21.4s, #0
-; CHECK-LE-NEXT: bit v3.16b, v18.16b, v22.16b
+; CHECK-LE-NEXT: ldp q5, q2, [x2, #64]
+; CHECK-LE-NEXT: cmtst v17.4s, v6.4s, v17.4s
+; CHECK-LE-NEXT: ldp q21, q22, [x3, #64]
+; CHECK-LE-NEXT: adrp x9, .LCPI2_4
+; CHECK-LE-NEXT: cmtst v20.4s, v6.4s, v20.4s
+; CHECK-LE-NEXT: cmtst v23.4s, v6.4s, v23.4s
+; CHECK-LE-NEXT: ldp q4, q3, [x2, #96]
+; CHECK-LE-NEXT: ldr q24, [x9, :lo12:.LCPI2_4]
+; CHECK-LE-NEXT: ldp q18, q19, [x3, #96]
+; CHECK-LE-NEXT: adrp x9, .LCPI2_3
+; CHECK-LE-NEXT: ldr q25, [x9, :lo12:.LCPI2_3]
+; CHECK-LE-NEXT: adrp x9, .LCPI2_2
+; CHECK-LE-NEXT: adrp x8, .LCPI2_0
+; CHECK-LE-NEXT: bif v5.16b, v21.16b, v17.16b
+; CHECK-LE-NEXT: ldr q17, [x9, :lo12:.LCPI2_2]
+; CHECK-LE-NEXT: adrp x9, .LCPI2_1
+; CHECK-LE-NEXT: cmtst v21.4s, v6.4s, v24.4s
+; CHECK-LE-NEXT: ldr q24, [x9, :lo12:.LCPI2_1]
+; CHECK-LE-NEXT: bif v4.16b, v18.16b, v20.16b
+; CHECK-LE-NEXT: ldr q18, [x8, :lo12:.LCPI2_0]
+; CHECK-LE-NEXT: cmtst v25.4s, v6.4s, v25.4s
+; CHECK-LE-NEXT: cmtst v17.4s, v6.4s, v17.4s
+; CHECK-LE-NEXT: bif v3.16b, v19.16b, v23.16b
+; CHECK-LE-NEXT: cmtst v23.4s, v6.4s, v24.4s
+; CHECK-LE-NEXT: cmtst v6.4s, v6.4s, v18.4s
; CHECK-LE-NEXT: ldp q1, q0, [x2, #32]
-; CHECK-LE-NEXT: bit v2.16b, v19.16b, v23.16b
-; CHECK-LE-NEXT: ldp q24, q25, [x2]
-; CHECK-LE-NEXT: ldp q17, q20, [x3, #32]
-; CHECK-LE-NEXT: cmeq v7.4s, v7.4s, #0
-; CHECK-LE-NEXT: ldp q18, q22, [x3]
-; CHECK-LE-NEXT: stp q4, q6, [x0, #96]
-; CHECK-LE-NEXT: mov v4.16b, v16.16b
-; CHECK-LE-NEXT: stp q3, q2, [x0, #64]
-; CHECK-LE-NEXT: mov v3.16b, v5.16b
-; CHECK-LE-NEXT: bit v1.16b, v17.16b, v7.16b
-; CHECK-LE-NEXT: bit v0.16b, v20.16b, v21.16b
-; CHECK-LE-NEXT: bsl v4.16b, v18.16b, v24.16b
-; CHECK-LE-NEXT: bsl v3.16b, v22.16b, v25.16b
+; CHECK-LE-NEXT: ldp q7, q16, [x2]
+; CHECK-LE-NEXT: bif v2.16b, v22.16b, v21.16b
+; CHECK-LE-NEXT: ldp q19, q20, [x3, #32]
+; CHECK-LE-NEXT: ldp q18, q21, [x3]
+; CHECK-LE-NEXT: stp q4, q3, [x0, #96]
+; CHECK-LE-NEXT: mov v3.16b, v23.16b
+; CHECK-LE-NEXT: mov v4.16b, v6.16b
+; CHECK-LE-NEXT: bif v1.16b, v19.16b, v25.16b
+; CHECK-LE-NEXT: bif v0.16b, v20.16b, v17.16b
+; CHECK-LE-NEXT: stp q5, q2, [x0, #64]
+; CHECK-LE-NEXT: bsl v3.16b, v7.16b, v18.16b
+; CHECK-LE-NEXT: bsl v4.16b, v16.16b, v21.16b
; CHECK-LE-NEXT: stp q1, q0, [x0, #32]
-; CHECK-LE-NEXT: stp q4, q3, [x0]
+; CHECK-LE-NEXT: stp q3, q4, [x0]
; CHECK-LE-NEXT: ret
;
; CHECK-BE-LABEL: if_then_else32:
; CHECK-BE: // %bb.0: // %start
+; CHECK-BE-NEXT: add x9, x2, #112
; CHECK-BE-NEXT: add x8, x2, #96
; CHECK-BE-NEXT: dup v19.4s, w1
-; CHECK-BE-NEXT: add x9, x2, #112
-; CHECK-BE-NEXT: ld1 { v5.4s }, [x8]
-; CHECK-BE-NEXT: add x8, x2, #80
; CHECK-BE-NEXT: ld1 { v6.4s }, [x9]
-; CHECK-BE-NEXT: ld1 { v1.4s }, [x8]
-; CHECK-BE-NEXT: add x8, x2, #32
-; CHECK-BE-NEXT: add x9, x2, #48
+; CHECK-BE-NEXT: add x9, x2, #32
; CHECK-BE-NEXT: ld1 { v4.4s }, [x8]
+; CHECK-BE-NEXT: add x8, x2, #64
+; CHECK-BE-NEXT: ld1 { v3.4s }, [x9]
+; CHECK-BE-NEXT: add x9, x3, #112
+; CHECK-BE-NEXT: ld1 { v7.4s }, [x8]
+; CHECK-BE-NEXT: add x8, x2, #80
+; CHECK-BE-NEXT: ld1 { v17.4s }, [x9]
+; CHECK-BE-NEXT: adrp x9, .LCPI2_5
+; CHECK-BE-NEXT: add x9, x9, :lo12:.LCPI2_5
+; CHECK-BE-NEXT: ld1 { v5.4s }, [x8]
+; CHECK-BE-NEXT: add x8, x2, #48
+; CHECK-BE-NEXT: ld1 { v20.4s }, [x9]
+; CHECK-BE-NEXT: adrp x9, .LCPI2_6
+; CHECK-BE-NEXT: add x9, x9, :lo12:.LCPI2_6
+; CHECK-BE-NEXT: ld1 { v2.4s }, [x8]
; CHECK-BE-NEXT: add x8, x2, #16
-; CHECK-BE-NEXT: adrp x12, .LCPI2_7
-; CHECK-BE-NEXT: add x12, x12, :lo12:.LCPI2_7
+; CHECK-BE-NEXT: ld1 { v22.4s }, [x9]
+; CHECK-BE-NEXT: adrp x10, .LCPI2_7
+; CHECK-BE-NEXT: add x10, x10, :lo12:.LCPI2_7
; CHECK-BE-NEXT: ld1 { v0.4s }, [x8]
; CHECK-BE-NEXT: add x8, x3, #96
-; CHECK-BE-NEXT: ld1 { v7.4s }, [x8]
-; CHECK-BE-NEXT: add x8, x3, #112
-; CHECK-BE-NEXT: add x10, x2, #64
-; CHECK-BE-NEXT: ld1 { v17.4s }, [x8]
-; CHECK-BE-NEXT: adrp x8, .LCPI2_5
-; CHECK-BE-NEXT: add x8, x8, :lo12:.LCPI2_5
-; CHECK-BE-NEXT: ld1 { v20.4s }, [x8]
-; CHECK-BE-NEXT: adrp x8, .LCPI2_6
-; CHECK-BE-NEXT: add x8, x8, :lo12:.LCPI2_6
-; CHECK-BE-NEXT: ld1 { v21.4s }, [x8]
-; CHECK-BE-NEXT: ld1 { v2.4s }, [x9]
-; CHECK-BE-NEXT: add x9, x3, #64
-; CHECK-BE-NEXT: ld1 { v22.4s }, [x12]
-; CHECK-BE-NEXT: ld1 { v16.4s }, [x10]
-; CHECK-BE-NEXT: ld1 { v18.4s }, [x9]
-; CHECK-BE-NEXT: and v20.16b, v19.16b, v20.16b
-; CHECK-BE-NEXT: add x8, x3, #80
-; CHECK-BE-NEXT: adrp x12, .LCPI2_4
-; CHECK-BE-NEXT: add x12, x12, :lo12:.LCPI2_4
-; CHECK-BE-NEXT: and v21.16b, v19.16b, v21.16b
-; CHECK-BE-NEXT: ld1 { v23.4s }, [x8]
-; CHECK-BE-NEXT: ld1 { v24.4s }, [x12]
-; CHECK-BE-NEXT: adrp x8, .LCPI2_3
-; CHECK-BE-NEXT: add x8, x8, :lo12:.LCPI2_3
-; CHECK-BE-NEXT: cmeq v20.4s, v20.4s, #0
-; CHECK-BE-NEXT: and v22.16b, v19.16b, v22.16b
-; CHECK-BE-NEXT: adrp x11, .LCPI2_2
-; CHECK-BE-NEXT: add x11, x11, :lo12:.LCPI2_2
-; CHECK-BE-NEXT: cmeq v21.4s, v21.4s, #0
-; CHECK-BE-NEXT: adrp x9, .LCPI2_0
-; CHECK-BE-NEXT: add x9, x9, :lo12:.LCPI2_0
-; CHECK-BE-NEXT: adrp x10, .LCPI2_1
-; CHECK-BE-NEXT: add x10, x10, :lo12:.LCPI2_1
-; CHECK-BE-NEXT: bit v16.16b, v18.16b, v20.16b
+; CHECK-BE-NEXT: ld1 { v23.4s }, [x10]
+; CHECK-BE-NEXT: ld1 { v16.4s }, [x8]
+; CHECK-BE-NEXT: add x8, x3, #64
+; CHECK-BE-NEXT: cmtst v20.4s, v19.4s, v20.4s
+; CHECK-BE-NEXT: adrp x10, .LCPI2_3
+; CHECK-BE-NEXT: add x10, x10, :lo12:.LCPI2_3
; CHECK-BE-NEXT: ld1 { v18.4s }, [x8]
-; CHECK-BE-NEXT: ld1 { v25.4s }, [x9]
-; CHECK-BE-NEXT: bit v6.16b, v17.16b, v21.16b
-; CHECK-BE-NEXT: ld1 { v17.4s }, [x11]
+; CHECK-BE-NEXT: cmtst v22.4s, v19.4s, v22.4s
+; CHECK-BE-NEXT: ld1 { v24.4s }, [x10]
+; CHECK-BE-NEXT: adrp x10, .LCPI2_4
+; CHECK-BE-NEXT: add x10, x10, :lo12:.LCPI2_4
+; CHECK-BE-NEXT: cmtst v23.4s, v19.4s, v23.4s
+; CHECK-BE-NEXT: add x8, x3, #80
+; CHECK-BE-NEXT: ld1 { v25.4s }, [x10]
+; CHECK-BE-NEXT: adrp x10, .LCPI2_2
+; CHECK-BE-NEXT: add x10, x10, :lo12:.LCPI2_2
+; CHECK-BE-NEXT: ld1 { v21.4s }, [x8]
+; CHECK-BE-NEXT: adrp x8, .LCPI2_0
+; CHECK-BE-NEXT: add x8, x8, :lo12:.LCPI2_0
+; CHECK-BE-NEXT: adrp x9, .LCPI2_1
+; CHECK-BE-NEXT: add x9, x9, :lo12:.LCPI2_1
+; CHECK-BE-NEXT: bif v7.16b, v18.16b, v20.16b
; CHECK-BE-NEXT: ld1 { v20.4s }, [x10]
-; CHECK-BE-NEXT: and v21.16b, v19.16b, v24.16b
-; CHECK-BE-NEXT: cmeq v22.4s, v22.4s, #0
-; CHECK-BE-NEXT: add x8, x3, #32
-; CHECK-BE-NEXT: and v18.16b, v19.16b, v18.16b
-; CHECK-BE-NEXT: and v25.16b, v19.16b, v25.16b
-; CHECK-BE-NEXT: ld1 { v24.4s }, [x8]
-; CHECK-BE-NEXT: and v17.16b, v19.16b, v17.16b
-; CHECK-BE-NEXT: and v20.16b, v19.16b, v20.16b
+; CHECK-BE-NEXT: bif v6.16b, v17.16b, v22.16b
+; CHECK-BE-NEXT: ld1 { v17.4s }, [x8]
+; CHECK-BE-NEXT: ld1 { v22.4s }, [x9]
+; CHECK-BE-NEXT: cmtst v25.4s, v19.4s, v25.4s
+; CHECK-BE-NEXT: add x11, x3, #32
+; CHECK-BE-NEXT: cmtst v24.4s, v19.4s, v24.4s
+; CHECK-BE-NEXT: bif v4.16b, v16.16b, v23.16b
+; CHECK-BE-NEXT: ld1 { v18.4s }, [x11]
; CHECK-BE-NEXT: add x8, x3, #48
-; CHECK-BE-NEXT: cmeq v21.4s, v21.4s, #0
-; CHECK-BE-NEXT: bit v5.16b, v7.16b, v22.16b
-; CHECK-BE-NEXT: ld1 { v19.4s }, [x8]
-; CHECK-BE-NEXT: cmeq v18.4s, v18.4s, #0
+; CHECK-BE-NEXT: cmtst v20.4s, v19.4s, v20.4s
+; CHECK-BE-NEXT: cmtst v17.4s, v19.4s, v17.4s
+; CHECK-BE-NEXT: ld1 { v16.4s }, [x8]
; CHECK-BE-NEXT: add x8, x3, #16
-; CHECK-BE-NEXT: ld1 { v3.4s }, [x2]
-; CHECK-BE-NEXT: cmeq v17.4s, v17.4s, #0
-; CHECK-BE-NEXT: ld1 { v7.4s }, [x3]
+; CHECK-BE-NEXT: cmtst v19.4s, v19.4s, v22.4s
+; CHECK-BE-NEXT: ld1 { v1.4s }, [x2]
+; CHECK-BE-NEXT: ld1 { v23.4s }, [x3]
; CHECK-BE-NEXT: ld1 { v22.4s }, [x8]
-; CHECK-BE-NEXT: cmeq v25.4s, v25.4s, #0
-; CHECK-BE-NEXT: cmeq v20.4s, v20.4s, #0
-; CHECK-BE-NEXT: bit v1.16b, v23.16b, v21.16b
+; CHECK-BE-NEXT: bif v5.16b, v21.16b, v25.16b
; CHECK-BE-NEXT: add x8, x0, #96
-; CHECK-BE-NEXT: bit v4.16b, v24.16b, v18.16b
-; CHECK-BE-NEXT: st1 { v5.4s }, [x8]
+; CHECK-BE-NEXT: bif v3.16b, v18.16b, v24.16b
+; CHECK-BE-NEXT: st1 { v4.4s }, [x8]
; CHECK-BE-NEXT: add x8, x0, #112
-; CHECK-BE-NEXT: bit v2.16b, v19.16b, v17.16b
+; CHECK-BE-NEXT: bif v2.16b, v16.16b, v20.16b
; CHECK-BE-NEXT: st1 { v6.4s }, [x8]
; CHECK-BE-NEXT: add x8, x0, #64
-; CHECK-BE-NEXT: bit v3.16b, v7.16b, v20.16b
-; CHECK-BE-NEXT: st1 { v16.4s }, [x8]
+; CHECK-BE-NEXT: bif v1.16b, v23.16b, v19.16b
+; CHECK-BE-NEXT: st1 { v7.4s }, [x8]
; CHECK-BE-NEXT: add x8, x0, #80
-; CHECK-BE-NEXT: bit v0.16b, v22.16b, v25.16b
-; CHECK-BE-NEXT: st1 { v1.4s }, [x8]
+; CHECK-BE-NEXT: bif v0.16b, v22.16b, v17.16b
+; CHECK-BE-NEXT: st1 { v5.4s }, [x8]
; CHECK-BE-NEXT: add x8, x0, #32
-; CHECK-BE-NEXT: st1 { v4.4s }, [x8]
+; CHECK-BE-NEXT: st1 { v3.4s }, [x8]
; CHECK-BE-NEXT: add x8, x0, #48
; CHECK-BE-NEXT: st1 { v2.4s }, [x8]
; CHECK-BE-NEXT: add x8, x0, #16
-; CHECK-BE-NEXT: st1 { v3.4s }, [x0]
+; CHECK-BE-NEXT: st1 { v1.4s }, [x0]
; CHECK-BE-NEXT: st1 { v0.4s }, [x8]
; CHECK-BE-NEXT: ret
start:
@@ -315,290 +286,272 @@ start:
define void @if_then_else64(ptr %out, i64 %mask, ptr %if_true, ptr %if_false) nounwind {
; CHECK-LE-LABEL: if_then_else64:
; CHECK-LE: // %bb.0: // %start
-; CHECK-LE-NEXT: sub sp, sp, #80
-; CHECK-LE-NEXT: fmov d21, x1
+; CHECK-LE-NEXT: sub sp, sp, #176
+; CHECK-LE-NEXT: fmov d16, x1
+; CHECK-LE-NEXT: adrp x8, .LCPI3_3
+; CHECK-LE-NEXT: stp d13, d12, [sp, #128] // 16-byte Folded Spill
+; CHECK-LE-NEXT: ldr q25, [x8, :lo12:.LCPI3_3]
+; CHECK-LE-NEXT: adrp x8, .LCPI3_5
+; CHECK-LE-NEXT: stp d11, d10, [sp, #144] // 16-byte Folded Spill
+; CHECK-LE-NEXT: ldr q31, [x8, :lo12:.LCPI3_5]
; CHECK-LE-NEXT: adrp x8, .LCPI3_6
-; CHECK-LE-NEXT: stp d11, d10, [sp, #48] // 16-byte Folded Spill
-; CHECK-LE-NEXT: ldr q26, [x8, :lo12:.LCPI3_6]
+; CHECK-LE-NEXT: stp d9, d8, [sp, #160] // 16-byte Folded Spill
+; CHECK-LE-NEXT: dup v26.4s, v16.s[1]
+; CHECK-LE-NEXT: ldp q1, q22, [x2, #160]
+; CHECK-LE-NEXT: ldp q8, q13, [x3, #176]
+; CHECK-LE-NEXT: ldr q10, [x8, :lo12:.LCPI3_6]
; CHECK-LE-NEXT: adrp x8, .LCPI3_7
-; CHECK-LE-NEXT: stp d9, d8, [sp, #64] // 16-byte Folded Spill
-; CHECK-LE-NEXT: ldr q27, [x8, :lo12:.LCPI3_7]
+; CHECK-LE-NEXT: stp d15, d14, [sp, #112] // 16-byte Folded Spill
+; CHECK-LE-NEXT: adrp x9, .LCPI3_4
+; CHECK-LE-NEXT: cmtst v30.4s, v26.4s, v25.4s
+; CHECK-LE-NEXT: ldr q14, [x8, :lo12:.LCPI3_7]
+; CHECK-LE-NEXT: cmtst v11.4s, v26.4s, v31.4s
+; CHECK-LE-NEXT: ldp q3, q2, [x2, #128]
+; CHECK-LE-NEXT: ldr q27, [x9, :lo12:.LCPI3_4]
+; CHECK-LE-NEXT: ldp q21, q18, [x2, #192]
+; CHECK-LE-NEXT: ldr q12, [x3, #208]
+; CHECK-LE-NEXT: ldp q17, q7, [x2, #224]
; CHECK-LE-NEXT: adrp x8, .LCPI3_0
-; CHECK-LE-NEXT: stp d15, d14, [sp, #16] // 16-byte Folded Spill
-; CHECK-LE-NEXT: dup v5.4s, v21.s[0]
-; CHECK-LE-NEXT: dup v28.4s, v21.s[1]
-; CHECK-LE-NEXT: ldr q22, [x8, :lo12:.LCPI3_0]
-; CHECK-LE-NEXT: ldp q25, q24, [x2, #96]
-; CHECK-LE-NEXT: adrp x8, .LCPI3_3
-; CHECK-LE-NEXT: ldp q21, q31, [x3, #96]
-; CHECK-LE-NEXT: stp d13, d12, [sp, #32] // 16-byte Folded Spill
-; CHECK-LE-NEXT: and v23.16b, v5.16b, v26.16b
-; CHECK-LE-NEXT: and v9.16b, v5.16b, v27.16b
-; CHECK-LE-NEXT: and v10.16b, v28.16b, v22.16b
-; CHECK-LE-NEXT: ldp q16, q0, [x2, #128]
-; CHECK-LE-NEXT: and v27.16b, v28.16b, v27.16b
-; CHECK-LE-NEXT: ldp q1, q7, [x2, #160]
-; CHECK-LE-NEXT: and v26.16b, v28.16b, v26.16b
-; CHECK-LE-NEXT: cmeq v8.4s, v23.4s, #0
-; CHECK-LE-NEXT: ldr q23, [x8, :lo12:.LCPI3_3]
-; CHECK-LE-NEXT: adrp x8, .LCPI3_4
-; CHECK-LE-NEXT: ldr q13, [x8, :lo12:.LCPI3_4]
-; CHECK-LE-NEXT: adrp x8, .LCPI3_5
-; CHECK-LE-NEXT: cmeq v27.4s, v27.4s, #0
-; CHECK-LE-NEXT: ldp q6, q2, [x2, #192]
-; CHECK-LE-NEXT: cmeq v26.4s, v26.4s, #0
-; CHECK-LE-NEXT: bif v21.16b, v25.16b, v8.16b
-; CHECK-LE-NEXT: cmeq v25.4s, v9.4s, #0
-; CHECK-LE-NEXT: cmeq v8.4s, v10.4s, #0
-; CHECK-LE-NEXT: and v9.16b, v28.16b, v23.16b
-; CHECK-LE-NEXT: ldp q14, q10, [x3, #128]
-; CHECK-LE-NEXT: and v15.16b, v28.16b, v13.16b
-; CHECK-LE-NEXT: ldp q12, q11, [x3, #192]
-; CHECK-LE-NEXT: bit v24.16b, v31.16b, v25.16b
-; CHECK-LE-NEXT: ldr q25, [x8, :lo12:.LCPI3_5]
-; CHECK-LE-NEXT: adrp x8, .LCPI3_2
-; CHECK-LE-NEXT: bit v16.16b, v14.16b, v8.16b
-; CHECK-LE-NEXT: cmeq v31.4s, v9.4s, #0
-; CHECK-LE-NEXT: str q0, [sp] // 16-byte Spill
-; CHECK-LE-NEXT: ldp q9, q8, [x3, #160]
-; CHECK-LE-NEXT: cmeq v14.4s, v15.4s, #0
-; CHECK-LE-NEXT: ldp q3, q4, [x2, #224]
-; CHECK-LE-NEXT: and v15.16b, v28.16b, v25.16b
-; CHECK-LE-NEXT: ldp q30, q29, [x3, #224]
-; CHECK-LE-NEXT: bit v7.16b, v8.16b, v31.16b
-; CHECK-LE-NEXT: ldr q31, [x8, :lo12:.LCPI3_2]
-; CHECK-LE-NEXT: bit v6.16b, v12.16b, v14.16b
-; CHECK-LE-NEXT: cmeq v14.4s, v15.4s, #0
-; CHECK-LE-NEXT: ldp q17, q19, [x2, #64]
-; CHECK-LE-NEXT: and v12.16b, v28.16b, v31.16b
-; CHECK-LE-NEXT: bit v4.16b, v29.16b, v27.16b
-; CHECK-LE-NEXT: bit v3.16b, v30.16b, v26.16b
-; CHECK-LE-NEXT: ldp q18, q20, [x2, #32]
+; CHECK-LE-NEXT: bif v22.16b, v8.16b, v30.16b
+; CHECK-LE-NEXT: cmtst v30.4s, v26.4s, v10.4s
+; CHECK-LE-NEXT: cmtst v8.4s, v26.4s, v14.4s
+; CHECK-LE-NEXT: ldp q29, q28, [x3, #224]
+; CHECK-LE-NEXT: stp q1, q2, [sp] // 32-byte Folded Spill
+; CHECK-LE-NEXT: ldp q2, q1, [x2, #96]
+; CHECK-LE-NEXT: cmtst v9.4s, v26.4s, v27.4s
+; CHECK-LE-NEXT: bif v18.16b, v12.16b, v11.16b
+; CHECK-LE-NEXT: ldr q11, [x8, :lo12:.LCPI3_0]
; CHECK-LE-NEXT: adrp x8, .LCPI3_1
-; CHECK-LE-NEXT: bit v2.16b, v11.16b, v14.16b
-; CHECK-LE-NEXT: ldp q29, q27, [x2]
-; CHECK-LE-NEXT: cmeq v12.4s, v12.4s, #0
-; CHECK-LE-NEXT: ldp q30, q26, [x3, #64]
-; CHECK-LE-NEXT: ldp q14, q11, [x3, #32]
-; CHECK-LE-NEXT: ldr q8, [x8, :lo12:.LCPI3_1]
-; CHECK-LE-NEXT: ldp q0, q15, [x3]
-; CHECK-LE-NEXT: stp q21, q24, [x0, #96]
-; CHECK-LE-NEXT: bit v1.16b, v9.16b, v12.16b
-; CHECK-LE-NEXT: stp q6, q2, [x0, #192]
-; CHECK-LE-NEXT: and v28.16b, v28.16b, v8.16b
-; CHECK-LE-NEXT: stp q3, q4, [x0, #224]
-; CHECK-LE-NEXT: and v4.16b, v5.16b, v25.16b
-; CHECK-LE-NEXT: and v3.16b, v5.16b, v13.16b
-; CHECK-LE-NEXT: and v2.16b, v5.16b, v23.16b
-; CHECK-LE-NEXT: and v6.16b, v5.16b, v31.16b
-; CHECK-LE-NEXT: ldr q25, [sp] // 16-byte Reload
-; CHECK-LE-NEXT: cmeq v28.4s, v28.4s, #0
-; CHECK-LE-NEXT: ldp d13, d12, [sp, #32] // 16-byte Folded Reload
-; CHECK-LE-NEXT: cmeq v4.4s, v4.4s, #0
-; CHECK-LE-NEXT: stp q1, q7, [x0, #160]
-; CHECK-LE-NEXT: and v7.16b, v5.16b, v8.16b
-; CHECK-LE-NEXT: and v5.16b, v5.16b, v22.16b
-; CHECK-LE-NEXT: cmeq v3.4s, v3.4s, #0
-; CHECK-LE-NEXT: cmeq v1.4s, v2.4s, #0
-; CHECK-LE-NEXT: bit v25.16b, v10.16b, v28.16b
-; CHECK-LE-NEXT: ldp d9, d8, [sp, #64] // 16-byte Folded Reload
-; CHECK-LE-NEXT: mov v2.16b, v4.16b
-; CHECK-LE-NEXT: cmeq v4.4s, v6.4s, #0
-; CHECK-LE-NEXT: cmeq v6.4s, v7.4s, #0
-; CHECK-LE-NEXT: cmeq v5.4s, v5.4s, #0
-; CHECK-LE-NEXT: bsl v3.16b, v30.16b, v17.16b
-; CHECK-LE-NEXT: bsl v1.16b, v11.16b, v20.16b
-; CHECK-LE-NEXT: ldp d11, d10, [sp, #48] // 16-byte Folded Reload
-; CHECK-LE-NEXT: bsl v2.16b, v26.16b, v19.16b
-; CHECK-LE-NEXT: bsl v4.16b, v14.16b, v18.16b
-; CHECK-LE-NEXT: bsl v6.16b, v15.16b, v27.16b
-; CHECK-LE-NEXT: bif v0.16b, v29.16b, v5.16b
-; CHECK-LE-NEXT: ldp d15, d14, [sp, #16] // 16-byte Folded Reload
-; CHECK-LE-NEXT: stp q16, q25, [x0, #128]
-; CHECK-LE-NEXT: stp q4, q1, [x0, #32]
-; CHECK-LE-NEXT: stp q0, q6, [x0]
-; CHECK-LE-NEXT: stp q3, q2, [x0, #64]
-; CHECK-LE-NEXT: add sp, sp, #80
+; CHECK-LE-NEXT: adrp x9, .LCPI3_2
+; CHECK-LE-NEXT: ldr q12, [x8, :lo12:.LCPI3_1]
+; CHECK-LE-NEXT: bif v17.16b, v29.16b, v30.16b
+; CHECK-LE-NEXT: ldr q29, [x9, :lo12:.LCPI3_2]
+; CHECK-LE-NEXT: bif v7.16b, v28.16b, v8.16b
+; CHECK-LE-NEXT: stp q3, q1, [sp, #32] // 32-byte Folded Spill
+; CHECK-LE-NEXT: ldp q0, q1, [x2, #64]
+; CHECK-LE-NEXT: dup v16.4s, v16.s[0]
+; CHECK-LE-NEXT: cmtst v30.4s, v26.4s, v11.4s
+; CHECK-LE-NEXT: cmtst v28.4s, v26.4s, v12.4s
+; CHECK-LE-NEXT: cmtst v26.4s, v26.4s, v29.4s
+; CHECK-LE-NEXT: bif v21.16b, v13.16b, v9.16b
+; CHECK-LE-NEXT: ldp q9, q15, [x3, #144]
+; CHECK-LE-NEXT: stp q2, q1, [sp, #64] // 32-byte Folded Spill
+; CHECK-LE-NEXT: ldp q19, q20, [x2, #32]
+; CHECK-LE-NEXT: str q0, [sp, #96] // 16-byte Spill
+; CHECK-LE-NEXT: ldp q23, q24, [x2]
+; CHECK-LE-NEXT: ldp q8, q13, [x3, #112]
+; CHECK-LE-NEXT: ldr q6, [x3]
+; CHECK-LE-NEXT: ldp q1, q0, [x3, #80]
+; CHECK-LE-NEXT: ldp q3, q2, [x3, #48]
+; CHECK-LE-NEXT: ldp q5, q4, [x3, #16]
+; CHECK-LE-NEXT: stp q21, q18, [x0, #192]
+; CHECK-LE-NEXT: stp q17, q7, [x0, #224]
+; CHECK-LE-NEXT: cmtst v7.4s, v16.4s, v14.4s
+; CHECK-LE-NEXT: ldr q14, [sp] // 16-byte Reload
+; CHECK-LE-NEXT: cmtst v18.4s, v16.4s, v31.4s
+; CHECK-LE-NEXT: cmtst v17.4s, v16.4s, v10.4s
+; CHECK-LE-NEXT: cmtst v21.4s, v16.4s, v27.4s
+; CHECK-LE-NEXT: bsl v26.16b, v14.16b, v15.16b
+; CHECK-LE-NEXT: ldr q27, [sp, #48] // 16-byte Reload
+; CHECK-LE-NEXT: ldr q10, [sp, #16] // 16-byte Reload
+; CHECK-LE-NEXT: ldr q31, [sp, #32] // 16-byte Reload
+; CHECK-LE-NEXT: ldp d15, d14, [sp, #112] // 16-byte Folded Reload
+; CHECK-LE-NEXT: bsl v7.16b, v27.16b, v8.16b
+; CHECK-LE-NEXT: bsl v28.16b, v10.16b, v9.16b
+; CHECK-LE-NEXT: bsl v30.16b, v31.16b, v13.16b
+; CHECK-LE-NEXT: ldp d9, d8, [sp, #160] // 16-byte Folded Reload
+; CHECK-LE-NEXT: stp q26, q22, [x0, #160]
+; CHECK-LE-NEXT: cmtst v22.4s, v16.4s, v25.4s
+; CHECK-LE-NEXT: ldp q26, q25, [sp, #64] // 32-byte Folded Reload
+; CHECK-LE-NEXT: stp q30, q28, [x0, #128]
+; CHECK-LE-NEXT: bit v1.16b, v25.16b, v18.16b
+; CHECK-LE-NEXT: ldr q25, [sp, #96] // 16-byte Reload
+; CHECK-LE-NEXT: bit v0.16b, v26.16b, v17.16b
+; CHECK-LE-NEXT: cmtst v17.4s, v16.4s, v29.4s
+; CHECK-LE-NEXT: cmtst v18.4s, v16.4s, v12.4s
+; CHECK-LE-NEXT: cmtst v16.4s, v16.4s, v11.4s
+; CHECK-LE-NEXT: bit v2.16b, v25.16b, v21.16b
+; CHECK-LE-NEXT: bit v3.16b, v20.16b, v22.16b
+; CHECK-LE-NEXT: ldp d11, d10, [sp, #144] // 16-byte Folded Reload
+; CHECK-LE-NEXT: stp q0, q7, [x0, #96]
+; CHECK-LE-NEXT: ldp d13, d12, [sp, #128] // 16-byte Folded Reload
+; CHECK-LE-NEXT: mov v0.16b, v18.16b
+; CHECK-LE-NEXT: bit v4.16b, v19.16b, v17.16b
+; CHECK-LE-NEXT: stp q2, q1, [x0, #64]
+; CHECK-LE-NEXT: mov v1.16b, v16.16b
+; CHECK-LE-NEXT: bsl v0.16b, v24.16b, v5.16b
+; CHECK-LE-NEXT: bsl v1.16b, v23.16b, v6.16b
+; CHECK-LE-NEXT: stp q4, q3, [x0, #32]
+; CHECK-LE-NEXT: stp q1, q0, [x0]
+; CHECK-LE-NEXT: add sp, sp, #176
; CHECK-LE-NEXT: ret
;
; CHECK-BE-LABEL: if_then_else64:
; CHECK-BE: // %bb.0: // %start
-; CHECK-BE-NEXT: stp d11, d10, [sp, #-32]! // 16-byte Folded Spill
-; CHECK-BE-NEXT: fmov d5, x1
-; CHECK-BE-NEXT: add x9, x2, #224
+; CHECK-BE-NEXT: str d14, [sp, #-64]! // 8-byte Folded Spill
; CHECK-BE-NEXT: add x8, x2, #240
-; CHECK-BE-NEXT: ld1 { v1.4s }, [x9]
-; CHECK-BE-NEXT: add x9, x2, #192
-; CHECK-BE-NEXT: adrp x10, .LCPI3_3
-; CHECK-BE-NEXT: add x10, x10, :lo12:.LCPI3_3
-; CHECK-BE-NEXT: ld1 { v3.4s }, [x9]
-; CHECK-BE-NEXT: add x9, x2, #128
-; CHECK-BE-NEXT: rev64 v17.4s, v5.4s
-; CHECK-BE-NEXT: ld1 { v18.4s }, [x9]
-; CHECK-BE-NEXT: add x9, x2, #80
-; CHECK-BE-NEXT: ld1 { v19.4s }, [x9]
-; CHECK-BE-NEXT: adrp x9, .LCPI3_4
-; CHECK-BE-NEXT: add x9, x9, :lo12:.LCPI3_4
-; CHECK-BE-NEXT: ld1 { v2.4s }, [x8]
-; CHECK-BE-NEXT: add x8, x2, #208
-; CHECK-BE-NEXT: ld1 { v24.4s }, [x10]
-; CHECK-BE-NEXT: ld1 { v28.4s }, [x9]
-; CHECK-BE-NEXT: add x9, x3, #96
-; CHECK-BE-NEXT: ld1 { v0.4s }, [x8]
-; CHECK-BE-NEXT: dup v7.4s, v17.s[0]
+; CHECK-BE-NEXT: fmov d16, x1
+; CHECK-BE-NEXT: add x9, x2, #224
+; CHECK-BE-NEXT: ld1 { v5.4s }, [x8]
+; CHECK-BE-NEXT: add x8, x2, #192
+; CHECK-BE-NEXT: ld1 { v6.4s }, [x9]
+; CHECK-BE-NEXT: ld1 { v7.4s }, [x8]
; CHECK-BE-NEXT: add x8, x2, #176
-; CHECK-BE-NEXT: ld1 { v23.4s }, [x9]
-; CHECK-BE-NEXT: add x9, x3, #48
+; CHECK-BE-NEXT: add x9, x2, #160
+; CHECK-BE-NEXT: ld1 { v18.4s }, [x8]
+; CHECK-BE-NEXT: add x8, x2, #128
+; CHECK-BE-NEXT: rev64 v29.4s, v16.4s
; CHECK-BE-NEXT: ld1 { v4.4s }, [x8]
-; CHECK-BE-NEXT: add x8, x2, #160
-; CHECK-BE-NEXT: ld1 { v29.4s }, [x9]
-; CHECK-BE-NEXT: adrp x9, .LCPI3_5
-; CHECK-BE-NEXT: add x9, x9, :lo12:.LCPI3_5
-; CHECK-BE-NEXT: ld1 { v5.4s }, [x8]
-; CHECK-BE-NEXT: add x8, x2, #144
-; CHECK-BE-NEXT: and v16.16b, v7.16b, v24.16b
-; CHECK-BE-NEXT: and v30.16b, v7.16b, v28.16b
-; CHECK-BE-NEXT: ld1 { v25.4s }, [x9]
-; CHECK-BE-NEXT: ld1 { v6.4s }, [x8]
-; CHECK-BE-NEXT: add x8, x2, #96
+; CHECK-BE-NEXT: add x8, x2, #80
+; CHECK-BE-NEXT: ld1 { v3.4s }, [x9]
+; CHECK-BE-NEXT: ld1 { v23.4s }, [x8]
+; CHECK-BE-NEXT: add x8, x2, #32
+; CHECK-BE-NEXT: add x9, x2, #112
+; CHECK-BE-NEXT: ld1 { v19.4s }, [x8]
+; CHECK-BE-NEXT: add x8, x3, #240
+; CHECK-BE-NEXT: ld1 { v20.4s }, [x9]
+; CHECK-BE-NEXT: ld1 { v26.4s }, [x8]
+; CHECK-BE-NEXT: add x8, x3, #224
+; CHECK-BE-NEXT: add x9, x2, #64
+; CHECK-BE-NEXT: ld1 { v25.4s }, [x8]
+; CHECK-BE-NEXT: add x8, x3, #208
+; CHECK-BE-NEXT: ld1 { v27.4s }, [x9]
+; CHECK-BE-NEXT: ld1 { v24.4s }, [x8]
+; CHECK-BE-NEXT: adrp x8, .LCPI3_4
+; CHECK-BE-NEXT: add x8, x8, :lo12:.LCPI3_4
+; CHECK-BE-NEXT: add x9, x2, #16
+; CHECK-BE-NEXT: dup v21.4s, v29.s[0]
+; CHECK-BE-NEXT: ld1 { v31.4s }, [x8]
+; CHECK-BE-NEXT: ld1 { v17.4s }, [x9]
+; CHECK-BE-NEXT: add x9, x3, #96
+; CHECK-BE-NEXT: adrp x8, .LCPI3_5
+; CHECK-BE-NEXT: add x8, x8, :lo12:.LCPI3_5
+; CHECK-BE-NEXT: ld1 { v30.4s }, [x9]
; CHECK-BE-NEXT: adrp x9, .LCPI3_6
; CHECK-BE-NEXT: add x9, x9, :lo12:.LCPI3_6
-; CHECK-BE-NEXT: ld1 { v22.4s }, [x8]
-; CHECK-BE-NEXT: add x8, x2, #48
-; CHECK-BE-NEXT: ld1 { v27.4s }, [x9]
-; CHECK-BE-NEXT: stp d9, d8, [sp, #16] // 16-byte Folded Spill
-; CHECK-BE-NEXT: ld1 { v20.4s }, [x8]
-; CHECK-BE-NEXT: cmeq v16.4s, v16.4s, #0
-; CHECK-BE-NEXT: and v8.16b, v7.16b, v25.16b
-; CHECK-BE-NEXT: cmeq v30.4s, v30.4s, #0
+; CHECK-BE-NEXT: stp d9, d8, [sp, #48] // 16-byte Folded Spill
+; CHECK-BE-NEXT: ld1 { v8.4s }, [x8]
+; CHECK-BE-NEXT: ld1 { v9.4s }, [x9]
+; CHECK-BE-NEXT: add x9, x3, #64
+; CHECK-BE-NEXT: cmtst v28.4s, v21.4s, v31.4s
+; CHECK-BE-NEXT: stp d11, d10, [sp, #32] // 16-byte Folded Spill
+; CHECK-BE-NEXT: add x10, x2, #208
; CHECK-BE-NEXT: add x8, x3, #80
-; CHECK-BE-NEXT: adrp x9, .LCPI3_7
-; CHECK-BE-NEXT: add x9, x9, :lo12:.LCPI3_7
-; CHECK-BE-NEXT: add x10, x2, #64
-; CHECK-BE-NEXT: ld1 { v26.4s }, [x8]
-; CHECK-BE-NEXT: add x8, x3, #64
-; CHECK-BE-NEXT: ld1 { v31.4s }, [x9]
-; CHECK-BE-NEXT: adrp x9, .LCPI3_0
-; CHECK-BE-NEXT: add x9, x9, :lo12:.LCPI3_0
-; CHECK-BE-NEXT: and v10.16b, v7.16b, v27.16b
-; CHECK-BE-NEXT: ld1 { v21.4s }, [x10]
-; CHECK-BE-NEXT: ld1 { v9.4s }, [x8]
-; CHECK-BE-NEXT: bsl v16.16b, v29.16b, v20.16b
-; CHECK-BE-NEXT: ld1 { v20.4s }, [x9]
-; CHECK-BE-NEXT: cmeq v8.4s, v8.4s, #0
-; CHECK-BE-NEXT: dup v29.4s, v17.s[1]
-; CHECK-BE-NEXT: mov v17.16b, v30.16b
-; CHECK-BE-NEXT: add x8, x2, #112
-; CHECK-BE-NEXT: and v11.16b, v7.16b, v31.16b
-; CHECK-BE-NEXT: cmeq v30.4s, v10.4s, #0
+; CHECK-BE-NEXT: ld1 { v11.4s }, [x9]
+; CHECK-BE-NEXT: ld1 { v2.4s }, [x10]
+; CHECK-BE-NEXT: add x10, x2, #144
+; CHECK-BE-NEXT: ld1 { v10.4s }, [x8]
+; CHECK-BE-NEXT: adrp x8, .LCPI3_7
+; CHECK-BE-NEXT: add x8, x8, :lo12:.LCPI3_7
+; CHECK-BE-NEXT: stp d13, d12, [sp, #16] // 16-byte Folded Spill
+; CHECK-BE-NEXT: ld1 { v1.4s }, [x10]
+; CHECK-BE-NEXT: add x10, x2, #96
+; CHECK-BE-NEXT: cmtst v12.4s, v21.4s, v8.4s
+; CHECK-BE-NEXT: ld1 { v13.4s }, [x8]
+; CHECK-BE-NEXT: adrp x8, .LCPI3_3
+; CHECK-BE-NEXT: add x8, x8, :lo12:.LCPI3_3
+; CHECK-BE-NEXT: cmtst v14.4s, v21.4s, v9.4s
+; CHECK-BE-NEXT: ld1 { v22.4s }, [x10]
+; CHECK-BE-NEXT: bif v27.16b, v11.16b, v28.16b
+; CHECK-BE-NEXT: ld1 { v28.4s }, [x8]
+; CHECK-BE-NEXT: dup v29.4s, v29.s[1]
+; CHECK-BE-NEXT: add x8, x3, #192
; CHECK-BE-NEXT: add x9, x3, #112
-; CHECK-BE-NEXT: bit v19.16b, v26.16b, v8.16b
-; CHECK-BE-NEXT: and v8.16b, v29.16b, v20.16b
-; CHECK-BE-NEXT: ld1 { v10.4s }, [x9]
-; CHECK-BE-NEXT: bsl v17.16b, v9.16b, v21.16b
-; CHECK-BE-NEXT: ld1 { v9.4s }, [x8]
-; CHECK-BE-NEXT: add x8, x2, #32
-; CHECK-BE-NEXT: ld1 { v21.4s }, [x8]
-; CHECK-BE-NEXT: add x8, x2, #16
-; CHECK-BE-NEXT: cmeq v26.4s, v11.4s, #0
-; CHECK-BE-NEXT: bif v23.16b, v22.16b, v30.16b
-; CHECK-BE-NEXT: ld1 { v22.4s }, [x8]
-; CHECK-BE-NEXT: add x8, x3, #128
-; CHECK-BE-NEXT: and v30.16b, v29.16b, v24.16b
+; CHECK-BE-NEXT: cmtst v11.4s, v21.4s, v13.4s
+; CHECK-BE-NEXT: bif v23.16b, v10.16b, v12.16b
+; CHECK-BE-NEXT: ld1 { v10.4s }, [x8]
+; CHECK-BE-NEXT: ld1 { v12.4s }, [x9]
+; CHECK-BE-NEXT: add x8, x3, #176
+; CHECK-BE-NEXT: bif v22.16b, v30.16b, v14.16b
+; CHECK-BE-NEXT: cmtst v30.4s, v29.4s, v28.4s
+; CHECK-BE-NEXT: ld1 { v14.4s }, [x8]
+; CHECK-BE-NEXT: cmtst v31.4s, v29.4s, v31.4s
+; CHECK-BE-NEXT: add x9, x3, #144
+; CHECK-BE-NEXT: cmtst v13.4s, v29.4s, v13.4s
+; CHECK-BE-NEXT: add x8, x3, #160
+; CHECK-BE-NEXT: bif v20.16b, v12.16b, v11.16b
+; CHECK-BE-NEXT: ld1 { v12.4s }, [x9]
+; CHECK-BE-NEXT: add x9, x3, #48
; CHECK-BE-NEXT: ld1 { v11.4s }, [x8]
-; CHECK-BE-NEXT: cmeq v8.4s, v8.4s, #0
-; CHECK-BE-NEXT: add x9, x3, #176
-; CHECK-BE-NEXT: bsl v26.16b, v10.16b, v9.16b
-; CHECK-BE-NEXT: add x8, x3, #240
-; CHECK-BE-NEXT: ld1 { v9.4s }, [x9]
-; CHECK-BE-NEXT: and v28.16b, v29.16b, v28.16b
-; CHECK-BE-NEXT: and v31.16b, v29.16b, v31.16b
-; CHECK-BE-NEXT: cmeq v30.4s, v30.4s, #0
-; CHECK-BE-NEXT: bit v18.16b, v11.16b, v8.16b
-; CHECK-BE-NEXT: ld1 { v8.4s }, [x8]
-; CHECK-BE-NEXT: add x8, x3, #224
+; CHECK-BE-NEXT: add x8, x3, #128
+; CHECK-BE-NEXT: bif v18.16b, v14.16b, v30.16b
+; CHECK-BE-NEXT: ld1 { v14.4s }, [x9]
; CHECK-BE-NEXT: adrp x9, .LCPI3_2
; CHECK-BE-NEXT: add x9, x9, :lo12:.LCPI3_2
-; CHECK-BE-NEXT: ld1 { v10.4s }, [x8]
-; CHECK-BE-NEXT: add x8, x3, #192
-; CHECK-BE-NEXT: cmeq v28.4s, v28.4s, #0
-; CHECK-BE-NEXT: bit v4.16b, v9.16b, v30.16b
+; CHECK-BE-NEXT: cmtst v9.4s, v29.4s, v9.4s
; CHECK-BE-NEXT: ld1 { v30.4s }, [x8]
-; CHECK-BE-NEXT: add x8, x3, #208
-; CHECK-BE-NEXT: ld1 { v9.4s }, [x8]
-; CHECK-BE-NEXT: and v27.16b, v29.16b, v27.16b
-; CHECK-BE-NEXT: cmeq v31.4s, v31.4s, #0
-; CHECK-BE-NEXT: adrp x8, .LCPI3_1
-; CHECK-BE-NEXT: add x8, x8, :lo12:.LCPI3_1
-; CHECK-BE-NEXT: and v25.16b, v29.16b, v25.16b
-; CHECK-BE-NEXT: bit v3.16b, v30.16b, v28.16b
-; CHECK-BE-NEXT: ld1 { v28.4s }, [x9]
-; CHECK-BE-NEXT: ld1 { v30.4s }, [x8]
-; CHECK-BE-NEXT: cmeq v27.4s, v27.4s, #0
-; CHECK-BE-NEXT: bit v2.16b, v8.16b, v31.16b
-; CHECK-BE-NEXT: add x8, x3, #160
-; CHECK-BE-NEXT: cmeq v25.4s, v25.4s, #0
-; CHECK-BE-NEXT: ld1 { v31.4s }, [x8]
-; CHECK-BE-NEXT: add x8, x3, #144
-; CHECK-BE-NEXT: and v8.16b, v29.16b, v28.16b
-; CHECK-BE-NEXT: and v29.16b, v29.16b, v30.16b
-; CHECK-BE-NEXT: add x9, x3, #32
-; CHECK-BE-NEXT: bit v1.16b, v10.16b, v27.16b
-; CHECK-BE-NEXT: ld1 { v27.4s }, [x8]
+; CHECK-BE-NEXT: adrp x8, .LCPI3_0
+; CHECK-BE-NEXT: add x8, x8, :lo12:.LCPI3_0
+; CHECK-BE-NEXT: bif v7.16b, v10.16b, v31.16b
+; CHECK-BE-NEXT: ld1 { v31.4s }, [x9]
+; CHECK-BE-NEXT: cmtst v8.4s, v29.4s, v8.4s
+; CHECK-BE-NEXT: adrp x9, .LCPI3_1
+; CHECK-BE-NEXT: add x9, x9, :lo12:.LCPI3_1
+; CHECK-BE-NEXT: bif v5.16b, v26.16b, v13.16b
+; CHECK-BE-NEXT: ld1 { v10.4s }, [x9]
+; CHECK-BE-NEXT: ld1 { v26.4s }, [x8]
+; CHECK-BE-NEXT: bif v6.16b, v25.16b, v9.16b
+; CHECK-BE-NEXT: cmtst v25.4s, v29.4s, v31.4s
; CHECK-BE-NEXT: add x8, x3, #16
-; CHECK-BE-NEXT: bit v0.16b, v9.16b, v25.16b
-; CHECK-BE-NEXT: ld1 { v25.4s }, [x8]
+; CHECK-BE-NEXT: add x10, x2, #48
+; CHECK-BE-NEXT: bif v2.16b, v24.16b, v8.16b
+; CHECK-BE-NEXT: add x9, x3, #32
+; CHECK-BE-NEXT: ld1 { v24.4s }, [x8]
+; CHECK-BE-NEXT: cmtst v9.4s, v29.4s, v10.4s
+; CHECK-BE-NEXT: cmtst v29.4s, v29.4s, v26.4s
; CHECK-BE-NEXT: add x8, x0, #240
-; CHECK-BE-NEXT: cmeq v8.4s, v8.4s, #0
-; CHECK-BE-NEXT: cmeq v29.4s, v29.4s, #0
-; CHECK-BE-NEXT: ld1 { v24.4s }, [x2]
-; CHECK-BE-NEXT: ld1 { v10.4s }, [x9]
-; CHECK-BE-NEXT: ld1 { v9.4s }, [x3]
-; CHECK-BE-NEXT: st1 { v2.4s }, [x8]
+; CHECK-BE-NEXT: ld1 { v0.4s }, [x10]
+; CHECK-BE-NEXT: ld1 { v16.4s }, [x2]
+; CHECK-BE-NEXT: ld1 { v13.4s }, [x9]
+; CHECK-BE-NEXT: ld1 { v8.4s }, [x3]
+; CHECK-BE-NEXT: st1 { v5.4s }, [x8]
; CHECK-BE-NEXT: add x8, x0, #224
-; CHECK-BE-NEXT: mov v2.16b, v8.16b
-; CHECK-BE-NEXT: st1 { v1.4s }, [x8]
-; CHECK-BE-NEXT: mov v1.16b, v29.16b
+; CHECK-BE-NEXT: bif v3.16b, v11.16b, v25.16b
+; CHECK-BE-NEXT: st1 { v6.4s }, [x8]
; CHECK-BE-NEXT: add x8, x0, #208
-; CHECK-BE-NEXT: st1 { v0.4s }, [x8]
+; CHECK-BE-NEXT: st1 { v2.4s }, [x8]
; CHECK-BE-NEXT: add x8, x0, #192
-; CHECK-BE-NEXT: and v0.16b, v7.16b, v28.16b
-; CHECK-BE-NEXT: bsl v2.16b, v31.16b, v5.16b
-; CHECK-BE-NEXT: bsl v1.16b, v27.16b, v6.16b
-; CHECK-BE-NEXT: st1 { v3.4s }, [x8]
+; CHECK-BE-NEXT: mov v2.16b, v29.16b
+; CHECK-BE-NEXT: st1 { v7.4s }, [x8]
; CHECK-BE-NEXT: add x8, x0, #176
-; CHECK-BE-NEXT: and v3.16b, v7.16b, v30.16b
-; CHECK-BE-NEXT: st1 { v4.4s }, [x8]
+; CHECK-BE-NEXT: bif v1.16b, v12.16b, v9.16b
+; CHECK-BE-NEXT: st1 { v18.4s }, [x8]
; CHECK-BE-NEXT: add x8, x0, #160
-; CHECK-BE-NEXT: and v4.16b, v7.16b, v20.16b
-; CHECK-BE-NEXT: cmeq v0.4s, v0.4s, #0
-; CHECK-BE-NEXT: st1 { v2.4s }, [x8]
+; CHECK-BE-NEXT: cmtst v5.4s, v21.4s, v26.4s
+; CHECK-BE-NEXT: bsl v2.16b, v4.16b, v30.16b
+; CHECK-BE-NEXT: st1 { v3.4s }, [x8]
+; CHECK-BE-NEXT: cmtst v3.4s, v21.4s, v31.4s
+; CHECK-BE-NEXT: cmtst v4.4s, v21.4s, v28.4s
; CHECK-BE-NEXT: add x8, x0, #144
; CHECK-BE-NEXT: st1 { v1.4s }, [x8]
; CHECK-BE-NEXT: add x8, x0, #128
-; CHECK-BE-NEXT: cmeq v1.4s, v3.4s, #0
-; CHECK-BE-NEXT: st1 { v18.4s }, [x8]
+; CHECK-BE-NEXT: cmtst v1.4s, v21.4s, v10.4s
+; CHECK-BE-NEXT: ldp d11, d10, [sp, #32] // 16-byte Folded Reload
+; CHECK-BE-NEXT: st1 { v2.4s }, [x8]
+; CHECK-BE-NEXT: mov v2.16b, v3.16b
; CHECK-BE-NEXT: add x8, x0, #112
-; CHECK-BE-NEXT: cmeq v2.4s, v4.4s, #0
-; CHECK-BE-NEXT: st1 { v26.4s }, [x8]
+; CHECK-BE-NEXT: mov v3.16b, v5.16b
+; CHECK-BE-NEXT: bif v0.16b, v14.16b, v4.16b
+; CHECK-BE-NEXT: st1 { v20.4s }, [x8]
; CHECK-BE-NEXT: add x8, x0, #96
-; CHECK-BE-NEXT: bsl v0.16b, v10.16b, v21.16b
-; CHECK-BE-NEXT: st1 { v23.4s }, [x8]
+; CHECK-BE-NEXT: bsl v1.16b, v17.16b, v24.16b
+; CHECK-BE-NEXT: bsl v2.16b, v19.16b, v13.16b
+; CHECK-BE-NEXT: st1 { v22.4s }, [x8]
; CHECK-BE-NEXT: add x8, x0, #80
-; CHECK-BE-NEXT: bsl v1.16b, v25.16b, v22.16b
-; CHECK-BE-NEXT: st1 { v19.4s }, [x8]
+; CHECK-BE-NEXT: st1 { v23.4s }, [x8]
; CHECK-BE-NEXT: add x8, x0, #64
-; CHECK-BE-NEXT: bsl v2.16b, v9.16b, v24.16b
-; CHECK-BE-NEXT: st1 { v17.4s }, [x8]
+; CHECK-BE-NEXT: bsl v3.16b, v16.16b, v8.16b
+; CHECK-BE-NEXT: st1 { v27.4s }, [x8]
; CHECK-BE-NEXT: add x8, x0, #48
-; CHECK-BE-NEXT: st1 { v16.4s }, [x8]
-; CHECK-BE-NEXT: add x8, x0, #32
-; CHECK-BE-NEXT: ldp d9, d8, [sp, #16] // 16-byte Folded Reload
; CHECK-BE-NEXT: st1 { v0.4s }, [x8]
+; CHECK-BE-NEXT: add x8, x0, #32
+; CHECK-BE-NEXT: ldp d9, d8, [sp, #48] // 16-byte Folded Reload
+; CHECK-BE-NEXT: st1 { v2.4s }, [x8]
+; CHECK-BE-NEXT: ldp d13, d12, [sp, #16] // 16-byte Folded Reload
; CHECK-BE-NEXT: add x8, x0, #16
-; CHECK-BE-NEXT: st1 { v2.4s }, [x0]
; CHECK-BE-NEXT: st1 { v1.4s }, [x8]
-; CHECK-BE-NEXT: ldp d11, d10, [sp], #32 // 16-byte Folded Reload
+; CHECK-BE-NEXT: st1 { v3.4s }, [x0]
+; CHECK-BE-NEXT: ldr d14, [sp], #64 // 8-byte Folded Reload
; CHECK-BE-NEXT: ret
start:
%if_true.val = load <64 x i32>, ptr %if_true, align 4
@@ -958,10 +911,9 @@ define void @if_then_else8_i8(ptr %out, i8 %mask, ptr %if_true, ptr %if_false) {
; CHECK-LE-NEXT: adrp x8, .LCPI12_0
; CHECK-LE-NEXT: ldr d2, [x3]
; CHECK-LE-NEXT: ldr d1, [x8, :lo12:.LCPI12_0]
-; CHECK-LE-NEXT: and v0.8b, v0.8b, v1.8b
+; CHECK-LE-NEXT: cmtst v0.8b, v0.8b, v1.8b
; CHECK-LE-NEXT: ldr d1, [x2]
-; CHECK-LE-NEXT: cmeq v0.8b, v0.8b, #0
-; CHECK-LE-NEXT: bsl v0.8b, v2.8b, v1.8b
+; CHECK-LE-NEXT: bsl v0.8b, v1.8b, v2.8b
; CHECK-LE-NEXT: str d0, [x0]
; CHECK-LE-NEXT: ret
;
@@ -972,10 +924,9 @@ define void @if_then_else8_i8(ptr %out, i8 %mask, ptr %if_true, ptr %if_false) {
; CHECK-BE-NEXT: add x8, x8, :lo12:.LCPI12_0
; CHECK-BE-NEXT: ld1 { v1.8b }, [x8]
; CHECK-BE-NEXT: ld1 { v2.8b }, [x3]
-; CHECK-BE-NEXT: and v0.8b, v0.8b, v1.8b
+; CHECK-BE-NEXT: cmtst v0.8b, v0.8b, v1.8b
; CHECK-BE-NEXT: ld1 { v1.8b }, [x2]
-; CHECK-BE-NEXT: cmeq v0.8b, v0.8b, #0
-; CHECK-BE-NEXT: bsl v0.8b, v2.8b, v1.8b
+; CHECK-BE-NEXT: bsl v0.8b, v1.8b, v2.8b
; CHECK-BE-NEXT: st1 { v0.8b }, [x0]
; CHECK-BE-NEXT: ret
start:
@@ -996,13 +947,11 @@ define void @if_then_else16_i16(ptr %out, i16 %mask, ptr %if_true, ptr %if_false
; CHECK-LE-NEXT: adrp x8, .LCPI13_0
; CHECK-LE-NEXT: ldr q2, [x8, :lo12:.LCPI13_0]
; CHECK-LE-NEXT: ldp q4, q3, [x2]
-; CHECK-LE-NEXT: and v1.16b, v0.16b, v1.16b
-; CHECK-LE-NEXT: and v0.16b, v0.16b, v2.16b
+; CHECK-LE-NEXT: cmtst v1.8h, v0.8h, v1.8h
+; CHECK-LE-NEXT: cmtst v0.8h, v0.8h, v2.8h
; CHECK-LE-NEXT: ldp q5, q2, [x3]
-; CHECK-LE-NEXT: cmeq v1.8h, v1.8h, #0
-; CHECK-LE-NEXT: cmeq v0.8h, v0.8h, #0
-; CHECK-LE-NEXT: bsl v1.16b, v2.16b, v3.16b
-; CHECK-LE-NEXT: bsl v0.16b, v5.16b, v4.16b
+; CHECK-LE-NEXT: bsl v1.16b, v3.16b, v2.16b
+; CHECK-LE-NEXT: bsl v0.16b, v4.16b, v5.16b
; CHECK-LE-NEXT: stp q0, q1, [x0]
; CHECK-LE-NEXT: ret
;
@@ -1017,17 +966,15 @@ define void @if_then_else16_i16(ptr %out, i16 %mask, ptr %if_true, ptr %if_false
; CHECK-BE-NEXT: ld1 { v2.8h }, [x8]
; CHECK-BE-NEXT: add x8, x2, #16
; CHECK-BE-NEXT: add x9, x3, #16
-; CHECK-BE-NEXT: ld1 { v3.8h }, [x9]
-; CHECK-BE-NEXT: ld1 { v4.8h }, [x2]
+; CHECK-BE-NEXT: ld1 { v3.8h }, [x8]
+; CHECK-BE-NEXT: ld1 { v4.8h }, [x9]
; CHECK-BE-NEXT: ld1 { v5.8h }, [x3]
-; CHECK-BE-NEXT: and v1.16b, v0.16b, v1.16b
-; CHECK-BE-NEXT: and v0.16b, v0.16b, v2.16b
-; CHECK-BE-NEXT: ld1 { v2.8h }, [x8]
+; CHECK-BE-NEXT: cmtst v1.8h, v0.8h, v1.8h
; CHECK-BE-NEXT: add x8, x0, #16
-; CHECK-BE-NEXT: cmeq v1.8h, v1.8h, #0
-; CHECK-BE-NEXT: cmeq v0.8h, v0.8h, #0
-; CHECK-BE-NEXT: bsl v1.16b, v3.16b, v2.16b
-; CHECK-BE-NEXT: bsl v0.16b, v5.16b, v4.16b
+; CHECK-BE-NEXT: cmtst v0.8h, v0.8h, v2.8h
+; CHECK-BE-NEXT: ld1 { v2.8h }, [x2]
+; CHECK-BE-NEXT: bsl v1.16b, v3.16b, v4.16b
+; CHECK-BE-NEXT: bsl v0.16b, v2.16b, v5.16b
; CHECK-BE-NEXT: st1 { v1.8h }, [x8]
; CHECK-BE-NEXT: st1 { v0.8h }, [x0]
; CHECK-BE-NEXT: ret
@@ -1053,13 +1000,11 @@ define void @if_then_else32_i8(ptr %out, i32 %mask, ptr %if_true, ptr %if_false)
; CHECK-LE-NEXT: ldp q4, q3, [x2]
; CHECK-LE-NEXT: tbl v1.16b, { v1.16b }, v2.16b
; CHECK-LE-NEXT: ldr q2, [x8, :lo12:.LCPI14_1]
-; CHECK-LE-NEXT: and v0.16b, v0.16b, v2.16b
-; CHECK-LE-NEXT: and v1.16b, v1.16b, v2.16b
+; CHECK-LE-NEXT: cmtst v0.16b, v0.16b, v2.16b
+; CHECK-LE-NEXT: cmtst v1.16b, v1.16b, v2.16b
; CHECK-LE-NEXT: ldp q5, q2, [x3]
-; CHECK-LE-NEXT: cmeq v0.16b, v0.16b, #0
-; CHECK-LE-NEXT: cmeq v1.16b, v1.16b, #0
-; CHECK-LE-NEXT: bsl v0.16b, v2.16b, v3.16b
-; CHECK-LE-NEXT: bsl v1.16b, v5.16b, v4.16b
+; CHECK-LE-NEXT: bsl v0.16b, v3.16b, v2.16b
+; CHECK-LE-NEXT: bsl v1.16b, v4.16b, v5.16b
; CHECK-LE-NEXT: stp q1, q0, [x0]
; CHECK-LE-NEXT: ret
;
@@ -1078,19 +1023,17 @@ define void @if_then_else32_i8(ptr %out, i32 %mask, ptr %if_true, ptr %if_false)
; CHECK-BE-NEXT: ld1 { v3.16b }, [x8]
; CHECK-BE-NEXT: add x8, x2, #16
; CHECK-BE-NEXT: add x9, x3, #16
-; CHECK-BE-NEXT: ld1 { v4.16b }, [x2]
; CHECK-BE-NEXT: ld1 { v5.16b }, [x3]
+; CHECK-BE-NEXT: ld1 { v4.16b }, [x9]
; CHECK-BE-NEXT: tbl v1.16b, { v0.16b }, v1.16b
; CHECK-BE-NEXT: tbl v0.16b, { v0.16b }, v2.16b
; CHECK-BE-NEXT: ld1 { v2.16b }, [x8]
; CHECK-BE-NEXT: add x8, x0, #16
-; CHECK-BE-NEXT: and v1.16b, v1.16b, v3.16b
-; CHECK-BE-NEXT: and v0.16b, v0.16b, v3.16b
-; CHECK-BE-NEXT: ld1 { v3.16b }, [x9]
-; CHECK-BE-NEXT: cmeq v1.16b, v1.16b, #0
-; CHECK-BE-NEXT: cmeq v0.16b, v0.16b, #0
-; CHECK-BE-NEXT: bsl v1.16b, v3.16b, v2.16b
-; CHECK-BE-NEXT: bsl v0.16b, v5.16b, v4.16b
+; CHECK-BE-NEXT: cmtst v1.16b, v1.16b, v3.16b
+; CHECK-BE-NEXT: cmtst v0.16b, v0.16b, v3.16b
+; CHECK-BE-NEXT: ld1 { v3.16b }, [x2]
+; CHECK-BE-NEXT: bsl v1.16b, v2.16b, v4.16b
+; CHECK-BE-NEXT: bsl v0.16b, v3.16b, v5.16b
; CHECK-BE-NEXT: st1 { v1.16b }, [x8]
; CHECK-BE-NEXT: st1 { v0.16b }, [x0]
; CHECK-BE-NEXT: ret
diff --git a/llvm/test/CodeGen/AArch64/urem-seteq-vec-splat.ll b/llvm/test/CodeGen/AArch64/urem-seteq-vec-splat.ll
index ab67be9445ed3..0d67bba700e85 100644
--- a/llvm/test/CodeGen/AArch64/urem-seteq-vec-splat.ll
+++ b/llvm/test/CodeGen/AArch64/urem-seteq-vec-splat.ll
@@ -165,10 +165,9 @@ define <4 x i32> @test_urem_pow2(<4 x i32> %X) nounwind {
; CHECK-LABEL: test_urem_pow2:
; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.4s, #15
-; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: cmtst v0.4s, v0.4s, v1.4s
; CHECK-NEXT: movi v1.4s, #1
-; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
-; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: bic v0.16b, v1.16b, v0.16b
; CHECK-NEXT: ret
%urem = urem <4 x i32> %X, <i32 16, i32 16, i32 16, i32 16>
%cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
diff --git a/llvm/test/CodeGen/AArch64/vec-combine-compare-to-bitmask.ll b/llvm/test/CodeGen/AArch64/vec-combine-compare-to-bitmask.ll
index f9ecae443d399..1b36b3c80b7ae 100644
--- a/llvm/test/CodeGen/AArch64/vec-combine-compare-to-bitmask.ll
+++ b/llvm/test/CodeGen/AArch64/vec-combine-compare-to-bitmask.ll
@@ -648,10 +648,9 @@ define i8 @convert_to_bitmask_8xi2(<8 x i2> %vec) {
; CHECK-SD: ; %bb.0:
; CHECK-SD-NEXT: movi.8b v1, #3
; CHECK-SD-NEXT: adrp x8, lCPI13_0 at PAGE
-; CHECK-SD-NEXT: and.8b v0, v0, v1
+; CHECK-SD-NEXT: cmtst.8b v0, v0, v1
; CHECK-SD-NEXT: ldr d1, [x8, lCPI13_0 at PAGEOFF]
-; CHECK-SD-NEXT: cmeq.8b v0, v0, #0
-; CHECK-SD-NEXT: bic.8b v0, v1, v0
+; CHECK-SD-NEXT: and.8b v0, v0, v1
; CHECK-SD-NEXT: addv.8b b0, v0
; CHECK-SD-NEXT: fmov w0, s0
; CHECK-SD-NEXT: ret
@@ -661,7 +660,8 @@ define i8 @convert_to_bitmask_8xi2(<8 x i2> %vec) {
; CHECK-GI-NEXT: sub sp, sp, #16
; CHECK-GI-NEXT: .cfi_def_cfa_offset 16
; CHECK-GI-NEXT: movi.8b v1, #3
-; CHECK-GI-NEXT: cmtst.8b v0, v0, v1
+; CHECK-GI-NEXT: and.8b v0, v0, v1
+; CHECK-GI-NEXT: cmtst.8b v0, v0, v0
; CHECK-GI-NEXT: umov.b w8, v0[1]
; CHECK-GI-NEXT: umov.b w9, v0[0]
; CHECK-GI-NEXT: umov.b w10, v0[2]
@@ -813,7 +813,8 @@ define i4 @convert_legalized_illegal_element_size(<4 x i22> %vec) {
; CHECK-GI-NEXT: sub sp, sp, #16
; CHECK-GI-NEXT: .cfi_def_cfa_offset 16
; CHECK-GI-NEXT: movi.4s v1, #63, msl #16
-; CHECK-GI-NEXT: cmtst.4s v0, v0, v1
+; CHECK-GI-NEXT: and.16b v0, v0, v1
+; CHECK-GI-NEXT: cmtst.4s v0, v0, v0
; CHECK-GI-NEXT: mov.s w8, v0[1]
; CHECK-GI-NEXT: mov.s w9, v0[2]
; CHECK-GI-NEXT: fmov w11, s0
diff --git a/llvm/test/CodeGen/AArch64/vector-popcnt-128-ult-ugt.ll b/llvm/test/CodeGen/AArch64/vector-popcnt-128-ult-ugt.ll
index 3003f15dd549a..a21ee0bc7f67c 100644
--- a/llvm/test/CodeGen/AArch64/vector-popcnt-128-ult-ugt.ll
+++ b/llvm/test/CodeGen/AArch64/vector-popcnt-128-ult-ugt.ll
@@ -175,8 +175,8 @@ define <8 x i16> @ult_2_v8i16(<8 x i16> %0) {
; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.2d, #0xffffffffffffffff
; CHECK-NEXT: add v1.8h, v0.8h, v1.8h
-; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
-; CHECK-NEXT: cmeq v0.8h, v0.8h, #0
+; CHECK-NEXT: cmtst v0.8h, v0.8h, v1.8h
+; CHECK-NEXT: mvn v0.16b, v0.16b
; CHECK-NEXT: ret
%2 = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %0)
%3 = icmp ult <8 x i16> %2, <i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2>
@@ -566,8 +566,8 @@ define <4 x i32> @ult_2_v4i32(<4 x i32> %0) {
; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.2d, #0xffffffffffffffff
; CHECK-NEXT: add v1.4s, v0.4s, v1.4s
-; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
-; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
+; CHECK-NEXT: cmtst v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: mvn v0.16b, v0.16b
; CHECK-NEXT: ret
%2 = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %0)
%3 = icmp ult <4 x i32> %2, <i32 2, i32 2, i32 2, i32 2>
@@ -1463,8 +1463,8 @@ define <2 x i64> @ult_2_v2i64(<2 x i64> %0) {
; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.2d, #0xffffffffffffffff
; CHECK-NEXT: add v1.2d, v0.2d, v1.2d
-; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
-; CHECK-NEXT: cmeq v0.2d, v0.2d, #0
+; CHECK-NEXT: cmtst v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: mvn v0.16b, v0.16b
; CHECK-NEXT: ret
%2 = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %0)
%3 = icmp ult <2 x i64> %2, <i64 2, i64 2>
@@ -1476,7 +1476,7 @@ define <2 x i64> @ugt_2_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_2_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #2
+; CHECK-NEXT: mov w8, #2 // =0x2
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -1493,7 +1493,7 @@ define <2 x i64> @ult_3_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_3_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #3
+; CHECK-NEXT: mov w8, #3 // =0x3
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -1510,7 +1510,7 @@ define <2 x i64> @ugt_3_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_3_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #3
+; CHECK-NEXT: mov w8, #3 // =0x3
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -1527,7 +1527,7 @@ define <2 x i64> @ult_4_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_4_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #4
+; CHECK-NEXT: mov w8, #4 // =0x4
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -1544,7 +1544,7 @@ define <2 x i64> @ugt_4_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_4_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #4
+; CHECK-NEXT: mov w8, #4 // =0x4
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -1561,7 +1561,7 @@ define <2 x i64> @ult_5_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_5_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #5
+; CHECK-NEXT: mov w8, #5 // =0x5
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -1578,7 +1578,7 @@ define <2 x i64> @ugt_5_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_5_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #5
+; CHECK-NEXT: mov w8, #5 // =0x5
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -1595,7 +1595,7 @@ define <2 x i64> @ult_6_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_6_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #6
+; CHECK-NEXT: mov w8, #6 // =0x6
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -1612,7 +1612,7 @@ define <2 x i64> @ugt_6_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_6_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #6
+; CHECK-NEXT: mov w8, #6 // =0x6
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -1629,7 +1629,7 @@ define <2 x i64> @ult_7_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_7_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #7
+; CHECK-NEXT: mov w8, #7 // =0x7
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -1646,7 +1646,7 @@ define <2 x i64> @ugt_7_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_7_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #7
+; CHECK-NEXT: mov w8, #7 // =0x7
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -1663,7 +1663,7 @@ define <2 x i64> @ult_8_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_8_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #8
+; CHECK-NEXT: mov w8, #8 // =0x8
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -1680,7 +1680,7 @@ define <2 x i64> @ugt_8_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_8_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #8
+; CHECK-NEXT: mov w8, #8 // =0x8
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -1697,7 +1697,7 @@ define <2 x i64> @ult_9_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_9_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #9
+; CHECK-NEXT: mov w8, #9 // =0x9
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -1714,7 +1714,7 @@ define <2 x i64> @ugt_9_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_9_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #9
+; CHECK-NEXT: mov w8, #9 // =0x9
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -1731,7 +1731,7 @@ define <2 x i64> @ult_10_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_10_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #10
+; CHECK-NEXT: mov w8, #10 // =0xa
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -1748,7 +1748,7 @@ define <2 x i64> @ugt_10_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_10_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #10
+; CHECK-NEXT: mov w8, #10 // =0xa
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -1765,7 +1765,7 @@ define <2 x i64> @ult_11_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_11_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #11
+; CHECK-NEXT: mov w8, #11 // =0xb
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -1782,7 +1782,7 @@ define <2 x i64> @ugt_11_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_11_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #11
+; CHECK-NEXT: mov w8, #11 // =0xb
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -1799,7 +1799,7 @@ define <2 x i64> @ult_12_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_12_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #12
+; CHECK-NEXT: mov w8, #12 // =0xc
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -1816,7 +1816,7 @@ define <2 x i64> @ugt_12_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_12_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #12
+; CHECK-NEXT: mov w8, #12 // =0xc
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -1833,7 +1833,7 @@ define <2 x i64> @ult_13_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_13_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #13
+; CHECK-NEXT: mov w8, #13 // =0xd
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -1850,7 +1850,7 @@ define <2 x i64> @ugt_13_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_13_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #13
+; CHECK-NEXT: mov w8, #13 // =0xd
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -1867,7 +1867,7 @@ define <2 x i64> @ult_14_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_14_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #14
+; CHECK-NEXT: mov w8, #14 // =0xe
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -1884,7 +1884,7 @@ define <2 x i64> @ugt_14_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_14_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #14
+; CHECK-NEXT: mov w8, #14 // =0xe
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -1901,7 +1901,7 @@ define <2 x i64> @ult_15_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_15_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #15
+; CHECK-NEXT: mov w8, #15 // =0xf
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -1918,7 +1918,7 @@ define <2 x i64> @ugt_15_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_15_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #15
+; CHECK-NEXT: mov w8, #15 // =0xf
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -1935,7 +1935,7 @@ define <2 x i64> @ult_16_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_16_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #16
+; CHECK-NEXT: mov w8, #16 // =0x10
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -1952,7 +1952,7 @@ define <2 x i64> @ugt_16_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_16_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #16
+; CHECK-NEXT: mov w8, #16 // =0x10
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -1969,7 +1969,7 @@ define <2 x i64> @ult_17_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_17_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #17
+; CHECK-NEXT: mov w8, #17 // =0x11
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -1986,7 +1986,7 @@ define <2 x i64> @ugt_17_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_17_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #17
+; CHECK-NEXT: mov w8, #17 // =0x11
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -2003,7 +2003,7 @@ define <2 x i64> @ult_18_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_18_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #18
+; CHECK-NEXT: mov w8, #18 // =0x12
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -2020,7 +2020,7 @@ define <2 x i64> @ugt_18_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_18_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #18
+; CHECK-NEXT: mov w8, #18 // =0x12
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -2037,7 +2037,7 @@ define <2 x i64> @ult_19_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_19_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #19
+; CHECK-NEXT: mov w8, #19 // =0x13
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -2054,7 +2054,7 @@ define <2 x i64> @ugt_19_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_19_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #19
+; CHECK-NEXT: mov w8, #19 // =0x13
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -2071,7 +2071,7 @@ define <2 x i64> @ult_20_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_20_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #20
+; CHECK-NEXT: mov w8, #20 // =0x14
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -2088,7 +2088,7 @@ define <2 x i64> @ugt_20_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_20_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #20
+; CHECK-NEXT: mov w8, #20 // =0x14
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -2105,7 +2105,7 @@ define <2 x i64> @ult_21_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_21_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #21
+; CHECK-NEXT: mov w8, #21 // =0x15
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -2122,7 +2122,7 @@ define <2 x i64> @ugt_21_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_21_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #21
+; CHECK-NEXT: mov w8, #21 // =0x15
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -2139,7 +2139,7 @@ define <2 x i64> @ult_22_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_22_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #22
+; CHECK-NEXT: mov w8, #22 // =0x16
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -2156,7 +2156,7 @@ define <2 x i64> @ugt_22_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_22_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #22
+; CHECK-NEXT: mov w8, #22 // =0x16
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -2173,7 +2173,7 @@ define <2 x i64> @ult_23_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_23_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #23
+; CHECK-NEXT: mov w8, #23 // =0x17
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -2190,7 +2190,7 @@ define <2 x i64> @ugt_23_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_23_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #23
+; CHECK-NEXT: mov w8, #23 // =0x17
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -2207,7 +2207,7 @@ define <2 x i64> @ult_24_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_24_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #24
+; CHECK-NEXT: mov w8, #24 // =0x18
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -2224,7 +2224,7 @@ define <2 x i64> @ugt_24_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_24_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #24
+; CHECK-NEXT: mov w8, #24 // =0x18
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -2241,7 +2241,7 @@ define <2 x i64> @ult_25_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_25_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #25
+; CHECK-NEXT: mov w8, #25 // =0x19
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -2258,7 +2258,7 @@ define <2 x i64> @ugt_25_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_25_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #25
+; CHECK-NEXT: mov w8, #25 // =0x19
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -2275,7 +2275,7 @@ define <2 x i64> @ult_26_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_26_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #26
+; CHECK-NEXT: mov w8, #26 // =0x1a
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -2292,7 +2292,7 @@ define <2 x i64> @ugt_26_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_26_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #26
+; CHECK-NEXT: mov w8, #26 // =0x1a
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -2309,7 +2309,7 @@ define <2 x i64> @ult_27_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_27_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #27
+; CHECK-NEXT: mov w8, #27 // =0x1b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -2326,7 +2326,7 @@ define <2 x i64> @ugt_27_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_27_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #27
+; CHECK-NEXT: mov w8, #27 // =0x1b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -2343,7 +2343,7 @@ define <2 x i64> @ult_28_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_28_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #28
+; CHECK-NEXT: mov w8, #28 // =0x1c
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -2360,7 +2360,7 @@ define <2 x i64> @ugt_28_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_28_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #28
+; CHECK-NEXT: mov w8, #28 // =0x1c
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -2377,7 +2377,7 @@ define <2 x i64> @ult_29_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_29_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #29
+; CHECK-NEXT: mov w8, #29 // =0x1d
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -2394,7 +2394,7 @@ define <2 x i64> @ugt_29_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_29_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #29
+; CHECK-NEXT: mov w8, #29 // =0x1d
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -2411,7 +2411,7 @@ define <2 x i64> @ult_30_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_30_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #30
+; CHECK-NEXT: mov w8, #30 // =0x1e
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -2428,7 +2428,7 @@ define <2 x i64> @ugt_30_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_30_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #30
+; CHECK-NEXT: mov w8, #30 // =0x1e
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -2445,7 +2445,7 @@ define <2 x i64> @ult_31_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_31_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #31
+; CHECK-NEXT: mov w8, #31 // =0x1f
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -2462,7 +2462,7 @@ define <2 x i64> @ugt_31_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_31_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #31
+; CHECK-NEXT: mov w8, #31 // =0x1f
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -2479,7 +2479,7 @@ define <2 x i64> @ult_32_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_32_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #32
+; CHECK-NEXT: mov w8, #32 // =0x20
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -2496,7 +2496,7 @@ define <2 x i64> @ugt_32_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_32_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #32
+; CHECK-NEXT: mov w8, #32 // =0x20
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -2513,7 +2513,7 @@ define <2 x i64> @ult_33_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_33_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #33
+; CHECK-NEXT: mov w8, #33 // =0x21
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -2530,7 +2530,7 @@ define <2 x i64> @ugt_33_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_33_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #33
+; CHECK-NEXT: mov w8, #33 // =0x21
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -2547,7 +2547,7 @@ define <2 x i64> @ult_34_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_34_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #34
+; CHECK-NEXT: mov w8, #34 // =0x22
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -2564,7 +2564,7 @@ define <2 x i64> @ugt_34_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_34_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #34
+; CHECK-NEXT: mov w8, #34 // =0x22
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -2581,7 +2581,7 @@ define <2 x i64> @ult_35_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_35_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #35
+; CHECK-NEXT: mov w8, #35 // =0x23
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -2598,7 +2598,7 @@ define <2 x i64> @ugt_35_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_35_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #35
+; CHECK-NEXT: mov w8, #35 // =0x23
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -2615,7 +2615,7 @@ define <2 x i64> @ult_36_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_36_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #36
+; CHECK-NEXT: mov w8, #36 // =0x24
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -2632,7 +2632,7 @@ define <2 x i64> @ugt_36_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_36_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #36
+; CHECK-NEXT: mov w8, #36 // =0x24
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -2649,7 +2649,7 @@ define <2 x i64> @ult_37_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_37_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #37
+; CHECK-NEXT: mov w8, #37 // =0x25
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -2666,7 +2666,7 @@ define <2 x i64> @ugt_37_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_37_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #37
+; CHECK-NEXT: mov w8, #37 // =0x25
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -2683,7 +2683,7 @@ define <2 x i64> @ult_38_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_38_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #38
+; CHECK-NEXT: mov w8, #38 // =0x26
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -2700,7 +2700,7 @@ define <2 x i64> @ugt_38_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_38_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #38
+; CHECK-NEXT: mov w8, #38 // =0x26
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -2717,7 +2717,7 @@ define <2 x i64> @ult_39_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_39_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #39
+; CHECK-NEXT: mov w8, #39 // =0x27
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -2734,7 +2734,7 @@ define <2 x i64> @ugt_39_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_39_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #39
+; CHECK-NEXT: mov w8, #39 // =0x27
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -2751,7 +2751,7 @@ define <2 x i64> @ult_40_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_40_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #40
+; CHECK-NEXT: mov w8, #40 // =0x28
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -2768,7 +2768,7 @@ define <2 x i64> @ugt_40_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_40_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #40
+; CHECK-NEXT: mov w8, #40 // =0x28
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -2785,7 +2785,7 @@ define <2 x i64> @ult_41_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_41_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #41
+; CHECK-NEXT: mov w8, #41 // =0x29
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -2802,7 +2802,7 @@ define <2 x i64> @ugt_41_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_41_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #41
+; CHECK-NEXT: mov w8, #41 // =0x29
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -2819,7 +2819,7 @@ define <2 x i64> @ult_42_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_42_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #42
+; CHECK-NEXT: mov w8, #42 // =0x2a
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -2836,7 +2836,7 @@ define <2 x i64> @ugt_42_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_42_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #42
+; CHECK-NEXT: mov w8, #42 // =0x2a
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -2853,7 +2853,7 @@ define <2 x i64> @ult_43_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_43_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #43
+; CHECK-NEXT: mov w8, #43 // =0x2b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -2870,7 +2870,7 @@ define <2 x i64> @ugt_43_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_43_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #43
+; CHECK-NEXT: mov w8, #43 // =0x2b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -2887,7 +2887,7 @@ define <2 x i64> @ult_44_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_44_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #44
+; CHECK-NEXT: mov w8, #44 // =0x2c
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -2904,7 +2904,7 @@ define <2 x i64> @ugt_44_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_44_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #44
+; CHECK-NEXT: mov w8, #44 // =0x2c
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -2921,7 +2921,7 @@ define <2 x i64> @ult_45_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_45_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #45
+; CHECK-NEXT: mov w8, #45 // =0x2d
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -2938,7 +2938,7 @@ define <2 x i64> @ugt_45_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_45_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #45
+; CHECK-NEXT: mov w8, #45 // =0x2d
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -2955,7 +2955,7 @@ define <2 x i64> @ult_46_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_46_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #46
+; CHECK-NEXT: mov w8, #46 // =0x2e
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -2972,7 +2972,7 @@ define <2 x i64> @ugt_46_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_46_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #46
+; CHECK-NEXT: mov w8, #46 // =0x2e
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -2989,7 +2989,7 @@ define <2 x i64> @ult_47_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_47_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #47
+; CHECK-NEXT: mov w8, #47 // =0x2f
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -3006,7 +3006,7 @@ define <2 x i64> @ugt_47_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_47_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #47
+; CHECK-NEXT: mov w8, #47 // =0x2f
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -3023,7 +3023,7 @@ define <2 x i64> @ult_48_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_48_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #48
+; CHECK-NEXT: mov w8, #48 // =0x30
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -3040,7 +3040,7 @@ define <2 x i64> @ugt_48_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_48_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #48
+; CHECK-NEXT: mov w8, #48 // =0x30
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -3057,7 +3057,7 @@ define <2 x i64> @ult_49_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_49_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #49
+; CHECK-NEXT: mov w8, #49 // =0x31
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -3074,7 +3074,7 @@ define <2 x i64> @ugt_49_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_49_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #49
+; CHECK-NEXT: mov w8, #49 // =0x31
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -3091,7 +3091,7 @@ define <2 x i64> @ult_50_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_50_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #50
+; CHECK-NEXT: mov w8, #50 // =0x32
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -3108,7 +3108,7 @@ define <2 x i64> @ugt_50_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_50_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #50
+; CHECK-NEXT: mov w8, #50 // =0x32
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -3125,7 +3125,7 @@ define <2 x i64> @ult_51_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_51_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #51
+; CHECK-NEXT: mov w8, #51 // =0x33
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -3142,7 +3142,7 @@ define <2 x i64> @ugt_51_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_51_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #51
+; CHECK-NEXT: mov w8, #51 // =0x33
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -3159,7 +3159,7 @@ define <2 x i64> @ult_52_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_52_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #52
+; CHECK-NEXT: mov w8, #52 // =0x34
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -3176,7 +3176,7 @@ define <2 x i64> @ugt_52_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_52_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #52
+; CHECK-NEXT: mov w8, #52 // =0x34
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -3193,7 +3193,7 @@ define <2 x i64> @ult_53_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_53_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #53
+; CHECK-NEXT: mov w8, #53 // =0x35
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -3210,7 +3210,7 @@ define <2 x i64> @ugt_53_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_53_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #53
+; CHECK-NEXT: mov w8, #53 // =0x35
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -3227,7 +3227,7 @@ define <2 x i64> @ult_54_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_54_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #54
+; CHECK-NEXT: mov w8, #54 // =0x36
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -3244,7 +3244,7 @@ define <2 x i64> @ugt_54_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_54_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #54
+; CHECK-NEXT: mov w8, #54 // =0x36
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -3261,7 +3261,7 @@ define <2 x i64> @ult_55_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_55_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #55
+; CHECK-NEXT: mov w8, #55 // =0x37
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -3278,7 +3278,7 @@ define <2 x i64> @ugt_55_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_55_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #55
+; CHECK-NEXT: mov w8, #55 // =0x37
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -3295,7 +3295,7 @@ define <2 x i64> @ult_56_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_56_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #56
+; CHECK-NEXT: mov w8, #56 // =0x38
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -3312,7 +3312,7 @@ define <2 x i64> @ugt_56_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_56_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #56
+; CHECK-NEXT: mov w8, #56 // =0x38
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -3329,7 +3329,7 @@ define <2 x i64> @ult_57_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_57_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #57
+; CHECK-NEXT: mov w8, #57 // =0x39
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -3346,7 +3346,7 @@ define <2 x i64> @ugt_57_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_57_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #57
+; CHECK-NEXT: mov w8, #57 // =0x39
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -3363,7 +3363,7 @@ define <2 x i64> @ult_58_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_58_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #58
+; CHECK-NEXT: mov w8, #58 // =0x3a
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -3380,7 +3380,7 @@ define <2 x i64> @ugt_58_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_58_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #58
+; CHECK-NEXT: mov w8, #58 // =0x3a
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -3397,7 +3397,7 @@ define <2 x i64> @ult_59_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_59_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #59
+; CHECK-NEXT: mov w8, #59 // =0x3b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -3414,7 +3414,7 @@ define <2 x i64> @ugt_59_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_59_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #59
+; CHECK-NEXT: mov w8, #59 // =0x3b
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -3431,7 +3431,7 @@ define <2 x i64> @ult_60_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_60_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #60
+; CHECK-NEXT: mov w8, #60 // =0x3c
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -3448,7 +3448,7 @@ define <2 x i64> @ugt_60_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_60_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #60
+; CHECK-NEXT: mov w8, #60 // =0x3c
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -3465,7 +3465,7 @@ define <2 x i64> @ult_61_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_61_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #61
+; CHECK-NEXT: mov w8, #61 // =0x3d
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -3482,7 +3482,7 @@ define <2 x i64> @ugt_61_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_61_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #61
+; CHECK-NEXT: mov w8, #61 // =0x3d
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -3499,7 +3499,7 @@ define <2 x i64> @ult_62_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ult_62_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #62
+; CHECK-NEXT: mov w8, #62 // =0x3e
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
@@ -3516,7 +3516,7 @@ define <2 x i64> @ugt_62_v2i64(<2 x i64> %0) {
; CHECK-LABEL: ugt_62_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cnt v0.16b, v0.16b
-; CHECK-NEXT: mov w8, #62
+; CHECK-NEXT: mov w8, #62 // =0x3e
; CHECK-NEXT: dup v1.2d, x8
; CHECK-NEXT: uaddlp v0.8h, v0.16b
; CHECK-NEXT: uaddlp v0.4s, v0.8h
>From d0fff3a74d9a0aa882c5a00a7895c80bee63b7d6 Mon Sep 17 00:00:00 2001
From: Mugundan <smugundan12a at gmail.com>
Date: Mon, 17 Aug 2026 12:11:39 +0530
Subject: [PATCH 6/6] Fix comments in test file
---
llvm/test/CodeGen/AArch64/cmtst-select-pow2-mask.ll | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/test/CodeGen/AArch64/cmtst-select-pow2-mask.ll b/llvm/test/CodeGen/AArch64/cmtst-select-pow2-mask.ll
index 60c837be638be..8dfd54a11973b 100644
--- a/llvm/test/CodeGen/AArch64/cmtst-select-pow2-mask.ll
+++ b/llvm/test/CodeGen/AArch64/cmtst-select-pow2-mask.ll
@@ -1,7 +1,7 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; Test: (X & Mask) == Mask, for a power-of-2 Mask, folds to CMTST
; instead of AND+CMEQ when used as a select condition inside a BSL/BSP fold.
; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
define <16 x i8> @cmtst_select_v16i8_pow2(<16 x i8> %x, <16 x i8> %y) {
; CHECK-LABEL: cmtst_select_v16i8_pow2:
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