[llvm] [mlir] [NVPTX] Add "exclusive" intrinsic variants for tcgen05.alloc/dealloc (PR #216016)

Rajat Bajpai via llvm-commits llvm-commits at lists.llvm.org
Sun Aug 16 23:30:32 PDT 2026

Previous message: [llvm] [mlir] [NVPTX] Add "exclusive" intrinsic variants for tcgen05.alloc/dealloc (PR #216016)
Next message: [llvm] 866bc8d - [RISCV] Fix prefetch ADDI-adjustment range upper bound (#215985)
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

rajatbajpai wrote:

PR #213110 will simplify backend lowering for this change. We should incorporate it.

https://github.com/llvm/llvm-project/pull/216016

Previous message: [llvm] [mlir] [NVPTX] Add "exclusive" intrinsic variants for tcgen05.alloc/dealloc (PR #216016)
Next message: [llvm] 866bc8d - [RISCV] Fix prefetch ADDI-adjustment range upper bound (#215985)
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

More information about the llvm-commits mailing list