[llvm] [AMDGPU] Fix s_buffer_load crash for illegal result types (PR #215483)
Arseniy Obolenskiy via llvm-commits
llvm-commits at lists.llvm.org
Sun Aug 16 23:14:11 PDT 2026
================
@@ -0,0 +1,348 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -global-isel=0 -mtriple=amdgpu6.00-amd-amdhsa -verify-machineinstrs < %s | FileCheck %s --check-prefix=GFX6
+; RUN: llc -global-isel=0 -mtriple=amdgpu9.00-amd-amdhsa -verify-machineinstrs < %s | FileCheck %s --check-prefix=GFX9
+; RUN: llc -global-isel=0 -mtriple=amdgpu11.00-amd-amdhsa -amdgpu-enable-vopd=0 -verify-machineinstrs < %s | FileCheck %s --check-prefix=GFX11
+; RUN: llc -global-isel=0 -mtriple=amdgpu12.00-amd-amdhsa -verify-machineinstrs < %s | FileCheck %s --check-prefix=GFX1200
+
+; llvm.amdgcn.ptr.s.buffer.load lowers through INTRINSIC_W_CHAIN, which was
+; missing Custom for these result types.
+
+define amdgpu_kernel void @ptr_s_buffer_load_i1(ptr addrspace(1) %out, ptr addrspace(8) inreg %rsrc, i32 inreg %offset) {
+; GFX6-LABEL: ptr_s_buffer_load_i1:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x4
+; GFX6-NEXT: s_load_dword s4, s[8:9], 0x8
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_buffer_load_dword s4, s[0:3], s4
+; GFX6-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
+; GFX6-NEXT: s_mov_b32 s3, 0x100f000
+; GFX6-NEXT: s_mov_b32 s2, -1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_and_b32 s4, s4, 1
+; GFX6-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-NEXT: buffer_store_byte v0, off, s[0:3], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX9-LABEL: ptr_s_buffer_load_i1:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x10
+; GFX9-NEXT: s_load_dword s6, s[8:9], 0x20
+; GFX9-NEXT: v_mov_b32_e32 v0, 0
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_buffer_load_dword s7, s[0:3], s6 offset:0x0
+; GFX9-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x0
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_and_b32 s0, s7, 1
+; GFX9-NEXT: v_mov_b32_e32 v1, s0
+; GFX9-NEXT: global_store_byte v0, v1, s[4:5]
+; GFX9-NEXT: s_endpgm
+;
+; GFX11-LABEL: ptr_s_buffer_load_i1:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_clause 0x1
+; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x10
+; GFX11-NEXT: s_load_b32 s6, s[4:5], 0x20
+; GFX11-NEXT: v_mov_b32_e32 v0, 0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_buffer_load_b32 s2, s[0:3], s6 offset:0x0
+; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_and_b32 s2, s2, 1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_mov_b32_e32 v1, s2
+; GFX11-NEXT: global_store_b8 v0, v1, s[0:1]
+; GFX11-NEXT: s_endpgm
+;
+; GFX1200-LABEL: ptr_s_buffer_load_i1:
+; GFX1200: ; %bb.0:
+; GFX1200-NEXT: s_clause 0x1
+; GFX1200-NEXT: s_load_b128 s[0:3], s[4:5], 0x10
+; GFX1200-NEXT: s_load_b32 s6, s[4:5], 0x20
+; GFX1200-NEXT: s_wait_kmcnt 0x0
+; GFX1200-NEXT: s_buffer_load_b32 s2, s[0:3], s6 offset:0x0
+; GFX1200-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
+; GFX1200-NEXT: s_wait_kmcnt 0x0
+; GFX1200-NEXT: s_and_b32 s2, s2, 1
+; GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1200-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GFX1200-NEXT: global_store_b8 v0, v1, s[0:1]
+; GFX1200-NEXT: s_endpgm
+ %load = call i1 @llvm.amdgcn.ptr.s.buffer.load.i1(ptr addrspace(8) %rsrc, i32 %offset, i32 0)
+ store i1 %load, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_kernel void @ptr_s_buffer_load_i4(ptr addrspace(1) %out, ptr addrspace(8) inreg %rsrc, i32 inreg %offset) {
+; GFX6-LABEL: ptr_s_buffer_load_i4:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x4
+; GFX6-NEXT: s_load_dword s4, s[8:9], 0x8
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_buffer_load_dword s4, s[0:3], s4
+; GFX6-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
+; GFX6-NEXT: s_mov_b32 s3, 0x100f000
+; GFX6-NEXT: s_mov_b32 s2, -1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_and_b32 s4, s4, 15
+; GFX6-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-NEXT: buffer_store_byte v0, off, s[0:3], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX9-LABEL: ptr_s_buffer_load_i4:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x10
+; GFX9-NEXT: s_load_dword s6, s[8:9], 0x20
+; GFX9-NEXT: v_mov_b32_e32 v0, 0
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_buffer_load_dword s7, s[0:3], s6 offset:0x0
+; GFX9-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x0
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_and_b32 s0, s7, 15
+; GFX9-NEXT: v_mov_b32_e32 v1, s0
+; GFX9-NEXT: global_store_byte v0, v1, s[4:5]
+; GFX9-NEXT: s_endpgm
+;
+; GFX11-LABEL: ptr_s_buffer_load_i4:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_clause 0x1
+; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x10
+; GFX11-NEXT: s_load_b32 s6, s[4:5], 0x20
+; GFX11-NEXT: v_mov_b32_e32 v0, 0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_buffer_load_b32 s2, s[0:3], s6 offset:0x0
+; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_and_b32 s2, s2, 15
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_mov_b32_e32 v1, s2
+; GFX11-NEXT: global_store_b8 v0, v1, s[0:1]
+; GFX11-NEXT: s_endpgm
+;
+; GFX1200-LABEL: ptr_s_buffer_load_i4:
+; GFX1200: ; %bb.0:
+; GFX1200-NEXT: s_clause 0x1
+; GFX1200-NEXT: s_load_b128 s[0:3], s[4:5], 0x10
+; GFX1200-NEXT: s_load_b32 s6, s[4:5], 0x20
+; GFX1200-NEXT: s_wait_kmcnt 0x0
+; GFX1200-NEXT: s_buffer_load_b32 s2, s[0:3], s6 offset:0x0
+; GFX1200-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
+; GFX1200-NEXT: s_wait_kmcnt 0x0
+; GFX1200-NEXT: s_and_b32 s2, s2, 15
+; GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1200-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GFX1200-NEXT: global_store_b8 v0, v1, s[0:1]
+; GFX1200-NEXT: s_endpgm
+ %load = call i4 @llvm.amdgcn.ptr.s.buffer.load.i4(ptr addrspace(8) %rsrc, i32 %offset, i32 0)
+ store i4 %load, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_kernel void @ptr_s_buffer_load_v2i1(ptr addrspace(1) %out, ptr addrspace(8) inreg %rsrc, i32 inreg %offset) {
+; GFX6-LABEL: ptr_s_buffer_load_v2i1:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x4
+; GFX6-NEXT: s_load_dword s4, s[8:9], 0x8
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_buffer_load_dword s4, s[0:3], s4
+; GFX6-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
+; GFX6-NEXT: s_mov_b32 s3, 0x100f000
+; GFX6-NEXT: s_mov_b32 s2, -1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_and_b32 s4, s4, 3
+; GFX6-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-NEXT: buffer_store_byte v0, off, s[0:3], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX9-LABEL: ptr_s_buffer_load_v2i1:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x10
+; GFX9-NEXT: s_load_dword s6, s[8:9], 0x20
+; GFX9-NEXT: v_mov_b32_e32 v0, 0
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_buffer_load_dword s7, s[0:3], s6 offset:0x0
+; GFX9-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x0
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_and_b32 s0, s7, 3
+; GFX9-NEXT: v_mov_b32_e32 v1, s0
+; GFX9-NEXT: global_store_byte v0, v1, s[4:5]
+; GFX9-NEXT: s_endpgm
+;
+; GFX11-LABEL: ptr_s_buffer_load_v2i1:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_clause 0x1
+; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x10
+; GFX11-NEXT: s_load_b32 s6, s[4:5], 0x20
+; GFX11-NEXT: v_mov_b32_e32 v0, 0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_buffer_load_b32 s2, s[0:3], s6 offset:0x0
+; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_and_b32 s2, s2, 3
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_mov_b32_e32 v1, s2
+; GFX11-NEXT: global_store_b8 v0, v1, s[0:1]
+; GFX11-NEXT: s_endpgm
+;
+; GFX1200-LABEL: ptr_s_buffer_load_v2i1:
+; GFX1200: ; %bb.0:
+; GFX1200-NEXT: s_clause 0x1
+; GFX1200-NEXT: s_load_b128 s[0:3], s[4:5], 0x10
+; GFX1200-NEXT: s_load_b32 s6, s[4:5], 0x20
+; GFX1200-NEXT: s_wait_kmcnt 0x0
+; GFX1200-NEXT: s_buffer_load_b32 s2, s[0:3], s6 offset:0x0
+; GFX1200-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
+; GFX1200-NEXT: s_wait_kmcnt 0x0
+; GFX1200-NEXT: s_and_b32 s2, s2, 3
+; GFX1200-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1200-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GFX1200-NEXT: global_store_b8 v0, v1, s[0:1]
+; GFX1200-NEXT: s_endpgm
+ %load = call <2 x i1> @llvm.amdgcn.ptr.s.buffer.load.v2i1(ptr addrspace(8) %rsrc, i32 %offset, i32 0)
+ store <2 x i1> %load, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_kernel void @ptr_s_buffer_load_v6i8(ptr addrspace(1) %out, ptr addrspace(8) inreg %rsrc, i32 inreg %offset) {
+; GFX6-LABEL: ptr_s_buffer_load_v6i8:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x4
+; GFX6-NEXT: s_load_dword s4, s[8:9], 0x8
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_buffer_load_dwordx2 s[4:5], s[0:3], s4
+; GFX6-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
+; GFX6-NEXT: s_mov_b32 s3, 0x100f000
+; GFX6-NEXT: s_mov_b32 s2, -1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s5
+; GFX6-NEXT: v_mov_b32_e32 v1, s4
+; GFX6-NEXT: buffer_store_short v0, off, s[0:3], 0 offset:4
+; GFX6-NEXT: buffer_store_dword v1, off, s[0:3], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX9-LABEL: ptr_s_buffer_load_v6i8:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x10
+; GFX9-NEXT: s_load_dword s10, s[8:9], 0x20
+; GFX9-NEXT: v_mov_b32_e32 v0, 0
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_buffer_load_dwordx2 s[4:5], s[0:3], s10 offset:0x0
+; GFX9-NEXT: s_load_dwordx2 s[6:7], s[8:9], 0x0
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: v_mov_b32_e32 v1, s5
+; GFX9-NEXT: v_mov_b32_e32 v2, s4
+; GFX9-NEXT: global_store_short v0, v1, s[6:7] offset:4
+; GFX9-NEXT: global_store_dword v0, v2, s[6:7]
+; GFX9-NEXT: s_endpgm
+;
+; GFX11-LABEL: ptr_s_buffer_load_v6i8:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_clause 0x1
+; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x10
+; GFX11-NEXT: s_load_b32 s6, s[4:5], 0x20
+; GFX11-NEXT: v_mov_b32_e32 v0, 0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_buffer_load_b64 s[0:1], s[0:3], s6 offset:0x0
+; GFX11-NEXT: s_load_b64 s[2:3], s[4:5], 0x0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: v_mov_b32_e32 v1, s1
+; GFX11-NEXT: v_mov_b32_e32 v2, s0
+; GFX11-NEXT: s_clause 0x1
+; GFX11-NEXT: global_store_b16 v0, v1, s[2:3] offset:4
+; GFX11-NEXT: global_store_b32 v0, v2, s[2:3]
+; GFX11-NEXT: s_endpgm
+;
+; GFX1200-LABEL: ptr_s_buffer_load_v6i8:
+; GFX1200: ; %bb.0:
+; GFX1200-NEXT: s_clause 0x1
+; GFX1200-NEXT: s_load_b128 s[0:3], s[4:5], 0x10
+; GFX1200-NEXT: s_load_b32 s6, s[4:5], 0x20
+; GFX1200-NEXT: s_wait_kmcnt 0x0
+; GFX1200-NEXT: s_buffer_load_b64 s[0:1], s[0:3], s6 offset:0x0
+; GFX1200-NEXT: s_load_b64 s[2:3], s[4:5], 0x0
+; GFX1200-NEXT: s_wait_kmcnt 0x0
+; GFX1200-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s1
+; GFX1200-NEXT: v_mov_b32_e32 v2, s0
+; GFX1200-NEXT: s_clause 0x1
+; GFX1200-NEXT: global_store_b16 v0, v1, s[2:3] offset:4
+; GFX1200-NEXT: global_store_b32 v0, v2, s[2:3]
+; GFX1200-NEXT: s_endpgm
+ %load = call <6 x i8> @llvm.amdgcn.ptr.s.buffer.load.v6i8(ptr addrspace(8) %rsrc, i32 %offset, i32 0)
+ store <6 x i8> %load, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_kernel void @ptr_s_buffer_load_i128(ptr addrspace(1) %out, ptr addrspace(8) inreg %rsrc, i32 inreg %offset) {
+; GFX6-LABEL: ptr_s_buffer_load_i128:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x4
+; GFX6-NEXT: s_load_dword s4, s[8:9], 0x8
+; GFX6-NEXT: s_mov_b32 s7, 0x100f000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_buffer_load_dwordx4 s[0:3], s[0:3], s4
+; GFX6-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x0
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s0
+; GFX6-NEXT: v_mov_b32_e32 v1, s1
+; GFX6-NEXT: v_mov_b32_e32 v2, s2
+; GFX6-NEXT: v_mov_b32_e32 v3, s3
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX9-LABEL: ptr_s_buffer_load_i128:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x10
+; GFX9-NEXT: s_load_dword s12, s[8:9], 0x20
+; GFX9-NEXT: v_mov_b32_e32 v4, 0
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_buffer_load_dwordx4 s[4:7], s[0:3], s12 offset:0x0
+; GFX9-NEXT: s_load_dwordx2 s[10:11], s[8:9], 0x0
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: v_mov_b32_e32 v0, s4
+; GFX9-NEXT: v_mov_b32_e32 v1, s5
+; GFX9-NEXT: v_mov_b32_e32 v2, s6
+; GFX9-NEXT: v_mov_b32_e32 v3, s7
+; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[10:11]
+; GFX9-NEXT: s_endpgm
+;
+; GFX11-LABEL: ptr_s_buffer_load_i128:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_clause 0x1
+; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x10
+; GFX11-NEXT: s_load_b32 s6, s[4:5], 0x20
+; GFX11-NEXT: v_mov_b32_e32 v4, 0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_buffer_load_b128 s[0:3], s[0:3], s6 offset:0x0
+; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: v_mov_b32_e32 v0, s0
+; GFX11-NEXT: v_mov_b32_e32 v1, s1
+; GFX11-NEXT: v_mov_b32_e32 v2, s2
+; GFX11-NEXT: v_mov_b32_e32 v3, s3
+; GFX11-NEXT: global_store_b128 v4, v[0:3], s[4:5]
+; GFX11-NEXT: s_endpgm
+;
+; GFX1200-LABEL: ptr_s_buffer_load_i128:
+; GFX1200: ; %bb.0:
+; GFX1200-NEXT: s_clause 0x1
+; GFX1200-NEXT: s_load_b128 s[0:3], s[4:5], 0x10
+; GFX1200-NEXT: s_load_b32 s6, s[4:5], 0x20
+; GFX1200-NEXT: s_wait_kmcnt 0x0
+; GFX1200-NEXT: s_buffer_load_b128 s[0:3], s[0:3], s6 offset:0x0
+; GFX1200-NEXT: s_load_b64 s[4:5], s[4:5], 0x0
+; GFX1200-NEXT: s_wait_kmcnt 0x0
+; GFX1200-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v1, s1
+; GFX1200-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s3
+; GFX1200-NEXT: v_mov_b32_e32 v2, s2
+; GFX1200-NEXT: global_store_b128 v4, v[0:3], s[4:5]
+; GFX1200-NEXT: s_endpgm
+ %load = call i128 @llvm.amdgcn.ptr.s.buffer.load.i128(ptr addrspace(8) %rsrc, i32 %offset, i32 0)
+ store i128 %load, ptr addrspace(1) %out
+ ret void
+}
+
+declare i1 @llvm.amdgcn.ptr.s.buffer.load.i1(ptr addrspace(8) nocapture readonly, i32, i32 immarg)
+declare i4 @llvm.amdgcn.ptr.s.buffer.load.i4(ptr addrspace(8) nocapture readonly, i32, i32 immarg)
+declare <2 x i1> @llvm.amdgcn.ptr.s.buffer.load.v2i1(ptr addrspace(8) nocapture readonly, i32, i32 immarg)
+declare <6 x i8> @llvm.amdgcn.ptr.s.buffer.load.v6i8(ptr addrspace(8) nocapture readonly, i32, i32 immarg)
+declare i128 @llvm.amdgcn.ptr.s.buffer.load.i128(ptr addrspace(8) nocapture readonly, i32, i32 immarg)
----------------
aobolensk wrote:
Removed
https://github.com/llvm/llvm-project/pull/215483
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