[llvm] [BOLT][AArch64] Add support for LDR relaxation on LDRSl/LDRDl/LDRQl (PR #196983)

[YongKang Zhu via llvm-commits]

yozhu wrote:

> But changing `DefaultAlignment` to 16 cannot fix the same `BOLT-ERROR` reported by the other 2 test cases guarded by `RELAX_MISALIGNED_LDR` and `RELAX_MISALIGNED_LDR_FP`, whereas using `adrp+add+ldr` will fix all the three test cases.

Thinking this more, IIUC, this pass is mainly to undo the linker relaxation to cover LDR from address that can potentially go out of range. In most cases we would just turn the adjacent `NOP+LDR` into `ADRP+LDR`, not increasing code size.

With a conservative assumption that data being accessed is only 1-byte aligned or misaligned, we would then generate a longer sequence, which is a waste in most (common) cases.

Given where this relaxation is currently placed in the pass pipeline and that we are not achieving 100% coverage (like for non-simple functions if NOP cannot be found next to LDR we will error out), maybe we just make a good tradeoff here, covering most common cases and erroring out on rare cases?

Internally, we have been testing a version of this LDR relaxation pass in some applications, with a 16-byte default constant island alignment and using register analysis for FP load relaxation. And it has been working fine ..


https://github.com/llvm/llvm-project/pull/196983