[llvm] X86: Emit adox instead of adc for overflow add (PR #216609)
via llvm-commits
llvm-commits at lists.llvm.org
Sun Aug 16 15:57:48 PDT 2026
https://github.com/AZero13 updated https://github.com/llvm/llvm-project/pull/216609
>From db54443a51f8a26cc44ae91fbdc248951eab5e03 Mon Sep 17 00:00:00 2001
From: AZero13 <gfunni234 at gmail.com>
Date: Sun, 16 Aug 2026 18:07:16 -0400
Subject: [PATCH 1/2] [X86] Precommit adox.ll test
---
llvm/test/CodeGen/X86/adox.ll | 121 ++++++++++++++++++++++++++++++++++
1 file changed, 121 insertions(+)
create mode 100644 llvm/test/CodeGen/X86/adox.ll
diff --git a/llvm/test/CodeGen/X86/adox.ll b/llvm/test/CodeGen/X86/adox.ll
new file mode 100644
index 0000000000000..f0e0b0b2717bb
--- /dev/null
+++ b/llvm/test/CodeGen/X86/adox.ll
@@ -0,0 +1,121 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+adx | FileCheck %s --check-prefixes=CHECK,ADX
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=-adx | FileCheck %s --check-prefixes=CHECK,NOADX
+
+define i32 @adox_test_i32(i32 %a, i32 %b, i8 %c, i8 %d) {
+; CHECK-LABEL: adox_test_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: # kill: def $esi killed $esi def $rsi
+; CHECK-NEXT: # kill: def $edi killed $edi def $rdi
+; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: cmpb %cl, %dl
+; CHECK-NEXT: seto %al
+; CHECK-NEXT: addl %edi, %eax
+; CHECK-NEXT: addl %esi, %eax
+; CHECK-NEXT: retq
+ %ssub = call { i8, i1 } @llvm.ssub.with.overflow.i8(i8 %c, i8 %d)
+ %ov = extractvalue { i8, i1 } %ssub, 1
+ %ov.ext = zext i1 %ov to i32
+ %sum = add i32 %a, %b
+ %res = add i32 %sum, %ov.ext
+ ret i32 %res
+}
+
+define i64 @adox_test_i64(i64 %a, i64 %b, i8 %c, i8 %d) {
+; CHECK-LABEL: adox_test_i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: cmpb %cl, %dl
+; CHECK-NEXT: seto %al
+; CHECK-NEXT: addq %rdi, %rax
+; CHECK-NEXT: addq %rsi, %rax
+; CHECK-NEXT: retq
+ %ssub = call { i8, i1 } @llvm.ssub.with.overflow.i8(i8 %c, i8 %d)
+ %ov = extractvalue { i8, i1 } %ssub, 1
+ %ov.ext = zext i1 %ov to i64
+ %sum = add i64 %a, %b
+ %res = add i64 %sum, %ov.ext
+ ret i64 %res
+}
+
+declare { i8, i1 } @llvm.ssub.with.overflow.i8(i8, i8)
+
+define i32 @adox_test_i32_mem(i32 %a, ptr %b_ptr, i8 %c, i8 %d) {
+; CHECK-LABEL: adox_test_i32_mem:
+; CHECK: # %bb.0:
+; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: cmpb %cl, %dl
+; CHECK-NEXT: seto %al
+; CHECK-NEXT: addl (%rsi), %edi
+; CHECK-NEXT: addl %edi, %eax
+; CHECK-NEXT: retq
+ %b = load i32, ptr %b_ptr
+ %ssub = call { i8, i1 } @llvm.ssub.with.overflow.i8(i8 %c, i8 %d)
+ %ov = extractvalue { i8, i1 } %ssub, 1
+ %ov.ext = zext i1 %ov to i32
+ %add = add i32 %a, %b
+ %add2 = add i32 %add, %ov.ext
+ ret i32 %add2
+}
+
+define i64 @adox_test_i64_mem(i64 %a, ptr %b_ptr, i8 %c, i8 %d) {
+; CHECK-LABEL: adox_test_i64_mem:
+; CHECK: # %bb.0:
+; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: cmpb %cl, %dl
+; CHECK-NEXT: seto %al
+; CHECK-NEXT: addq (%rsi), %rdi
+; CHECK-NEXT: addq %rdi, %rax
+; CHECK-NEXT: retq
+ %b = load i64, ptr %b_ptr
+ %ssub = call { i8, i1 } @llvm.ssub.with.overflow.i8(i8 %c, i8 %d)
+ %ov = extractvalue { i8, i1 } %ssub, 1
+ %ov.ext = zext i1 %ov to i64
+ %add = add i64 %a, %b
+ %add2 = add i64 %add, %ov.ext
+ ret i64 %add2
+}
+
+define i32 @adox_test_sadd_i32(i32 %a, i32 %b, i8 %c, i8 %d) {
+; CHECK-LABEL: adox_test_sadd_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: # kill: def $esi killed $esi def $rsi
+; CHECK-NEXT: # kill: def $edi killed $edi def $rdi
+; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: addb %cl, %dl
+; CHECK-NEXT: seto %al
+; CHECK-NEXT: addl %edi, %eax
+; CHECK-NEXT: addl %esi, %eax
+; CHECK-NEXT: retq
+ %sadd = call { i8, i1 } @llvm.sadd.with.overflow.i8(i8 %c, i8 %d)
+ %ov = extractvalue { i8, i1 } %sadd, 1
+ %ov.ext = zext i1 %ov to i32
+ %add = add i32 %a, %b
+ %add2 = add i32 %add, %ov.ext
+ ret i32 %add2
+}
+
+declare { i8, i1 } @llvm.sadd.with.overflow.i8(i8, i8)
+
+define i16 @adox_test_i16(i16 %a, i16 %b, i8 %c, i8 %d) {
+; CHECK-LABEL: adox_test_i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: # kill: def $esi killed $esi def $rsi
+; CHECK-NEXT: # kill: def $edi killed $edi def $rdi
+; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: cmpb %cl, %dl
+; CHECK-NEXT: seto %al
+; CHECK-NEXT: addl %edi, %eax
+; CHECK-NEXT: addl %esi, %eax
+; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
+; CHECK-NEXT: retq
+ %ssub = call { i8, i1 } @llvm.ssub.with.overflow.i8(i8 %c, i8 %d)
+ %ov = extractvalue { i8, i1 } %ssub, 1
+ %ov.ext = zext i1 %ov to i16
+ %sum = add i16 %a, %b
+ %res = add i16 %sum, %ov.ext
+ ret i16 %res
+}
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; ADX: {{.*}}
+; NOADX: {{.*}}
>From 142d906e64ca5cbeb0187ff02065728d47ef158d Mon Sep 17 00:00:00 2001
From: AZero13 <gfunni234 at gmail.com>
Date: Sun, 16 Aug 2026 18:45:50 -0400
Subject: [PATCH 2/2] X86: Emit adox instead of adc for overflow add
ADOX is like ADC but with OF and can only be encoded with a pair of 32 or 64 bit regs.
---
llvm/lib/Target/X86/X86ISelLowering.cpp | 36 +++-
llvm/lib/Target/X86/X86InstrArithmetic.td | 23 +++
llvm/lib/Target/X86/X86InstrFragments.td | 1 +
llvm/lib/Target/X86/X86InstrPredicates.td | 2 +
llvm/test/CodeGen/X86/adox.ll | 196 +++++++++++++++-------
5 files changed, 199 insertions(+), 59 deletions(-)
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 0dc3340a13c73..a972d44aa7bff 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -25338,8 +25338,9 @@ static bool isX86LogicalCmp(SDValue Op) {
return true;
if (Op.getResNo() == 1 &&
(Opc == X86ISD::ADD || Opc == X86ISD::SUB || Opc == X86ISD::ADC ||
- Opc == X86ISD::SBB || Opc == X86ISD::SMUL || Opc == X86ISD::UMUL ||
- Opc == X86ISD::OR || Opc == X86ISD::XOR || Opc == X86ISD::AND))
+ Opc == X86ISD::ADOX || Opc == X86ISD::SBB || Opc == X86ISD::SMUL ||
+ Opc == X86ISD::UMUL || Opc == X86ISD::OR || Opc == X86ISD::XOR ||
+ Opc == X86ISD::AND))
return true;
return false;
@@ -53534,6 +53535,12 @@ static SDValue combineAddOrSubToADCOrSBB(bool IsSub, const SDLoc &DL, EVT VT,
DAG.getVTList(VT, MVT::i32), X,
DAG.getConstant(0, DL, VT), EFLAGS);
}
+ if (!IsSub && CC == X86::COND_O && (VT == MVT::i32 || VT == MVT::i64) &&
+ DAG.getSubtarget<X86Subtarget>().hasADX()) {
+ // X + (overflow_from_OF ? 1 : 0) --> adox X, 0
+ return DAG.getNode(X86ISD::ADOX, DL, DAG.getVTList(VT, MVT::i32), X,
+ DAG.getConstant(0, DL, VT), EFLAGS);
+ }
if (ZeroSecondOpOnly)
return SDValue();
@@ -59769,6 +59776,30 @@ static SDValue combineADC(SDNode *N, SelectionDAG &DAG,
return SDValue();
}
+// Optimize RES, EFLAGS = X86ISD::ADOX LHS, RHS, EFLAGS
+static SDValue combineADOX(SDNode *N, SelectionDAG &DAG) {
+ SDValue LHS = N->getOperand(0);
+ SDValue RHS = N->getOperand(1);
+ SDValue CarryIn = N->getOperand(2);
+ auto *LHSC = dyn_cast<ConstantSDNode>(LHS);
+ auto *RHSC = dyn_cast<ConstantSDNode>(RHS);
+
+ // Canonicalize constant to RHS.
+ if (LHSC && !RHSC)
+ return DAG.getNode(X86ISD::ADOX, SDLoc(N), N->getVTList(), RHS, LHS,
+ CarryIn);
+
+ // Fold ADOX(ADD(X,Y),0,Carry) -> ADOX(X,Y,Carry)
+ // ISD::ADD produces no EFLAGS, so we only need to ensure the ADOX's own
+ // flag output is not needed before replacing it with a 2-operand ADOX.
+ if (LHS.getOpcode() == ISD::ADD && RHSC && RHSC->isZero() &&
+ !needCarryOrOverflowFlag(SDValue(N, 1)))
+ return DAG.getNode(X86ISD::ADOX, SDLoc(N), N->getVTList(),
+ LHS.getOperand(0), LHS.getOperand(1), CarryIn);
+
+ return SDValue();
+}
+
static SDValue matchPMADDWD(SelectionDAG &DAG, SDNode *N,
const SDLoc &DL, EVT VT,
const X86Subtarget &Subtarget) {
@@ -63454,6 +63485,7 @@ SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
case X86ISD::CLOAD:
case X86ISD::CSTORE: return combineX86CloadCstore(N, DAG);
case X86ISD::SBB: return combineSBB(N, DAG);
+ case X86ISD::ADOX: return combineADOX(N, DAG);
case X86ISD::ADC: return combineADC(N, DAG, DCI);
case ISD::MUL: return combineMul(N, DAG, DCI, Subtarget);
case ISD::UDIV:
diff --git a/llvm/lib/Target/X86/X86InstrArithmetic.td b/llvm/lib/Target/X86/X86InstrArithmetic.td
index c91600525d1eb..ac368b988993a 100644
--- a/llvm/lib/Target/X86/X86InstrArithmetic.td
+++ b/llvm/lib/Target/X86/X86InstrArithmetic.td
@@ -1493,3 +1493,26 @@ let Form = MRMSrcMem in {
def ADOX64rm_ND : BinOpRMF_RF<0x66, "adox", Xi64, null_frag, 1>, XS;
}
}
+
+// ADOX patterns
+let Predicates = [HasADX, HasNDD] in {
+ def : Pat<(X86adox_flag GR32:$src1, GR32:$src2, EFLAGS),
+ (ADOX32rr_ND GR32:$src1, GR32:$src2)>;
+ def : Pat<(X86adox_flag GR64:$src1, GR64:$src2, EFLAGS),
+ (ADOX64rr_ND GR64:$src1, GR64:$src2)>;
+ def : Pat<(X86adox_flag GR32:$src1, (loadi32 addr:$src2), EFLAGS),
+ (ADOX32rm_ND GR32:$src1, addr:$src2)>;
+ def : Pat<(X86adox_flag GR64:$src1, (loadi64 addr:$src2), EFLAGS),
+ (ADOX64rm_ND GR64:$src1, addr:$src2)>;
+}
+
+let Predicates = [HasADX] in {
+ def : Pat<(X86adox_flag GR32:$src1, GR32:$src2, EFLAGS),
+ (ADOX32rr GR32:$src1, GR32:$src2)>;
+ def : Pat<(X86adox_flag GR64:$src1, GR64:$src2, EFLAGS),
+ (ADOX64rr GR64:$src1, GR64:$src2)>;
+ def : Pat<(X86adox_flag GR32:$src1, (loadi32 addr:$src2), EFLAGS),
+ (ADOX32rm GR32:$src1, addr:$src2)>;
+ def : Pat<(X86adox_flag GR64:$src1, (loadi64 addr:$src2), EFLAGS),
+ (ADOX64rm GR64:$src1, addr:$src2)>;
+}
diff --git a/llvm/lib/Target/X86/X86InstrFragments.td b/llvm/lib/Target/X86/X86InstrFragments.td
index c183849d4f575..9e6048b93cb00 100644
--- a/llvm/lib/Target/X86/X86InstrFragments.td
+++ b/llvm/lib/Target/X86/X86InstrFragments.td
@@ -390,6 +390,7 @@ def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags,
def X86umul_flag : SDNode<"X86ISD::UMUL", SDTBinaryArithWithFlags,
[SDNPCommutative]>;
def X86adc_flag : SDNode<"X86ISD::ADC", SDTBinaryArithWithFlagsInOut>;
+def X86adox_flag : SDNode<"X86ISD::ADOX", SDTBinaryArithWithFlagsInOut>;
def X86sbb_flag : SDNode<"X86ISD::SBB", SDTBinaryArithWithFlagsInOut>;
def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags,
diff --git a/llvm/lib/Target/X86/X86InstrPredicates.td b/llvm/lib/Target/X86/X86InstrPredicates.td
index fd03fa24a18c8..5c104d6c44101 100644
--- a/llvm/lib/Target/X86/X86InstrPredicates.td
+++ b/llvm/lib/Target/X86/X86InstrPredicates.td
@@ -269,3 +269,5 @@ def NotUseIndirectThunkCalls : Predicate<"!Subtarget->useIndirectThunkCalls()">;
defvar X86_32 = DefaultMode;
def X86_64 : HwMode<[In64BitMode, NotX32Mode]>;
def X86_64_X32 : HwMode<[IsX32Mode]>;
+def HasADX : Predicate<"Subtarget->hasADX()">;
+
diff --git a/llvm/test/CodeGen/X86/adox.ll b/llvm/test/CodeGen/X86/adox.ll
index f0e0b0b2717bb..f4b198f37854c 100644
--- a/llvm/test/CodeGen/X86/adox.ll
+++ b/llvm/test/CodeGen/X86/adox.ll
@@ -1,18 +1,32 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+adx,+ndd | FileCheck %s --check-prefixes=CHECK,NDD
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+adx | FileCheck %s --check-prefixes=CHECK,ADX
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=-adx | FileCheck %s --check-prefixes=CHECK,NOADX
define i32 @adox_test_i32(i32 %a, i32 %b, i8 %c, i8 %d) {
-; CHECK-LABEL: adox_test_i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: # kill: def $esi killed $esi def $rsi
-; CHECK-NEXT: # kill: def $edi killed $edi def $rdi
-; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: cmpb %cl, %dl
-; CHECK-NEXT: seto %al
-; CHECK-NEXT: addl %edi, %eax
-; CHECK-NEXT: addl %esi, %eax
-; CHECK-NEXT: retq
+; NDD-LABEL: adox_test_i32:
+; NDD: # %bb.0:
+; NDD-NEXT: cmpb %cl, %dl
+; NDD-NEXT: adoxl %esi, %edi, %eax
+; NDD-NEXT: retq
+;
+; ADX-LABEL: adox_test_i32:
+; ADX: # %bb.0:
+; ADX-NEXT: movl %edi, %eax
+; ADX-NEXT: cmpb %cl, %dl
+; ADX-NEXT: adoxl %esi, %eax
+; ADX-NEXT: retq
+;
+; NOADX-LABEL: adox_test_i32:
+; NOADX: # %bb.0:
+; NOADX-NEXT: # kill: def $esi killed $esi def $rsi
+; NOADX-NEXT: # kill: def $edi killed $edi def $rdi
+; NOADX-NEXT: xorl %eax, %eax
+; NOADX-NEXT: cmpb %cl, %dl
+; NOADX-NEXT: seto %al
+; NOADX-NEXT: addl %edi, %eax
+; NOADX-NEXT: addl %esi, %eax
+; NOADX-NEXT: retq
%ssub = call { i8, i1 } @llvm.ssub.with.overflow.i8(i8 %c, i8 %d)
%ov = extractvalue { i8, i1 } %ssub, 1
%ov.ext = zext i1 %ov to i32
@@ -22,14 +36,27 @@ define i32 @adox_test_i32(i32 %a, i32 %b, i8 %c, i8 %d) {
}
define i64 @adox_test_i64(i64 %a, i64 %b, i8 %c, i8 %d) {
-; CHECK-LABEL: adox_test_i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: cmpb %cl, %dl
-; CHECK-NEXT: seto %al
-; CHECK-NEXT: addq %rdi, %rax
-; CHECK-NEXT: addq %rsi, %rax
-; CHECK-NEXT: retq
+; NDD-LABEL: adox_test_i64:
+; NDD: # %bb.0:
+; NDD-NEXT: cmpb %cl, %dl
+; NDD-NEXT: adoxq %rsi, %rdi, %rax
+; NDD-NEXT: retq
+;
+; ADX-LABEL: adox_test_i64:
+; ADX: # %bb.0:
+; ADX-NEXT: movq %rdi, %rax
+; ADX-NEXT: cmpb %cl, %dl
+; ADX-NEXT: adoxq %rsi, %rax
+; ADX-NEXT: retq
+;
+; NOADX-LABEL: adox_test_i64:
+; NOADX: # %bb.0:
+; NOADX-NEXT: xorl %eax, %eax
+; NOADX-NEXT: cmpb %cl, %dl
+; NOADX-NEXT: seto %al
+; NOADX-NEXT: addq %rdi, %rax
+; NOADX-NEXT: addq %rsi, %rax
+; NOADX-NEXT: retq
%ssub = call { i8, i1 } @llvm.ssub.with.overflow.i8(i8 %c, i8 %d)
%ov = extractvalue { i8, i1 } %ssub, 1
%ov.ext = zext i1 %ov to i64
@@ -41,14 +68,27 @@ define i64 @adox_test_i64(i64 %a, i64 %b, i8 %c, i8 %d) {
declare { i8, i1 } @llvm.ssub.with.overflow.i8(i8, i8)
define i32 @adox_test_i32_mem(i32 %a, ptr %b_ptr, i8 %c, i8 %d) {
-; CHECK-LABEL: adox_test_i32_mem:
-; CHECK: # %bb.0:
-; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: cmpb %cl, %dl
-; CHECK-NEXT: seto %al
-; CHECK-NEXT: addl (%rsi), %edi
-; CHECK-NEXT: addl %edi, %eax
-; CHECK-NEXT: retq
+; NDD-LABEL: adox_test_i32_mem:
+; NDD: # %bb.0:
+; NDD-NEXT: cmpb %cl, %dl
+; NDD-NEXT: adoxl (%rsi), %edi, %eax
+; NDD-NEXT: retq
+;
+; ADX-LABEL: adox_test_i32_mem:
+; ADX: # %bb.0:
+; ADX-NEXT: movl %edi, %eax
+; ADX-NEXT: cmpb %cl, %dl
+; ADX-NEXT: adoxl (%rsi), %eax
+; ADX-NEXT: retq
+;
+; NOADX-LABEL: adox_test_i32_mem:
+; NOADX: # %bb.0:
+; NOADX-NEXT: xorl %eax, %eax
+; NOADX-NEXT: cmpb %cl, %dl
+; NOADX-NEXT: seto %al
+; NOADX-NEXT: addl (%rsi), %edi
+; NOADX-NEXT: addl %edi, %eax
+; NOADX-NEXT: retq
%b = load i32, ptr %b_ptr
%ssub = call { i8, i1 } @llvm.ssub.with.overflow.i8(i8 %c, i8 %d)
%ov = extractvalue { i8, i1 } %ssub, 1
@@ -59,14 +99,27 @@ define i32 @adox_test_i32_mem(i32 %a, ptr %b_ptr, i8 %c, i8 %d) {
}
define i64 @adox_test_i64_mem(i64 %a, ptr %b_ptr, i8 %c, i8 %d) {
-; CHECK-LABEL: adox_test_i64_mem:
-; CHECK: # %bb.0:
-; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: cmpb %cl, %dl
-; CHECK-NEXT: seto %al
-; CHECK-NEXT: addq (%rsi), %rdi
-; CHECK-NEXT: addq %rdi, %rax
-; CHECK-NEXT: retq
+; NDD-LABEL: adox_test_i64_mem:
+; NDD: # %bb.0:
+; NDD-NEXT: cmpb %cl, %dl
+; NDD-NEXT: adoxq (%rsi), %rdi, %rax
+; NDD-NEXT: retq
+;
+; ADX-LABEL: adox_test_i64_mem:
+; ADX: # %bb.0:
+; ADX-NEXT: movq %rdi, %rax
+; ADX-NEXT: cmpb %cl, %dl
+; ADX-NEXT: adoxq (%rsi), %rax
+; ADX-NEXT: retq
+;
+; NOADX-LABEL: adox_test_i64_mem:
+; NOADX: # %bb.0:
+; NOADX-NEXT: xorl %eax, %eax
+; NOADX-NEXT: cmpb %cl, %dl
+; NOADX-NEXT: seto %al
+; NOADX-NEXT: addq (%rsi), %rdi
+; NOADX-NEXT: addq %rdi, %rax
+; NOADX-NEXT: retq
%b = load i64, ptr %b_ptr
%ssub = call { i8, i1 } @llvm.ssub.with.overflow.i8(i8 %c, i8 %d)
%ov = extractvalue { i8, i1 } %ssub, 1
@@ -77,16 +130,29 @@ define i64 @adox_test_i64_mem(i64 %a, ptr %b_ptr, i8 %c, i8 %d) {
}
define i32 @adox_test_sadd_i32(i32 %a, i32 %b, i8 %c, i8 %d) {
-; CHECK-LABEL: adox_test_sadd_i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: # kill: def $esi killed $esi def $rsi
-; CHECK-NEXT: # kill: def $edi killed $edi def $rdi
-; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: addb %cl, %dl
-; CHECK-NEXT: seto %al
-; CHECK-NEXT: addl %edi, %eax
-; CHECK-NEXT: addl %esi, %eax
-; CHECK-NEXT: retq
+; NDD-LABEL: adox_test_sadd_i32:
+; NDD: # %bb.0:
+; NDD-NEXT: addb %cl, %dl, %al
+; NDD-NEXT: adoxl %esi, %edi, %eax
+; NDD-NEXT: retq
+;
+; ADX-LABEL: adox_test_sadd_i32:
+; ADX: # %bb.0:
+; ADX-NEXT: movl %edi, %eax
+; ADX-NEXT: addb %cl, %dl
+; ADX-NEXT: adoxl %esi, %eax
+; ADX-NEXT: retq
+;
+; NOADX-LABEL: adox_test_sadd_i32:
+; NOADX: # %bb.0:
+; NOADX-NEXT: # kill: def $esi killed $esi def $rsi
+; NOADX-NEXT: # kill: def $edi killed $edi def $rdi
+; NOADX-NEXT: xorl %eax, %eax
+; NOADX-NEXT: addb %cl, %dl
+; NOADX-NEXT: seto %al
+; NOADX-NEXT: addl %edi, %eax
+; NOADX-NEXT: addl %esi, %eax
+; NOADX-NEXT: retq
%sadd = call { i8, i1 } @llvm.sadd.with.overflow.i8(i8 %c, i8 %d)
%ov = extractvalue { i8, i1 } %sadd, 1
%ov.ext = zext i1 %ov to i32
@@ -98,17 +164,34 @@ define i32 @adox_test_sadd_i32(i32 %a, i32 %b, i8 %c, i8 %d) {
declare { i8, i1 } @llvm.sadd.with.overflow.i8(i8, i8)
define i16 @adox_test_i16(i16 %a, i16 %b, i8 %c, i8 %d) {
-; CHECK-LABEL: adox_test_i16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: # kill: def $esi killed $esi def $rsi
-; CHECK-NEXT: # kill: def $edi killed $edi def $rdi
-; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: cmpb %cl, %dl
-; CHECK-NEXT: seto %al
-; CHECK-NEXT: addl %edi, %eax
-; CHECK-NEXT: addl %esi, %eax
-; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
-; CHECK-NEXT: retq
+; NDD-LABEL: adox_test_i16:
+; NDD: # %bb.0:
+; NDD-NEXT: xorl %eax, %eax
+; NDD-NEXT: cmpb %cl, %dl
+; NDD-NEXT: seto %al
+; NDD-NEXT: addw %si, %di, %cx
+; NDD-NEXT: addw %cx, %ax
+; NDD-NEXT: retq
+;
+; ADX-LABEL: adox_test_i16:
+; ADX: # %bb.0:
+; ADX-NEXT: movl %edi, %eax
+; ADX-NEXT: cmpb %cl, %dl
+; ADX-NEXT: adoxl %esi, %eax
+; ADX-NEXT: # kill: def $ax killed $ax killed $eax
+; ADX-NEXT: retq
+;
+; NOADX-LABEL: adox_test_i16:
+; NOADX: # %bb.0:
+; NOADX-NEXT: # kill: def $esi killed $esi def $rsi
+; NOADX-NEXT: # kill: def $edi killed $edi def $rdi
+; NOADX-NEXT: xorl %eax, %eax
+; NOADX-NEXT: cmpb %cl, %dl
+; NOADX-NEXT: seto %al
+; NOADX-NEXT: addl %edi, %eax
+; NOADX-NEXT: addl %esi, %eax
+; NOADX-NEXT: # kill: def $ax killed $ax killed $eax
+; NOADX-NEXT: retq
%ssub = call { i8, i1 } @llvm.ssub.with.overflow.i8(i8 %c, i8 %d)
%ov = extractvalue { i8, i1 } %ssub, 1
%ov.ext = zext i1 %ov to i16
@@ -117,5 +200,4 @@ define i16 @adox_test_i16(i16 %a, i16 %b, i8 %c, i8 %d) {
ret i16 %res
}
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; ADX: {{.*}}
-; NOADX: {{.*}}
+; CHECK: {{.*}}
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