[llvm] X86: Emit adox instead of adc for overflow add (PR #216609)
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Sun Aug 16 15:18:33 PDT 2026
https://github.com/AZero13 created https://github.com/llvm/llvm-project/pull/216609
ADOX is like ADC but with OF and can only be encoded with a pair of 32 or 64 bit regs
>From b8b685f3684d9681b86064a6cdc87420c0a31953 Mon Sep 17 00:00:00 2001
From: AZero13 <gfunni234 at gmail.com>
Date: Sun, 16 Aug 2026 18:07:16 -0400
Subject: [PATCH 1/2] [X86] Precommit adox.ll test
---
llvm/test/CodeGen/X86/adox.ll | 40 +++++++++++++++++++++++++++++++++++
1 file changed, 40 insertions(+)
create mode 100644 llvm/test/CodeGen/X86/adox.ll
diff --git a/llvm/test/CodeGen/X86/adox.ll b/llvm/test/CodeGen/X86/adox.ll
new file mode 100644
index 0000000000000..ae5e4084a4e70
--- /dev/null
+++ b/llvm/test/CodeGen/X86/adox.ll
@@ -0,0 +1,40 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+adx | FileCheck %s
+
+define i32 @adox_test_i32(i32 %a, i32 %b, i8 %c, i8 %d) {
+; CHECK-LABEL: adox_test_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: # kill: def $esi killed $esi def $rsi
+; CHECK-NEXT: # kill: def $edi killed $edi def $rdi
+; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: cmpb %cl, %dl
+; CHECK-NEXT: seto %al
+; CHECK-NEXT: addl %edi, %eax
+; CHECK-NEXT: addl %esi, %eax
+; CHECK-NEXT: retq
+ %ssub = call { i8, i1 } @llvm.ssub.with.overflow.i8(i8 %c, i8 %d)
+ %ov = extractvalue { i8, i1 } %ssub, 1
+ %ov.ext = zext i1 %ov to i32
+ %sum = add i32 %a, %b
+ %res = add i32 %sum, %ov.ext
+ ret i32 %res
+}
+
+define i64 @adox_test_i64(i64 %a, i64 %b, i8 %c, i8 %d) {
+; CHECK-LABEL: adox_test_i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: cmpb %cl, %dl
+; CHECK-NEXT: seto %al
+; CHECK-NEXT: addq %rdi, %rax
+; CHECK-NEXT: addq %rsi, %rax
+; CHECK-NEXT: retq
+ %ssub = call { i8, i1 } @llvm.ssub.with.overflow.i8(i8 %c, i8 %d)
+ %ov = extractvalue { i8, i1 } %ssub, 1
+ %ov.ext = zext i1 %ov to i64
+ %sum = add i64 %a, %b
+ %res = add i64 %sum, %ov.ext
+ ret i64 %res
+}
+
+declare { i8, i1 } @llvm.ssub.with.overflow.i8(i8, i8)
>From ad1805ac031c8f84bd0c391b07d80a03af858690 Mon Sep 17 00:00:00 2001
From: AZero13 <gfunni234 at gmail.com>
Date: Sun, 16 Aug 2026 18:16:27 -0400
Subject: [PATCH 2/2] X86: Emit adox instead of adc for overflow add
---
llvm/lib/Target/X86/X86ISelLowering.cpp | 9 ++++++++-
llvm/lib/Target/X86/X86InstrArithmetic.td | 13 +++++++++++++
llvm/lib/Target/X86/X86InstrFragments.td | 1 +
llvm/lib/Target/X86/X86InstrPredicates.td | 1 +
llvm/test/CodeGen/X86/adox.ll | 14 ++++++--------
5 files changed, 29 insertions(+), 9 deletions(-)
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 0dc3340a13c73..69f6ff623c8e1 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -25338,7 +25338,7 @@ static bool isX86LogicalCmp(SDValue Op) {
return true;
if (Op.getResNo() == 1 &&
(Opc == X86ISD::ADD || Opc == X86ISD::SUB || Opc == X86ISD::ADC ||
- Opc == X86ISD::SBB || Opc == X86ISD::SMUL || Opc == X86ISD::UMUL ||
+ Opc == X86ISD::ADOX || Opc == X86ISD::SBB || Opc == X86ISD::SMUL || Opc == X86ISD::UMUL ||
Opc == X86ISD::OR || Opc == X86ISD::XOR || Opc == X86ISD::AND))
return true;
@@ -53534,6 +53534,13 @@ static SDValue combineAddOrSubToADCOrSBB(bool IsSub, const SDLoc &DL, EVT VT,
DAG.getVTList(VT, MVT::i32), X,
DAG.getConstant(0, DL, VT), EFLAGS);
}
+
+ if (!IsSub && CC == X86::COND_O && DAG.getSubtarget<X86Subtarget>().hasADX()) {
+ // X + SETO Z --> adox X, 0
+ return DAG.getNode(X86ISD::ADOX, DL,
+ DAG.getVTList(VT, MVT::i32), X,
+ DAG.getConstant(0, DL, VT), EFLAGS);
+ }
if (ZeroSecondOpOnly)
return SDValue();
diff --git a/llvm/lib/Target/X86/X86InstrArithmetic.td b/llvm/lib/Target/X86/X86InstrArithmetic.td
index c91600525d1eb..edb36b75c51a3 100644
--- a/llvm/lib/Target/X86/X86InstrArithmetic.td
+++ b/llvm/lib/Target/X86/X86InstrArithmetic.td
@@ -1493,3 +1493,16 @@ let Form = MRMSrcMem in {
def ADOX64rm_ND : BinOpRMF_RF<0x66, "adox", Xi64, null_frag, 1>, XS;
}
}
+
+
+// ADOX patterns
+let Predicates = [HasADX] in {
+ def : Pat<(X86adox_flag GR32:$src1, GR32:$src2, EFLAGS),
+ (ADOX32rr GR32:$src1, GR32:$src2)>;
+ def : Pat<(X86adox_flag GR64:$src1, GR64:$src2, EFLAGS),
+ (ADOX64rr GR64:$src1, GR64:$src2)>;
+ def : Pat<(X86adox_flag GR32:$src1, (loadi32 addr:$src2), EFLAGS),
+ (ADOX32rm GR32:$src1, addr:$src2)>;
+ def : Pat<(X86adox_flag GR64:$src1, (loadi64 addr:$src2), EFLAGS),
+ (ADOX64rm GR64:$src1, addr:$src2)>;
+}
diff --git a/llvm/lib/Target/X86/X86InstrFragments.td b/llvm/lib/Target/X86/X86InstrFragments.td
index c183849d4f575..9e6048b93cb00 100644
--- a/llvm/lib/Target/X86/X86InstrFragments.td
+++ b/llvm/lib/Target/X86/X86InstrFragments.td
@@ -390,6 +390,7 @@ def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags,
def X86umul_flag : SDNode<"X86ISD::UMUL", SDTBinaryArithWithFlags,
[SDNPCommutative]>;
def X86adc_flag : SDNode<"X86ISD::ADC", SDTBinaryArithWithFlagsInOut>;
+def X86adox_flag : SDNode<"X86ISD::ADOX", SDTBinaryArithWithFlagsInOut>;
def X86sbb_flag : SDNode<"X86ISD::SBB", SDTBinaryArithWithFlagsInOut>;
def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags,
diff --git a/llvm/lib/Target/X86/X86InstrPredicates.td b/llvm/lib/Target/X86/X86InstrPredicates.td
index fd03fa24a18c8..ccb382f35ec21 100644
--- a/llvm/lib/Target/X86/X86InstrPredicates.td
+++ b/llvm/lib/Target/X86/X86InstrPredicates.td
@@ -269,3 +269,4 @@ def NotUseIndirectThunkCalls : Predicate<"!Subtarget->useIndirectThunkCalls()">;
defvar X86_32 = DefaultMode;
def X86_64 : HwMode<[In64BitMode, NotX32Mode]>;
def X86_64_X32 : HwMode<[IsX32Mode]>;
+def HasADX : Predicate<"Subtarget->hasADX()">;
diff --git a/llvm/test/CodeGen/X86/adox.ll b/llvm/test/CodeGen/X86/adox.ll
index ae5e4084a4e70..03ef3ee39857f 100644
--- a/llvm/test/CodeGen/X86/adox.ll
+++ b/llvm/test/CodeGen/X86/adox.ll
@@ -6,11 +6,10 @@ define i32 @adox_test_i32(i32 %a, i32 %b, i8 %c, i8 %d) {
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $esi killed $esi def $rsi
; CHECK-NEXT: # kill: def $edi killed $edi def $rdi
-; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: leal (%rdi,%rsi), %eax
+; CHECK-NEXT: xorl %esi, %esi
; CHECK-NEXT: cmpb %cl, %dl
-; CHECK-NEXT: seto %al
-; CHECK-NEXT: addl %edi, %eax
-; CHECK-NEXT: addl %esi, %eax
+; CHECK-NEXT: adoxl %esi, %eax
; CHECK-NEXT: retq
%ssub = call { i8, i1 } @llvm.ssub.with.overflow.i8(i8 %c, i8 %d)
%ov = extractvalue { i8, i1 } %ssub, 1
@@ -23,11 +22,10 @@ define i32 @adox_test_i32(i32 %a, i32 %b, i8 %c, i8 %d) {
define i64 @adox_test_i64(i64 %a, i64 %b, i8 %c, i8 %d) {
; CHECK-LABEL: adox_test_i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: leaq (%rdi,%rsi), %rax
+; CHECK-NEXT: xorl %esi, %esi
; CHECK-NEXT: cmpb %cl, %dl
-; CHECK-NEXT: seto %al
-; CHECK-NEXT: addq %rdi, %rax
-; CHECK-NEXT: addq %rsi, %rax
+; CHECK-NEXT: adoxq %rsi, %rax
; CHECK-NEXT: retq
%ssub = call { i8, i1 } @llvm.ssub.with.overflow.i8(i8 %c, i8 %d)
%ov = extractvalue { i8, i1 } %ssub, 1
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