[llvm] [X86] Lower scalar integer div/rem to FP division (PR #216589)

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``````````diff
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 1f10178fa..4432db86b 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -50720,7 +50720,6 @@ static SDValue combineIntDivRem(SDNode *N, SelectionDAG &DAG,
   EVT VT = N->getValueType(0);
   SDLoc DL(N);
 
-  
   if (!Subtarget.hasSSE2())
     return SDValue();
 
@@ -50736,16 +50735,14 @@ static SDValue combineIntDivRem(SDNode *N, SelectionDAG &DAG,
   bool IsSigned = Opc == ISD::SDIV || Opc == ISD::SREM;
 
   // Scalar functions that do not use XMM registers must not get this combine.
-  if (!VT.isVector() &&
-      (Subtarget.useSoftFloat() ||
-       DAG.getMachineFunction().getFunction().hasFnAttribute(
-           Attribute::NoImplicitFloat)))
+  if (!VT.isVector() && (Subtarget.useSoftFloat() ||
+                         DAG.getMachineFunction().getFunction().hasFnAttribute(
+                             Attribute::NoImplicitFloat)))
     return SDValue();
 
   // If the result is only read back as scalar extracts, scalarization computes
   // just the demanded lanes.
-  if (VT.isVector() &&
-      all_of(N->users(), [](const SDNode *U) {
+  if (VT.isVector() && all_of(N->users(), [](const SDNode *U) {
         return U->getOpcode() == ISD::EXTRACT_VECTOR_ELT;
       }))
     return SDValue();
@@ -50795,11 +50792,11 @@ static SDValue combineIntDivRem(SDNode *N, SelectionDAG &DAG,
 
   // Nothing will split an illegal FP type after type legalization and the
   // strict SAE divide is 512-bit only. Scalar f32/f64 are always legal.
-  bool FPVTUsable = !VT.isVector() ||
-                     (IsStrict
-                          ? FPVT.getSizeInBits() <= 512
-                          : DCI.isBeforeLegalize() ||
-                                DAG.getTargetLoweringInfo().isTypeLegal(FPVT));
+  bool FPVTUsable =
+      !VT.isVector() ||
+      (IsStrict ? FPVT.getSizeInBits() <= 512
+                : DCI.isBeforeLegalize() ||
+                      DAG.getTargetLoweringInfo().isTypeLegal(FPVT));
 
   // Halve the divide while the integer halves stay legal.
   if (!FPVTUsable) {

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https://github.com/llvm/llvm-project/pull/216589