[llvm] [IR] Implementation and lowering of bitinsert and bitextract (PR #200605)
Alexis Engelke via llvm-commits
llvm-commits at lists.llvm.org
Sun Aug 16 07:13:03 PDT 2026
================
@@ -0,0 +1,528 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=aarch64 < %s | FileCheck %s --check-prefix=AARCH64
+
+define half @test_bitextract_half_full(b16 %src) {
+; AARCH64-LABEL: test_bitextract_half_full:
+; AARCH64: // %bb.0:
+; AARCH64-NEXT: fmov s0, w0
+; AARCH64-NEXT: // kill: def $h0 killed $h0 killed $q0
+; AARCH64-NEXT: ret
+ %result = bitextract half, b16 %src, i32 0
+ ret half %result
+}
+
+define half @test_bitextract_half_const(b32 %src) {
+; AARCH64-LABEL: test_bitextract_half_const:
+; AARCH64: // %bb.0:
+; AARCH64-NEXT: lsr w8, w0, #8
+; AARCH64-NEXT: fmov s0, w8
+; AARCH64-NEXT: // kill: def $h0 killed $h0 killed $q0
+; AARCH64-NEXT: ret
+ %result = bitextract half, b32 %src, i32 8
+ ret half %result
+}
+
+define half @test_bitextract_half_var(b32 %src, i32 %off) {
+; AARCH64-LABEL: test_bitextract_half_var:
+; AARCH64: // %bb.0:
+; AARCH64-NEXT: lsr w8, w0, w1
+; AARCH64-NEXT: fmov s0, w8
+; AARCH64-NEXT: // kill: def $h0 killed $h0 killed $q0
+; AARCH64-NEXT: ret
+ %result = bitextract half, b32 %src, i32 %off
+ ret half %result
+}
+
+define float @test_bitextract_float_full(b32 %src) {
+; AARCH64-LABEL: test_bitextract_float_full:
+; AARCH64: // %bb.0:
+; AARCH64-NEXT: fmov s0, w0
+; AARCH64-NEXT: ret
+ %result = bitextract float, b32 %src, i32 0
+ ret float %result
+}
+
+define float @test_bitextract_float_const(b64 %src) {
+; AARCH64-LABEL: test_bitextract_float_const:
+; AARCH64: // %bb.0:
+; AARCH64-NEXT: lsr x8, x0, #32
+; AARCH64-NEXT: fmov s0, w8
+; AARCH64-NEXT: ret
+ %result = bitextract float, b64 %src, i32 32
+ ret float %result
+}
+
+define float @test_bitextract_float_var(b64 %src, i32 %off) {
+; AARCH64-LABEL: test_bitextract_float_var:
+; AARCH64: // %bb.0:
+; AARCH64-NEXT: // kill: def $w1 killed $w1 def $x1
+; AARCH64-NEXT: lsr x8, x0, x1
+; AARCH64-NEXT: fmov s0, w8
+; AARCH64-NEXT: ret
+ %result = bitextract float, b64 %src, i32 %off
+ ret float %result
+}
+
+define float @test_bitextract_float_b87_var(b87 %src, i32 %off) {
+; AARCH64-LABEL: test_bitextract_float_b87_var:
+; AARCH64: // %bb.0:
+; AARCH64-NEXT: and x8, x1, #0x7fffff
+; AARCH64-NEXT: mov w10, w2
+; AARCH64-NEXT: mvn w11, w2
+; AARCH64-NEXT: lsl x9, x8, #1
+; AARCH64-NEXT: lsr x12, x0, x10
+; AARCH64-NEXT: lsr x8, x8, x10
+; AARCH64-NEXT: tst x10, #0x40
+; AARCH64-NEXT: lsl x9, x9, x11
+; AARCH64-NEXT: orr x9, x9, x12
+; AARCH64-NEXT: csel x8, x8, x9, ne
+; AARCH64-NEXT: fmov s0, w8
+; AARCH64-NEXT: ret
+ %result = bitextract float, b87 %src, i32 %off
+ ret float %result
+}
+
+define float @test_bitextract_float_b87_crossword(b87 %src) {
+; AARCH64-LABEL: test_bitextract_float_b87_crossword:
+; AARCH64: // %bb.0:
+; AARCH64-NEXT: lsr x8, x0, #60
+; AARCH64-NEXT: bfi w8, w1, #4, #23
+; AARCH64-NEXT: fmov s0, w8
+; AARCH64-NEXT: ret
+ %result = bitextract float, b87 %src, i32 60
+ ret float %result
+}
+
+define double @test_bitextract_double_full(b64 %src) {
+; AARCH64-LABEL: test_bitextract_double_full:
+; AARCH64: // %bb.0:
+; AARCH64-NEXT: fmov d0, x0
+; AARCH64-NEXT: ret
+ %result = bitextract double, b64 %src, i32 0
+ ret double %result
+}
+
+define double @test_bitextract_double_const(b128 %src) {
+; AARCH64-LABEL: test_bitextract_double_const:
+; AARCH64: // %bb.0:
+; AARCH64-NEXT: fmov d0, x1
+; AARCH64-NEXT: ret
+ %result = bitextract double, b128 %src, i32 64
+ ret double %result
+}
+
+define double @test_bitextract_double_var(b128 %src, i32 %off) {
+; AARCH64-LABEL: test_bitextract_double_var:
+; AARCH64: // %bb.0:
+; AARCH64-NEXT: lsl x8, x1, #1
+; AARCH64-NEXT: mov w9, w2
+; AARCH64-NEXT: mvn w10, w2
+; AARCH64-NEXT: lsr x11, x0, x9
+; AARCH64-NEXT: tst x9, #0x40
+; AARCH64-NEXT: lsl x8, x8, x10
+; AARCH64-NEXT: lsr x10, x1, x9
+; AARCH64-NEXT: orr x8, x8, x11
+; AARCH64-NEXT: csel x8, x10, x8, ne
+; AARCH64-NEXT: fmov d0, x8
+; AARCH64-NEXT: ret
+ %result = bitextract double, b128 %src, i32 %off
+ ret double %result
+}
+
+define double @test_bitextract_double_b231_var(b231 %src, i32 %off) {
+; AARCH64-LABEL: test_bitextract_double_b231_var:
+; AARCH64: // %bb.0:
+; AARCH64-NEXT: stp x0, x1, [sp, #-64]!
+; AARCH64-NEXT: .cfi_def_cfa_offset 64
+; AARCH64-NEXT: movi v0.2d, #0000000000000000
+; AARCH64-NEXT: mov w8, w4
+; AARCH64-NEXT: and x10, x3, #0x7fffffffff
+; AARCH64-NEXT: lsr x9, x8, #3
+; AARCH64-NEXT: mov x11, sp
+; AARCH64-NEXT: stp x2, x10, [sp, #16]
+; AARCH64-NEXT: and x9, x9, #0x18
+; AARCH64-NEXT: stp q0, q0, [sp, #32]
+; AARCH64-NEXT: add x9, x11, x9
+; AARCH64-NEXT: mvn w11, w4
+; AARCH64-NEXT: ldp x9, x10, [x9]
+; AARCH64-NEXT: lsl x10, x10, #1
+; AARCH64-NEXT: lsr x8, x9, x8
+; AARCH64-NEXT: lsl x10, x10, x11
+; AARCH64-NEXT: orr x8, x10, x8
+; AARCH64-NEXT: fmov d0, x8
+; AARCH64-NEXT: add sp, sp, #64
+; AARCH64-NEXT: ret
+ %result = bitextract double, b231 %src, i32 %off
+ ret double %result
+}
+
+define double @test_bitextract_double_b231_crossword(b231 %src) {
+; AARCH64-LABEL: test_bitextract_double_b231_crossword:
+; AARCH64: // %bb.0:
+; AARCH64-NEXT: and x8, x3, #0x7fffffffff
+; AARCH64-NEXT: extr x8, x8, x2, #62
+; AARCH64-NEXT: fmov d0, x8
+; AARCH64-NEXT: ret
+ %result = bitextract double, b231 %src, i32 190
+ ret double %result
+}
+
+define b16 @test_bitinsert_half_full(b16 %base, half %val) {
+; AARCH64-LABEL: test_bitinsert_half_full:
+; AARCH64: // %bb.0:
+; AARCH64-NEXT: // kill: def $h0 killed $h0 def $s0
+; AARCH64-NEXT: fmov w0, s0
+; AARCH64-NEXT: ret
+ %result = bitinsert b16 %base, half %val, i32 0
+ ret b16 %result
+}
+
+define b32 @test_bitinsert_half_const(b32 %base, half %val) {
+; AARCH64-LABEL: test_bitinsert_half_const:
+; AARCH64: // %bb.0:
+; AARCH64-NEXT: // kill: def $h0 killed $h0 def $s0
+; AARCH64-NEXT: fmov w9, s0
+; AARCH64-NEXT: ror w8, w0, #8
+; AARCH64-NEXT: bfxil w8, w9, #0, #16
+; AARCH64-NEXT: ror w0, w8, #24
+; AARCH64-NEXT: ret
+ %result = bitinsert b32 %base, half %val, i32 8
+ ret b32 %result
+}
+
+define b32 @test_bitinsert_half_var(b32 %base, half %val, i32 %off) {
+; AARCH64-LABEL: test_bitinsert_half_var:
+; AARCH64: // %bb.0:
+; AARCH64-NEXT: // kill: def $h0 killed $h0 def $s0
+; AARCH64-NEXT: fmov w9, s0
+; AARCH64-NEXT: ror w8, w0, w1
+; AARCH64-NEXT: bfxil w8, w9, #0, #16
+; AARCH64-NEXT: neg w9, w1
+; AARCH64-NEXT: ror w0, w8, w9
+; AARCH64-NEXT: ret
+ %result = bitinsert b32 %base, half %val, i32 %off
+ ret b32 %result
+}
+
+define b32 @test_bitinsert_float_full(b32 %base, float %val) {
+; AARCH64-LABEL: test_bitinsert_float_full:
+; AARCH64: // %bb.0:
+; AARCH64-NEXT: fmov w0, s0
+; AARCH64-NEXT: ret
+ %result = bitinsert b32 %base, float %val, i32 0
+ ret b32 %result
+}
+
+define b64 @test_bitinsert_float_const(b64 %base, float %val) {
+; AARCH64-LABEL: test_bitinsert_float_const:
+; AARCH64: // %bb.0:
+; AARCH64-NEXT: fmov w8, s0
+; AARCH64-NEXT: orr x8, x8, x0, lsl #32
+; AARCH64-NEXT: ror x0, x8, #32
+; AARCH64-NEXT: ret
+ %result = bitinsert b64 %base, float %val, i32 32
+ ret b64 %result
+}
+
+define b64 @test_bitinsert_float_var(b64 %base, float %val, i32 %off) {
+; AARCH64-LABEL: test_bitinsert_float_var:
+; AARCH64: // %bb.0:
+; AARCH64-NEXT: // kill: def $w1 killed $w1 def $x1
+; AARCH64-NEXT: fmov w8, s0
+; AARCH64-NEXT: ror x9, x0, x1
+; AARCH64-NEXT: neg w10, w1
+; AARCH64-NEXT: and x9, x9, #0xffffffff00000000
+; AARCH64-NEXT: orr x8, x9, x8
+; AARCH64-NEXT: ror x0, x8, x10
+; AARCH64-NEXT: ret
+ %result = bitinsert b64 %base, float %val, i32 %off
+ ret b64 %result
+}
+
+define b87 @test_bitinsert_float_b87_var(b87 %base, float %val, i32 %off) {
+; AARCH64-LABEL: test_bitinsert_float_b87_var:
+; AARCH64: // %bb.0:
+; AARCH64-NEXT: mov x8, #39171 // =0x9903
+; AARCH64-NEXT: mov w9, w2
+; AARCH64-NEXT: mov w10, #87 // =0x57
+; AARCH64-NEXT: movk x8, #12052, lsl #16
+; AARCH64-NEXT: extr x12, x1, x0, #63
+; AARCH64-NEXT: ubfx x13, x0, #0, #63
+; AARCH64-NEXT: movk x8, #18832, lsl #32
+; AARCH64-NEXT: lsl x11, x0, #1
+; AARCH64-NEXT: movk x8, #753, lsl #48
+; AARCH64-NEXT: umulh x8, x9, x8
+; AARCH64-NEXT: umsubl x8, w8, w10, x9
+; AARCH64-NEXT: and x10, x1, #0x7fffff
+; AARCH64-NEXT: mov w9, #86 // =0x56
+; AARCH64-NEXT: lsl x14, x10, #1
+; AARCH64-NEXT: mvn w15, w8
+; AARCH64-NEXT: sub x9, x9, x8
+; AARCH64-NEXT: lsr x16, x0, x8
+; AARCH64-NEXT: lsl x14, x14, x15
+; AARCH64-NEXT: mvn w17, w9
+; AARCH64-NEXT: lsr x10, x10, x8
+; AARCH64-NEXT: lsl x12, x12, x9
+; AARCH64-NEXT: lsr x13, x13, x17
+; AARCH64-NEXT: tst x8, #0x40
+; AARCH64-NEXT: lsl x11, x11, x9
+; AARCH64-NEXT: orr x14, x14, x16
+; AARCH64-NEXT: csel x16, xzr, x10, ne
+; AARCH64-NEXT: csel x10, x10, x14, ne
+; AARCH64-NEXT: tst x9, #0x40
+; AARCH64-NEXT: orr x12, x12, x13
+; AARCH64-NEXT: fmov w13, s0
+; AARCH64-NEXT: csel x14, xzr, x11, ne
+; AARCH64-NEXT: csel x11, x11, x12, ne
+; AARCH64-NEXT: orr x10, x10, x14
+; AARCH64-NEXT: orr w11, w16, w11
+; AARCH64-NEXT: and x10, x10, #0xffffffff00000000
+; AARCH64-NEXT: ubfx x12, x11, #1, #22
+; AARCH64-NEXT: orr x10, x10, x13
+; AARCH64-NEXT: extr x13, x11, x10, #1
+; AARCH64-NEXT: lsl x14, x12, #1
+; AARCH64-NEXT: lsr x16, x10, #1
+; AARCH64-NEXT: and x11, x11, #0x7fffff
+; AARCH64-NEXT: lsl x10, x10, x8
+; AARCH64-NEXT: lsr x13, x13, x9
+; AARCH64-NEXT: lsl x14, x14, x17
+; AARCH64-NEXT: lsr x9, x12, x9
+; AARCH64-NEXT: lsl x11, x11, x8
+; AARCH64-NEXT: lsr x12, x16, x15
+; AARCH64-NEXT: orr x13, x14, x13
+; AARCH64-NEXT: csel x13, x9, x13, ne
+; AARCH64-NEXT: csel x9, xzr, x9, ne
+; AARCH64-NEXT: tst x8, #0x40
+; AARCH64-NEXT: orr x8, x11, x12
+; AARCH64-NEXT: csel x8, x10, x8, ne
+; AARCH64-NEXT: csel x10, xzr, x10, ne
+; AARCH64-NEXT: orr x0, x10, x13
+; AARCH64-NEXT: orr x1, x8, x9
+; AARCH64-NEXT: ret
+ %result = bitinsert b87 %base, float %val, i32 %off
+ ret b87 %result
+}
+
+define b87 @test_bitinsert_float_b87_crossword(b87 %base, float %val) {
+; AARCH64-LABEL: test_bitinsert_float_b87_crossword:
+; AARCH64: // %bb.0:
+; AARCH64-NEXT: fmov w8, s0
+; AARCH64-NEXT: lsr x9, x0, #5
+; AARCH64-NEXT: lsr x11, x0, #37
+; AARCH64-NEXT: mov x10, x8
+; AARCH64-NEXT: bfi x10, x9, #32, #32
+; AARCH64-NEXT: ubfx w9, w11, #1, #22
+; AARCH64-NEXT: extr x12, x11, x10, #1
+; AARCH64-NEXT: extr x1, x11, x10, #4
+; AARCH64-NEXT: extr x9, x9, x12, #26
+; AARCH64-NEXT: orr x0, x9, x8, lsl #60
+; AARCH64-NEXT: ret
+ %result = bitinsert b87 %base, float %val, i32 60
+ ret b87 %result
+}
+
+define b64 @test_bitinsert_double_full(b64 %base, double %val) {
+; AARCH64-LABEL: test_bitinsert_double_full:
+; AARCH64: // %bb.0:
+; AARCH64-NEXT: fmov x0, d0
+; AARCH64-NEXT: ret
+ %result = bitinsert b64 %base, double %val, i32 0
+ ret b64 %result
+}
+
+define b128 @test_bitinsert_double_const(b128 %base, double %val) {
+; AARCH64-LABEL: test_bitinsert_double_const:
+; AARCH64: // %bb.0:
+; AARCH64-NEXT: fmov x1, d0
+; AARCH64-NEXT: ret
+ %result = bitinsert b128 %base, double %val, i32 64
+ ret b128 %result
+}
+
+define b128 @test_bitinsert_double_var(b128 %base, double %val, i32 %off) {
+; AARCH64-LABEL: test_bitinsert_double_var:
+; AARCH64: // %bb.0:
+; AARCH64-NEXT: mov w8, w2
+; AARCH64-NEXT: mvn w11, w2
+; AARCH64-NEXT: fmov x12, d0
+; AARCH64-NEXT: tst x8, #0x40
+; AARCH64-NEXT: csel x9, x0, x1, eq
+; AARCH64-NEXT: csel x10, x1, x0, eq
+; AARCH64-NEXT: lsl x9, x9, #1
+; AARCH64-NEXT: lsr x10, x10, x8
+; AARCH64-NEXT: lsl x9, x9, x11
+; AARCH64-NEXT: orr x9, x9, x10
+; AARCH64-NEXT: csel x10, x9, x12, ne
+; AARCH64-NEXT: csel x9, x12, x9, ne
+; AARCH64-NEXT: lsr x12, x9, #1
+; AARCH64-NEXT: lsr x13, x10, #1
+; AARCH64-NEXT: lsl x10, x10, x8
+; AARCH64-NEXT: lsl x8, x9, x8
+; AARCH64-NEXT: lsr x12, x12, x11
+; AARCH64-NEXT: lsr x9, x13, x11
+; AARCH64-NEXT: orr x0, x10, x12
+; AARCH64-NEXT: orr x1, x8, x9
+; AARCH64-NEXT: ret
+ %result = bitinsert b128 %base, double %val, i32 %off
+ ret b128 %result
+}
+
+define b231 @test_bitinsert_double_b231_var(b231 %base, double %val, i32 %off) {
+; AARCH64-LABEL: test_bitinsert_double_b231_var:
+; AARCH64: // %bb.0:
+; AARCH64-NEXT: sub sp, sp, #272
+; AARCH64-NEXT: str x29, [sp, #256] // 8-byte Spill
+; AARCH64-NEXT: .cfi_def_cfa_offset 272
+; AARCH64-NEXT: .cfi_offset w29, -16
+; AARCH64-NEXT: mov x8, #53905 // =0xd291
+; AARCH64-NEXT: mov w11, w4
+; AARCH64-NEXT: extr x9, x3, x2, #63
+; AARCH64-NEXT: movk x8, #1134, lsl #16
+; AARCH64-NEXT: extr x10, x2, x1, #63
+; AARCH64-NEXT: extr x12, x1, x0, #63
+; AARCH64-NEXT: movk x8, #46244, lsl #32
+; AARCH64-NEXT: movi v1.2d, #0000000000000000
+; AARCH64-NEXT: stp x1, x2, [sp, #200]
+; AARCH64-NEXT: movk x8, #283, lsl #48
+; AARCH64-NEXT: stp x10, x9, [sp, #176]
+; AARCH64-NEXT: lsl x9, x0, #1
+; AARCH64-NEXT: umulh x8, x11, x8
+; AARCH64-NEXT: and x10, x3, #0x7fffffffff
+; AARCH64-NEXT: str x0, [sp, #192]
+; AARCH64-NEXT: stp x9, x12, [sp, #160]
+; AARCH64-NEXT: mov w9, #231 // =0xe7
+; AARCH64-NEXT: add x14, sp, #192
+; AARCH64-NEXT: str x10, [sp, #216]
+; AARCH64-NEXT: ldr x29, [sp, #256] // 8-byte Reload
+; AARCH64-NEXT: stp q1, q1, [sp, #96]
+; AARCH64-NEXT: stp q1, q1, [sp, #128]
+; AARCH64-NEXT: umsubl x8, w8, w9, x11
+; AARCH64-NEXT: mov w9, #230 // =0xe6
+; AARCH64-NEXT: add x11, sp, #128
+; AARCH64-NEXT: add x11, x11, #32
+; AARCH64-NEXT: stp q1, q1, [sp, #224]
+; AARCH64-NEXT: sub x9, x9, x8
+; AARCH64-NEXT: lsr x10, x8, #3
+; AARCH64-NEXT: lsr x12, x9, #3
+; AARCH64-NEXT: and x13, x10, #0x18
+; AARCH64-NEXT: and x10, x9, #0x3f
+; AARCH64-NEXT: and x12, x12, #0x18
+; AARCH64-NEXT: add x17, x14, x13
+; AARCH64-NEXT: eor x10, x10, #0x3f
+; AARCH64-NEXT: sub x15, x11, x12
+; AARCH64-NEXT: ldr x14, [x17, #24]
+; AARCH64-NEXT: ldp x18, x11, [x15, #16]
+; AARCH64-NEXT: lsr x0, x14, x8
+; AARCH64-NEXT: lsl x1, x14, #1
+; AARCH64-NEXT: mvn w14, w9
+; AARCH64-NEXT: lsr x16, x18, #1
+; AARCH64-NEXT: lsl x11, x11, x9
+; AARCH64-NEXT: lsl x18, x18, x9
+; AARCH64-NEXT: lsr x16, x16, x10
+; AARCH64-NEXT: orr x11, x0, x11
+; AARCH64-NEXT: orr x16, x11, x16
+; AARCH64-NEXT: ubfx x11, x16, #1, #38
+; AARCH64-NEXT: str x11, [sp, #88]
+; AARCH64-NEXT: and x11, x8, #0x3f
+; AARCH64-NEXT: ldr x0, [x15, #8]
+; AARCH64-NEXT: ldr x2, [x17, #16]
+; AARCH64-NEXT: eor x11, x11, #0x3f
+; AARCH64-NEXT: lsl x1, x1, x11
+; AARCH64-NEXT: lsr x3, x0, #1
+; AARCH64-NEXT: lsr x4, x2, x8
+; AARCH64-NEXT: lsl x0, x0, x9
+; AARCH64-NEXT: lsr x3, x3, x14
+; AARCH64-NEXT: orr x1, x1, x4
+; AARCH64-NEXT: orr x18, x18, x3
+; AARCH64-NEXT: orr x18, x1, x18
+; AARCH64-NEXT: extr x1, x16, x18, #1
+; AARCH64-NEXT: and x16, x16, #0x7fffffffff
+; AARCH64-NEXT: str x1, [sp, #80]
+; AARCH64-NEXT: lsl x1, x2, #1
+; AARCH64-NEXT: ldr x15, [x15]
+; AARCH64-NEXT: ldr x17, [x17, #8]
+; AARCH64-NEXT: str d0, [sp, #32]
+; AARCH64-NEXT: stp q1, q1, [sp]
+; AARCH64-NEXT: lsr x2, x15, #1
+; AARCH64-NEXT: mvn w15, w8
+; AARCH64-NEXT: lsr x17, x17, x8
+; AARCH64-NEXT: lsl x1, x1, x15
+; AARCH64-NEXT: str x16, [sp, #56]
+; AARCH64-NEXT: lsr x2, x2, x10
+; AARCH64-NEXT: orr x17, x17, x1
+; AARCH64-NEXT: orr x0, x0, x2
+; AARCH64-NEXT: orr x17, x17, x0
+; AARCH64-NEXT: fmov x0, d0
+; AARCH64-NEXT: extr x1, x18, x17, #1
+; AARCH64-NEXT: stp x17, x18, [sp, #40]
+; AARCH64-NEXT: extr x0, x17, x0, #1
+; AARCH64-NEXT: stp x0, x1, [sp, #64]
+; AARCH64-NEXT: add x0, sp, #64
+; AARCH64-NEXT: mov x1, sp
+; AARCH64-NEXT: add x12, x0, x12
+; AARCH64-NEXT: add x18, x1, #32
+; AARCH64-NEXT: ldp x16, x0, [x12, #16]
+; AARCH64-NEXT: sub x13, x18, x13
+; AARCH64-NEXT: ldp x18, x17, [x13]
+; AARCH64-NEXT: ldp x12, x1, [x12]
+; AARCH64-NEXT: lsl x2, x16, #1
+; AARCH64-NEXT: ldp x3, x13, [x13, #16]
+; AARCH64-NEXT: lsl x5, x17, x8
+; AARCH64-NEXT: lsr x16, x16, x9
+; AARCH64-NEXT: lsr x17, x17, #1
+; AARCH64-NEXT: lsr x4, x1, x9
+; AARCH64-NEXT: lsl x14, x2, x14
+; AARCH64-NEXT: lsr x2, x18, #1
+; AARCH64-NEXT: lsr x12, x12, x9
+; AARCH64-NEXT: lsr x9, x0, x9
+; AARCH64-NEXT: lsl x0, x0, #1
+; AARCH64-NEXT: lsl x18, x18, x8
+; AARCH64-NEXT: lsl x13, x13, x8
+; AARCH64-NEXT: lsl x8, x3, x8
+; AARCH64-NEXT: lsl x1, x1, #1
+; AARCH64-NEXT: lsr x3, x3, #1
+; AARCH64-NEXT: lsr x15, x17, x15
+; AARCH64-NEXT: lsr x17, x2, x11
+; AARCH64-NEXT: lsl x0, x0, x10
+; AARCH64-NEXT: orr x12, x18, x12
+; AARCH64-NEXT: lsl x10, x1, x10
+; AARCH64-NEXT: lsr x11, x3, x11
+; AARCH64-NEXT: orr x14, x4, x14
+; AARCH64-NEXT: orr x17, x5, x17
+; AARCH64-NEXT: orr x16, x0, x16
+; AARCH64-NEXT: orr x8, x8, x15
+; AARCH64-NEXT: orr x9, x13, x9
+; AARCH64-NEXT: orr x0, x12, x10
+; AARCH64-NEXT: orr x1, x17, x14
+; AARCH64-NEXT: orr x2, x8, x16
+; AARCH64-NEXT: orr x3, x9, x11
+; AARCH64-NEXT: add sp, sp, #272
+; AARCH64-NEXT: ret
+ %result = bitinsert b231 %base, double %val, i32 %off
----------------
aengelke wrote:
Wow, this is really bad codegen. Why do we have multiplications (probably divisions/remainder) here? Is this an artifact of using rotate instead of shift? I still don't understand the benefit of using rotate at all, please explain this in the commit message=PR description.
https://github.com/llvm/llvm-project/pull/200605
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