[llvm] [CodeGen] Replace CodeGenPassBuilder CRTP with virtual hooks (PR #216468)
via llvm-commits
llvm-commits at lists.llvm.org
Sat Aug 15 01:27:57 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-amdgpu
@llvm/pr-subscribers-backend-x86
Author: Fangrui Song (MaskRay)
<details>
<summary>Changes</summary>
Make the hooks that were dispatched through derived() virtual, drop both
template parameters, and outline the pipeline into
lib/Passes/CodeGenPassBuilder.cpp, mirroring TargetPassConfig. The pass
headers move out of CodeGenPassBuilder.h.
The outlined bodies are moved verbatim, apart from dropping now-redundant
std::move on returned Errors.
MSP430CodeGenPassBuilder.cpp.o .text: 84685 -> 11240 (-87%); compile
time: 1.75s -> 0.64s. llc .text: -293824 bytes; .data.rel.ro: +2784 (the
9 new vtables). The vtable slots are link-time constants in the default
non-PIE llc; with -pie they become 333 relative relocations, which RELR
packs into 40 bytes.
Overriding is now compiler-checked, which surfaced
AMDGPUCodeGenPassBuilder::addPreEmitRegAlloc (not a hook, never defined
or called); remove it. Add `Passes` dependency to targets that are
missing it.
A function pointer table in the builder, as `PassConcept` uses, avoids the
vtables but measures larger.
LLM-aided
---
Patch is 141.77 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/216468.diff
15 Files Affected:
- (modified) llvm/include/llvm/Passes/CodeGenPassBuilder.h (+77-995)
- (modified) llvm/lib/Passes/CodeGenPassBuilder.cpp (+926-1)
- (modified) llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp (+64-56)
- (modified) llvm/lib/Target/AMDGPU/R600TargetMachine.cpp (+11-12)
- (modified) llvm/lib/Target/BPF/BPFCodeGenPassBuilder.cpp (+22-20)
- (modified) llvm/lib/Target/Lanai/CMakeLists.txt (+1)
- (modified) llvm/lib/Target/Lanai/LanaiCodeGenPassBuilder.cpp (+21-19)
- (modified) llvm/lib/Target/MSP430/CMakeLists.txt (+1)
- (modified) llvm/lib/Target/MSP430/MSP430CodeGenPassBuilder.cpp (+19-18)
- (modified) llvm/lib/Target/RISCV/RISCVCodeGenPassBuilder.cpp (+34-32)
- (modified) llvm/lib/Target/WebAssembly/CMakeLists.txt (+1)
- (modified) llvm/lib/Target/WebAssembly/WebAssemblyCodeGenPassBuilder.cpp (+29-31)
- (modified) llvm/lib/Target/X86/CMakeLists.txt (+1)
- (modified) llvm/lib/Target/X86/X86AsmPrinter.cpp (+1)
- (modified) llvm/lib/Target/X86/X86CodeGenPassBuilder.cpp (+39-37)
``````````diff
diff --git a/llvm/include/llvm/Passes/CodeGenPassBuilder.h b/llvm/include/llvm/Passes/CodeGenPassBuilder.h
index 11e448dd7f78b..7eeab0db58f3c 100644
--- a/llvm/include/llvm/Passes/CodeGenPassBuilder.h
+++ b/llvm/include/llvm/Passes/CodeGenPassBuilder.h
@@ -14,116 +14,18 @@
#ifndef LLVM_PASSES_CODEGENPASSBUILDER_H
#define LLVM_PASSES_CODEGENPASSBUILDER_H
+#include "llvm/ADT/FunctionExtras.h"
+#include "llvm/ADT/STLForwardCompat.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringRef.h"
-#include "llvm/Analysis/BasicAliasAnalysis.h"
-#include "llvm/Analysis/CGSCCPassManager.h"
-#include "llvm/Analysis/ProfileSummaryInfo.h"
-#include "llvm/Analysis/RuntimeLibcallInfo.h"
-#include "llvm/Analysis/ScopedNoAliasAA.h"
-#include "llvm/Analysis/TargetTransformInfo.h"
-#include "llvm/Analysis/TypeBasedAliasAnalysis.h"
-#include "llvm/CodeGen/AsmPrinter.h"
-#include "llvm/CodeGen/AsmPrinterAnalysis.h"
-#include "llvm/CodeGen/BranchFoldingPass.h"
-#include "llvm/CodeGen/CodeGenPrepare.h"
-#include "llvm/CodeGen/DeadMachineInstructionElim.h"
-#include "llvm/CodeGen/DetectDeadLanes.h"
-#include "llvm/CodeGen/DwarfEHPrepare.h"
-#include "llvm/CodeGen/ExpandIRInsts.h"
-#include "llvm/CodeGen/ExpandPostRAPseudos.h"
-#include "llvm/CodeGen/ExpandReductions.h"
-#include "llvm/CodeGen/FEntryInserter.h"
-#include "llvm/CodeGen/FinalizeISel.h"
-#include "llvm/CodeGen/FixupStatepointCallerSaved.h"
-#include "llvm/CodeGen/GCEmptyBasicBlocks.h"
-#include "llvm/CodeGen/GCMetadata.h"
-#include "llvm/CodeGen/GlobalMerge.h"
-#include "llvm/CodeGen/GlobalMergeFunctions.h"
-#include "llvm/CodeGen/IndirectBrExpand.h"
-#include "llvm/CodeGen/InitUndef.h"
-#include "llvm/CodeGen/InlineAsmPrepare.h"
-#include "llvm/CodeGen/InterleavedAccess.h"
-#include "llvm/CodeGen/InterleavedLoadCombine.h"
-#include "llvm/CodeGen/LiveDebugValuesPass.h"
-#include "llvm/CodeGen/LiveIntervals.h"
-#include "llvm/CodeGen/LiveVariables.h"
-#include "llvm/CodeGen/LocalStackSlotAllocation.h"
-#include "llvm/CodeGen/LowerEmuTLS.h"
-#include "llvm/CodeGen/MIRPrinter.h"
-#include "llvm/CodeGen/MachineBlockPlacement.h"
-#include "llvm/CodeGen/MachineCSE.h"
-#include "llvm/CodeGen/MachineCopyPropagation.h"
-#include "llvm/CodeGen/MachineFunctionAnalysis.h"
-#include "llvm/CodeGen/MachineLICM.h"
-#include "llvm/CodeGen/MachineLateInstrsCleanup.h"
-#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/MachinePassManager.h"
-#include "llvm/CodeGen/MachineScheduler.h"
-#include "llvm/CodeGen/MachineSink.h"
-#include "llvm/CodeGen/MachineVerifier.h"
-#include "llvm/CodeGen/OptimizePHIs.h"
-#include "llvm/CodeGen/PEI.h"
-#include "llvm/CodeGen/PHIElimination.h"
-#include "llvm/CodeGen/PatchableFunction.h"
-#include "llvm/CodeGen/PeepholeOptimizer.h"
-#include "llvm/CodeGen/PostRAMachineSink.h"
-#include "llvm/CodeGen/PostRASchedulerList.h"
-#include "llvm/CodeGen/PreISelIntrinsicLowering.h"
-#include "llvm/CodeGen/ProcessImplicitDefs.h"
-#include "llvm/CodeGen/RegAllocEvictionAdvisor.h"
-#include "llvm/CodeGen/RegAllocFast.h"
-#include "llvm/CodeGen/RegAllocGreedyPass.h"
-#include "llvm/CodeGen/RegUsageInfoCollector.h"
-#include "llvm/CodeGen/RegUsageInfoPropagate.h"
-#include "llvm/CodeGen/RegisterCoalescerPass.h"
-#include "llvm/CodeGen/RegisterUsageInfo.h"
-#include "llvm/CodeGen/RemoveLoadsIntoFakeUses.h"
-#include "llvm/CodeGen/RemoveRedundantDebugValues.h"
-#include "llvm/CodeGen/RenameIndependentSubregs.h"
-#include "llvm/CodeGen/ReplaceWithVeclib.h"
-#include "llvm/CodeGen/SafeStack.h"
-#include "llvm/CodeGen/SanitizerBinaryMetadata.h"
-#include "llvm/CodeGen/SelectOptimize.h"
-#include "llvm/CodeGen/ShadowStackGCLowering.h"
-#include "llvm/CodeGen/ShrinkWrap.h"
-#include "llvm/CodeGen/SjLjEHPrepare.h"
-#include "llvm/CodeGen/StackColoring.h"
-#include "llvm/CodeGen/StackFrameLayoutAnalysisPass.h"
-#include "llvm/CodeGen/StackProtector.h"
-#include "llvm/CodeGen/StackSlotColoring.h"
-#include "llvm/CodeGen/TailDuplication.h"
#include "llvm/CodeGen/TargetPassConfig.h"
-#include "llvm/CodeGen/TwoAddressInstructionPass.h"
-#include "llvm/CodeGen/UnreachableBlockElim.h"
-#include "llvm/CodeGen/VirtRegMap.h"
-#include "llvm/CodeGen/WasmEHPrepare.h"
-#include "llvm/CodeGen/WinEHPrepare.h"
-#include "llvm/CodeGen/XRayInstrumentation.h"
#include "llvm/IR/PassManager.h"
-#include "llvm/IR/Verifier.h"
-#include "llvm/IRPrinter/IRPrintingPasses.h"
-#include "llvm/MC/MCAsmInfo.h"
-#include "llvm/MC/MCTargetOptions.h"
-#include "llvm/MC/TargetRegistry.h"
#include "llvm/Support/CodeGen.h"
-#include "llvm/Support/Debug.h"
+#include "llvm/Support/Compiler.h"
#include "llvm/Support/Error.h"
-#include "llvm/Support/ErrorHandling.h"
#include "llvm/Target/CGPassBuilderOption.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Transforms/ObjCARC.h"
-#include "llvm/Transforms/Scalar/ConstantHoisting.h"
-#include "llvm/Transforms/Scalar/LoopPassManager.h"
-#include "llvm/Transforms/Scalar/LoopStrengthReduce.h"
-#include "llvm/Transforms/Scalar/LoopTermFold.h"
-#include "llvm/Transforms/Scalar/LowerConstantIntrinsics.h"
-#include "llvm/Transforms/Scalar/MergeICmps.h"
-#include "llvm/Transforms/Scalar/PartiallyInlineLibCalls.h"
-#include "llvm/Transforms/Scalar/ScalarizeMaskedMemIntrin.h"
-#include "llvm/Transforms/Utils/CanonicalizeFreezeInLoops.h"
-#include "llvm/Transforms/Utils/EntryExitInstrumenter.h"
-#include "llvm/Transforms/Utils/LowerInvoke.h"
#include <cassert>
#include <utility>
@@ -163,7 +65,6 @@ class PassManagerWrapper {
FunctionPassManager FPM;
MachineFunctionPassManager MFPM;
- template <typename DerivedT, typename TargetMachineT>
friend class CodeGenPassBuilder;
};
@@ -173,41 +74,26 @@ class PassManagerWrapper {
/// construction. The \c MachinePassRegistry.def file specifies how to construct
/// all of the built-in passes, and those may reference these members during
/// construction.
-template <typename DerivedT, typename TargetMachineT> class CodeGenPassBuilder {
+///
+/// Targets customize the pipeline by deriving from this class and overriding
+/// the virtual add* hooks below: the add%Stage hooks replace a whole stage of
+/// the pipeline, while the addPre%Stage / addPost%Stage hooks inject passes
+/// around one. See addMachinePasses for how they fit together.
+///
+/// Dispatch is virtual rather than templated on the derived builder so that the
+/// target-independent pipeline is emitted once for the whole build instead of
+/// once per target.
+class LLVM_ABI CodeGenPassBuilder {
public:
- explicit CodeGenPassBuilder(TargetMachineT &TM,
- const CGPassBuilderOption &Opts,
- PassInstrumentationCallbacks *PIC)
- : TM(TM), Opt(Opts), PIC(PIC) {
- // Target could set CGPassBuilderOption::MISchedPostRA to true to achieve
- // substitutePass(&PostRASchedulerID, &PostMachineSchedulerID)
-
- // Target should override TM.Options.EnableIPRA in their target-specific
- // LLVMTM ctor. See TargetMachine::setGlobalISel for example.
- if (Opt.EnableIPRA) {
- TM.Options.EnableIPRA = *Opt.EnableIPRA;
- } else {
- // If not explicitly specified, use target default.
- TM.Options.EnableIPRA |= TM.useIPRA();
- }
-
- if (Opt.EnableGlobalISelAbort)
- TM.Options.GlobalISelAbort = *Opt.EnableGlobalISelAbort;
-
- // An explicit RegAlloc choice implies its pipeline: only the fast
- // allocator uses the unoptimized one.
- if (Opt.OptimizeRegAlloc == cl::boolOrDefault::BOU_UNSET) {
- bool Optimized = Opt.RegAlloc > RegAllocType::Default
- ? Opt.RegAlloc != RegAllocType::Fast
- : getOptLevel() != CodeGenOptLevel::None;
- Opt.OptimizeRegAlloc = Optimized ? cl::boolOrDefault::BOU_TRUE
- : cl::boolOrDefault::BOU_FALSE;
- }
- }
+ CodeGenPassBuilder(TargetMachine &TM, const CGPassBuilderOption &Opts,
+ PassInstrumentationCallbacks *PIC);
+ CodeGenPassBuilder(const CodeGenPassBuilder &) = delete;
+ CodeGenPassBuilder &operator=(const CodeGenPassBuilder &) = delete;
+ virtual ~CodeGenPassBuilder();
Error buildPipeline(ModulePassManager &MPM, ModuleAnalysisManager &MAM,
raw_pwrite_stream &Out, raw_pwrite_stream *DwoOut,
- CodeGenFileType FileType, MCContext &Ctx) const;
+ CodeGenFileType FileType, MCContext &Ctx);
PassInstrumentationCallbacks *getPassInstrumentationCallbacks() const {
return PIC;
@@ -229,8 +115,7 @@ template <typename DerivedT, typename TargetMachineT> class CodeGenPassBuilder {
template <typename PassT>
void addFunctionPass(PassT &&Pass, PassManagerWrapper &PMW,
- bool Force = false,
- StringRef Name = PassT::name()) const {
+ bool Force = false, StringRef Name = PassT::name()) {
static_assert(is_detected<is_function_pass_t, PassT>::value &&
"Only function passes are supported.");
if (!Force && !runBeforeAdding(Name))
@@ -240,7 +125,7 @@ template <typename DerivedT, typename TargetMachineT> class CodeGenPassBuilder {
template <typename PassT>
void addModulePass(PassT &&Pass, PassManagerWrapper &PMW, bool Force = false,
- StringRef Name = PassT::name()) const {
+ StringRef Name = PassT::name()) {
static_assert(is_detected<is_module_pass_t, PassT>::value &&
"Only module passes are suported.");
assert(PMW.FPM.isEmpty() && PMW.MFPM.isEmpty() &&
@@ -254,7 +139,7 @@ template <typename DerivedT, typename TargetMachineT> class CodeGenPassBuilder {
template <typename PassT>
void addMachineFunctionPass(PassT &&Pass, PassManagerWrapper &PMW,
bool Force = false,
- StringRef Name = PassT::name()) const {
+ StringRef Name = PassT::name()) {
static_assert(is_detected<is_machine_function_pass_t, PassT>::value &&
"Only machine function passes are supported.");
@@ -266,26 +151,9 @@ template <typename DerivedT, typename TargetMachineT> class CodeGenPassBuilder {
}
void flushFPMsToMPM(PassManagerWrapper &PMW,
- bool FreeMachineFunctions = false) const {
- if (PMW.FPM.isEmpty() && PMW.MFPM.isEmpty())
- return;
- if (!PMW.MFPM.isEmpty()) {
- PMW.FPM.addPass(
- createFunctionToMachineFunctionPassAdaptor(std::move(PMW.MFPM)));
- PMW.MFPM = MachineFunctionPassManager();
- }
- if (FreeMachineFunctions)
- PMW.FPM.addPass(FreeMachineFunctionPass());
- if (AddInCGSCCOrder) {
- PMW.MPM.addPass(createModuleToPostOrderCGSCCPassAdaptor(
- createCGSCCToFunctionPassAdaptor(std::move(PMW.FPM))));
- } else {
- PMW.MPM.addPass(createModuleToFunctionPassAdaptor(std::move(PMW.FPM)));
- }
- PMW.FPM = FunctionPassManager();
- }
+ bool FreeMachineFunctions = false);
- void requireCGSCCOrder(PassManagerWrapper &PMW) const {
+ void requireCGSCCOrder(PassManagerWrapper &PMW) {
assert(!AddInCGSCCOrder);
assert(PMW.FPM.isEmpty() && PMW.MFPM.isEmpty() &&
"Requiring CGSCC ordering requires flushing the current function "
@@ -293,7 +161,7 @@ template <typename DerivedT, typename TargetMachineT> class CodeGenPassBuilder {
AddInCGSCCOrder = true;
}
- void stopAddingInCGSCCOrder(PassManagerWrapper &PMW) const {
+ void stopAddingInCGSCCOrder(PassManagerWrapper &PMW) {
assert(AddInCGSCCOrder);
assert(PMW.FPM.isEmpty() && PMW.MFPM.isEmpty() &&
"Stopping CGSCC ordering requires flushing the current function "
@@ -301,11 +169,10 @@ template <typename DerivedT, typename TargetMachineT> class CodeGenPassBuilder {
AddInCGSCCOrder = false;
}
- TargetMachineT &TM;
+ TargetMachine &TM;
CGPassBuilderOption Opt;
PassInstrumentationCallbacks *PIC;
- template <typename TMC> TMC &getTM() const { return static_cast<TMC &>(TM); }
CodeGenOptLevel getOptLevel() const { return TM.getOptLevel(); }
/// Check whether or not GlobalISel should abort on error.
@@ -324,13 +191,10 @@ template <typename DerivedT, typename TargetMachineT> class CodeGenPassBuilder {
/// addInstSelector - This method should install an instruction selector pass,
/// which converts from LLVM code to machine instructions.
- Error addInstSelector(PassManagerWrapper &PMW) const {
- return make_error<StringError>("addInstSelector is not overridden",
- inconvertibleErrorCode());
- }
+ virtual Error addInstSelector(PassManagerWrapper &PMW);
/// Target can override this to add GlobalMergePass before all IR passes.
- void addGlobalMergePass(PassManagerWrapper &PMW) const {}
+ virtual void addGlobalMergePass(PassManagerWrapper &PMW) {}
/// Add passes that optimize instruction level parallelism for out-of-order
/// targets. These passes are run while the machine code is still in SSA
@@ -338,11 +202,11 @@ template <typename DerivedT, typename TargetMachineT> class CodeGenPassBuilder {
///
/// All passes added here should preserve the MachineDominatorTree,
/// MachineLoopInfo, and MachineTraceMetrics analyses.
- void addILPOpts(PassManagerWrapper &PMW) const {}
+ virtual void addILPOpts(PassManagerWrapper &PMW) {}
/// This method may be implemented by targets that want to run passes
/// immediately before register allocation.
- void addPreRegAlloc(PassManagerWrapper &PMW) const {}
+ virtual void addPreRegAlloc(PassManagerWrapper &PMW) {}
/// addPreRewrite - Add passes to the optimized register allocation pipeline
/// after register allocation is complete, but before virtual registers are
@@ -356,111 +220,98 @@ template <typename DerivedT, typename TargetMachineT> class CodeGenPassBuilder {
/// Note if the target overloads addRegAssignAndRewriteOptimized, this may not
/// be honored. This is also not generally used for the fast variant,
/// where the allocation and rewriting are done in one pass.
- void addPreRewrite(PassManagerWrapper &PMW) const {}
+ virtual void addPreRewrite(PassManagerWrapper &PMW) {}
/// Add passes to be run immediately after virtual registers are rewritten
/// to physical registers.
- void addPostRewrite(PassManagerWrapper &PMW) const {}
+ virtual void addPostRewrite(PassManagerWrapper &PMW) {}
/// This method may be implemented by targets that want to run passes after
/// register allocation pass pipeline but before prolog-epilog insertion.
- void addPostRegAlloc(PassManagerWrapper &PMW) const {}
+ virtual void addPostRegAlloc(PassManagerWrapper &PMW) {}
/// This method may be implemented by targets that want to run passes after
/// prolog-epilog insertion and before the second instruction scheduling pass.
- void addPreSched2(PassManagerWrapper &PMW) const {}
+ virtual void addPreSched2(PassManagerWrapper &PMW) {}
/// This pass may be implemented by targets that want to run passes
/// immediately before machine code is emitted.
- void addPreEmitPass(PassManagerWrapper &PMW) const {}
+ virtual void addPreEmitPass(PassManagerWrapper &PMW) {}
/// Targets may add passes immediately before machine code is emitted in this
/// callback. This is called even later than `addPreEmitPass`.
// FIXME: Rename `addPreEmitPass` to something more sensible given its actual
// position and remove the `2` suffix here as this callback is what
// `addPreEmitPass` *should* be but in reality isn't.
- void addPreEmitPass2(PassManagerWrapper &PMW) const {}
+ virtual void addPreEmitPass2(PassManagerWrapper &PMW) {}
/// {{@ For GlobalISel
///
/// addPreISel - This method should add any "last minute" LLVM->LLVM
/// passes (which are run just before instruction selector).
- void addPreISel(PassManagerWrapper &PMW) const {}
+ virtual void addPreISel(PassManagerWrapper &PMW) {}
/// This method should install an IR translator pass, which converts from
/// LLVM code to machine instructions with possibly generic opcodes.
- Error addIRTranslator(PassManagerWrapper &PMW) const {
- return make_error<StringError>("addIRTranslator is not overridden",
- inconvertibleErrorCode());
- }
+ virtual Error addIRTranslator(PassManagerWrapper &PMW);
/// This method may be implemented by targets that want to run passes
/// immediately before legalization.
- void addPreLegalizeMachineIR(PassManagerWrapper &PMW) const {}
+ virtual void addPreLegalizeMachineIR(PassManagerWrapper &PMW) {}
/// This method should install a legalize pass, which converts the instruction
/// sequence into one that can be selected by the target.
- Error addLegalizeMachineIR(PassManagerWrapper &PMW) const {
- return make_error<StringError>("addLegalizeMachineIR is not overridden",
- inconvertibleErrorCode());
- }
+ virtual Error addLegalizeMachineIR(PassManagerWrapper &PMW);
/// This method may be implemented by targets that want to run passes
/// immediately before the register bank selection.
- void addPreRegBankSelect(PassManagerWrapper &PMW) const {}
+ virtual void addPreRegBankSelect(PassManagerWrapper &PMW) {}
/// This method should install a register bank selector pass, which
/// assigns register banks to virtual registers without a register
/// class or register banks.
- Error addRegBankSelect(PassManagerWrapper &PMW) const {
- return make_error<StringError>("addRegBankSelect is not overridden",
- inconvertibleErrorCode());
- }
+ virtual Error addRegBankSelect(PassManagerWrapper &PMW);
/// This method may be implemented by targets that want to run passes
/// immediately before the (global) instruction selection.
- void addPreGlobalInstructionSelect(PassManagerWrapper &PMW) const {}
+ virtual void addPreGlobalInstructionSelect(PassManagerWrapper &PMW) {}
/// This method should install a (global) instruction selector pass, which
/// converts possibly generic instructions to fully target-specific
/// instructions, thereby constraining all generic virtual registers to
/// register classes.
- Error addGlobalInstructionSelect(PassManagerWrapper &PMWM) const {
- return make_error<StringError>(
- "addGlobalInstructionSelect is not overridden",
- inconvertibleErrorCode());
- }
+ virtual Error addGlobalInstructionSelect(PassManagerWrapper &PMW);
/// @}}
/// High level function that adds all passes necessary to go from llvm IR
/// representation to the MI representation.
/// Adds IR based lowering and target specific optimization passes and finally
/// the core instruction selection passes.
- void addISelPasses(PassManagerWrapper &PMW) const;
+ void addISelPasses(PassManagerWrapper &PMW);
/// Add the actual instruction selection passes. This does not include
/// preparation passes on IR.
- Error addCoreISelPasses(PassManagerWrapper &PMW) const;
+ Error addCoreISelPasses(PassManagerWrapper &PMW);
/// Add the complete, standard set of LLVM CodeGen passes.
/// Fully developed targets will not generally override this.
- Error addMachinePasses(PassManagerWrapper &PMW) const;
+ virtual Error addMachinePasses(PassManagerWrapper &PMW);
/// Add passes to lower exception handling for the code generator.
- void addPassesToHandleExceptions(PassManagerWrapper &PMW) const;
+ void addPassesToHandleExceptions(PassManagerWrapper &PMW);
/// Add common target configurable passes that perform LLVM IR to IR
/// transforms following machine independent optimization.
- void addIRPasses(PassManagerWrapper &PMW) const;
+ virtual void addIRPasses(PassManagerWrapper &PMW);
/// Add pass to prepare the LLVM IR for code generation. This should be done
/// before exception handling preparation passes.
- void addCodeGenPrepare(PassManagerWrapper &PMW) const;
+ virtual void addCodeGenPrepare(PassManagerWrapper &PMW);
/// Add common passes that perform LLVM IR to IR transforms in preparation for
/// instruction selection.
- void addISelPrepare(PassManagerWrapper &PMW) const;
+ virtual void addISelPrepare(PassManagerWrapper &PMW);
/// Methods with trivial inline returns are convenient points in the common
/// codeg...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/216468
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