[llvm] [SDAG] Fix invalid sign bit condition for abs(sub) -> abdu fold (PR #215548)

[Craig Topper via llvm-commits]

topperc wrote:

> The patch, as is, is incorrent for the case of IsAdd. Please change the code as described by @topperc : ``` bool Op1SignBitIsOne = DAG.computeKnownBits(Op1).isNegative(); bool AbsOpInSignedRange = DAG.SignBitIsZero(Op0) && (IsAdd ? Op1SignBitIsOne: DAG.SignBitIsZero(Op1)); ``` The condition should be inverted.
> […](#)
> On August 14, 2026 5:57:48 PM GMT+02:00, Craig Topper ***@***.***> wrote: @topperc approved this pull request. LGTM -- Reply to this email directly or view it on GitHub: [#215548 (review)](https://github.com/llvm/llvm-project/pull/215548#pullrequestreview-4939024026) You are receiving this because you were mentioned. Message ID: ***@***.***>

My comments were just trying to understand the history. The IsAdd code was removed in a later commit but left the  subtract broken due to the inverted conditional that existed when add was removed.

https://github.com/llvm/llvm-project/pull/215548