[llvm] [RISCV] Remove short-forward-branch-imm. (PR #216401)

Craig Topper via llvm-commits llvm-commits at lists.llvm.org
Fri Aug 14 13:59:37 PDT 2026 

https://github.com/topperc created https://github.com/llvm/llvm-project/pull/216401

I hope implentations that implement short-forward-branch, do it equally for all branch types. Doing anything else would create complex tradeoffs.

I'm planning to add conditional c.mv fusion support for Zibi and I don't want to add an immediate version flag there.

The patterns that checked NoShortForwardBranchImm were not checking that a immediate branch ISA was enabled. So I've changed them to NoVendorXqcibiOrNoShortForwardBranch.

>From d23ed0fea45ad511cac40daa5ce37087dc5960a1 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Fri, 14 Aug 2026 13:44:51 -0700
Subject: [PATCH] [RISCV] Remove short-forward-branch-imm.

I hope implentations that implement short-forward-branch, do it
equally for all branch types. Doing anything else would create
complex tradeoffs.

I'm planning to add conditional c.mv fusion support for Zibi and
I don't want to add an immediate version flag there.

The patterns that checked NoShortForwardBranchImm were not checking
that a immediate branch ISA was enabled. So I've changed them
to NoVendorXqcibiOrNoShortForwardBranch.
---
 llvm/lib/Target/RISCV/RISCVFeatures.td             |  9 ++-------
 llvm/lib/Target/RISCV/RISCVInstrInfoSFB.td         |  4 ++--
 llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td        | 14 +++++++-------
 llvm/test/CodeGen/RISCV/features-info.ll           |  1 -
 llvm/test/CodeGen/RISCV/sfb-merge-base-offset.ll   |  6 +++---
 ...branch-opt-with-branch-with-immediates_32_eq.ll |  2 +-
 ...branch-opt-with-branch-with-immediates_32_ne.ll |  2 +-
 ...ranch-opt-with-branch-with-immediates_32_sge.ll |  2 +-
 ...ranch-opt-with-branch-with-immediates_32_slt.ll |  2 +-
 ...ranch-opt-with-branch-with-immediates_32_uge.ll |  2 +-
 ...ranch-opt-with-branch-with-immediates_32_ult.ll |  2 +-
 ...branch-opt-with-branch-with-immediates_48_eq.ll |  2 +-
 ...branch-opt-with-branch-with-immediates_48_ne.ll |  2 +-
 ...ranch-opt-with-branch-with-immediates_48_sge.ll |  2 +-
 ...ranch-opt-with-branch-with-immediates_48_slt.ll |  2 +-
 ...ranch-opt-with-branch-with-immediates_48_uge.ll |  2 +-
 ...ranch-opt-with-branch-with-immediates_48_ult.ll |  2 +-
 .../CodeGen/RISCV/short-forward-branch-opt-zibi.ll |  4 ++--
 .../TargetParser/RISCVTargetParserTest.cpp         |  3 +--
 19 files changed, 29 insertions(+), 36 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 4e9710e2ecb7e..2abc78ff874c2 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -1697,6 +1697,8 @@ def HasVendorXqcibi
     : Predicate<"Subtarget->hasVendorXqcibi()">,
       AssemblerPredicate<(all_of FeatureVendorXqcibi),
                          "'Xqcibi' (Qualcomm uC Branch Immediate Extension)">;
+def NoVendorXqcibiOrNoShortForwardBranch
+    : Predicate<"!Subtarget->hasVendorXqcibi() || !Subtarget->hasShortForwardBranchIALU()">;
 
 def FeatureVendorXqcibm
     : RISCVExtension<0, 8, "Qualcomm uC Bit Manipulation Extension",
@@ -2167,13 +2169,6 @@ def TuneShortForwardBranchILoad
           [TuneShortForwardBranchIALU]>;
 def HasShortForwardBranchILoad : Predicate<"Subtarget->hasShortForwardBranchILoad()">;
 
-def TuneShortForwardBranchImm
-    : RISCVSimpleTuneFeature<"short-forward-branch-imm", "HasShortForwardBranchImm",
-                             "true", "Enable short forward branch optimization for branches with immediates",
-                             [TuneShortForwardBranchIALU]>;
-def HasShortForwardBranchImm : Predicate<"Subtarget->hasShortForwardBranchImm()">;
-def NoShortForwardBranchImm : Predicate<"!Subtarget->hasShortForwardBranchImm()">;
-
 // Some subtargets require a S2V transfer buffer to move scalars into vectors.
 // FIXME: Forming .vx/.vf/.wx/.wf can reduce register pressure.
 def TuneNoSinkSplatOperands
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoSFB.td b/llvm/lib/Target/RISCV/RISCVInstrInfoSFB.td
index 409aeb4c86546..3c9023b7f23f4 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoSFB.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoSFB.td
@@ -269,7 +269,7 @@ class SelectZibiSFB<CondCode Cond>
           (PseudoCCMOVGPR GPR:$falsev, GPR:$truev, (CCtoZibiBCC $cc), GPR:$lhs,
                           imm5_zibi:$cimm)>;
 
-let Predicates = [HasStdExtZibi, HasShortForwardBranchImm] in {
+let Predicates = [HasStdExtZibi, HasShortForwardBranchIALU] in {
   def : SelectZibiSFB<SETEQ>;
   def : SelectZibiSFB<SETNE>;
-} // Predicates = [HasStdExtZibi, HasShortForwardBranchImm]
+} // Predicates = [HasStdExtZibi, HasShortForwardBranchIALU]
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
index 9eac989ded9cd..a81887652991b 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
@@ -1639,7 +1639,7 @@ def : PatGprNoX0GprNoX0<sshlsat, QC_SHLSAT>;
 } // Predicates = [HasVendorXqcia, IsRV32]
 
 let Predicates = [HasVendorXqcibi, IsRV32] in {
-let append Predicates = [HasShortForwardBranchImm] in {
+let append Predicates = [HasShortForwardBranchIALU] in {
 def : SelectQCbiSFB<SETEQ, simm5nonzero, CCtoQC_BccI>;
 def : SelectQCbiSFB<SETNE, simm5nonzero, CCtoQC_BccI>;
 def : SelectQCbiSFB<SETGE, simm5nonzero, CCtoQC_BccI>;
@@ -1653,7 +1653,7 @@ def : SelectQCbiSFB<SETLT, simm16nonzero, CCtoQC_E_BccI>;
 def : SelectQCbiSFB<SETNE, simm16nonzero, CCtoQC_E_BccI>;
 def : SelectQCbiSFB<SETULT, uimm16nonzero, CCtoQC_E_BccI>;
 def : SelectQCbiSFB<SETUGE, uimm16nonzero, CCtoQC_E_BccI>;
-} // append Predicates = [HasShortForwardBranchImm]
+} // append Predicates = [HasShortForwardBranchIALU]
 
 /// Branches
 
@@ -1671,7 +1671,7 @@ def : Bcci48Pat<SETGE, QC_E_BGEI, simm16nonzero>;
 def : Bcci48Pat<SETULT, QC_E_BLTUI, uimm16nonzero>;
 def : Bcci48Pat<SETUGE, QC_E_BGEUI, uimm16nonzero>;
 
-let append Predicates = [NoShortForwardBranchImm] in {
+let append Predicates = [NoVendorXqcibiOrNoShortForwardBranch] in {
 def : SelectQCbi<SETEQ, simm5nonzero, Select_GPRNoX0_Using_CC_SImm5NonZero_QC>;
 def : SelectQCbi<SETNE, simm5nonzero, Select_GPRNoX0_Using_CC_SImm5NonZero_QC>;
 def : SelectQCbi<SETLT, simm5nonzero, Select_GPRNoX0_Using_CC_SImm5NonZero_QC>;
@@ -1685,7 +1685,7 @@ def : SelectQCbi<SETLT, simm16nonzero, Select_GPRNoX0_Using_CC_SImm16NonZero_QC>
 def : SelectQCbi<SETGE, simm16nonzero, Select_GPRNoX0_Using_CC_SImm16NonZero_QC>;
 def : SelectQCbi<SETULT, uimm16nonzero, Select_GPRNoX0_Using_CC_UImm16NonZero_QC>;
 def : SelectQCbi<SETUGE, uimm16nonzero, Select_GPRNoX0_Using_CC_UImm16NonZero_QC>;
-} // append Predicates = [NoShortForwardBranchImm]
+} // append Predicates = [NoShortForwardBranch]
 } // Predicates = [HasVendorXqcibi, IsRV32]
 
 def QC_EXTXForm : SDNodeXForm<imm, [{
@@ -1747,7 +1747,7 @@ def : QCIMVCCIZeroPat<SETGE,  QC_MVGEI>;
 def : QCIMVCCIZeroPat<SETUGE, QC_MVGEUI>;
 }
 
-let Predicates = [HasVendorXqcicm, NoShortForwardBranchImm, IsRV32] in {
+let Predicates = [HasVendorXqcicm, NoVendorXqcibiOrNoShortForwardBranch, IsRV32] in {
 // These all use *imm5nonzero because we want to use PseudoCCMOVGPR with X0 when SFB is enabled.
 // When SFB is not enabled, the `QCIMVCCIZeroPat`s above will be used if RHS=0.
 def : QCIMVCCIPat<SETEQ,  QC_MVEQI,  simm5nonzero>;
@@ -1812,13 +1812,13 @@ def : QCISELECTICCIPatInv<SETNE,  QC_SELECTIEQI>;
 def : QCISELECTIICCPat<SETEQ,  QC_SELECTIIEQ>;
 def : QCISELECTIICCPat<SETNE,  QC_SELECTIINE>;
 
-let append Predicates = [NoShortForwardBranchImm] in {
+let append Predicates = [NoVendorXqcibiOrNoShortForwardBranch] in {
 def : QCISELECTICCPat<SETEQ,  QC_SELECTIEQ>;
 def : QCISELECTICCPat<SETNE,  QC_SELECTINE>;
 
 def : QCISELECTICCPatInv<SETEQ,  QC_SELECTINE>;
 def : QCISELECTICCPatInv<SETNE,  QC_SELECTIEQ>;
-} // append Predicates = [NoShortForwardBranchImm]
+} // append Predicates = [NoVendorXqcibiOrNoShortForwardBranch]
 
 // Prioritize Xqcicm over these patterns, because Xqcicm is compressible.
 let append Predicates = [NoVendorXqcicm] in {
diff --git a/llvm/test/CodeGen/RISCV/features-info.ll b/llvm/test/CodeGen/RISCV/features-info.ll
index febe312db5836..08cf62f61296c 100644
--- a/llvm/test/CodeGen/RISCV/features-info.ll
+++ b/llvm/test/CodeGen/RISCV/features-info.ll
@@ -161,7 +161,6 @@
 ; CHECK-NEXT:   short-forward-branch-ialu        - Enable short forward branch optimization for RVI base instructions.
 ; CHECK-NEXT:   short-forward-branch-iload       - Enable short forward branch optimization for load instructions.
 ; CHECK-NEXT:   short-forward-branch-iminmax     - Enable short forward branch optimization for MIN,MAX instructions in Zbb.
-; CHECK-NEXT:   short-forward-branch-imm         - Enable short forward branch optimization for branches with immediates.
 ; CHECK-NEXT:   short-forward-branch-imul        - Enable short forward branch optimization for MUL instruction.
 ; CHECK-NEXT:   shtvala                          - 'Shtvala' (htval provides all needed values).
 ; CHECK-NEXT:   shvsatpa                         - 'Shvsatpa' (vsatp supports all modes supported by satp).
diff --git a/llvm/test/CodeGen/RISCV/sfb-merge-base-offset.ll b/llvm/test/CodeGen/RISCV/sfb-merge-base-offset.ll
index 2cd2d29e5e164..c7690639c872d 100644
--- a/llvm/test/CodeGen/RISCV/sfb-merge-base-offset.ll
+++ b/llvm/test/CodeGen/RISCV/sfb-merge-base-offset.ll
@@ -1,11 +1,11 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
 
-; RUN: llc -mtriple=riscv32 -verify-machineinstrs -mattr=+short-forward-branch-iload,+short-forward-branch-imm < %s \
+; RUN: llc -mtriple=riscv32 -verify-machineinstrs -mattr=+short-forward-branch-iload < %s \
 ; RUN:   | FileCheck -check-prefix=RV32I-WITH-SFB %s
-; RUN: llc -mtriple=riscv32 -verify-machineinstrs -mattr=+xqci,+short-forward-branch-iload,+short-forward-branch-imm < %s \
+; RUN: llc -mtriple=riscv32 -verify-machineinstrs -mattr=+xqci,+short-forward-branch-iload < %s \
 ; RUN:   | FileCheck -check-prefix=XQCI-WITH-SFB %s
 
-; RUN: llc -mtriple=riscv64 -verify-machineinstrs -mattr=+short-forward-branch-iload,+short-forward-branch-imm < %s \
+; RUN: llc -mtriple=riscv64 -verify-machineinstrs -mattr=+short-forward-branch-iload < %s \
 ; RUN:   | FileCheck -check-prefix=RV64I-WITH-SFB %s
 
 
diff --git a/llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_32_eq.ll b/llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_32_eq.ll
index 5dca26357cfe7..a2678154c5ba7 100644
--- a/llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_32_eq.ll
+++ b/llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_32_eq.ll
@@ -1,6 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
 ; RUN: llc < %s -verify-machineinstrs -mtriple=riscv32 | FileCheck %s --check-prefixes=RV32I
-; RUN: llc < %s -verify-machineinstrs -mtriple=riscv32 -mattr=+xqci,+short-forward-branch-ialu,+short-forward-branch-imul,+short-forward-branch-iload,+short-forward-branch-imm,+m | \
+; RUN: llc < %s -verify-machineinstrs -mtriple=riscv32 -mattr=+xqci,+short-forward-branch-ialu,+short-forward-branch-imul,+short-forward-branch-iload,+m | \
 ; RUN:   FileCheck %s --check-prefixes=RV32I-SFB-WITH-IMM
 
 define i32 @branch_with_immSFB_mv(i32 %a, i32 %c, i32 %d) {
diff --git a/llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_32_ne.ll b/llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_32_ne.ll
index 6b04167d98b44..f93cf13093457 100644
--- a/llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_32_ne.ll
+++ b/llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_32_ne.ll
@@ -1,6 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
 ; RUN: llc < %s -verify-machineinstrs -mtriple=riscv32 | FileCheck %s --check-prefixes=RV32I
-; RUN: llc < %s -verify-machineinstrs -mtriple=riscv32 -mattr=+xqci,+short-forward-branch-ialu,+short-forward-branch-imul,+short-forward-branch-iload,+short-forward-branch-imm,+m | \
+; RUN: llc < %s -verify-machineinstrs -mtriple=riscv32 -mattr=+xqci,+short-forward-branch-ialu,+short-forward-branch-imul,+short-forward-branch-iload,+m | \
 ; RUN:   FileCheck %s --check-prefixes=RV32I-SFB-WITH-IMM
 
 define i32 @branch_with_immSFB_mv(i32 %a, i32 %c, i32 %d) {
diff --git a/llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_32_sge.ll b/llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_32_sge.ll
index 20fe6f4b14218..429ba499f4d78 100644
--- a/llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_32_sge.ll
+++ b/llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_32_sge.ll
@@ -1,6 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
 ; RUN: llc < %s -verify-machineinstrs -mtriple=riscv32 | FileCheck %s --check-prefixes=RV32I
-; RUN: llc < %s -verify-machineinstrs -mtriple=riscv32 -mattr=+xqci,+short-forward-branch-ialu,+short-forward-branch-imul,+short-forward-branch-iload,+short-forward-branch-imm,+m | \
+; RUN: llc < %s -verify-machineinstrs -mtriple=riscv32 -mattr=+xqci,+short-forward-branch-ialu,+short-forward-branch-imul,+short-forward-branch-iload,+m | \
 ; RUN:   FileCheck %s --check-prefixes=RV32I-SFB-WITH-IMM
 
 define i32 @branch_with_immSFB_mv(i32 %a, i32 %c, i32 %d) {
diff --git a/llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_32_slt.ll b/llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_32_slt.ll
index 705bbc8a67598..9a1b6ebb42397 100644
--- a/llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_32_slt.ll
+++ b/llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_32_slt.ll
@@ -1,6 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
 ; RUN: llc < %s -verify-machineinstrs -mtriple=riscv32 | FileCheck %s --check-prefixes=RV32I
-; RUN: llc < %s -verify-machineinstrs -mtriple=riscv32 -mattr=+xqci,+short-forward-branch-ialu,+short-forward-branch-imul,+short-forward-branch-iload,+short-forward-branch-imm,+m | \
+; RUN: llc < %s -verify-machineinstrs -mtriple=riscv32 -mattr=+xqci,+short-forward-branch-ialu,+short-forward-branch-imul,+short-forward-branch-iload,+m | \
 ; RUN:   FileCheck %s --check-prefixes=RV32I-SFB-WITH-IMM
 
 define i32 @branch_with_immSFB_mv(i32 %a, i32 %c, i32 %d) {
diff --git a/llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_32_uge.ll b/llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_32_uge.ll
index 1c8040e72c8a3..9ffa5498a7156 100644
--- a/llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_32_uge.ll
+++ b/llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_32_uge.ll
@@ -1,6 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
 ; RUN: llc < %s -verify-machineinstrs -mtriple=riscv32 | FileCheck %s --check-prefixes=RV32I
-; RUN: llc < %s -verify-machineinstrs -mtriple=riscv32 -mattr=+xqci,+short-forward-branch-ialu,+short-forward-branch-imul,+short-forward-branch-iload,+short-forward-branch-imm,+m | \
+; RUN: llc < %s -verify-machineinstrs -mtriple=riscv32 -mattr=+xqci,+short-forward-branch-ialu,+short-forward-branch-imul,+short-forward-branch-iload,+m | \
 ; RUN:   FileCheck %s --check-prefixes=RV32I-SFB-WITH-IMM
 
 define i32 @branch_with_immSFB_mv(i32 %a, i32 %c, i32 %d) {
diff --git a/llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_32_ult.ll b/llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_32_ult.ll
index bf489ff670b48..f9aa83ac1f8e5 100644
--- a/llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_32_ult.ll
+++ b/llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_32_ult.ll
@@ -1,6 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
 ; RUN: llc < %s -verify-machineinstrs -mtriple=riscv32 | FileCheck %s --check-prefixes=RV32I
-; RUN: llc < %s -verify-machineinstrs -mtriple=riscv32 -mattr=+xqci,+short-forward-branch-ialu,+short-forward-branch-imul,+short-forward-branch-iload,+short-forward-branch-imm,+m | \
+; RUN: llc < %s -verify-machineinstrs -mtriple=riscv32 -mattr=+xqci,+short-forward-branch-ialu,+short-forward-branch-imul,+short-forward-branch-iload,+m | \
 ; RUN:   FileCheck %s --check-prefixes=RV32I-SFB-WITH-IMM
 
 define i32 @branch_with_immSFB_mv(i32 %a, i32 %c, i32 %d) {
diff --git a/llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_48_eq.ll b/llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_48_eq.ll
index 859d5897a3ac3..2f6595aba1f58 100644
--- a/llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_48_eq.ll
+++ b/llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_48_eq.ll
@@ -1,6 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
 ; RUN: llc < %s -verify-machineinstrs -mtriple=riscv32 | FileCheck %s --check-prefixes=RV32I
-; RUN: llc < %s -verify-machineinstrs -mtriple=riscv32 -mattr=+xqci,+short-forward-branch-ialu,+short-forward-branch-imul,+short-forward-branch-iload,+short-forward-branch-imm,+m | \
+; RUN: llc < %s -verify-machineinstrs -mtriple=riscv32 -mattr=+xqci,+short-forward-branch-ialu,+short-forward-branch-imul,+short-forward-branch-iload,+m | \
 ; RUN:   FileCheck %s --check-prefixes=RV32I-SFB-WITH-IMM
 
 define i32 @branch_with_immSFB_mv(i32 %a, i32 %c, i32 %d) {
diff --git a/llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_48_ne.ll b/llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_48_ne.ll
index e98b2a44d4a7f..c82f8c7b048dd 100644
--- a/llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_48_ne.ll
+++ b/llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_48_ne.ll
@@ -1,6 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
 ; RUN: llc < %s -verify-machineinstrs -mtriple=riscv32 | FileCheck %s --check-prefixes=RV32I
-; RUN: llc < %s -verify-machineinstrs -mtriple=riscv32 -mattr=+xqci,+short-forward-branch-ialu,+short-forward-branch-imul,+short-forward-branch-iload,+short-forward-branch-imm,+m | \
+; RUN: llc < %s -verify-machineinstrs -mtriple=riscv32 -mattr=+xqci,+short-forward-branch-ialu,+short-forward-branch-imul,+short-forward-branch-iload,+m | \
 ; RUN:   FileCheck %s --check-prefixes=RV32I-SFB-WITH-IMM
 
 define i32 @branch_with_immSFB_mv(i32 %a, i32 %c, i32 %d) {
diff --git a/llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_48_sge.ll b/llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_48_sge.ll
index 7d0d5ec80eda0..039731bdf49cd 100644
--- a/llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_48_sge.ll
+++ b/llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_48_sge.ll
@@ -1,6 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
 ; RUN: llc < %s -verify-machineinstrs -mtriple=riscv32 | FileCheck %s --check-prefixes=RV32I
-; RUN: llc < %s -verify-machineinstrs -mtriple=riscv32 -mattr=+xqci,+short-forward-branch-ialu,+short-forward-branch-imul,+short-forward-branch-iload,+short-forward-branch-imm,+m | \
+; RUN: llc < %s -verify-machineinstrs -mtriple=riscv32 -mattr=+xqci,+short-forward-branch-ialu,+short-forward-branch-imul,+short-forward-branch-iload,+m | \
 ; RUN:   FileCheck %s --check-prefixes=RV32I-SFB-WITH-IMM
 
 define i32 @branch_with_immSFB_mv(i32 %a, i32 %c, i32 %d) {
diff --git a/llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_48_slt.ll b/llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_48_slt.ll
index f1ba557e59f93..c51c28781d8c8 100644
--- a/llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_48_slt.ll
+++ b/llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_48_slt.ll
@@ -1,6 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
 ; RUN: llc < %s -verify-machineinstrs -mtriple=riscv32 | FileCheck %s --check-prefixes=RV32I
-; RUN: llc < %s -verify-machineinstrs -mtriple=riscv32 -mattr=+xqci,+short-forward-branch-ialu,+short-forward-branch-imul,+short-forward-branch-iload,+short-forward-branch-imm,+m | \
+; RUN: llc < %s -verify-machineinstrs -mtriple=riscv32 -mattr=+xqci,+short-forward-branch-ialu,+short-forward-branch-imul,+short-forward-branch-iload,+m | \
 ; RUN:   FileCheck %s --check-prefixes=RV32I-SFB-WITH-IMM
 
 define i32 @branch_with_immSFB_mv(i32 %a, i32 %c, i32 %d) {
diff --git a/llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_48_uge.ll b/llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_48_uge.ll
index 37baf90890edf..3c7c7317e9556 100644
--- a/llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_48_uge.ll
+++ b/llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_48_uge.ll
@@ -1,6 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
 ; RUN: llc < %s -verify-machineinstrs -mtriple=riscv32 | FileCheck %s --check-prefixes=RV32I
-; RUN: llc < %s -verify-machineinstrs -mtriple=riscv32 -mattr=+xqci,+short-forward-branch-ialu,+short-forward-branch-imul,+short-forward-branch-iload,+short-forward-branch-imm,+m | \
+; RUN: llc < %s -verify-machineinstrs -mtriple=riscv32 -mattr=+xqci,+short-forward-branch-ialu,+short-forward-branch-imul,+short-forward-branch-iload,+m | \
 ; RUN:   FileCheck %s --check-prefixes=RV32I-SFB-WITH-IMM
 
 define i32 @branch_with_immSFB_mv(i32 %a, i32 %c, i32 %d) {
diff --git a/llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_48_ult.ll b/llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_48_ult.ll
index 12ffa568fdb6c..b08ecf91eb097 100644
--- a/llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_48_ult.ll
+++ b/llvm/test/CodeGen/RISCV/short-forward-branch-opt-with-branch-with-immediates_48_ult.ll
@@ -1,6 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
 ; RUN: llc < %s -verify-machineinstrs -mtriple=riscv32 | FileCheck %s --check-prefixes=RV32I
-; RUN: llc < %s -verify-machineinstrs -mtriple=riscv32 -mattr=+xqci,+short-forward-branch-ialu,+short-forward-branch-imul,+short-forward-branch-iload,+short-forward-branch-imm,+m | \
+; RUN: llc < %s -verify-machineinstrs -mtriple=riscv32 -mattr=+xqci,+short-forward-branch-ialu,+short-forward-branch-imul,+short-forward-branch-iload,+m | \
 ; RUN:   FileCheck %s --check-prefixes=RV32I-SFB-WITH-IMM
 
 define i32 @branch_with_immSFB_mv(i32 %a, i32 %c, i32 %d) {
diff --git a/llvm/test/CodeGen/RISCV/short-forward-branch-opt-zibi.ll b/llvm/test/CodeGen/RISCV/short-forward-branch-opt-zibi.ll
index 1e5c313da73cc..0009afc19c9a0 100644
--- a/llvm/test/CodeGen/RISCV/short-forward-branch-opt-zibi.ll
+++ b/llvm/test/CodeGen/RISCV/short-forward-branch-opt-zibi.ll
@@ -1,11 +1,11 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zibi -verify-machineinstrs < %s \
 ; RUN:     | FileCheck %s --check-prefixes=RV32
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-zibi,+short-forward-branch-ialu,+short-forward-branch-imm -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zibi,+short-forward-branch-ialu -verify-machineinstrs < %s \
 ; RUN:     | FileCheck %s --check-prefixes=RV32-SFB
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zibi -verify-machineinstrs < %s \
 ; RUN:     | FileCheck %s --check-prefixes=RV64
-; RUN: llc -mtriple=riscv64 -mattr=+experimental-zibi,+short-forward-branch-ialu,+short-forward-branch-imm -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zibi,+short-forward-branch-ialu -verify-machineinstrs < %s \
 ; RUN:     | FileCheck %s --check-prefixes=RV64-SFB
 
 ; Basic select eq with Zibi immediate: should use bnei+mv SFB pattern when SFB enabled.
diff --git a/llvm/unittests/TargetParser/RISCVTargetParserTest.cpp b/llvm/unittests/TargetParser/RISCVTargetParserTest.cpp
index bb4e0548b57d7..df3bcc09f2b6a 100644
--- a/llvm/unittests/TargetParser/RISCVTargetParserTest.cpp
+++ b/llvm/unittests/TargetParser/RISCVTargetParserTest.cpp
@@ -109,7 +109,7 @@ TEST(RISCVTuneFeature, AllTuneFeatures) {
   RISCV::getAllTuneFeatures(AllTuneFeatures);
   // Only allowed subtarget features that are explicitly marked by
   // special TableGen class.
-  EXPECT_EQ(AllTuneFeatures.size(), 21U);
+  EXPECT_EQ(AllTuneFeatures.size(), 20U);
   for (auto F : {"conditional-cmv-fusion",
                  "disable-latency-sched-heuristic",
                  "disable-misched-load-clustering",
@@ -128,7 +128,6 @@ TEST(RISCVTuneFeature, AllTuneFeatures) {
                  "short-forward-branch-iminmax",
                  "short-forward-branch-imul",
                  "short-forward-branch-iload",
-                 "short-forward-branch-imm",
                  "vl-dependent-latency",
                  "vxrm-pipeline-flush"})
     EXPECT_TRUE(is_contained(AllTuneFeatures, F));

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