[llvm] [CodeGen] Avoid register pressure limit underflow (PR #216372)

[via llvm-commits]

https://github.com/hjagasiaAMD created https://github.com/llvm/llvm-project/pull/216372

Keep the target-provided limit when reserved-register weight meets or exceeds it, preventing unsigned wraparound from disabling pressure checks.

>From 4d1979158f32ceadb5602b532f72f942a2fb5cf3 Mon Sep 17 00:00:00 2001
From: Harsha Jagasia <harsha.jagasia at amd.com>
Date: Fri, 14 Aug 2026 17:55:50 +0000
Subject: [PATCH] [CodeGen] Avoid register pressure limit underflow

Keep the target-provided limit when reserved-register weight meets or exceeds it, preventing unsigned wraparound from disabling pressure checks.
---
 llvm/lib/CodeGen/RegisterClassInfo.cpp        |  5 ++-
 .../AMDGPU/register-class-info-pset-limit.mir | 41 +++++++++++++++++++
 2 files changed, 45 insertions(+), 1 deletion(-)
 create mode 100644 llvm/test/CodeGen/AMDGPU/register-class-info-pset-limit.mir

diff --git a/llvm/lib/CodeGen/RegisterClassInfo.cpp b/llvm/lib/CodeGen/RegisterClassInfo.cpp
index 4b011001aa6ce..80a584f917150 100644
--- a/llvm/lib/CodeGen/RegisterClassInfo.cpp
+++ b/llvm/lib/CodeGen/RegisterClassInfo.cpp
@@ -213,7 +213,10 @@ unsigned RegisterClassInfo::computePSetLimit(unsigned Idx) const {
   if (NAllocatableRegs == 0)
     return RegPressureSetLimit;
   unsigned NReserved = RC->getNumRegs() - NAllocatableRegs;
-  return RegPressureSetLimit - TRI->getRegClassWeight(RC).RegWeight * NReserved;
+  unsigned ReservedRegWeight = TRI->getRegClassWeight(RC).RegWeight * NReserved;
+  if (ReservedRegWeight >= RegPressureSetLimit)
+    return RegPressureSetLimit;
+  return RegPressureSetLimit - ReservedRegWeight;
 }
 
 INITIALIZE_PASS(MachineRegisterClassInfoWrapperPass,
diff --git a/llvm/test/CodeGen/AMDGPU/register-class-info-pset-limit.mir b/llvm/test/CodeGen/AMDGPU/register-class-info-pset-limit.mir
new file mode 100644
index 0000000000000..30bb1c6ad461d
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/register-class-info-pset-limit.mir
@@ -0,0 +1,41 @@
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -run-pass=machine-scheduler \
+# RUN:   -debug-only=machine-scheduler -o /dev/null %s 2>&1 | FileCheck %s
+# REQUIRES: asserts
+
+# The reported SGPR pressure-set limit is smaller than the weight of the
+# registers reserved from SGPR_32. Check that subtracting the reserved weight
+# does not wrap around.
+
+# CHECK: SReg_32 Limit 6 Actual 13
+# CHECK: Excess PSets: SReg_32
+
+--- |
+  define amdgpu_kernel void @reserved_weight_exceeds_limit() #0 {
+    ret void
+  }
+
+  attributes #0 = { "amdgpu-num-sgpr"="12" }
+...
+---
+name: reserved_weight_exceeds_limit
+tracksRegLiveness: true
+machineFunctionInfo:
+  isEntryFunction: true
+body: |
+  bb.0:
+    %0:sgpr_32 = S_MOV_B32 0
+    %1:sgpr_32 = S_MOV_B32 1
+    %2:sgpr_32 = S_MOV_B32 2
+    %3:sgpr_32 = S_MOV_B32 3
+    %4:sgpr_32 = S_MOV_B32 4
+    %5:sgpr_32 = S_MOV_B32 5
+    %6:sgpr_32 = S_MOV_B32 6
+    %7:sgpr_32 = S_MOV_B32 7
+    %8:sgpr_32 = S_MOV_B32 8
+    %9:sgpr_32 = S_MOV_B32 9
+    %10:sgpr_32 = S_MOV_B32 10
+    %11:sgpr_32 = S_MOV_B32 11
+    %12:sgpr_32 = S_MOV_B32 12
+    S_NOP 0, implicit %0, implicit %1, implicit %2, implicit %3, implicit %4, implicit %5, implicit %6, implicit %7, implicit %8, implicit %9, implicit %10, implicit %11, implicit %12
+    S_ENDPGM 0
+...