[llvm] [AMDGPU] Hints for prefering allocating AGPR registers for buffer loads (PR #215697)
Haohui Mai via llvm-commits
llvm-commits at lists.llvm.org
Fri Aug 14 11:01:19 PDT 2026
https://github.com/haohui updated https://github.com/llvm/llvm-project/pull/215697
>From 9427f19c039e6a00de4fcb3cd3088f1fc38890d4 Mon Sep 17 00:00:00 2001
From: Haohui Mai <haohui at causalflow.ai>
Date: Wed, 5 Aug 2026 21:15:20 +0000
Subject: [PATCH 1/2] Support prefer AGPR allocation for buffer load
---
.../Target/AMDGPU/AMDGPUPrepareAGPRAlloc.cpp | 33 ++++++++++
llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 6 ++
llvm/lib/Target/AMDGPU/SIRegisterInfo.h | 4 +-
.../AMDGPU/buffer-load-prefer-agpr.mir | 64 +++++++++++++++++++
4 files changed, 105 insertions(+), 2 deletions(-)
create mode 100644 llvm/test/CodeGen/AMDGPU/buffer-load-prefer-agpr.mir
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUPrepareAGPRAlloc.cpp b/llvm/lib/Target/AMDGPU/AMDGPUPrepareAGPRAlloc.cpp
index a43600af8b085..0fa21e09002e4 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUPrepareAGPRAlloc.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUPrepareAGPRAlloc.cpp
@@ -22,11 +22,17 @@
#include "llvm/CodeGen/LiveIntervals.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/InitializePasses.h"
+#include "llvm/Support/CommandLine.h"
using namespace llvm;
#define DEBUG_TYPE "amdgpu-prepare-agpr-alloc"
+static cl::opt<bool> BufferLoadPreferAGPR(
+ "amdgpu-buffer-load-prefer-agpr",
+ cl::desc("Prefer AGPRs for eligible buffer load results"), cl::Hidden,
+ cl::init(false));
+
namespace {
class AMDGPUPrepareAGPRAllocImpl {
@@ -35,6 +41,7 @@ class AMDGPUPrepareAGPRAllocImpl {
MachineRegisterInfo &MRI;
bool isAV64Imm(const MachineOperand &MO) const;
+ bool shouldPreferAGPR(Register Reg) const;
public:
AMDGPUPrepareAGPRAllocImpl(const GCNSubtarget &ST, MachineRegisterInfo &MRI)
@@ -86,6 +93,22 @@ bool AMDGPUPrepareAGPRAllocImpl::isAV64Imm(const MachineOperand &MO) const {
return MO.isImm() && TII.isLegalAV64PseudoImm(MO.getImm());
}
+bool AMDGPUPrepareAGPRAllocImpl::shouldPreferAGPR(Register Reg) const {
+ const TargetRegisterClass *RC = MRI.getRegClass(Reg);
+ if (!SIRegisterInfo::hasVGPRs(RC) || !SIRegisterInfo::hasAGPRs(RC))
+ return false;
+
+ for (const MachineOperand &Use : MRI.use_nodbg_operands(Reg)) {
+ const MachineInstr &UseMI = *Use.getParent();
+ const TargetRegisterClass *UseRC = UseMI.getRegClassConstraint(
+ Use.getOperandNo(), &TII, &TII.getRegisterInfo());
+ if (UseRC && !SIRegisterInfo::hasAGPRs(UseRC))
+ return false;
+ }
+
+ return true;
+}
+
bool AMDGPUPrepareAGPRAllocImpl::run(MachineFunction &MF) {
if (MRI.isReserved(AMDGPU::AGPR0))
return false;
@@ -96,6 +119,16 @@ bool AMDGPUPrepareAGPRAllocImpl::run(MachineFunction &MF) {
bool Changed = false;
for (MachineBasicBlock &MBB : MF) {
for (MachineInstr &MI : MBB) {
+ if (BufferLoadPreferAGPR && TII.isMUBUF(MI) && MI.mayLoad() &&
+ !MI.mayStore() && MI.getOperand(0).isReg() &&
+ MI.getOperand(0).isDef()) {
+ Register DstReg = MI.getOperand(0).getReg();
+ if (DstReg.isVirtual() && shouldPreferAGPR(DstReg)) {
+ MRI.setRegAllocationHint(DstReg, AMDGPURI::PreferAGPR, Register());
+ Changed = true;
+ }
+ }
+
if ((MI.getOpcode() == AMDGPU::V_MOV_B32_e32 &&
TII.isInlineConstant(MI, 1)) ||
(MI.getOpcode() == AMDGPU::V_ACCVGPR_WRITE_B32_e64 &&
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
index c661787b301c0..3f418c7c91f46 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -4167,6 +4167,12 @@ bool SIRegisterInfo::getRegAllocationHints(Register VirtReg,
}
return false;
}
+ case AMDGPURI::PreferAGPR:
+ for (MCPhysReg PhysReg : Order) {
+ if (TRI->isAGPR(MRI, PhysReg) && !MRI.isReserved(PhysReg))
+ Hints.push_back(PhysReg);
+ }
+ return false;
default:
return TargetRegisterInfo::getRegAllocationHints(VirtReg, Order, Hints, MF,
VRM);
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
index e464c9334ffea..863ab83d01914 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
@@ -30,10 +30,10 @@ class MachineInstrBuilder;
class RegisterBank;
struct SGPRSpillBuilder;
-/// Register allocation hint types. Helps eliminate unneeded COPY with True16
+/// AMDGPU-specific register allocation hint types.
namespace AMDGPURI {
-enum { Size16 = 1, Size32 = 2 };
+enum { Size16 = 1, Size32 = 2, PreferAGPR = 3 };
} // end namespace AMDGPURI
diff --git a/llvm/test/CodeGen/AMDGPU/buffer-load-prefer-agpr.mir b/llvm/test/CodeGen/AMDGPU/buffer-load-prefer-agpr.mir
new file mode 100644
index 0000000000000..fd9cf5c0eabfb
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/buffer-load-prefer-agpr.mir
@@ -0,0 +1,64 @@
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 \
+# RUN: -run-pass=amdgpu-prepare-agpr-alloc,greedy,virtregrewriter \
+# RUN: -verify-regalloc -verify-machineinstrs -o - %s | \
+# RUN: FileCheck --check-prefixes=VGPR,COMMON %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 \
+# RUN: -amdgpu-buffer-load-prefer-agpr=false \
+# RUN: -run-pass=amdgpu-prepare-agpr-alloc,greedy,virtregrewriter \
+# RUN: -verify-regalloc -verify-machineinstrs -o - %s | \
+# RUN: FileCheck --check-prefixes=VGPR,COMMON %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 \
+# RUN: -amdgpu-buffer-load-prefer-agpr=true \
+# RUN: -run-pass=amdgpu-prepare-agpr-alloc,greedy,virtregrewriter \
+# RUN: -verify-regalloc -verify-machineinstrs -o - %s | \
+# RUN: FileCheck --check-prefixes=AGPR,COMMON %s
+
+--- |
+ define amdgpu_kernel void @prefer_agpr_mfma() {
+ ret void
+ }
+
+ define amdgpu_kernel void @require_vgpr() {
+ ret void
+ }
+...
+---
+name: prefer_agpr_mfma
+tracksRegLiveness: true
+body: |
+ ; AGPR-LABEL: name: prefer_agpr_mfma
+ ; AGPR: [[LOAD:\$agpr[0-9]+_agpr[0-9]+]] = BUFFER_LOAD_DWORDX2_OFFSET
+ ; AGPR: V_SMFMAC_F32_16X16X32_F16_e64 [[LOAD]],
+ ; AGPR: BUFFER_STORE_DWORDX2_OFFSET killed renamable [[LOAD]],
+ ; VGPR-LABEL: name: prefer_agpr_mfma
+ ; VGPR: [[LOAD:\$vgpr[0-9]+_vgpr[0-9]+]] = BUFFER_LOAD_DWORDX2_OFFSET
+ ; VGPR: V_SMFMAC_F32_16X16X32_F16_e64 [[LOAD]],
+ ; VGPR: BUFFER_STORE_DWORDX2_OFFSET killed renamable [[LOAD]],
+ bb.0:
+ %0:av_64_align2 = BUFFER_LOAD_DWORDX2_OFFSET undef %1:sgpr_128, 0, 0, 0, 0, implicit $exec
+ %2:av_128_align2 = IMPLICIT_DEF
+ %3:vgpr_32 = IMPLICIT_DEF
+ %4:av_128_align2 = IMPLICIT_DEF
+ %4:av_128_align2 = V_SMFMAC_F32_16X16X32_F16_e64 %0, %2, %3, 0, 0, %4, implicit $mode, implicit $exec
+ BUFFER_STORE_DWORDX4_OFFSET %4, undef %1:sgpr_128, 0, 0, 0, 0, implicit $exec
+ BUFFER_STORE_DWORDX2_OFFSET %0, undef %1:sgpr_128, 0, 8, 0, 0, implicit $exec
+ S_ENDPGM 0
+...
+---
+name: require_vgpr
+tracksRegLiveness: true
+body: |
+ ; COMMON-LABEL: name: require_vgpr
+ ; COMMON: [[LOAD_LO:\$vgpr[0-9]+]]_[[LOAD_HI:vgpr[0-9]+]] = BUFFER_LOAD_DWORDX2_OFFSET
+ ; COMMON: V_SMFMAC_F32_16X16X32_F16_e64 [[LOAD_LO]]_[[LOAD_HI]],
+ ; COMMON: V_ADD_U32_e32 killed [[LOAD_LO]],
+ bb.0:
+ ; The VGPR-only add constrains the load result to a VGPR register class.
+ %0:vreg_64_align2 = BUFFER_LOAD_DWORDX2_OFFSET undef %1:sgpr_128, 0, 0, 0, 0, implicit $exec
+ %2:av_128_align2 = IMPLICIT_DEF
+ %3:vgpr_32 = IMPLICIT_DEF
+ %4:av_128_align2 = IMPLICIT_DEF
+ %4:av_128_align2 = V_SMFMAC_F32_16X16X32_F16_e64 %0, %2, %3, 0, 0, %4, implicit $mode, implicit $exec
+ %5:vgpr_32 = V_ADD_U32_e32 %0.sub0, %3, implicit $exec
+ S_ENDPGM 0
+...
>From cb9b93ec98a3cb611c9a4f34564166b08799402a Mon Sep 17 00:00:00 2001
From: Haohui Mai <ricetons at gmail.com>
Date: Wed, 12 Aug 2026 15:56:36 +0000
Subject: [PATCH 2/2] Address comments
---
.../Target/AMDGPU/AMDGPUPrepareAGPRAlloc.cpp | 23 +++--
.../AMDGPU/buffer-load-prefer-agpr.mir | 64 --------------
.../CodeGen/AMDGPU/memory-prefer-agpr.mir | 85 +++++++++++++++++++
3 files changed, 95 insertions(+), 77 deletions(-)
delete mode 100644 llvm/test/CodeGen/AMDGPU/buffer-load-prefer-agpr.mir
create mode 100644 llvm/test/CodeGen/AMDGPU/memory-prefer-agpr.mir
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUPrepareAGPRAlloc.cpp b/llvm/lib/Target/AMDGPU/AMDGPUPrepareAGPRAlloc.cpp
index 0fa21e09002e4..6ffe9174d5d07 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUPrepareAGPRAlloc.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUPrepareAGPRAlloc.cpp
@@ -22,17 +22,11 @@
#include "llvm/CodeGen/LiveIntervals.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/InitializePasses.h"
-#include "llvm/Support/CommandLine.h"
using namespace llvm;
#define DEBUG_TYPE "amdgpu-prepare-agpr-alloc"
-static cl::opt<bool> BufferLoadPreferAGPR(
- "amdgpu-buffer-load-prefer-agpr",
- cl::desc("Prefer AGPRs for eligible buffer load results"), cl::Hidden,
- cl::init(false));
-
namespace {
class AMDGPUPrepareAGPRAllocImpl {
@@ -119,13 +113,16 @@ bool AMDGPUPrepareAGPRAllocImpl::run(MachineFunction &MF) {
bool Changed = false;
for (MachineBasicBlock &MBB : MF) {
for (MachineInstr &MI : MBB) {
- if (BufferLoadPreferAGPR && TII.isMUBUF(MI) && MI.mayLoad() &&
- !MI.mayStore() && MI.getOperand(0).isReg() &&
- MI.getOperand(0).isDef()) {
- Register DstReg = MI.getOperand(0).getReg();
- if (DstReg.isVirtual() && shouldPreferAGPR(DstReg)) {
- MRI.setRegAllocationHint(DstReg, AMDGPURI::PreferAGPR, Register());
- Changed = true;
+ if (MI.mayLoadOrStore()) {
+ for (const MachineOperand &MO : MI.operands()) {
+ if (!MO.isReg())
+ continue;
+
+ Register Reg = MO.getReg();
+ if (Reg.isVirtual() && shouldPreferAGPR(Reg)) {
+ MRI.setRegAllocationHint(Reg, AMDGPURI::PreferAGPR, Register());
+ Changed = true;
+ }
}
}
diff --git a/llvm/test/CodeGen/AMDGPU/buffer-load-prefer-agpr.mir b/llvm/test/CodeGen/AMDGPU/buffer-load-prefer-agpr.mir
deleted file mode 100644
index fd9cf5c0eabfb..0000000000000
--- a/llvm/test/CodeGen/AMDGPU/buffer-load-prefer-agpr.mir
+++ /dev/null
@@ -1,64 +0,0 @@
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 \
-# RUN: -run-pass=amdgpu-prepare-agpr-alloc,greedy,virtregrewriter \
-# RUN: -verify-regalloc -verify-machineinstrs -o - %s | \
-# RUN: FileCheck --check-prefixes=VGPR,COMMON %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 \
-# RUN: -amdgpu-buffer-load-prefer-agpr=false \
-# RUN: -run-pass=amdgpu-prepare-agpr-alloc,greedy,virtregrewriter \
-# RUN: -verify-regalloc -verify-machineinstrs -o - %s | \
-# RUN: FileCheck --check-prefixes=VGPR,COMMON %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 \
-# RUN: -amdgpu-buffer-load-prefer-agpr=true \
-# RUN: -run-pass=amdgpu-prepare-agpr-alloc,greedy,virtregrewriter \
-# RUN: -verify-regalloc -verify-machineinstrs -o - %s | \
-# RUN: FileCheck --check-prefixes=AGPR,COMMON %s
-
---- |
- define amdgpu_kernel void @prefer_agpr_mfma() {
- ret void
- }
-
- define amdgpu_kernel void @require_vgpr() {
- ret void
- }
-...
----
-name: prefer_agpr_mfma
-tracksRegLiveness: true
-body: |
- ; AGPR-LABEL: name: prefer_agpr_mfma
- ; AGPR: [[LOAD:\$agpr[0-9]+_agpr[0-9]+]] = BUFFER_LOAD_DWORDX2_OFFSET
- ; AGPR: V_SMFMAC_F32_16X16X32_F16_e64 [[LOAD]],
- ; AGPR: BUFFER_STORE_DWORDX2_OFFSET killed renamable [[LOAD]],
- ; VGPR-LABEL: name: prefer_agpr_mfma
- ; VGPR: [[LOAD:\$vgpr[0-9]+_vgpr[0-9]+]] = BUFFER_LOAD_DWORDX2_OFFSET
- ; VGPR: V_SMFMAC_F32_16X16X32_F16_e64 [[LOAD]],
- ; VGPR: BUFFER_STORE_DWORDX2_OFFSET killed renamable [[LOAD]],
- bb.0:
- %0:av_64_align2 = BUFFER_LOAD_DWORDX2_OFFSET undef %1:sgpr_128, 0, 0, 0, 0, implicit $exec
- %2:av_128_align2 = IMPLICIT_DEF
- %3:vgpr_32 = IMPLICIT_DEF
- %4:av_128_align2 = IMPLICIT_DEF
- %4:av_128_align2 = V_SMFMAC_F32_16X16X32_F16_e64 %0, %2, %3, 0, 0, %4, implicit $mode, implicit $exec
- BUFFER_STORE_DWORDX4_OFFSET %4, undef %1:sgpr_128, 0, 0, 0, 0, implicit $exec
- BUFFER_STORE_DWORDX2_OFFSET %0, undef %1:sgpr_128, 0, 8, 0, 0, implicit $exec
- S_ENDPGM 0
-...
----
-name: require_vgpr
-tracksRegLiveness: true
-body: |
- ; COMMON-LABEL: name: require_vgpr
- ; COMMON: [[LOAD_LO:\$vgpr[0-9]+]]_[[LOAD_HI:vgpr[0-9]+]] = BUFFER_LOAD_DWORDX2_OFFSET
- ; COMMON: V_SMFMAC_F32_16X16X32_F16_e64 [[LOAD_LO]]_[[LOAD_HI]],
- ; COMMON: V_ADD_U32_e32 killed [[LOAD_LO]],
- bb.0:
- ; The VGPR-only add constrains the load result to a VGPR register class.
- %0:vreg_64_align2 = BUFFER_LOAD_DWORDX2_OFFSET undef %1:sgpr_128, 0, 0, 0, 0, implicit $exec
- %2:av_128_align2 = IMPLICIT_DEF
- %3:vgpr_32 = IMPLICIT_DEF
- %4:av_128_align2 = IMPLICIT_DEF
- %4:av_128_align2 = V_SMFMAC_F32_16X16X32_F16_e64 %0, %2, %3, 0, 0, %4, implicit $mode, implicit $exec
- %5:vgpr_32 = V_ADD_U32_e32 %0.sub0, %3, implicit $exec
- S_ENDPGM 0
-...
diff --git a/llvm/test/CodeGen/AMDGPU/memory-prefer-agpr.mir b/llvm/test/CodeGen/AMDGPU/memory-prefer-agpr.mir
new file mode 100644
index 0000000000000..39e996bdd5d70
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/memory-prefer-agpr.mir
@@ -0,0 +1,85 @@
+# RUN: llc -mtriple=amdgpu9.42-amd-amdhsa \
+# RUN: -run-pass=amdgpu-prepare-agpr-alloc,greedy,virtregrewriter \
+# RUN: -verify-regalloc -verify-machineinstrs -o - %s | \
+# RUN: FileCheck %s
+
+--- |
+ define amdgpu_kernel void @prefer_agpr_mfma() {
+ ret void
+ }
+
+ define amdgpu_kernel void @require_vgpr() {
+ ret void
+ }
+
+ define amdgpu_kernel void @prefer_agpr_store() {
+ ret void
+ }
+
+ define amdgpu_kernel void @prefer_agpr_flat_load() {
+ ret void
+ }
+...
+---
+name: prefer_agpr_mfma
+tracksRegLiveness: true
+body: |
+ ; CHECK-LABEL: name: prefer_agpr_mfma
+ ; CHECK: [[LOAD:\$agpr[0-9]+_agpr[0-9]+]] = BUFFER_LOAD_DWORDX2_OFFSET
+ ; CHECK: V_SMFMAC_F32_16X16X32_F16_e64 {{(killed )?}}[[LOAD]],
+ ; CHECK: BUFFER_STORE_DWORDX2_OFFSET killed renamable [[LOAD]],
+ bb.0:
+ %0:av_64_align2 = BUFFER_LOAD_DWORDX2_OFFSET undef %1:sgpr_128, 0, 0, 0, 0, implicit $exec
+ %2:av_128_align2 = IMPLICIT_DEF
+ %3:vgpr_32 = IMPLICIT_DEF
+ %4:av_128_align2 = IMPLICIT_DEF
+ %4:av_128_align2 = V_SMFMAC_F32_16X16X32_F16_e64 %0, %2, %3, 0, 0, %4, implicit $mode, implicit $exec
+ BUFFER_STORE_DWORDX4_OFFSET %4, undef %1:sgpr_128, 0, 0, 0, 0, implicit $exec
+ BUFFER_STORE_DWORDX2_OFFSET %0, undef %1:sgpr_128, 0, 8, 0, 0, implicit $exec
+ S_ENDPGM 0
+...
+---
+name: require_vgpr
+tracksRegLiveness: true
+body: |
+ ; CHECK-LABEL: name: require_vgpr
+ ; CHECK: [[LOAD_LO:\$vgpr[0-9]+]]_[[LOAD_HI:vgpr[0-9]+]] = BUFFER_LOAD_DWORDX2_OFFSET
+ ; CHECK: V_SMFMAC_F32_16X16X32_F16_e64 [[LOAD_LO]]_[[LOAD_HI]],
+ ; CHECK: V_ADD_U32_e32 killed [[LOAD_LO]],
+ bb.0:
+ ; The VGPR-only add constrains the load result to a VGPR register class.
+ %0:vreg_64_align2 = BUFFER_LOAD_DWORDX2_OFFSET undef %1:sgpr_128, 0, 0, 0, 0, implicit $exec
+ %2:av_128_align2 = IMPLICIT_DEF
+ %3:vgpr_32 = IMPLICIT_DEF
+ %4:av_128_align2 = IMPLICIT_DEF
+ %4:av_128_align2 = V_SMFMAC_F32_16X16X32_F16_e64 %0, %2, %3, 0, 0, %4, implicit $mode, implicit $exec
+ %5:vgpr_32 = V_ADD_U32_e32 %0.sub0, %3, implicit $exec
+ S_ENDPGM 0
+...
+---
+name: prefer_agpr_store
+tracksRegLiveness: true
+body: |
+ ; CHECK-LABEL: name: prefer_agpr_store
+ ; CHECK: [[VALUE:\$agpr[0-9]+_agpr[0-9]+]] = IMPLICIT_DEF
+ ; CHECK: BUFFER_STORE_DWORDX2_OFFSET killed renamable [[VALUE]],
+ bb.0:
+ %0:av_64_align2 = IMPLICIT_DEF
+ BUFFER_STORE_DWORDX2_OFFSET %0, undef %1:sgpr_128, 0, 0, 0, 0, implicit $exec
+ S_ENDPGM 0
+...
+---
+name: prefer_agpr_flat_load
+tracksRegLiveness: true
+body: |
+ ; CHECK-LABEL: name: prefer_agpr_flat_load
+ ; CHECK: [[LOAD:\$agpr[0-9]+_agpr[0-9]+]] = FLAT_LOAD_DWORDX2
+ ; CHECK: V_SMFMAC_F32_16X16X32_F16_e64 {{(killed )?}}[[LOAD]],
+ bb.0:
+ %0:av_64_align2 = FLAT_LOAD_DWORDX2 undef %1:vreg_64_align2, 0, 0, implicit $exec, implicit $flat_scr
+ %2:av_128_align2 = IMPLICIT_DEF
+ %3:vgpr_32 = IMPLICIT_DEF
+ %4:av_128_align2 = IMPLICIT_DEF
+ %4:av_128_align2 = V_SMFMAC_F32_16X16X32_F16_e64 %0, %2, %3, 0, 0, %4, implicit $mode, implicit $exec
+ S_ENDPGM 0
+...
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