[llvm] [AMDGPU][GlobalISel] Assign bank to vregs created by RegBankCombiner (PR #216270)

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llvmorg-github-actions[bot] wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-llvm-globalisel

Author: Arseniy Obolenskiy (aobolensk)

<details>
<summary>Changes</summary>



---
Full diff: https://github.com/llvm/llvm-project/pull/216270.diff


3 Files Affected:

- (modified) llvm/lib/Target/AMDGPU/AMDGPUCombine.td (+1) 
- (modified) llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp (+23-1) 
- (added) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-same-val-zero.mir (+71) 


``````````diff
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCombine.td b/llvm/lib/Target/AMDGPU/AMDGPUCombine.td
index 0c348bb647c0c..2737400bb6d20 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUCombine.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPUCombine.td
@@ -271,4 +271,5 @@ def AMDGPURegBankCombiner : GICombiner<
    d16_load, smax_to_minmax3, smin_to_minmax3, umax_to_minmax3,
    umin_to_minmax3, fmax_to_minmax3, fmin_to_minmax3, fmaximum_to_minmax3,
    fminimum_to_minmax3, fmax_ieee_to_minmax3, fmin_ieee_to_minmax3]> {
+  let CombineAllMethodName = "tryCombineAllImpl";
 }
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp
index e218bdd826bab..433552bdfaff7 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp
@@ -45,7 +45,7 @@ class AMDGPURegBankCombinerImpl : public Combiner {
 protected:
   const AMDGPURegBankCombinerImplRuleConfig &RuleConfig;
   const GCNSubtarget &STI;
-  const RegisterBankInfo &RBI;
+  const AMDGPURegisterBankInfo &RBI;
   const TargetRegisterInfo &TRI;
   const SIInstrInfo &TII;
   const CombinerHelper Helper;
@@ -60,6 +60,7 @@ class AMDGPURegBankCombinerImpl : public Combiner {
 
   static const char *getName() { return "AMDGPURegBankCombinerImpl"; }
 
+  bool tryCombineAllImpl(MachineInstr &I) const;
   bool tryCombineAll(MachineInstr &I) const override;
 
   bool isVgprRegBank(Register Reg) const;
@@ -139,6 +140,27 @@ AMDGPURegBankCombinerImpl::AMDGPURegBankCombinerImpl(
 {
 }
 
+bool AMDGPURegBankCombinerImpl::tryCombineAll(MachineInstr &MI) const {
+  unsigned NumRegs = MRI.getNumVirtRegs();
+  if (!tryCombineAllImpl(MI))
+    return false;
+
+  // Generated apply patterns (e.g. same_val_zero) create vregs with no bank,
+  // but every vreg needs one after RegBankSelect, which already ran.
+  for (unsigned Idx = NumRegs, End = MRI.getNumVirtRegs(); Idx != End; ++Idx) {
+    Register Reg = Register::index2VirtReg(Idx);
+    if (MRI.getRegClassOrRegBank(Reg))
+      continue;
+    MachineInstr *Def = MRI.getVRegDef(Reg);
+    if (!Def)
+      continue;
+    unsigned BankID =
+        RBI.isSALUMapping(*Def) ? AMDGPU::SGPRRegBankID : AMDGPU::VGPRRegBankID;
+    MRI.setRegBank(Reg, RBI.getRegBank(BankID));
+  }
+  return true;
+}
+
 bool AMDGPURegBankCombinerImpl::isVgprRegBank(Register Reg) const {
   return RBI.getRegBank(Reg, MRI, TRI)->getID() == AMDGPU::VGPRRegBankID;
 }
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-same-val-zero.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-same-val-zero.mir
new file mode 100644
index 0000000000000..617558c8f02f5
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-same-val-zero.mir
@@ -0,0 +1,71 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1030 -run-pass=amdgpu-regbank-combiner -verify-machineinstrs %s -o - | FileCheck %s
+
+# same_val_zero (xor x, x -> 0) creates a vreg with no bank after RegBankSelect.
+
+---
+name: xor_same_val_v2s16
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: $sgpr0
+
+    ; CHECK-LABEL: name: xor_same_val_v2s16
+    ; CHECK: liveins: $sgpr0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s16) = G_CONSTANT i16 0
+    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<2 x s16>) = G_BUILD_VECTOR [[C]](s16), [[C]](s16)
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY [[BUILD_VECTOR]](<2 x s16>)
+    ; CHECK-NEXT: $vgpr0 = COPY [[COPY]](<2 x s16>)
+    %0:sgpr(<2 x s16>) = COPY $sgpr0
+    %1:vgpr(<2 x s16>) = COPY %0(<2 x s16>)
+    %2:vgpr(<2 x s16>) = COPY %0(<2 x s16>)
+    %3:vgpr(<2 x s16>) = G_XOR %1, %2
+    $vgpr0 = COPY %3(<2 x s16>)
+...
+---
+name: xor_same_val_s32
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: $vgpr0
+
+    ; CHECK-LABEL: name: xor_same_val_s32
+    ; CHECK: liveins: $vgpr0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
+    ; CHECK-NEXT: $vgpr0 = COPY [[COPY]](s32)
+    %0:vgpr(s32) = COPY $vgpr0
+    %1:vgpr(s32) = G_XOR %0, %0
+    $vgpr0 = COPY %1(s32)
+...
+---
+name: xor_same_val_s1_vcc
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: $vgpr0, $vgpr1
+
+    ; CHECK-LABEL: name: xor_same_val_s1_vcc
+    ; CHECK: liveins: $vgpr0, $vgpr1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
+    ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s1) = G_CONSTANT i1 false
+    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[C]](s1)
+    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY2]](s1), [[COPY]], [[COPY1]]
+    ; CHECK-NEXT: $vgpr0 = COPY [[SELECT]](s32)
+    %0:vgpr(s32) = COPY $vgpr0
+    %1:vgpr(s32) = COPY $vgpr1
+    %2:vcc(s1) = G_ICMP intpred(eq), %0(s32), %1(s32)
+    %3:vcc(s1) = G_XOR %2, %2
+    %4:vgpr(s32) = G_SELECT %3(s1), %0(s32), %1(s32)
+    $vgpr0 = COPY %4(s32)
+...

``````````

</details>


https://github.com/llvm/llvm-project/pull/216270