[llvm] [SDAG] Fix invalid sign bit condition for abs(sub) -> abdu fold (PR #215548)

[via llvm-commits]

DaKnig wrote:

That sounds to be right.

On August 13, 2026 10:24:09 PM GMT+02:00, Craig Topper ***@***.***> wrote:
>topperc left a comment (llvm/llvm-project#215548)
>
>When https://github.com/llvm/llvm-project/pull/186659 added `fold (abs (add x, -y)) -> abdu(x, y)` did it get this conditional operator reversed?
>
>````
>    bool Op1SignBitIsOne = DAG.computeKnownBits(Op1).isNegative();
>    bool AbsOpWillNUW = DAG.SignBitIsZero(Op0) &&
>                        (IsAdd ? DAG.SignBitIsZero(Op1) : Op1SignBitIsOne);
>```
>
>Prior to that there was a `DAG.SignBitIsZero(Op1)`, but after it looks like the Op1SignBitIsOne is applied to sub?
>
>-- 
>Reply to this email directly or view it on GitHub:
>https://github.com/llvm/llvm-project/pull/215548#issuecomment-5285974184
>You are receiving this because you were mentioned.
>
>Message ID: ***@***.***>

https://github.com/llvm/llvm-project/pull/215548