[llvm] [RISCV][MC] Prioritize features in MultiMismatchFallback (PR #215737)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Aug 14 00:36:33 PDT 2026
https://github.com/saloni-shinde-Q updated https://github.com/llvm/llvm-project/pull/215737
>From c2bd63fe8deb71db062a12a6a5ac0e0b45523413 Mon Sep 17 00:00:00 2001
From: Saloni Shinde <saloshin at qti.qualcomm.com>
Date: Tue, 11 Aug 2026 23:27:44 -0700
Subject: [PATCH 1/2] [RISCV][MC] Prioritize features in MultiMismatchFallback
---
llvm/include/llvm/Target/Target.td | 9 ++
llvm/lib/Target/RISCV/RISCV.td | 1 +
llvm/test/MC/RISCV/priv-invalid.s | 8 +-
llvm/test/MC/RISCV/rv32d-invalid.s | 15 ++--
llvm/test/MC/RISCV/rv32zclsd-invalid.s | 12 +--
llvm/test/MC/RISCV/rv32zdinx-invalid.s | 2 +-
llvm/test/MC/RISCV/rv32zfh-invalid.s | 6 +-
llvm/test/MC/RISCV/rv32zfinx-invalid.s | 2 +-
llvm/test/MC/RISCV/rv32zhinx-invalid.s | 2 +-
llvm/test/MC/RISCV/rv32zhinxmin-invalid.s | 2 +-
llvm/test/MC/RISCV/rv64d-invalid.s | 12 ++-
llvm/test/MC/RISCV/rv64f-invalid.s | 12 ++-
llvm/test/MC/RISCV/rv64xtheadmemidx-invalid.s | 46 +++++++---
llvm/test/MC/RISCV/rv64zdinx-invalid.s | 2 +-
llvm/test/MC/RISCV/rv64zfh-invalid.s | 26 ++++--
llvm/test/MC/RISCV/rv64zfinx-invalid.s | 2 +-
llvm/test/MC/RISCV/rv64zhinx-invalid.s | 2 +-
llvm/test/MC/RISCV/rv64zhinxmin-invalid.s | 4 +-
llvm/test/MC/RISCV/tlsdesc.s | 16 ++--
llvm/test/MC/RISCV/xqcia-invalid.s | 2 +-
llvm/test/MC/RISCV/xqciac-invalid.s | 4 +-
llvm/test/MC/RISCV/xqciio-invalid.s | 10 +--
llvm/test/MC/RISCV/xqcili-invalid.s | 2 +-
llvm/test/MC/RISCV/xqcilo-invalid.s | 48 +++++++----
llvm/test/MC/RISCV/xqcilo-pseudos-invalid.s | 24 +++---
llvm/test/MC/RISCV/xqcilsm-invalid.s | 22 ++---
llvm/utils/TableGen/AsmMatcherEmitter.cpp | 86 +++++++++++++------
27 files changed, 243 insertions(+), 136 deletions(-)
diff --git a/llvm/include/llvm/Target/Target.td b/llvm/include/llvm/Target/Target.td
index 7d1e7a28b7b6e..c8800177c2d77 100644
--- a/llvm/include/llvm/Target/Target.td
+++ b/llvm/include/llvm/Target/Target.td
@@ -1866,6 +1866,15 @@ class AsmParser {
// messages.
bit ReportMultipleNearMisses = false;
+ // PrioritizeFeatureInMultipleNearMisses -
+ // When 0, operand near-misses and feature near-misses are treated equally
+ // in the multiple near-miss reporting path.
+ // When 1, feature near-misses are prioritized over operand near-misses
+ // when multiple near-misses are recorded for the same instruction encoding,
+ // so that diagnostics point to the missing extension rather than a operand
+ // mismatch. Only effective when ReportMultipleNearMisses is also 1.
+ bit PrioritizeFeatureInMultipleNearMisses = false;
+
// OperandParserMethod - If non-empty, this is the name of a custom
// member function of the AsmParser class to call for every custom instruction
// operand to be parsed. If unset, this defaults to calling the generated
diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td
index bc56b3e059ca5..001207db1b251 100644
--- a/llvm/lib/Target/RISCV/RISCV.td
+++ b/llvm/lib/Target/RISCV/RISCV.td
@@ -93,6 +93,7 @@ def RISCVAsmParser : AsmParser {
let ShouldEmitMatchRegisterAltName = true;
let AllowDuplicateRegisterNames = true;
let ReportMultipleNearMisses = true;
+ let PrioritizeFeatureInMultipleNearMisses = true;
let EmitTokenDiagnosticTypes = true;
}
diff --git a/llvm/test/MC/RISCV/priv-invalid.s b/llvm/test/MC/RISCV/priv-invalid.s
index a3346ace3da28..c4bd1e8d74135 100644
--- a/llvm/test/MC/RISCV/priv-invalid.s
+++ b/llvm/test/MC/RISCV/priv-invalid.s
@@ -17,13 +17,13 @@ sfence.w.inval 0x10 # CHECK: :[[@LINE]]:1: error: invalid instruction
sfence.inval.ir 0x10 # CHECK: :[[@LINE]]:1: error: invalid instruction
-hfence.vvma zero, a1, a2 # CHECK: :[[@LINE]]:13: error: unexpected extra operand for instruction
+hfence.vvma zero, a1, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'H' (Hypervisor)
-hfence.vvma a0, 0x10 # CHECK: :[[@LINE]]:13: error: unexpected extra operand for instruction
+hfence.vvma a0, 0x10 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'H' (Hypervisor)
-hfence.gvma zero, a1, a2 # CHECK: :[[@LINE]]:13: error: unexpected extra operand for instruction
+hfence.gvma zero, a1, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'H' (Hypervisor)
-hfence.gvma a0, 0x10 # CHECK: :[[@LINE]]:13: error: unexpected extra operand for instruction
+hfence.gvma a0, 0x10 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'H' (Hypervisor)
hinval.vvma zero, a1, a2 # CHECK: :[[@LINE]]:1: error: invalid instruction
diff --git a/llvm/test/MC/RISCV/rv32d-invalid.s b/llvm/test/MC/RISCV/rv32d-invalid.s
index 4bcb342f7b2e6..f0ac4aca1e118 100644
--- a/llvm/test/MC/RISCV/rv32d-invalid.s
+++ b/llvm/test/MC/RISCV/rv32d-invalid.s
@@ -15,10 +15,15 @@ fld ft1, 100(a10) # CHECK: :[[@LINE]]:14: error: expected register
fsgnjn.d fa100, fa2, fa3 # CHECK: :[[@LINE]]:10: error: register must be a FPR
# Integer registers where FP regs are expected
-fadd.d a2, a1, a0 # CHECK: :[[@LINE]]:1: error: invalid instruction, any one of the following would fix this:
-# CHECK: :[[@LINE-1]]:8: note: register must be a FPR
-# CHECK: :[[@LINE-2]]:8: note: register must be a GPR when used as an FP operand
-# CHECK: :[[@LINE-3]]:8: note: register must be an even-numbered GPR when used as an FP operand
+fadd.d a2, a1, a0
+# CHECK: :[[@LINE-1]]:1: error: invalid instruction, any one of the following would fix this:
+# CHECK: :[[@LINE-2]]:8: note: register must be a FPR
+# CHECK: :[[@LINE-3]]:1: note: instruction requires the following: 'Zdinx' (Double in Integer), RV64I Base Instruction Set
+# CHECK: :[[@LINE-4]]:1: note: instruction requires the following: 'Zdinx' (Double in Integer)
# FP registers where integer regs are expected
-fcvt.wu.d ft2, a1 # CHECK: :[[@LINE]]:11: error: register must be a GPR
+fcvt.wu.d ft2, a1
+# CHECK: :[[@LINE-1]]:1: error: invalid instruction, any one of the following would fix this:
+# CHECK: :[[@LINE-2]]:11: note: register must be a GPR
+# CHECK: :[[@LINE-3]]:1: note: instruction requires the following: 'Zdinx' (Double in Integer), RV64I Base Instruction Set
+# CHECK: :[[@LINE-4]]:1: note: instruction requires the following: 'Zdinx' (Double in Integer)
diff --git a/llvm/test/MC/RISCV/rv32zclsd-invalid.s b/llvm/test/MC/RISCV/rv32zclsd-invalid.s
index 3337e6dd4a029..011a0d72c867a 100644
--- a/llvm/test/MC/RISCV/rv32zclsd-invalid.s
+++ b/llvm/test/MC/RISCV/rv32zclsd-invalid.s
@@ -3,23 +3,23 @@
## GPRPairC
c.ld t1, 4(sp)
# CHECK: :[[@LINE-1]]:1: error: invalid instruction, any one of the following would fix this:
-# CHECK: :[[@LINE-2]]:6: note: register must be a GPR from x8 to x15
+# CHECK: :[[@LINE-2]]:1: note: instruction requires the following: RV64I Base Instruction Set
# CHECK: :[[@LINE-3]]:6: note: register pair must start with x8, x10, x12, or x14
c.sd s2, 4(sp)
# CHECK: :[[@LINE-1]]:1: error: invalid instruction, any one of the following would fix this:
-# CHECK: :[[@LINE-2]]:6: note: register must be a GPR from x8 to x15
+# CHECK: :[[@LINE-2]]:1: note: instruction requires the following: RV64I Base Instruction Set
# CHECK: :[[@LINE-3]]:6: note: register pair must start with x8, x10, x12, or x14
## GPRPairNoX0
c.ldsp x0, 4(sp)
# CHECK: :[[@LINE-1]]:1: error: invalid instruction, any one of the following would fix this:
-# CHECK: :[[@LINE-2]]:9: note: register must be a GPR excluding zero (x0)
+# CHECK: :[[@LINE-2]]:1: note: instruction requires the following: RV64I Base Instruction Set
# CHECK: :[[@LINE-3]]:9: note: register pair must start with an even GPR other than x0
c.ldsp zero, 4(sp)
# CHECK: :[[@LINE-1]]:1: error: invalid instruction, any one of the following would fix this:
-# CHECK: :[[@LINE-2]]:9: note: register must be a GPR excluding zero (x0)
+# CHECK: :[[@LINE-2]]:1: note: instruction requires the following: RV64I Base Instruction Set
# CHECK: :[[@LINE-3]]:9: note: register pair must start with an even GPR other than x0
## uimm9_lsb000
@@ -29,12 +29,12 @@ c.sdsp t1, -8(sp) # CHECK: :[[@LINE]]:12: error: immediate must be a multiple of
## uimm8_lsb000
c.ld s0, -8(sp)
# CHECK: :[[@LINE-1]]:1: error: invalid instruction, any one of the following would fix this:
-# CHECK: :[[@LINE-2]]:7: note: register must be a GPR from x8 to x15
+# CHECK: :[[@LINE-2]]:1: note: instruction requires the following: RV64I Base Instruction Set
# CHECK: :[[@LINE-3]]:11: note: immediate must be a multiple of 8 bytes in the range [0, 248]
c.sd s0, 256(sp)
# CHECK: :[[@LINE-1]]:1: error: invalid instruction, any one of the following would fix this:
-# CHECK: :[[@LINE-2]]:7: note: register must be a GPR from x8 to x15
+# CHECK: :[[@LINE-2]]:1: note: instruction requires the following: RV64I Base Instruction Set
# CHECK: :[[@LINE-3]]:11: note: immediate must be a multiple of 8 bytes in the range [0, 248]
# Invalid register names
diff --git a/llvm/test/MC/RISCV/rv32zdinx-invalid.s b/llvm/test/MC/RISCV/rv32zdinx-invalid.s
index 172f4d6940e91..7aa49c9bcee9b 100644
--- a/llvm/test/MC/RISCV/rv32zdinx-invalid.s
+++ b/llvm/test/MC/RISCV/rv32zdinx-invalid.s
@@ -8,7 +8,7 @@ flw fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following
fadd.d fa0, fa1, fa2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'D' (Double-Precision Floating-Point){{$}}
# Invalid instructions
-fsw a5, 12(sp) # CHECK: :[[@LINE]]:5: error: register must be a FPR
+fsw a5, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'F' (Single-Precision Floating-Point)
fmv.x.w s0, s1 # CHECK: :[[@LINE]]:1: error: invalid instruction
# Invalid register names
diff --git a/llvm/test/MC/RISCV/rv32zfh-invalid.s b/llvm/test/MC/RISCV/rv32zfh-invalid.s
index 5cdca074f469c..139b8af37b46a 100644
--- a/llvm/test/MC/RISCV/rv32zfh-invalid.s
+++ b/llvm/test/MC/RISCV/rv32zfh-invalid.s
@@ -32,7 +32,9 @@ fnmsub.h f18, f19, f20, f21, 0b111 # CHECK: :[[@LINE]]:30: error: operand must b
# Integer registers where FP regs are expected
fadd.h a2, a1, a0 # CHECK: :[[@LINE]]:1: error: invalid instruction, any one of the following would fix this:
# CHECK: :[[@LINE-1]]:8: note: register must be a FPR
-# CHECK: :[[@LINE-2]]:8: note: register must be a GPR when used as an FP operand
+# CHECK: :[[@LINE-2]]:1: note: instruction requires the following: 'Zhinx' (Half Float in Integer)
# FP registers where integer regs are expected
-fcvt.wu.h ft2, a1 # CHECK: :[[@LINE]]:11: error: register must be a GPR
+fcvt.wu.h ft2, a1 # CHECK: :[[@LINE]]:1: error: invalid instruction, any one of the following would fix this:
+# CHECK: :[[@LINE-1]]:11: note: register must be a GPR
+# CHECK: :[[@LINE-2]]:1: note: instruction requires the following: 'Zhinx' (Half Float in Integer)
diff --git a/llvm/test/MC/RISCV/rv32zfinx-invalid.s b/llvm/test/MC/RISCV/rv32zfinx-invalid.s
index 5c47ad769f659..ec2335e3e7e2a 100644
--- a/llvm/test/MC/RISCV/rv32zfinx-invalid.s
+++ b/llvm/test/MC/RISCV/rv32zfinx-invalid.s
@@ -5,7 +5,7 @@ flw fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following
fadd.s fa0, fa1, fa2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'F' (Single-Precision Floating-Point){{$}}
# Invalid instructions
-fsw a5, 12(sp) # CHECK: :[[@LINE]]:5: error: register must be a FPR
+fsw a5, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'F' (Single-Precision Floating-Point)
fmv.x.w s0, s1 # CHECK: :[[@LINE]]:1: error: invalid instruction
fadd.d t1, t3, t5 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zdinx' (Double in Integer){{$}}
diff --git a/llvm/test/MC/RISCV/rv32zhinx-invalid.s b/llvm/test/MC/RISCV/rv32zhinx-invalid.s
index 7077b41cba368..a1bd3116d6d1c 100644
--- a/llvm/test/MC/RISCV/rv32zhinx-invalid.s
+++ b/llvm/test/MC/RISCV/rv32zhinx-invalid.s
@@ -5,7 +5,7 @@ flw fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following
fadd.h fa0, fa1, fa2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point){{$}}
# Invalid instructions
-fsw a5, 12(sp) # CHECK: :[[@LINE]]:5: error: register must be a FPR
+fsw a5, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'F' (Single-Precision Floating-Point)
fmv.x.h s0, s1 # CHECK: :[[@LINE]]:1: error: invalid instruction
# Invalid register names
diff --git a/llvm/test/MC/RISCV/rv32zhinxmin-invalid.s b/llvm/test/MC/RISCV/rv32zhinxmin-invalid.s
index 94bede5c4b46a..86eacff480885 100644
--- a/llvm/test/MC/RISCV/rv32zhinxmin-invalid.s
+++ b/llvm/test/MC/RISCV/rv32zhinxmin-invalid.s
@@ -5,7 +5,7 @@ flw fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following
fcvt.h.s fa0, fa1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal){{$}}
# Invalid instructions
-fsw a5, 12(sp) # CHECK: :[[@LINE]]:5: error: register must be a FPR
+fsw a5, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'F' (Single-Precision Floating-Point)
fmv.x.h s0, s1 # CHECK: :[[@LINE]]:1: error: invalid instruction
# Invalid register names
diff --git a/llvm/test/MC/RISCV/rv64d-invalid.s b/llvm/test/MC/RISCV/rv64d-invalid.s
index 9a211986f6765..79a8bcbf41d8c 100644
--- a/llvm/test/MC/RISCV/rv64d-invalid.s
+++ b/llvm/test/MC/RISCV/rv64d-invalid.s
@@ -1,17 +1,21 @@
# RUN: not llvm-mc -triple riscv64 -mattr=+d < %s 2>&1 | FileCheck %s
# Integer registers where FP regs are expected
-fcvt.l.d ft0, a0 # CHECK: :[[@LINE]]:10: error: register must be a GPR
-fcvt.lu.d ft1, a1 # CHECK: :[[@LINE]]:11: error: register must be a GPR
+fcvt.l.d ft0, a0 # CHECK: :[[@LINE]]:1: error: invalid instruction, any one of the following would fix this:
+# CHECK: :[[@LINE-1]]:10: note: register must be a GPR
+# CHECK: :[[@LINE-2]]:1: note: instruction requires the following: 'Zdinx' (Double in Integer)
+fcvt.lu.d ft1, a1 # CHECK: :[[@LINE]]:1: error: invalid instruction, any one of the following would fix this:
+# CHECK: :[[@LINE-1]]:11: note: register must be a GPR
+# CHECK: :[[@LINE-2]]:1: note: instruction requires the following: 'Zdinx' (Double in Integer)
fmv.x.d ft2, a2 # CHECK: :[[@LINE]]:9: error: register must be a GPR
# FP registers where integer regs are expected
fcvt.d.l a3, ft3 # CHECK: :[[@LINE]]:1: error: invalid instruction, any one of the following would fix this:
# CHECK: :[[@LINE-1]]:10: note: register must be a FPR
-# CHECK: :[[@LINE-2]]:10: note: register must be a GPR when used as an FP operand
+# CHECK: :[[@LINE-2]]:1: note: instruction requires the following: 'Zdinx' (Double in Integer)
fcvt.d.lu a4, ft4 # CHECK: :[[@LINE]]:1: error: invalid instruction, any one of the following would fix this:
# CHECK: :[[@LINE-1]]:11: note: register must be a FPR
-# CHECK: :[[@LINE-2]]:11: note: register must be a GPR when used as an FP operand
+# CHECK: :[[@LINE-2]]:1: note: instruction requires the following: 'Zdinx' (Double in Integer)
fmv.d.x a5, ft5 # CHECK: :[[@LINE]]:9: error: register must be a FPR
diff --git a/llvm/test/MC/RISCV/rv64f-invalid.s b/llvm/test/MC/RISCV/rv64f-invalid.s
index d547a27ee497d..b11e124712781 100644
--- a/llvm/test/MC/RISCV/rv64f-invalid.s
+++ b/llvm/test/MC/RISCV/rv64f-invalid.s
@@ -1,14 +1,18 @@
# RUN: not llvm-mc -triple riscv64 -mattr=+f < %s 2>&1 | FileCheck %s
# Integer registers where FP regs are expected
-fcvt.l.s ft0, a0 # CHECK: :[[@LINE]]:10: error: register must be a GPR
-fcvt.lu.s ft1, a1 # CHECK: :[[@LINE]]:11: error: register must be a GPR
+fcvt.l.s ft0, a0 # CHECK: :[[@LINE]]:1: error: invalid instruction, any one of the following would fix this:
+# CHECK: :[[@LINE-1]]:10: note: register must be a GPR
+# CHECK: :[[@LINE-2]]:1: note: instruction requires the following: 'Zfinx' (Float in Integer)
+fcvt.lu.s ft1, a1 # CHECK: :[[@LINE]]:1: error: invalid instruction, any one of the following would fix this:
+# CHECK: :[[@LINE-1]]:11: note: register must be a GPR
+# CHECK: :[[@LINE-2]]:1: note: instruction requires the following: 'Zfinx' (Float in Integer)
# FP registers where integer regs are expected
fcvt.s.l a2, ft2 # CHECK: :[[@LINE]]:1: error: invalid instruction, any one of the following would fix this:
# CHECK: :[[@LINE-1]]:10: note: register must be a FPR
-# CHECK: :[[@LINE-2]]:10: note: register must be a GPR when used as an FP operand
+# CHECK: :[[@LINE-2]]:1: note: instruction requires the following: 'Zfinx' (Float in Integer)
fcvt.s.lu a3, ft3 # CHECK: :[[@LINE]]:1: error: invalid instruction, any one of the following would fix this:
# CHECK: :[[@LINE-1]]:11: note: register must be a FPR
-# CHECK: :[[@LINE-2]]:11: note: register must be a GPR when used as an FP operand
+# CHECK: :[[@LINE-2]]:1: note: instruction requires the following: 'Zfinx' (Float in Integer)
diff --git a/llvm/test/MC/RISCV/rv64xtheadmemidx-invalid.s b/llvm/test/MC/RISCV/rv64xtheadmemidx-invalid.s
index 0b3d8a7040e78..5e38d155f5840 100644
--- a/llvm/test/MC/RISCV/rv64xtheadmemidx-invalid.s
+++ b/llvm/test/MC/RISCV/rv64xtheadmemidx-invalid.s
@@ -1,13 +1,35 @@
-# RUN: not llvm-mc -triple riscv32 -mattr=+xtheadmemidx < %s 2>&1 | FileCheck %s
-# RUN: not llvm-mc -triple riscv64 -mattr=+xtheadmemidx < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv32 -mattr=+xtheadmemidx < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-RV32 %s
+# RUN: not llvm-mc -triple riscv64 -mattr=+xtheadmemidx < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-RV64 %s
-th.ldia 0(a0), (a1), 0, 0 # CHECK: :[[@LINE]]:10: error: register must be a GPR
-th.ldib a0, 2(a1), 15, 1 # CHECK: :[[@LINE]]:14: error: expected '('
-th.lwia a0, (a1), 30, 2 # CHECK: :[[@LINE]]:20: error: immediate must be an integer in the range [-16, 15]
-th.lwib a0, (a1), -16, 43 # CHECK: :[[@LINE]]:25: error: immediate must be an integer in the range [0, 3]
-th.lhib a0, (a1), -17, 3 # CHECK: :[[@LINE]]:20: error: immediate must be an integer in the range [-16, 15]
-th.lrb -2(a0), a1, a2, 0 # CHECK: :[[@LINE]]:9: error: register must be a GPR
-th.lrw a0, 3(a1), a2, 1 # CHECK: :[[@LINE]]:13: error: register must be a GPR
-th.lrw a0, a1, 4(a2), 2 # CHECK: :[[@LINE]]:17: error: register must be a GPR
-th.lrh a0, a1, a2, 5 # CHECK: :[[@LINE]]:21: error: immediate must be an integer in the range [0, 3]
-th.lrhu a0, a1, a2, -1 # CHECK: :[[@LINE]]:22: error: immediate must be an integer in the range [0, 3]
+# CHECK-RV32: :[[@LINE+2]]:1: error: instruction requires the following: RV64I Base Instruction Set
+# CHECK-RV64: :[[@LINE+1]]:9: error: register must be a GPR
+th.ldia 0(a0), (a1), 0, 0
+# CHECK-RV32: :[[@LINE+2]]:1: error: instruction requires the following: RV64I Base Instruction Set
+# CHECK-RV64: :[[@LINE+1]]:14: error: expected '('
+th.ldib a0, 2(a1), 15, 1
+# CHECK-RV32: :[[@LINE+2]]:20: error: immediate must be an integer in the range [-16, 15]
+# CHECK-RV64: :[[@LINE+1]]:20: error: immediate must be an integer in the range [-16, 15]
+th.lwia a0, (a1), 30, 2
+# CHECK-RV32: :[[@LINE+2]]:25: error: immediate must be an integer in the range [0, 3]
+# CHECK-RV64: :[[@LINE+1]]:25: error: immediate must be an integer in the range [0, 3]
+th.lwib a0, (a1), -16, 43
+# CHECK-RV32: :[[@LINE+2]]:20: error: immediate must be an integer in the range [-16, 15]
+# CHECK-RV64: :[[@LINE+1]]:20: error: immediate must be an integer in the range [-16, 15]
+th.lhib a0, (a1), -17, 3
+# CHECK-RV32: :[[@LINE+2]]:9: error: register must be a GPR
+# CHECK-RV64: :[[@LINE+1]]:9: error: register must be a GPR
+th.lrb -2(a0), a1, a2, 0
+# CHECK-RV32: :[[@LINE+2]]:13: error: register must be a GPR
+# CHECK-RV64: :[[@LINE+1]]:13: error: register must be a GPR
+th.lrw a0, 3(a1), a2, 1
+# CHECK-RV32: :[[@LINE+2]]:17: error: register must be a GPR
+# CHECK-RV64: :[[@LINE+1]]:17: error: register must be a GPR
+th.lrw a0, a1, 4(a2), 2
+# CHECK-RV32: :[[@LINE+2]]:21: error: immediate must be an integer in the range [0, 3]
+# CHECK-RV64: :[[@LINE+1]]:21: error: immediate must be an integer in the range [0, 3]
+th.lrh a0, a1, a2, 5
+# CHECK-RV32: :[[@LINE+2]]:22: error: immediate must be an integer in the range [0, 3]
+# CHECK-RV64: :[[@LINE+1]]:22: error: immediate must be an integer in the range [0, 3]
+th.lrhu a0, a1, a2, -1
diff --git a/llvm/test/MC/RISCV/rv64zdinx-invalid.s b/llvm/test/MC/RISCV/rv64zdinx-invalid.s
index 9c2c38e8d10fa..9d1431bb30792 100644
--- a/llvm/test/MC/RISCV/rv64zdinx-invalid.s
+++ b/llvm/test/MC/RISCV/rv64zdinx-invalid.s
@@ -5,7 +5,7 @@ fld fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following
ld a0, -2049(a1) # CHECK: :[[@LINE]]:8: error: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo specifier or an integer in the range [-2048, 2047]
# Invalid instructions
-fsd a5, 12(sp) # CHECK: :[[@LINE]]:5: error: register must be a FPR
+fsd a5, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'D' (Double-Precision Floating-Point)
sd fa4, 64(sp) # CHECK: :[[@LINE]]:4: error: register must be a GPR
fmv.x.d t2, a2 # CHECK: :[[@LINE]]:1: error: invalid instruction
fmv.d.x a5, t5 # CHECK: :[[@LINE]]:1: error: invalid instruction
diff --git a/llvm/test/MC/RISCV/rv64zfh-invalid.s b/llvm/test/MC/RISCV/rv64zfh-invalid.s
index 4c5a21c690616..b2513d47e3727 100644
--- a/llvm/test/MC/RISCV/rv64zfh-invalid.s
+++ b/llvm/test/MC/RISCV/rv64zfh-invalid.s
@@ -7,13 +7,23 @@ flh ft1, -2049(a0) # CHECK: :[[@LINE]]:10: error: operand must be a symbol with
fsh ft2, 2048(a1) # CHECK: :[[@LINE]]:10: error: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo specifier or an integer in the range [-2048, 2047]
# Integer registers where FP regs are expected
-fcvt.l.h ft0, a0 # CHECK: :[[@LINE]]:10: error: register must be a GPR
-fcvt.lu.h ft1, a1 # CHECK: :[[@LINE]]:11: error: register must be a GPR
+fcvt.l.h ft0, a0
+# CHECK: :[[@LINE-1]]:1: error: invalid instruction, any one of the following would fix this:
+# CHECK: :[[@LINE-2]]:10: note: register must be a GPR
+# CHECK: :[[@LINE-3]]:1: note: instruction requires the following: 'Zhinx' (Half Float in Integer)
+
+fcvt.lu.h ft1, a1
+# CHECK: :[[@LINE-1]]:1: error: invalid instruction, any one of the following would fix this:
+# CHECK: :[[@LINE-2]]:11: note: register must be a GPR
+# CHECK: :[[@LINE-3]]:1: note: instruction requires the following: 'Zhinx' (Half Float in Integer)
# FP registers where integer regs are expected
-fcvt.h.l a2, ft2 # CHECK: :[[@LINE]]:1: error: invalid instruction, any one of the following would fix this:
-# CHECK: :[[@LINE-1]]:10: note: register must be a FPR
-# CHECK: :[[@LINE-2]]:10: note: register must be a GPR when used as an FP operand
-fcvt.h.lu a3, ft3 # CHECK: :[[@LINE]]:1: error: invalid instruction, any one of the following would fix this:
-# CHECK: :[[@LINE-1]]:11: note: register must be a FPR
-# CHECK: :[[@LINE-2]]:11: note: register must be a GPR when used as an FP operand
+fcvt.h.l a2, ft2
+# CHECK: :[[@LINE-1]]:1: error: invalid instruction, any one of the following would fix this:
+# CHECK: :[[@LINE-2]]:10: note: register must be a FPR
+# CHECK: :[[@LINE-3]]:1: note: instruction requires the following: 'Zhinx' (Half Float in Integer)
+
+fcvt.h.lu a3, ft3
+# CHECK: :[[@LINE-1]]:1: error: invalid instruction, any one of the following would fix this:
+# CHECK: :[[@LINE-2]]:11: note: register must be a FPR
+# CHECK: :[[@LINE-3]]:1: note: instruction requires the following: 'Zhinx' (Half Float in Integer)
diff --git a/llvm/test/MC/RISCV/rv64zfinx-invalid.s b/llvm/test/MC/RISCV/rv64zfinx-invalid.s
index b5b4a27df1ab1..a065eedabf39a 100644
--- a/llvm/test/MC/RISCV/rv64zfinx-invalid.s
+++ b/llvm/test/MC/RISCV/rv64zfinx-invalid.s
@@ -4,7 +4,7 @@
flw fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'F' (Single-Precision Floating-Point){{$}}
# Invalid instructions
-fsw a5, 12(sp) # CHECK: :[[@LINE]]:5: error: register must be a FPR
+fsw a5, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'F' (Single-Precision Floating-Point)
fmv.x.w t2, a2 # CHECK: :[[@LINE]]:1: error: invalid instruction
fmv.w.x a5, t5 # CHECK: :[[@LINE]]:1: error: invalid instruction
diff --git a/llvm/test/MC/RISCV/rv64zhinx-invalid.s b/llvm/test/MC/RISCV/rv64zhinx-invalid.s
index e2fc5151434bc..87bfcb497d6f1 100644
--- a/llvm/test/MC/RISCV/rv64zhinx-invalid.s
+++ b/llvm/test/MC/RISCV/rv64zhinx-invalid.s
@@ -4,7 +4,7 @@
flh fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal) or 'Zfbfmin' (Scalar BF16 Converts){{$}}
# Invalid instructions
-fsh a5, 12(sp) # CHECK: :[[@LINE]]:5: error: register must be a FPR
+fsh a5, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal) or 'Zfbfmin' (Scalar BF16 Converts)
fmv.x.h t2, a2 # CHECK: :[[@LINE]]:1: error: invalid instruction
fmv.h.x a5, t5 # CHECK: :[[@LINE]]:1: error: invalid instruction
diff --git a/llvm/test/MC/RISCV/rv64zhinxmin-invalid.s b/llvm/test/MC/RISCV/rv64zhinxmin-invalid.s
index 97453be594f17..72755f9e052a4 100644
--- a/llvm/test/MC/RISCV/rv64zhinxmin-invalid.s
+++ b/llvm/test/MC/RISCV/rv64zhinxmin-invalid.s
@@ -4,10 +4,10 @@
flh fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal) or 'Zfbfmin' (Scalar BF16 Converts){{$}}
# Invalid instructions
-fsh a5, 12(sp) # CHECK: :[[@LINE]]:5: error: register must be a FPR
+fsh a5, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal) or 'Zfbfmin' (Scalar BF16 Converts)
fmv.x.h t2, a2 # CHECK: :[[@LINE]]:1: error: invalid instruction
fmv.h.x a5, t5 # CHECK: :[[@LINE]]:1: error: invalid instruction
# FP registers where integer regs are expected
-fcvt.d.h a0, fa2 # CHECK: :[[@LINE]]:10: error: register must be an even-numbered GPR when used as an FP operand
+fcvt.d.h a0, fa2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zdinx' (Double in Integer), RV32I Base Instruction Set
fcvt.h.d a0, fa2 # CHECK: :[[@LINE]]:1: error: invalid instruction
diff --git a/llvm/test/MC/RISCV/tlsdesc.s b/llvm/test/MC/RISCV/tlsdesc.s
index 32a110d789392..e4feb0cbef35f 100644
--- a/llvm/test/MC/RISCV/tlsdesc.s
+++ b/llvm/test/MC/RISCV/tlsdesc.s
@@ -5,8 +5,8 @@
# RUN: llvm-mc -filetype=obj -triple riscv64 < %s --mattr=+relax | llvm-objdump -dr -M no-aliases - | FileCheck %s --check-prefixes=INST,RELAX,RV64
-# RUN: not llvm-mc -triple riscv32 < %s --defsym RV32=1 --defsym ERR=1 2>&1 | FileCheck %s --check-prefixes=ERR --implicit-check-not="error:" --implicit-check-not="note:"
-# RUN: not llvm-mc -triple riscv64 < %s --defsym ERR=1 2>&1 | FileCheck %s --check-prefixes=ERR --implicit-check-not="error:" --implicit-check-not="note:"
+# RUN: not llvm-mc -triple riscv32 < %s --defsym RV32=1 --defsym ERR=1 2>&1 | FileCheck %s --check-prefixes=ERR,ERR-RV32
+# RUN: not llvm-mc -triple riscv64 < %s --defsym ERR=1 2>&1 | FileCheck %s --check-prefixes=ERR,ERR-RV64
start: # @start
# %bb.0: # %entry
@@ -50,10 +50,14 @@ start: # @start
lw a0, t0, %tlsdesc_load_lo(a_symbol)
# ERR: :[[#@LINE-1]]:15: error: unexpected extra operand for instruction
lw a0, t0, %tlsdesc_load_lo(a_symbol)(a4)
-# ERR: :[[#@LINE-1]]:2: error: invalid instruction, any one of the following would fix this:
-# ERR: :[[#@LINE-2]]:15: note: unexpected extra operand for instruction
-# ERR: :[[#@LINE-3]]:11: note: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo specifier or an integer in the range [-2048, 2047]
-# ERR: :[[#@LINE-4]]:11: note: immediate must be an integer in the range [-2048, 2047]
+# ERR-RV32: :[[#@LINE-1]]:2: error: invalid instruction, any one of the following would fix this:
+# ERR-RV32: :[[#@LINE-2]]:15: note: unexpected extra operand for instruction
+# ERR-RV32: :[[#@LINE-3]]:11: note: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo specifier or an integer in the range [-2048, 2047]
+# ERR-RV32: :[[#@LINE-4]]:11: note: immediate must be an integer in the range [-2048, 2047]
+# ERR-RV64: :[[#@LINE-5]]:2: error: invalid instruction, any one of the following would fix this:
+# ERR-RV64: :[[#@LINE-6]]:15: note: unexpected extra operand for instruction
+# ERR-RV64: :[[#@LINE-7]]:11: note: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo specifier or an integer in the range [-2048, 2047]
+# ERR-RV64: :[[#@LINE-8]]:2: note: instruction requires the following: RV32I Base Instruction Set
addi a0, t0, %tlsdesc_add_lo(a_symbol)(a4)
# ERR: :[[#@LINE-1]]:41: error: unexpected extra operand for instruction
diff --git a/llvm/test/MC/RISCV/xqcia-invalid.s b/llvm/test/MC/RISCV/xqcia-invalid.s
index 0f8ca1649ad4b..c4a51a40a0011 100644
--- a/llvm/test/MC/RISCV/xqcia-invalid.s
+++ b/llvm/test/MC/RISCV/xqcia-invalid.s
@@ -169,7 +169,7 @@ qc.wrap x3, x30, x23
# CHECK-PLUS: :[[@LINE+2]]:10: error: register must be a GPR excluding zero (x0)
-# CHECK-MINUS: :[[@LINE+1]]:10: error: register must be a GPR excluding zero (x0)
+# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcia' (Qualcomm uC Arithmetic Extension)
qc.wrapi x0, 12, 2047
# CHECK-PLUS: :[[@LINE+2]]:10: error: register must be a GPR excluding zero (x0)
diff --git a/llvm/test/MC/RISCV/xqciac-invalid.s b/llvm/test/MC/RISCV/xqciac-invalid.s
index 319624a68e6f4..511ec5de0e868 100644
--- a/llvm/test/MC/RISCV/xqciac-invalid.s
+++ b/llvm/test/MC/RISCV/xqciac-invalid.s
@@ -20,7 +20,7 @@ qc.c.muliadd x10, x15, 20
# CHECK-PLUS: :[[@LINE+2]]:12: error: register must be a GPR excluding zero (x0)
-# CHECK-MINUS: :[[@LINE+1]]:12: error: register must be a GPR excluding zero (x0)
+# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqciac' (Qualcomm uC Load-Store Address Calculation Extension)
qc.muliadd x0, x10, 1048577
# CHECK-PLUS: :[[@LINE+2]]:15: error: too few operands for instruction
@@ -35,7 +35,7 @@ qc.muliadd x10, x15, 577
# CHECK-PLUS: :[[@LINE+2]]:11: error: register must be a GPR excluding zero (x0)
-# CHECK-MINUS: :[[@LINE+1]]:11: error: register must be a GPR excluding zero (x0)
+# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqciac' (Qualcomm uC Load-Store Address Calculation Extension)
qc.shladd 0, x10, 1048577
# CHECK-PLUS: :[[@LINE+2]]:14: error: too few operands for instruction
diff --git a/llvm/test/MC/RISCV/xqciio-invalid.s b/llvm/test/MC/RISCV/xqciio-invalid.s
index 0627f00ac5df5..05ddcc9e47eac 100644
--- a/llvm/test/MC/RISCV/xqciio-invalid.s
+++ b/llvm/test/MC/RISCV/xqciio-invalid.s
@@ -12,9 +12,7 @@ qc.outw x5, 2048(10)
# CHECK-PLUS: :[[@LINE+1]]:13: note: immediate must be a multiple of 4 bytes in the range [0, 16380]
qc.outw x5, x10
-# CHECK-MINUS: :[[@LINE+3]]:1: error: invalid instruction, any one of the following would fix this:
-# CHECK-MINUS: :[[@LINE+2]]:13: note: expected '('
-# CHECK-MINUS: :[[@LINE+1]]:13: note: immediate must be a multiple of 4 bytes in the range [0, 16380]
+# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqciio' (Qualcomm uC External Input Output Extension)
qc.outw x5, x10
# CHECK-PLUS: :[[@LINE+1]]:13: error: immediate must be a multiple of 4 bytes in the range [0, 16380]
@@ -32,13 +30,11 @@ qc.inw x23, 16380(17)
# CHECK-PLUS: :[[@LINE+1]]:13: note: immediate must be a multiple of 4 bytes in the range [0, 16380]
qc.inw x23, x17
-# CHECK-MINUS: :[[@LINE+3]]:1: error: invalid instruction, any one of the following would fix this:
-# CHECK-MINUS: :[[@LINE+2]]:13: note: expected '('
-# CHECK-MINUS: :[[@LINE+1]]:13: note: immediate must be a multiple of 4 bytes in the range [0, 16380]
+# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqciio' (Qualcomm uC External Input Output Extension)
qc.inw x23, x17
# CHECK-PLUS: :[[@LINE+2]]:8: error: register must be a GPR excluding zero (x0)
-# CHECK-MINUS: :[[@LINE+1]]:8: error: register must be a GPR excluding zero (x0)
+# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqciio' (Qualcomm uC External Input Output Extension)
qc.inw x0, 16380(x17)
# CHECK-PLUS: :[[@LINE+1]]:13: error: immediate must be a multiple of 4 bytes in the range [0, 16380]
diff --git a/llvm/test/MC/RISCV/xqcili-invalid.s b/llvm/test/MC/RISCV/xqcili-invalid.s
index b6a5f0144f4ca..81775ee4367c8 100644
--- a/llvm/test/MC/RISCV/xqcili-invalid.s
+++ b/llvm/test/MC/RISCV/xqcili-invalid.s
@@ -5,7 +5,7 @@
# RUN: | FileCheck -check-prefixes=CHECK-MINUS %s
# CHECK-PLUS: :[[@LINE+2]]:9: error: register must be a GPR excluding zero (x0)
-# CHECK-MINUS: :[[@LINE+1]]:9: error: register must be a GPR
+# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcili' (Qualcomm uC Load Large Immediate Extension)
qc.e.li 9, 33554432
# CHECK-PLUS: :[[@LINE+2]]:11: error: too few operands for instruction
diff --git a/llvm/test/MC/RISCV/xqcilo-invalid.s b/llvm/test/MC/RISCV/xqcilo-invalid.s
index 47362dcf5ba69..43ab53053399b 100644
--- a/llvm/test/MC/RISCV/xqcilo-invalid.s
+++ b/llvm/test/MC/RISCV/xqcilo-invalid.s
@@ -4,8 +4,10 @@
# RUN: not llvm-mc -triple riscv32 -mattr=-xqcilo < %s 2>&1 \
# RUN: | FileCheck -check-prefixes=CHECK-MINUS %s
-# CHECK-PLUS: :[[@LINE+2]]:9: error: register must be a GPR
-# CHECK-MINUS: :[[@LINE+1]]:9: error: register must be a GPR
+# CHECK-PLUS: :[[@LINE+4]]:9: error: register must be a GPR
+# CHECK-MINUS: :[[@LINE+3]]:1: error: invalid instruction, any one of the following would fix this:
+# CHECK-MINUS: :[[@LINE+2]]:1: note: instruction requires the following: 'Xqcili' (Qualcomm uC Load Large Immediate Extension), 'Xqcilo' (Qualcomm uC Large Offset Load Store Extension)
+# CHECK-MINUS: :[[@LINE+1]]:1: note: instruction requires the following: 'Xqcilo' (Qualcomm uC Large Offset Load Store Extension)
qc.e.lb 11, 12(x10)
# CHECK-PLUS: :[[@LINE+2]]:12: error: too few operands for instruction
@@ -19,8 +21,10 @@ qc.e.lb x11, 33445562212(x10)
qc.e.lb x11, 12(x10)
-# CHECK-PLUS: :[[@LINE+2]]:10: error: register must be a GPR
-# CHECK-MINUS: :[[@LINE+1]]:10: error: register must be a GPR
+# CHECK-PLUS: :[[@LINE+4]]:10: error: register must be a GPR
+# CHECK-MINUS: :[[@LINE+3]]:1: error: invalid instruction, any one of the following would fix this:
+# CHECK-MINUS: :[[@LINE+2]]:1: note: instruction requires the following: 'Xqcili' (Qualcomm uC Load Large Immediate Extension), 'Xqcilo' (Qualcomm uC Large Offset Load Store Extension)
+# CHECK-MINUS: :[[@LINE+1]]:1: note: instruction requires the following: 'Xqcilo' (Qualcomm uC Large Offset Load Store Extension)
qc.e.lbu 11, 12(x10)
# CHECK-PLUS: :[[@LINE+2]]:13: error: too few operands for instruction
@@ -34,8 +38,10 @@ qc.e.lbu x11, 33445562212(x10)
qc.e.lbu x11, 12(x10)
-# CHECK-PLUS: :[[@LINE+2]]:9: error: register must be a GPR
-# CHECK-MINUS: :[[@LINE+1]]:9: error: register must be a GPR
+# CHECK-PLUS: :[[@LINE+4]]:9: error: register must be a GPR
+# CHECK-MINUS: :[[@LINE+3]]:1: error: invalid instruction, any one of the following would fix this:
+# CHECK-MINUS: :[[@LINE+2]]:1: note: instruction requires the following: 'Xqcili' (Qualcomm uC Load Large Immediate Extension), 'Xqcilo' (Qualcomm uC Large Offset Load Store Extension)
+# CHECK-MINUS: :[[@LINE+1]]:1: note: instruction requires the following: 'Xqcilo' (Qualcomm uC Large Offset Load Store Extension)
qc.e.lh 11, 12(x10)
# CHECK-PLUS: :[[@LINE+2]]:12: error: too few operands for instruction
@@ -49,8 +55,10 @@ qc.e.lh x11, 33445562212(x10)
qc.e.lh x11, 12(x10)
-# CHECK-PLUS: :[[@LINE+2]]:10: error: register must be a GPR
-# CHECK-MINUS: :[[@LINE+1]]:10: error: register must be a GPR
+# CHECK-PLUS: :[[@LINE+4]]:10: error: register must be a GPR
+# CHECK-MINUS: :[[@LINE+3]]:1: error: invalid instruction, any one of the following would fix this:
+# CHECK-MINUS: :[[@LINE+2]]:1: note: instruction requires the following: 'Xqcili' (Qualcomm uC Load Large Immediate Extension), 'Xqcilo' (Qualcomm uC Large Offset Load Store Extension)
+# CHECK-MINUS: :[[@LINE+1]]:1: note: instruction requires the following: 'Xqcilo' (Qualcomm uC Large Offset Load Store Extension)
qc.e.lhu 11, 12(x10)
# CHECK-PLUS: :[[@LINE+2]]:13: error: too few operands for instruction
@@ -64,8 +72,10 @@ qc.e.lhu x11, 33445562212(x10)
qc.e.lhu x11, 12(x10)
-# CHECK-PLUS: :[[@LINE+2]]:9: error: register must be a GPR
-# CHECK-MINUS: :[[@LINE+1]]:9: error: register must be a GPR
+# CHECK-PLUS: :[[@LINE+4]]:9: error: register must be a GPR
+# CHECK-MINUS: :[[@LINE+3]]:1: error: invalid instruction, any one of the following would fix this:
+# CHECK-MINUS: :[[@LINE+2]]:1: note: instruction requires the following: 'Xqcili' (Qualcomm uC Load Large Immediate Extension), 'Xqcilo' (Qualcomm uC Large Offset Load Store Extension)
+# CHECK-MINUS: :[[@LINE+1]]:1: note: instruction requires the following: 'Xqcilo' (Qualcomm uC Large Offset Load Store Extension)
qc.e.lw 11, 12(x10)
# CHECK-PLUS: :[[@LINE+2]]:12: error: too few operands for instruction
@@ -79,8 +89,10 @@ qc.e.lw x11, 33445562212(x10)
qc.e.lw x11, 12(x10)
-# CHECK-PLUS: :[[@LINE+2]]:9: error: register must be a GPR
-# CHECK-MINUS: :[[@LINE+1]]:9: error: register must be a GPR
+# CHECK-PLUS: :[[@LINE+4]]:9: error: register must be a GPR
+# CHECK-MINUS: :[[@LINE+3]]:1: error: invalid instruction, any one of the following would fix this:
+# CHECK-MINUS: :[[@LINE+2]]:1: note: instruction requires the following: 'Xqcili' (Qualcomm uC Load Large Immediate Extension), 'Xqcilo' (Qualcomm uC Large Offset Load Store Extension)
+# CHECK-MINUS: :[[@LINE+1]]:1: note: instruction requires the following: 'Xqcilo' (Qualcomm uC Large Offset Load Store Extension)
qc.e.sb 11, 12(x10)
# CHECK-PLUS: :[[@LINE+2]]:12: error: too few operands for instruction
@@ -94,8 +106,10 @@ qc.e.sb x11, 33445562212(x10)
qc.e.sb x11, 12(x10)
-# CHECK-PLUS: :[[@LINE+2]]:9: error: register must be a GPR
-# CHECK-MINUS: :[[@LINE+1]]:9: error: register must be a GPR
+# CHECK-PLUS: :[[@LINE+4]]:9: error: register must be a GPR
+# CHECK-MINUS: :[[@LINE+3]]:1: error: invalid instruction, any one of the following would fix this:
+# CHECK-MINUS: :[[@LINE+2]]:1: note: instruction requires the following: 'Xqcili' (Qualcomm uC Load Large Immediate Extension), 'Xqcilo' (Qualcomm uC Large Offset Load Store Extension)
+# CHECK-MINUS: :[[@LINE+1]]:1: note: instruction requires the following: 'Xqcilo' (Qualcomm uC Large Offset Load Store Extension)
qc.e.sh 11, 12(x10)
# CHECK-PLUS: :[[@LINE+2]]:12: error: too few operands for instruction
@@ -109,8 +123,10 @@ qc.e.sh x11, 33445562212(x10)
qc.e.sh x11, 12(x10)
-# CHECK-PLUS: :[[@LINE+2]]:9: error: register must be a GPR
-# CHECK-MINUS: :[[@LINE+1]]:9: error: register must be a GPR
+# CHECK-PLUS: :[[@LINE+4]]:9: error: register must be a GPR
+# CHECK-MINUS: :[[@LINE+3]]:1: error: invalid instruction, any one of the following would fix this:
+# CHECK-MINUS: :[[@LINE+2]]:1: note: instruction requires the following: 'Xqcili' (Qualcomm uC Load Large Immediate Extension), 'Xqcilo' (Qualcomm uC Large Offset Load Store Extension)
+# CHECK-MINUS: :[[@LINE+1]]:1: note: instruction requires the following: 'Xqcilo' (Qualcomm uC Large Offset Load Store Extension)
qc.e.sw 11, 12(x10)
# CHECK-PLUS: :[[@LINE+2]]:12: error: too few operands for instruction
diff --git a/llvm/test/MC/RISCV/xqcilo-pseudos-invalid.s b/llvm/test/MC/RISCV/xqcilo-pseudos-invalid.s
index 6b087979c8ccc..6b6df88e2ac53 100644
--- a/llvm/test/MC/RISCV/xqcilo-pseudos-invalid.s
+++ b/llvm/test/MC/RISCV/xqcilo-pseudos-invalid.s
@@ -7,49 +7,49 @@
# CHECK-ENABLED: [[@LINE+4]]:1: error: invalid instruction, any one of the following would fix this:
# CHECK-ENABLED: [[@LINE+3]]:13: note: operand must be a bare symbol name
# CHECK-ENABLED: [[@LINE+2]]:19: note: too few operands for instruction
-# CHECK-DISABLED: :[[@LINE+1]]:13: error: expected '('
+# CHECK-DISABLED: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcilo' (Qualcomm uC Large Offset Load Store Extension)
qc.e.lb a0, 0xf000
# CHECK-ENABLED: [[@LINE+4]]:1: error: invalid instruction, any one of the following would fix this:
# CHECK-ENABLED: [[@LINE+3]]:13: note: operand must be a bare symbol name
# CHECK-ENABLED: [[@LINE+2]]:19: note: too few operands for instruction
-# CHECK-DISABLED: :[[@LINE+1]]:13: error: expected '('
+# CHECK-DISABLED: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcilo' (Qualcomm uC Large Offset Load Store Extension)
qc.e.lb a0, 0xf000
# CHECK-ENABLED: [[@LINE+4]]:1: error: invalid instruction, any one of the following would fix this:
# CHECK-ENABLED: [[@LINE+3]]:14: note: operand must be a bare symbol name
# CHECK-ENABLED: [[@LINE+2]]:20: note: too few operands for instruction
-# CHECK-DISABLED: :[[@LINE+1]]:14: error: expected '('
+# CHECK-DISABLED: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcilo' (Qualcomm uC Large Offset Load Store Extension)
qc.e.lbu a0, 0xf000
# CHECK-ENABLED: [[@LINE+4]]:1: error: invalid instruction, any one of the following would fix this:
# CHECK-ENABLED: [[@LINE+3]]:13: note: operand must be a bare symbol name
# CHECK-ENABLED: [[@LINE+2]]:19: note: too few operands for instruction
-# CHECK-DISABLED: :[[@LINE+1]]:13: error: expected '('
+# CHECK-DISABLED: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcilo' (Qualcomm uC Large Offset Load Store Extension)
qc.e.lh a0, 0xf000
# CHECK-ENABLED: [[@LINE+4]]:1: error: invalid instruction, any one of the following would fix this:
# CHECK-ENABLED: [[@LINE+3]]:14: note: operand must be a bare symbol name
# CHECK-ENABLED: [[@LINE+2]]:20: note: too few operands for instruction
-# CHECK-DISABLED: :[[@LINE+1]]:14: error: expected '('
+# CHECK-DISABLED: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcilo' (Qualcomm uC Large Offset Load Store Extension)
qc.e.lhu a0, 0xf000
# CHECK-ENABLED: [[@LINE+4]]:1: error: invalid instruction, any one of the following would fix this:
# CHECK-ENABLED: [[@LINE+3]]:13: note: operand must be a bare symbol name
# CHECK-ENABLED: [[@LINE+2]]:19: note: too few operands for instruction
-# CHECK-DISABLED: :[[@LINE+1]]:13: error: expected '('
+# CHECK-DISABLED: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcilo' (Qualcomm uC Large Offset Load Store Extension)
qc.e.lw a0, 0xf000
# CHECK-ENABLED: [[@LINE+2]]:13: error: operand must be a bare symbol name
-# CHECK-DISABLED: [[@LINE+1]]:1: error: invalid instruction
+# CHECK-DISABLED: [[@LINE+1]]:1: error: instruction requires the following: 'Xqcilo' (Qualcomm uC Large Offset Load Store Extension)
qc.e.sb a0, 0xf000, t0
# CHECK-ENABLED: [[@LINE+2]]:13: error: operand must be a bare symbol name
-# CHECK-DISABLED: [[@LINE+1]]:1: error: invalid instruction
+# CHECK-DISABLED: [[@LINE+1]]:1: error: instruction requires the following: 'Xqcilo' (Qualcomm uC Large Offset Load Store Extension)
qc.e.sh a0, 0xf000, t0
# CHECK-ENABLED: [[@LINE+2]]:13: error: operand must be a bare symbol name
-# CHECK-DISABLED: [[@LINE+1]]:1: error: invalid instruction
+# CHECK-DISABLED: [[@LINE+1]]:1: error: instruction requires the following: 'Xqcilo' (Qualcomm uC Large Offset Load Store Extension)
qc.e.sw a0, 0xf000, t0
# CHECK-DISABLED: [[@LINE+1]]:1: error: instruction requires the following: 'Xqcili' (Qualcomm uC Load Large Immediate Extension), 'Xqcilo' (Qualcomm uC Large Offset Load Store Extension)
@@ -70,13 +70,13 @@ qc.e.sh a0, undefined, t0
qc.e.sw a0, undefined, t0
# CHECK-ENABLED: [[@LINE+2]]:22: error: too few operands for instruction
-# CHECK-DISABLED: [[@LINE+1]]:1: error: invalid instruction
+# CHECK-DISABLED: [[@LINE+1]]:1: error: instruction requires the following: 'Xqcilo' (Qualcomm uC Large Offset Load Store Extension)
qc.e.sb a0, undefined
# CHECK-ENABLED: [[@LINE+2]]:22: error: too few operands for instruction
-# CHECK-DISABLED: [[@LINE+1]]:1: error: invalid instruction
+# CHECK-DISABLED: [[@LINE+1]]:1: error: instruction requires the following: 'Xqcilo' (Qualcomm uC Large Offset Load Store Extension)
qc.e.sh a0, undefined
# CHECK-ENABLED: [[@LINE+2]]:22: error: too few operands for instruction
-# CHECK-DISABLED: [[@LINE+1]]:1: error: invalid instruction
+# CHECK-DISABLED: [[@LINE+1]]:1: error: instruction requires the following: 'Xqcilo' (Qualcomm uC Large Offset Load Store Extension)
qc.e.sw a0, undefined
diff --git a/llvm/test/MC/RISCV/xqcilsm-invalid.s b/llvm/test/MC/RISCV/xqcilsm-invalid.s
index 38e5282969970..864fd0fbefade 100644
--- a/llvm/test/MC/RISCV/xqcilsm-invalid.s
+++ b/llvm/test/MC/RISCV/xqcilsm-invalid.s
@@ -8,11 +8,11 @@
qc.swm x5, x20, 12(20)
# CHECK-PLUS: :[[@LINE+2]]:8: error: register must be a GPR excluding zero (x0)
-# CHECK-MINUS: :[[@LINE+1]]:8: error: register must be a GPR excluding zero (x0)
+# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcilsm' (Qualcomm uC Load Store Multiple Extension)
qc.swm x0, x20, 12(x3)
# CHECK-PLUS: :[[@LINE+2]]:12: error: register must be a GPR excluding zero (x0)
-# CHECK-MINUS: :[[@LINE+1]]:12: error: register must be a GPR excluding zero (x0)
+# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcilsm' (Qualcomm uC Load Store Multiple Extension)
qc.swm x5, x0, 12(x3)
# CHECK-PLUS: :[[@LINE+2]]:14: error: too few operands for instruction
@@ -30,11 +30,11 @@ qc.swm x5, x20, 12(x3)
qc.swmi x10, 4, 20(4)
# CHECK-PLUS: :[[@LINE+2]]:9: error: register must be a GPR excluding zero (x0)
-# CHECK-MINUS: :[[@LINE+1]]:9: error: register must be a GPR excluding zero (x0)
+# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcilsm' (Qualcomm uC Load Store Multiple Extension)
qc.swmi x0, 4, 20(x4)
# CHECK-PLUS: :[[@LINE+2]]:19: error: too few operands for instruction
-# CHECK-MINUS: :[[@LINE+1]]:17: error: expected '('
+# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcilsm' (Qualcomm uC Load Store Multiple Extension)
qc.swmi x10, 4, 20
# CHECK-PLUS: :[[@LINE+1]]:14: error: immediate must be an integer in the range [1, 31]
@@ -54,11 +54,11 @@ qc.swmi x10, 4, 20(x4)
qc.setwm x4, x30, 124(2)
# CHECK-PLUS: :[[@LINE+2]]:14: error: register must be a GPR excluding zero (x0)
-# CHECK-MINUS: :[[@LINE+1]]:14: error: register must be a GPR excluding zero (x0)
+# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcilsm' (Qualcomm uC Load Store Multiple Extension)
qc.setwm x4, x0, 124(x2)
# CHECK-PLUS: :[[@LINE+2]]:22: error: too few operands for instruction
-# CHECK-MINUS: :[[@LINE+1]]:19: error: expected '('
+# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcilsm' (Qualcomm uC Load Store Multiple Extension)
qc.setwm x4, x30, 124
# CHECK-PLUS: :[[@LINE+1]]:19: error: immediate must be a multiple of 4 bytes in the range [0, 124]
@@ -72,7 +72,7 @@ qc.setwm x4, x30, 124(x2)
qc.setwmi x5, 31, 12(12)
# CHECK-PLUS: :[[@LINE+2]]:21: error: too few operands for instruction
-# CHECK-MINUS: :[[@LINE+1]]:19: error: expected '('
+# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcilsm' (Qualcomm uC Load Store Multiple Extension)
qc.setwmi x5, 31, 12
# CHECK-PLUS: :[[@LINE+1]]:15: error: immediate must be an integer in the range [1, 31]
@@ -92,11 +92,11 @@ qc.setwmi x5, 31, 12(x12)
qc.lwm x7, x1, 24(20)
# CHECK-PLUS: :[[@LINE+2]]:18: error: too few operands for instruction
-# CHECK-MINUS: :[[@LINE+1]]:16: error: expected '('
+# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcilsm' (Qualcomm uC Load Store Multiple Extension)
qc.lwm x7, x1, 24
# CHECK-PLUS: :[[@LINE+2]]:8: error: register must be a GPR excluding zero (x0)
-# CHECK-MINUS: :[[@LINE+1]]:8: error: register must be a GPR excluding zero (x0)
+# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcilsm' (Qualcomm uC Load Store Multiple Extension)
qc.lwm x0, x1, 24(x20)
# CHECK-PLUS: :[[@LINE+1]]:16: error: immediate must be a multiple of 4 bytes in the range [0, 124]
@@ -110,11 +110,11 @@ qc.lwm x7, x1, 24(x20)
qc.lwmi x13, 9, 4(23)
# CHECK-PLUS: :[[@LINE+2]]:18: error: too few operands for instruction
-# CHECK-MINUS: :[[@LINE+1]]:17: error: expected '('
+# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcilsm' (Qualcomm uC Load Store Multiple Extension)
qc.lwmi x13, 9, 4
# CHECK-PLUS: :[[@LINE+2]]:9: error: register must be a GPR excluding zero (x0)
-# CHECK-MINUS: :[[@LINE+1]]:9: error: register must be a GPR excluding zero (x0)
+# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcilsm' (Qualcomm uC Load Store Multiple Extension)
qc.lwmi x0, 9, 4(x23)
# CHECK-PLUS: :[[@LINE+1]]:14: error: immediate must be an integer in the range [1, 31]
diff --git a/llvm/utils/TableGen/AsmMatcherEmitter.cpp b/llvm/utils/TableGen/AsmMatcherEmitter.cpp
index 96188225c472e..57ed87aa3522b 100644
--- a/llvm/utils/TableGen/AsmMatcherEmitter.cpp
+++ b/llvm/utils/TableGen/AsmMatcherEmitter.cpp
@@ -3522,6 +3522,8 @@ void AsmMatcherEmitter::run(raw_ostream &OS) {
bool HasOptionalOperands = Info.hasOptionalOperands();
bool ReportMultipleNearMisses =
AsmParser->getValueAsBit("ReportMultipleNearMisses");
+ bool PrioritizeFeatureInMultipleNearMisses =
+ AsmParser->getValueAsBit("PrioritizeFeatureInMultipleNearMisses");
// Write the output.
@@ -4114,10 +4116,28 @@ void AsmMatcherEmitter::run(raw_ostream &OS) {
OS << " }\n\n";
}
- if (ReportMultipleNearMisses)
+ if (ReportMultipleNearMisses && PrioritizeFeatureInMultipleNearMisses) {
+ // Emit check that the required features are available.
+ OS << " if (!HasRequiredFeatures) {\n";
+ OS << " FeatureBitset NewMissingFeatures = RequiredFeatures & "
+ "~AvailableFeatures;\n";
+ OS << " DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"Missing target "
+ "features:\";\n";
+ OS << " for (unsigned I = 0, E = "
+ "NewMissingFeatures.size(); I != E; ++I)\n";
+ OS << " if (NewMissingFeatures[I])\n";
+ OS << " dbgs() << ' ' << I;\n";
+ OS << " dbgs() << \"\\n\");\n";
+ OS << " FeaturesNearMiss = "
+ "NearMissInfo::getMissedFeature(NewMissingFeatures);\n";
+ OS << " }\n";
+ }
+
+ if (ReportMultipleNearMisses) {
OS << " if (MultipleInvalidOperands) {\n";
- else
+ } else {
OS << " if (!OperandsValid) {\n";
+ }
OS << " DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"Opcode result: "
"multiple \"\n";
OS << " \"operand mismatches, "
@@ -4127,35 +4147,49 @@ void AsmMatcherEmitter::run(raw_ostream &OS) {
OS << " // Too many invalid operands to report a single near-miss;\n";
OS << " // keep the first one as a fallback in case no opcode\n";
OS << " // matches more closely.\n";
- OS << " if (OperandNearMiss)\n";
- OS << " MultiMismatchFallback.push_back(OperandNearMiss);\n";
+ if (PrioritizeFeatureInMultipleNearMisses) {
+ OS << " // If the opcode also has missing features, promote the\n";
+ OS << " // feature near-miss instead of the operand near-miss so\n";
+ OS << " // that the diagnostic points to the missing extension.\n";
+ OS << " if (FeaturesNearMiss)\n";
+ OS << " MultiMismatchFallback.push_back(FeaturesNearMiss);\n";
+ OS << " else if (OperandNearMiss)\n";
+ OS << " MultiMismatchFallback.push_back(OperandNearMiss);\n";
+ } else {
+ OS << " if (OperandNearMiss)\n";
+ OS << " MultiMismatchFallback.push_back(OperandNearMiss);\n";
+ }
}
OS << " continue;\n";
OS << " }\n";
- // Emit check that the required features are available.
- OS << " if (!HasRequiredFeatures) {\n";
- if (!ReportMultipleNearMisses)
- OS << " HadMatchOtherThanFeatures = true;\n";
- OS << " FeatureBitset NewMissingFeatures = RequiredFeatures & "
- "~AvailableFeatures;\n";
- OS << " DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"Missing target "
- "features:\";\n";
- OS << " for (unsigned I = 0, E = "
- "NewMissingFeatures.size(); I != E; ++I)\n";
- OS << " if (NewMissingFeatures[I])\n";
- OS << " dbgs() << ' ' << I;\n";
- OS << " dbgs() << \"\\n\");\n";
- if (ReportMultipleNearMisses) {
- OS << " FeaturesNearMiss = "
- "NearMissInfo::getMissedFeature(NewMissingFeatures);\n";
- } else {
- OS << " if (NewMissingFeatures.count() <=\n"
- " MissingFeatures.count())\n";
- OS << " MissingFeatures = NewMissingFeatures;\n";
- OS << " continue;\n";
+ if (!PrioritizeFeatureInMultipleNearMisses) {
+ // Emit check that the required features are available.
+ OS << " if (!HasRequiredFeatures) {\n";
+ if (!ReportMultipleNearMisses) {
+ OS << " HadMatchOtherThanFeatures = true;\n";
+ }
+ OS << " FeatureBitset NewMissingFeatures = RequiredFeatures & "
+ "~AvailableFeatures;\n";
+ OS << " DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"Missing target "
+ "features:\";\n";
+ OS << " for (unsigned I = 0, E = "
+ "NewMissingFeatures.size(); I != E; ++I)\n";
+ OS << " if (NewMissingFeatures[I])\n";
+ OS << " dbgs() << ' ' << I;\n";
+ OS << " dbgs() << \"\\n\");\n";
+ if (ReportMultipleNearMisses) {
+ OS << " FeaturesNearMiss = "
+ "NearMissInfo::getMissedFeature(NewMissingFeatures);\n";
+ } else {
+ OS << " if (NewMissingFeatures.count() <=\n"
+ " MissingFeatures.count())\n";
+ OS << " MissingFeatures = NewMissingFeatures;\n";
+ OS << " continue;\n";
+ }
+ OS << " }\n";
}
- OS << " }\n";
+
OS << "\n";
OS << " Inst.clear();\n\n";
OS << " Inst.setOpcode(it->Opcode);\n";
>From 2e334eb774c0bda7c2823bfacc975592f42073cd Mon Sep 17 00:00:00 2001
From: Saloni Shinde <saloshin at qti.qualcomm.com>
Date: Fri, 14 Aug 2026 00:36:12 -0700
Subject: [PATCH 2/2] [RISCV][MC] Validate near-miss prioritization settings
---
llvm/utils/TableGen/AsmMatcherEmitter.cpp | 75 +++++++++++------------
1 file changed, 37 insertions(+), 38 deletions(-)
diff --git a/llvm/utils/TableGen/AsmMatcherEmitter.cpp b/llvm/utils/TableGen/AsmMatcherEmitter.cpp
index 57ed87aa3522b..6589e9f89a3d5 100644
--- a/llvm/utils/TableGen/AsmMatcherEmitter.cpp
+++ b/llvm/utils/TableGen/AsmMatcherEmitter.cpp
@@ -3455,6 +3455,33 @@ getNameForFeatureBitset(ArrayRef<const Record *> FeatureBitset) {
return Name;
}
+static void emitFeatureCheck(raw_ostream &OS,
+ bool ReportMultipleNearMisses) {
+ OS << " if (!HasRequiredFeatures) {\n";
+ if (!ReportMultipleNearMisses)
+ OS << " HadMatchOtherThanFeatures = true;\n";
+
+ OS << " FeatureBitset NewMissingFeatures = RequiredFeatures & "
+ "~AvailableFeatures;\n";
+ OS << " DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"Missing target "
+ "features:\";\n";
+ OS << " for (unsigned I = 0, E = "
+ "NewMissingFeatures.size(); I != E; ++I)\n";
+ OS << " if (NewMissingFeatures[I])\n";
+ OS << " dbgs() << ' ' << I;\n";
+ OS << " dbgs() << \"\\n\");\n";
+ if (ReportMultipleNearMisses) {
+ OS << " FeaturesNearMiss = "
+ "NearMissInfo::getMissedFeature(NewMissingFeatures);\n";
+ } else {
+ OS << " if (NewMissingFeatures.count() <=\n"
+ " MissingFeatures.count())\n";
+ OS << " MissingFeatures = NewMissingFeatures;\n";
+ OS << " continue;\n";
+ }
+ OS << " }\n";
+}
+
void AsmMatcherEmitter::run(raw_ostream &OS) {
CodeGenTarget Target(Records);
const Record *AsmParser = Target.getAsmParser();
@@ -3525,6 +3552,14 @@ void AsmMatcherEmitter::run(raw_ostream &OS) {
bool PrioritizeFeatureInMultipleNearMisses =
AsmParser->getValueAsBit("PrioritizeFeatureInMultipleNearMisses");
+ if (PrioritizeFeatureInMultipleNearMisses &&
+ !ReportMultipleNearMisses) {
+ PrintFatalError(
+ AsmParser->getLoc(),
+ "'PrioritizeFeatureInMultipleNearMisses' requires "
+ "'ReportMultipleNearMisses' to be set");
+ }
+
// Write the output.
// Information for the class declaration.
@@ -4117,20 +4152,7 @@ void AsmMatcherEmitter::run(raw_ostream &OS) {
}
if (ReportMultipleNearMisses && PrioritizeFeatureInMultipleNearMisses) {
- // Emit check that the required features are available.
- OS << " if (!HasRequiredFeatures) {\n";
- OS << " FeatureBitset NewMissingFeatures = RequiredFeatures & "
- "~AvailableFeatures;\n";
- OS << " DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"Missing target "
- "features:\";\n";
- OS << " for (unsigned I = 0, E = "
- "NewMissingFeatures.size(); I != E; ++I)\n";
- OS << " if (NewMissingFeatures[I])\n";
- OS << " dbgs() << ' ' << I;\n";
- OS << " dbgs() << \"\\n\");\n";
- OS << " FeaturesNearMiss = "
- "NearMissInfo::getMissedFeature(NewMissingFeatures);\n";
- OS << " }\n";
+ emitFeatureCheck(OS, ReportMultipleNearMisses);
}
if (ReportMultipleNearMisses) {
@@ -4164,30 +4186,7 @@ void AsmMatcherEmitter::run(raw_ostream &OS) {
OS << " }\n";
if (!PrioritizeFeatureInMultipleNearMisses) {
- // Emit check that the required features are available.
- OS << " if (!HasRequiredFeatures) {\n";
- if (!ReportMultipleNearMisses) {
- OS << " HadMatchOtherThanFeatures = true;\n";
- }
- OS << " FeatureBitset NewMissingFeatures = RequiredFeatures & "
- "~AvailableFeatures;\n";
- OS << " DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"Missing target "
- "features:\";\n";
- OS << " for (unsigned I = 0, E = "
- "NewMissingFeatures.size(); I != E; ++I)\n";
- OS << " if (NewMissingFeatures[I])\n";
- OS << " dbgs() << ' ' << I;\n";
- OS << " dbgs() << \"\\n\");\n";
- if (ReportMultipleNearMisses) {
- OS << " FeaturesNearMiss = "
- "NearMissInfo::getMissedFeature(NewMissingFeatures);\n";
- } else {
- OS << " if (NewMissingFeatures.count() <=\n"
- " MissingFeatures.count())\n";
- OS << " MissingFeatures = NewMissingFeatures;\n";
- OS << " continue;\n";
- }
- OS << " }\n";
+ emitFeatureCheck(OS, ReportMultipleNearMisses);
}
OS << "\n";
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