[llvm] [DAG] narrowExtractedVectorLoad - add frozen load handling (PR #216120)

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<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-x86

@llvm/pr-subscribers-llvm-selectiondag

Author: Simon Pilgrim (RKSimon)

<details>
<summary>Changes</summary>

Fixes #<!-- -->216115

---
Full diff: https://github.com/llvm/llvm-project/pull/216120.diff


2 Files Affected:

- (modified) llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (+7) 
- (modified) llvm/test/CodeGen/X86/extractsubvector-load.ll (+5-18) 


``````````diff
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 595cc5d653de6..6083111185ac2 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -28236,6 +28236,13 @@ SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode *N) {
   if (SDValue NarrowLoad = narrowExtractedVectorLoad(NVT, V, ExtIdx, DL, DAG))
     return NarrowLoad;
 
+  // Peek through frozen loads, but ensure the load has a single use.
+  if (V.getOpcode() == ISD::FREEZE && V.hasOneUse() &&
+      V.getOperand(0).hasOneUse())
+    if (SDValue NarrowLoad =
+            narrowExtractedVectorLoad(NVT, V.getOperand(0), ExtIdx, DL, DAG))
+      return DAG.getFreeze(NarrowLoad);
+
   // Combine an extract of an extract into a single extract_subvector.
   // ext (ext X, C1), C2 --> ext X, C1 + C2
   if (V.getOpcode() == ISD::EXTRACT_SUBVECTOR && V.hasOneUse()) {
diff --git a/llvm/test/CodeGen/X86/extractsubvector-load.ll b/llvm/test/CodeGen/X86/extractsubvector-load.ll
index cd6814d00cbbb..1b679631f4207 100644
--- a/llvm/test/CodeGen/X86/extractsubvector-load.ll
+++ b/llvm/test/CodeGen/X86/extractsubvector-load.ll
@@ -178,9 +178,7 @@ define <4 x i32> @load_v8i32_v4i32_ofs4_freeze(ptr %val) nounwind {
 ;
 ; X64-AVX-LABEL: load_v8i32_v4i32_ofs4_freeze:
 ; X64-AVX:       # %bb.0:
-; X64-AVX-NEXT:    vmovaps (%rdi), %ymm0
-; X64-AVX-NEXT:    vextractf128 $1, %ymm0, %xmm0
-; X64-AVX-NEXT:    vzeroupper
+; X64-AVX-NEXT:    vmovaps 16(%rdi), %xmm0
 ; X64-AVX-NEXT:    retq
   %ld = load <8 x i32>, ptr %val
   %fr = freeze <8 x i32> %ld
@@ -202,21 +200,10 @@ define <4 x double> @load_v8f64_v4f64_ofs0_freeze(ptr %val) nounwind {
 ; X64-SSE-NEXT:    movaps 16(%rdi), %xmm1
 ; X64-SSE-NEXT:    retq
 ;
-; X64-AVX1-LABEL: load_v8f64_v4f64_ofs0_freeze:
-; X64-AVX1:       # %bb.0:
-; X64-AVX1-NEXT:    vmovaps (%rdi), %ymm0
-; X64-AVX1-NEXT:    retq
-;
-; X64-AVX2-LABEL: load_v8f64_v4f64_ofs0_freeze:
-; X64-AVX2:       # %bb.0:
-; X64-AVX2-NEXT:    vmovaps (%rdi), %ymm0
-; X64-AVX2-NEXT:    retq
-;
-; X64-AVX512-LABEL: load_v8f64_v4f64_ofs0_freeze:
-; X64-AVX512:       # %bb.0:
-; X64-AVX512-NEXT:    vmovaps (%rdi), %zmm0
-; X64-AVX512-NEXT:    # kill: def $ymm0 killed $ymm0 killed $zmm0
-; X64-AVX512-NEXT:    retq
+; X64-AVX-LABEL: load_v8f64_v4f64_ofs0_freeze:
+; X64-AVX:       # %bb.0:
+; X64-AVX-NEXT:    vmovaps (%rdi), %ymm0
+; X64-AVX-NEXT:    retq
   %ld = load <8 x double>, ptr %val
   %fr = freeze <8 x double> %ld
   %sub = shufflevector <8 x double> %fr, <8 x double> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>

``````````

</details>


https://github.com/llvm/llvm-project/pull/216120