[llvm] [CodeGen] Adding v1024i16 and v2048i16 (PR #216118)
Frank Schlimbach via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 13 09:58:20 PDT 2026
https://github.com/fschlimb created https://github.com/llvm/llvm-project/pull/216118
Filling an obviously missing ValueTypes.
Needed in a downstream project.
>From fc7099b5502857724fce3979874c9e184dacfe3a Mon Sep 17 00:00:00 2001
From: fschlimb <frank.schlimbach at intel.com>
Date: Thu, 13 Aug 2026 09:50:52 -0700
Subject: [PATCH] adding v1024i16 and v2048i16
---
llvm/include/llvm/CodeGen/ValueTypes.td | 3 +++
llvm/test/TableGen/CPtrWildcard.td | 4 ++--
llvm/unittests/CodeGen/ScalableVectorMVTsTest.cpp | 4 ++++
3 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/ValueTypes.td b/llvm/include/llvm/CodeGen/ValueTypes.td
index 4709a7d72ba8f..aff2a4b0074c3 100644
--- a/llvm/include/llvm/CodeGen/ValueTypes.td
+++ b/llvm/include/llvm/CodeGen/ValueTypes.td
@@ -146,6 +146,8 @@ def v64i16 : VTVec<64, i16>; // 64 x i16 vector value
def v128i16 : VTVec<128, i16>; // 128 x i16 vector value
def v256i16 : VTVec<256, i16>; // 256 x i16 vector value
def v512i16 : VTVec<512, i16>; // 512 x i16 vector value
+def v1024i16 : VTVec<1024, i16>; // 1024 x i16 vector value
+def v2048i16 : VTVec<2048, i16>; // 2048 x i16 vector value
def v4096i16 : VTVec<4096, i16>; // 4096 x i16 vector value
def v1i32 : VTVec<1, i32>; // 1 x i32 vector value
@@ -213,6 +215,7 @@ def v64bf16 : VTVec<64, bf16>; // 64 x bf16 vector value
def v128bf16 : VTVec<128, bf16>; // 128 x bf16 vector value
def v256bf16 : VTVec<256, bf16>; // 256 x bf16 vector value
def v512bf16 : VTVec<512, bf16>; // 512 x bf16 vector value
+def v1024bf16 : VTVec<1024, bf16>; // 1024 x bf16 vector value
def v2048bf16 : VTVec<2048, bf16>; // 2048 x bf16 vector value
def v4096bf16 : VTVec<4096, bf16>; // 4096 x bf16 vector value
diff --git a/llvm/test/TableGen/CPtrWildcard.td b/llvm/test/TableGen/CPtrWildcard.td
index 082e510f5a595..82eb54dc53ac9 100644
--- a/llvm/test/TableGen/CPtrWildcard.td
+++ b/llvm/test/TableGen/CPtrWildcard.td
@@ -8,13 +8,13 @@
// CHECK-NEXT:/* 3*/ OPC_CheckChild0Integer, [[#]],
// CHECK-NEXT:/* 5*/ OPC_RecordChild1, // #0 = $src
// CHECK-NEXT:/* 6*/ OPC_Scope /*2 children */, 9, // ->17
-// CHECK-NEXT:/* 8*/ OPC_CheckChild1Type, /*MVT::c64*/6|128,2/*262*/,
+// CHECK-NEXT:/* 8*/ OPC_CheckChild1Type, /*MVT::c64*/9|128,2/*265*/,
// CHECK-NEXT:/* 11*/ OPC_MorphNodeTo1None, TARGET_VAL(MyTarget::C64_TO_I64),
// CHECK-NEXT: MVT::i64, 1/*#Ops*/, /*OperandList*/0, // Ops = #0
// CHECK-NEXT: // Src: (intrinsic_wo_chain:{ *:[i64] } [[#]]:{ *:[iPTR] }, c64:{ *:[c64] }:$src) - Complexity = 8
// CHECK-NEXT: // Dst: (C64_TO_I64:{ *:[i64] } ?:{ *:[c64] }:$src)
// CHECK-NEXT:/* 17*/ /*Scope*/ 9, // ->27
-// CHECK-NEXT:/* 18*/ OPC_CheckChild1Type, /*MVT::c128*/7|128,2/*263*/,
+// CHECK-NEXT:/* 18*/ OPC_CheckChild1Type, /*MVT::c128*/10|128,2/*266*/,
// CHECK-NEXT:/* 21*/ OPC_MorphNodeTo1None, TARGET_VAL(MyTarget::C128_TO_I64),
// CHECK-NEXT: MVT::i64, 1/*#Ops*/, /*OperandList*/0, // Ops = #0
// CHECK-NEXT: // Src: (intrinsic_wo_chain:{ *:[i64] } [[#]]:{ *:[iPTR] }, c128:{ *:[c128] }:$src) - Complexity = 8
diff --git a/llvm/unittests/CodeGen/ScalableVectorMVTsTest.cpp b/llvm/unittests/CodeGen/ScalableVectorMVTsTest.cpp
index c343465ae4c72..bf2a6a575c5e6 100644
--- a/llvm/unittests/CodeGen/ScalableVectorMVTsTest.cpp
+++ b/llvm/unittests/CodeGen/ScalableVectorMVTsTest.cpp
@@ -69,6 +69,10 @@ TEST(ScalableVectorMVTsTest, HelperFuncs) {
// Check that float->int conversion works
EVT Vnx2f64 = EVT::getVectorVT(Ctx, MVT::f64, ElementCount::getScalable(2));
EXPECT_EQ(Vnx2f64.changeTypeToInteger(), Vnx2i64);
+ EXPECT_EQ(MVT(MVT::v1024bf16).changeVectorElementTypeToInteger(),
+ MVT::v1024i16);
+ EXPECT_EQ(MVT(MVT::v2048bf16).changeVectorElementTypeToInteger(),
+ MVT::v2048i16);
// Check fields inside llvm::ElementCount
EltCnt = Vnx4i32.getVectorElementCount();
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