[llvm] [AArch64] Combine SVE shift and truncate into deinterleave (PR #213252)

[Sander de Smalen via llvm-commits]

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@@ -23642,8 +23643,84 @@ static SDValue trySQDMULHCombine(SDNode *N, SelectionDAG &DAG) {
   return DAG.getNode(ISD::SIGN_EXTEND, DL, DestVT, SQDMULH);
 }
 
+// Fold a shift by half the source element width followed by a truncation into
+// extraction of the upper half of each source element.
+static SDValue tryShiftTruncateCombine(SDNode *N, SelectionDAG &DAG,
+                                       TargetLowering::DAGCombinerInfo &DCI) {
+  if (!DCI.isBeforeLegalize())
+    return SDValue();
+
+  EVT DstVT = N->getValueType(0);
+  SDValue Shift = N->getOperand(0);
+
+  if (!DstVT.isScalableVector() || !DstVT.getVectorElementType().isInteger() ||
+      !DAG.getTargetLoweringInfo().isTypeLegal(DstVT))
+    return SDValue();
+
+  if ((Shift.getOpcode() != ISD::SRL && Shift.getOpcode() != ISD::SRA) ||
+      !Shift.hasOneUse())
+    return SDValue();
+
+  EVT SrcVT = Shift.getValueType();
+  if (!SrcVT.isScalableVector() || !SrcVT.getVectorElementType().isInteger() ||
+      SrcVT.getVectorElementCount() != DstVT.getVectorElementCount() ||
+      SrcVT.getScalarSizeInBits() != 2 * DstVT.getScalarSizeInBits() ||
+      SrcVT.getScalarSizeInBits() > 64)
+    return SDValue();
+
+  ConstantSDNode *ShiftAmount = isConstOrConstSplat(Shift.getOperand(1));
+  if (!ShiftAmount ||
+      ShiftAmount->getAsZExtVal() != DstVT.getScalarSizeInBits())
+    return SDValue();
+
+  // Preserve widening multiply patterns so they can select to SMULH or UMULH.
----------------
sdesmalen-arm wrote:

Doing this optimization this early, but anticipating later folds, makes things a little fragile. I think it makes more sense to match the pattern (after legalization) directly, so that we have more control about what pattern we want to fold. I'll put a separate PR for this.

https://github.com/llvm/llvm-project/pull/213252