[llvm] [LoongArch] Fix selection of BRCOND with constant conditions (PR #216027)

[via llvm-commits]

llvmorg-github-actions[bot] wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-loongarch

Author: hev (heiher)

<details>
<summary>Changes</summary>

LoongArch DAG instruction selection could fail to select `LoongArchISD::BRCOND` when its condition was a constant integer. Add patterns to lower constant zero and one conditions to `BEQZ` and `BNEZ`.

Fixes: https://github.com/llvm/llvm-project/issues/215935

---
Full diff: https://github.com/llvm/llvm-project/pull/216027.diff


2 Files Affected:

- (modified) llvm/lib/Target/LoongArch/LoongArchFloat32InstrInfo.td (+3) 
- (added) llvm/test/CodeGen/LoongArch/pr215935.ll (+50) 


``````````diff
diff --git a/llvm/lib/Target/LoongArch/LoongArchFloat32InstrInfo.td b/llvm/lib/Target/LoongArch/LoongArchFloat32InstrInfo.td
index a3c37c306c541..27d5fa1fab62a 100644
--- a/llvm/lib/Target/LoongArch/LoongArchFloat32InstrInfo.td
+++ b/llvm/lib/Target/LoongArch/LoongArchFloat32InstrInfo.td
@@ -232,6 +232,9 @@ def : PatFPSetcc<SETUNE, FCMP_CUNE_S, FPR32>;
 def : PatFPSetcc<SETUO,  FCMP_CUN_S,  FPR32>;
 def : PatFPSetcc<SETLT,  FCMP_CLT_S,  FPR32>;
 
+def : Pat<(loongarch_brcond (GRLenVT 0), bb:$imm21), (BNEZ R0, bb:$imm21)>;
+def : Pat<(loongarch_brcond (GRLenVT 1), bb:$imm21), (BEQZ R0, bb:$imm21)>;
+
 multiclass PatFPBrcond<CondCode cc, LAInst CmpInst, RegisterClass RegTy> {
   def : Pat<(loongarch_brcond (NotBoolXor (GRLenVT (setcc RegTy:$fj, RegTy:$fk, cc))),
                               bb:$imm21),
diff --git a/llvm/test/CodeGen/LoongArch/pr215935.ll b/llvm/test/CodeGen/LoongArch/pr215935.ll
new file mode 100644
index 0000000000000..661f7f9f60f88
--- /dev/null
+++ b/llvm/test/CodeGen/LoongArch/pr215935.ll
@@ -0,0 +1,50 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc --mtriple=loongarch64 -mattr=+lsx < %s | FileCheck %s
+
+define i64 @brcond_const_1(i64 %0) nounwind {
+; CHECK-LABEL: brcond_const_1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    beqz $zero, .LBB0_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    move $a0, $zero
+; CHECK-NEXT:    ret
+; CHECK-NEXT:  .LBB0_2:
+; CHECK-NEXT:    ori $a0, $zero, 1
+; CHECK-NEXT:    ret
+entry:
+  %2 = trunc i64 %0 to i32
+  %3 = trunc i64 %0 to i8
+  %4 = uitofp i8 %3 to double
+  %5 = and i32 %2, 255
+  %6 = uitofp i32 %5 to double
+  %7 = fcmp one double %4, %6
+  br i1 %7, label %8, label %9
+8:
+  ret i64 0
+9:
+  ret i64 1
+}
+
+define i64 @brcond_const_0(i64 %0) nounwind {
+; CHECK-LABEL: brcond_const_0:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    bnez $zero, .LBB1_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    move $a0, $zero
+; CHECK-NEXT:    ret
+; CHECK-NEXT:  .LBB1_2:
+; CHECK-NEXT:    ori $a0, $zero, 1
+; CHECK-NEXT:    ret
+entry:
+  %2 = trunc i64 %0 to i32
+  %3 = trunc i64 %0 to i8
+  %4 = uitofp i8 %3 to double
+  %5 = and i32 %2, 255
+  %6 = uitofp i32 %5 to double
+  %7 = fcmp oeq double %4, %6
+  br i1 %7, label %8, label %9
+8:
+  ret i64 0
+9:
+  ret i64 1
+}

``````````

</details>


https://github.com/llvm/llvm-project/pull/216027