[llvm] [LV] Use ScalarTy in isLegalGatherOrScatter (PR #215852)

[Florian Hahn via llvm-commits]

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@@ -17,69 +17,128 @@ define void @test_interleave_reduction(ptr %arg, ptr %arg1) {
 ; A320:       [[OUTER]]:
 ; A320-NEXT:    [[TPM26:%.*]] = add i64 0, 1
 ; A320-NEXT:    [[TPM10:%.*]] = alloca i32, align 8
+; A320-NEXT:    [[TPM102:%.*]] = ptrtoaddr ptr [[TPM10]] to i64
 ; A320-NEXT:    [[TPM27:%.*]] = getelementptr inbounds i32, ptr [[TPM10]], i64 [[TPM26]]
 ; A320-NEXT:    [[TPM28:%.*]] = getelementptr inbounds ptr, ptr [[TPM15]], i64 0
 ; A320-NEXT:    [[TPM29:%.*]] = load ptr, ptr [[TPM28]], align 8
+; A320-NEXT:    [[TMP0:%.*]] = ptrtoaddr ptr [[TPM29]] to i64
 ; A320-NEXT:    [[TPM17:%.*]] = alloca double, align 8
 ; A320-NEXT:    [[TPM32:%.*]] = getelementptr inbounds double, ptr [[TPM17]], i64 [[TPM26]]
-; A320-NEXT:    [[TMP0:%.*]] = ptrtoaddr ptr [[TPM29]] to i64
-; A320-NEXT:    [[TPM102:%.*]] = ptrtoaddr ptr [[TPM10]] to i64
 ; A320-NEXT:    [[TMP8:%.*]] = add i64 [[TMP0]], -8
 ; A320-NEXT:    [[TMP6:%.*]] = sub i64 [[TMP8]], [[TPM102]]
 ; A320-NEXT:    [[TMP2:%.*]] = lshr i64 [[TMP6]], 2
 ; A320-NEXT:    [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 1
-; A320-NEXT:    [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP3]], 2
+; A320-NEXT:    [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP3]], 4
 ; A320-NEXT:    br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
 ; A320:       [[VECTOR_PH]]:
-; A320-NEXT:    [[N_MOD_VF:%.*]] = and i64 [[TMP3]], 1
+; A320-NEXT:    [[MIN_ITERS_CHECK3:%.*]] = icmp ult i64 [[TMP3]], 16
+; A320-NEXT:    br i1 [[MIN_ITERS_CHECK3]], label %[[VEC_EPILOG_PH:.*]], label %[[VECTOR_PH1:.*]]
+; A320:       [[VECTOR_PH1]]:
+; A320-NEXT:    [[N_MOD_VF:%.*]] = and i64 [[TMP3]], 15
 ; A320-NEXT:    [[N_VEC:%.*]] = sub i64 [[TMP3]], [[N_MOD_VF]]
 ; A320-NEXT:    [[TMP4:%.*]] = shl i64 [[N_VEC]], 2
 ; A320-NEXT:    [[IND_END:%.*]] = getelementptr i8, ptr [[TPM27]], i64 [[TMP4]]
 ; A320-NEXT:    [[TMP5:%.*]] = shl i64 [[N_VEC]], 3
 ; A320-NEXT:    [[IND_END3:%.*]] = getelementptr i8, ptr [[TPM32]], i64 [[TMP5]]
 ; A320-NEXT:    br label %[[VECTOR_BODY:.*]]
 ; A320:       [[VECTOR_BODY]]:
-; A320-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
-; A320-NEXT:    [[VEC_PHI:%.*]] = phi double [ 0.000000e+00, %[[VECTOR_PH]] ], [ [[TMP22:%.*]], %[[VECTOR_BODY]] ]
-; A320-NEXT:    [[VEC_PHI5:%.*]] = phi double [ 0.000000e+00, %[[VECTOR_PH]] ], [ [[TMP23:%.*]], %[[VECTOR_BODY]] ]
+; A320-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH1]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; A320-NEXT:    [[VEC_PHI:%.*]] = phi <4 x double> [ zeroinitializer, %[[VECTOR_PH1]] ], [ [[TMP25:%.*]], %[[VECTOR_BODY]] ]
+; A320-NEXT:    [[VEC_PHI4:%.*]] = phi <4 x double> [ zeroinitializer, %[[VECTOR_PH1]] ], [ [[TMP26:%.*]], %[[VECTOR_BODY]] ]
+; A320-NEXT:    [[VEC_PHI5:%.*]] = phi <4 x double> [ zeroinitializer, %[[VECTOR_PH1]] ], [ [[TMP27:%.*]], %[[VECTOR_BODY]] ]
+; A320-NEXT:    [[VEC_PHI6:%.*]] = phi <4 x double> [ zeroinitializer, %[[VECTOR_PH1]] ], [ [[TMP28:%.*]], %[[VECTOR_BODY]] ]
 ; A320-NEXT:    [[OFFSET_IDX:%.*]] = shl i64 [[INDEX]], 2
-; A320-NEXT:    [[TMP7:%.*]] = add i64 [[OFFSET_IDX]], 4
 ; A320-NEXT:    [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[TPM27]], i64 [[OFFSET_IDX]]
+; A320-NEXT:    [[TMP10:%.*]] = shl i64 [[INDEX]], 3
+; A320-NEXT:    [[NEXT_GEP7:%.*]] = getelementptr i8, ptr [[TPM32]], i64 [[TMP10]]
+; A320-NEXT:    [[TMP11:%.*]] = getelementptr double, ptr [[NEXT_GEP7]], i64 4
+; A320-NEXT:    [[TMP12:%.*]] = getelementptr double, ptr [[NEXT_GEP7]], i64 8
+; A320-NEXT:    [[TMP13:%.*]] = getelementptr double, ptr [[NEXT_GEP7]], i64 12
+; A320-NEXT:    [[WIDE_LOAD:%.*]] = load <4 x double>, ptr [[NEXT_GEP7]], align 8
+; A320-NEXT:    [[WIDE_LOAD8:%.*]] = load <4 x double>, ptr [[TMP11]], align 8
+; A320-NEXT:    [[WIDE_LOAD9:%.*]] = load <4 x double>, ptr [[TMP12]], align 8
+; A320-NEXT:    [[WIDE_LOAD10:%.*]] = load <4 x double>, ptr [[TMP13]], align 8
+; A320-NEXT:    [[TMP14:%.*]] = getelementptr i32, ptr [[NEXT_GEP]], i64 4
+; A320-NEXT:    [[TMP15:%.*]] = getelementptr i32, ptr [[NEXT_GEP]], i64 8
+; A320-NEXT:    [[TMP16:%.*]] = getelementptr i32, ptr [[NEXT_GEP]], i64 12
+; A320-NEXT:    [[WIDE_LOAD11:%.*]] = load <4 x i32>, ptr [[NEXT_GEP]], align 4
+; A320-NEXT:    [[WIDE_LOAD12:%.*]] = load <4 x i32>, ptr [[TMP14]], align 4
+; A320-NEXT:    [[WIDE_LOAD13:%.*]] = load <4 x i32>, ptr [[TMP15]], align 4
+; A320-NEXT:    [[WIDE_LOAD14:%.*]] = load <4 x i32>, ptr [[TMP16]], align 4
+; A320-NEXT:    [[TMP17:%.*]] = zext <4 x i32> [[WIDE_LOAD11]] to <4 x i64>
+; A320-NEXT:    [[TMP18:%.*]] = zext <4 x i32> [[WIDE_LOAD12]] to <4 x i64>
+; A320-NEXT:    [[TMP19:%.*]] = zext <4 x i32> [[WIDE_LOAD13]] to <4 x i64>
+; A320-NEXT:    [[TMP20:%.*]] = zext <4 x i32> [[WIDE_LOAD14]] to <4 x i64>
+; A320-NEXT:    [[WIDE_GEP:%.*]] = getelementptr inbounds double, ptr [[TPM19]], <4 x i64> [[TMP17]]
+; A320-NEXT:    [[WIDE_GEP15:%.*]] = getelementptr inbounds double, ptr [[TPM19]], <4 x i64> [[TMP18]]
+; A320-NEXT:    [[WIDE_GEP16:%.*]] = getelementptr inbounds double, ptr [[TPM19]], <4 x i64> [[TMP19]]
+; A320-NEXT:    [[WIDE_GEP17:%.*]] = getelementptr inbounds double, ptr [[TPM19]], <4 x i64> [[TMP20]]
+; A320-NEXT:    [[WIDE_MASKED_GATHER:%.*]] = call <4 x double> @llvm.masked.gather.v4f64.v4p0(<4 x ptr> align 8 [[WIDE_GEP]], <4 x i1> splat (i1 true), <4 x double> poison)
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fhahn wrote:

I am not sure that is right, I think the masked gather would be scalarized on `cortex-a320`?

https://github.com/llvm/llvm-project/pull/215852