[llvm] [RISCV][P-ext] Select scalar mulhr/mulhru/mulhrsu for RV32 v2i32 (PR #215938)

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llvmorg-github-actions[bot] wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-risc-v

Author: SiHuaN (sihuan)

<details>
<summary>Changes</summary>

The `combinePExtTruncate` DAGCombine bailed out on RV32 for both
`v4i16` and `v2i32` 64-bit packed types. The `v4i16` case is correct
(no paired rounding multiply-high for 16-bit lanes), but `v2i32` was
incorrectly excluded.

RV32 provides scalar `mulhr`/`mulhru`/`mulhrsu` instructions. Since
`v2i32` on RV32 is a GPRPair, splitting into two scalar operations in
the combine — while the widening multiply shape is still visible —
reuses those instructions directly.

The non-rounding forms (`mulh`/`mulhu`/`mulhsu`) already scalarize
correctly through the generic legalizer, so only the rounding case
needs explicit handling here.

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Full diff: https://github.com/llvm/llvm-project/pull/215938.diff


2 Files Affected:

- (modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (+16-1) 
- (modified) llvm/test/CodeGen/RISCV/rvp-simd-64.ll (+8-24) 


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</details>


https://github.com/llvm/llvm-project/pull/215938