[llvm] [SelectionDAG] Fix soft-promotion of f16 BUILD_VECTOR for MSA targets (PR #210515)

[Matt Arsenault via llvm-commits]

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@@ -1,41 +1,146 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
 ; RUN: llc -mtriple=mipsel-unknown-linux-gnu -mcpu=mips32r5 -mattr=+fp64,+msa < %s | FileCheck %s --check-prefix=MIPS32
-; RUN: llc -mtriple=mips64el-unknown-linux-gnuabi64 -mcpu=mips64r5 -mattr=+fp64,+msa -target-abi n64 < %s | FileCheck %s --check-prefix=MIPS64
+; RUN: llc -mtriple=mips64el-unknown-linux-gnuabi64 -mcpu=mips64r5 -mattr=+fp64,+msa < %s | FileCheck %s --check-prefix=MIPS64
 
-; Test that f16 vectors can be passed as arguments and returned without crashing.
-; This is a regression test for a crash in soft-promotion of BUILD_VECTOR operands.
+; Test that f16 vectors can be built from scalar f16 values without crashing.
+; This is a regression test for a crash in soft-promotion of BUILD_VECTOR
+; operands.
 
-define <8 x half> @f16vec_add(<8 x half> %a, <8 x half> %b) {
-; MIPS32-LABEL: f16vec_add:
-; MIPS32:         insert.w
-; MIPS32:         insert.w
+define <8 x half> @build_v8f16(half %a, half %b, half %c, half %d, half %e, half %f, half %g, half %h) {
+; MIPS32-LABEL: build_v8f16:
+; MIPS32:       # %bb.0:
+; MIPS32-NEXT:    insert.h $w0[0], $5
+; MIPS32-NEXT:    insert.h $w0[1], $6
+; MIPS32-NEXT:    insert.h $w0[2], $7
+; MIPS32-NEXT:    lhu $1, 16($sp)
+; MIPS32-NEXT:    insert.h $w0[3], $1
+; MIPS32-NEXT:    lhu $1, 20($sp)
+; MIPS32-NEXT:    insert.h $w0[4], $1
+; MIPS32-NEXT:    lhu $1, 24($sp)
+; MIPS32-NEXT:    insert.h $w0[5], $1
+; MIPS32-NEXT:    lhu $1, 28($sp)
+; MIPS32-NEXT:    insert.h $w0[6], $1
+; MIPS32-NEXT:    lhu $1, 32($sp)
+; MIPS32-NEXT:    insert.h $w0[7], $1
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    st.h $w0, 0($4)
 ;
-; MIPS64-LABEL: f16vec_add:
-; MIPS64:         insert.d
-; MIPS64:         insert.d
-  %c = fadd <8 x half> %a, %b
-  ret <8 x half> %c
+; MIPS64-LABEL: build_v8f16:
+; MIPS64:       # %bb.0:
+; MIPS64-NEXT:    sll $1, $5, 0
+; MIPS64-NEXT:    sll $2, $4, 0
+; MIPS64-NEXT:    insert.h $w0[0], $2
+; MIPS64-NEXT:    insert.h $w0[1], $1
+; MIPS64-NEXT:    sll $1, $6, 0
+; MIPS64-NEXT:    insert.h $w0[2], $1
+; MIPS64-NEXT:    sll $1, $7, 0
+; MIPS64-NEXT:    insert.h $w0[3], $1
+; MIPS64-NEXT:    sll $1, $8, 0
+; MIPS64-NEXT:    insert.h $w0[4], $1
+; MIPS64-NEXT:    sll $1, $9, 0
+; MIPS64-NEXT:    insert.h $w0[5], $1
+; MIPS64-NEXT:    sll $1, $11, 0
+; MIPS64-NEXT:    sll $2, $10, 0
+; MIPS64-NEXT:    insert.h $w0[6], $2
+; MIPS64-NEXT:    insert.h $w0[7], $1
+; MIPS64-NEXT:    copy_s.d $2, $w0[0]
+; MIPS64-NEXT:    jr $ra
+; MIPS64-NEXT:    copy_s.d $3, $w0[1]
+  %v0 = insertelement <8 x half> poison, half %a, i32 0
+  %v1 = insertelement <8 x half> %v0, half %b, i32 1
+  %v2 = insertelement <8 x half> %v1, half %c, i32 2
+  %v3 = insertelement <8 x half> %v2, half %d, i32 3
+  %v4 = insertelement <8 x half> %v3, half %e, i32 4
+  %v5 = insertelement <8 x half> %v4, half %f, i32 5
+  %v6 = insertelement <8 x half> %v5, half %g, i32 6
+  %v7 = insertelement <8 x half> %v6, half %h, i32 7
+  ret <8 x half> %v7
 }
 
-define <4 x half> @f16vec4_add(<4 x half> %a, <4 x half> %b) {
-; MIPS32-LABEL: f16vec4_add:
-; MIPS32:         fill.h
-; MIPS32:         fexupr.w
+define <4 x half> @build_v4f16(half %a, half %b, half %c, half %d) {
+; MIPS32-LABEL: build_v4f16:
+; MIPS32:       # %bb.0:
+; MIPS32-NEXT:    addiu $sp, $sp, -32
+; MIPS32-NEXT:    .cfi_def_cfa_offset 32
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arsenm wrote:

Add nounwind 

https://github.com/llvm/llvm-project/pull/210515