[clang] [llvm] [RISCV][P-ext] Support Packed Narrowing Clip Pair (PR #215779)
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llvm-commits at lists.llvm.org
Wed Aug 12 04:35:50 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-risc-v
Author: TelGome
<details>
<summary>Changes</summary>
This pr support RISC-V P extension intrinsics [Packed Narrowing Clip Pair](https://github.com/riscv/riscv-p-spec/blob/master/P-ext-intrinsics.adoc#packed-narrowing-clip-pair)
---
Patch is 34.06 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/215779.diff
10 Files Affected:
- (modified) clang/include/clang/Basic/BuiltinsRISCV.td (+14)
- (modified) clang/lib/CodeGen/TargetBuiltins/RISCV.cpp (+26-1)
- (modified) clang/lib/Headers/riscv_packed_simd.h (+14)
- (modified) clang/test/CodeGen/RISCV/rvp-intrinsics.c (+208)
- (modified) cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c (+76)
- (modified) llvm/include/llvm/IR/IntrinsicsRISCV.td (+8)
- (modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (+97)
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfoP.td (+28)
- (modified) llvm/test/CodeGen/RISCV/rvp-simd-32.ll (+103)
- (modified) llvm/test/CodeGen/RISCV/rvp-simd-64.ll (+99)
``````````diff
diff --git a/clang/include/clang/Basic/BuiltinsRISCV.td b/clang/include/clang/Basic/BuiltinsRISCV.td
index 1e55ab0bc56d5..82e8a2b62e645 100644
--- a/clang/include/clang/Basic/BuiltinsRISCV.td
+++ b/clang/include/clang/Basic/BuiltinsRISCV.td
@@ -275,6 +275,20 @@ def pmulqr_i16x4 : RISCVBuiltin<"_Vector<4, short>(_Vector<4, short>, _Vector<4,
def pmulq_i32x2 : RISCVBuiltin<"_Vector<2, int>(_Vector<2, int>, _Vector<2, int>)">;
def pmulqr_i32x2 : RISCVBuiltin<"_Vector<2, int>(_Vector<2, int>, _Vector<2, int>)">;
+// Packed Narrowing Clip Pair (32-bit)
+def pnclipp_i8x4 : RISCVBuiltin<"_Vector<4, signed char>(_Vector<2, short>, _Vector<2, short>)">;
+def pnclipup_u8x4 : RISCVBuiltin<"_Vector<4, unsigned char>(_Vector<2, unsigned short>, _Vector<2, unsigned short>)">;
+def pnclipp_i16x2 : RISCVBuiltin<"_Vector<2, short>(int, int)">;
+def pnclipup_u16x2 : RISCVBuiltin<"_Vector<2, unsigned short>(unsigned int, unsigned int)">;
+
+// Packed Narrowing Clip Pair (64-bit)
+def pnclipp_i8x8 : RISCVBuiltin<"_Vector<8, signed char>(_Vector<4, short>, _Vector<4, short>)">;
+def pnclipup_u8x8 : RISCVBuiltin<"_Vector<8, unsigned char>(_Vector<4, unsigned short>, _Vector<4, unsigned short>)">;
+def pnclipp_i16x4 : RISCVBuiltin<"_Vector<4, short>(_Vector<2, int>, _Vector<2, int>)">;
+def pnclipup_u16x4 : RISCVBuiltin<"_Vector<4, unsigned short>(_Vector<2, unsigned int>, _Vector<2, unsigned int>)">;
+def pnclipp_i32x2 : RISCVBuiltin<"_Vector<2, int>(int64_t, int64_t)">;
+def pnclipup_u32x2 : RISCVBuiltin<"_Vector<2, unsigned int>(uint64_t, uint64_t)">;
+
} // Features = "experimental-p"
//===----------------------------------------------------------------------===//
diff --git a/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp b/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp
index 65e43e928e1f0..189352468e1c0 100644
--- a/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp
+++ b/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp
@@ -1392,7 +1392,18 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID,
case RISCV::BI__builtin_riscv_predsumu_u16x4_u32:
case RISCV::BI__builtin_riscv_predsumu_u8x8_u64:
case RISCV::BI__builtin_riscv_predsumu_u16x4_u64:
- case RISCV::BI__builtin_riscv_predsumu_u32x2_u64: {
+ case RISCV::BI__builtin_riscv_predsumu_u32x2_u64:
+ // Packed Narrowing Clip Pair
+ case RISCV::BI__builtin_riscv_pnclipp_i8x4:
+ case RISCV::BI__builtin_riscv_pnclipp_i8x8:
+ case RISCV::BI__builtin_riscv_pnclipp_i16x2:
+ case RISCV::BI__builtin_riscv_pnclipp_i16x4:
+ case RISCV::BI__builtin_riscv_pnclipp_i32x2:
+ case RISCV::BI__builtin_riscv_pnclipup_u8x4:
+ case RISCV::BI__builtin_riscv_pnclipup_u8x8:
+ case RISCV::BI__builtin_riscv_pnclipup_u16x2:
+ case RISCV::BI__builtin_riscv_pnclipup_u16x4:
+ case RISCV::BI__builtin_riscv_pnclipup_u32x2: {
switch (BuiltinID) {
default:
llvm_unreachable("unexpected builtin ID");
@@ -1414,6 +1425,20 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID,
case RISCV::BI__builtin_riscv_predsumu_u32x2_u64:
ID = Intrinsic::riscv_predsumu;
break;
+ case RISCV::BI__builtin_riscv_pnclipp_i8x4:
+ case RISCV::BI__builtin_riscv_pnclipp_i8x8:
+ case RISCV::BI__builtin_riscv_pnclipp_i16x2:
+ case RISCV::BI__builtin_riscv_pnclipp_i16x4:
+ case RISCV::BI__builtin_riscv_pnclipp_i32x2:
+ ID = Intrinsic::riscv_pnclipp;
+ break;
+ case RISCV::BI__builtin_riscv_pnclipup_u8x4:
+ case RISCV::BI__builtin_riscv_pnclipup_u8x8:
+ case RISCV::BI__builtin_riscv_pnclipup_u16x2:
+ case RISCV::BI__builtin_riscv_pnclipup_u16x4:
+ case RISCV::BI__builtin_riscv_pnclipup_u32x2:
+ ID = Intrinsic::riscv_pnclipup;
+ break;
}
IntrinsicTypes = {ResultType, Ops[0]->getType()};
diff --git a/clang/lib/Headers/riscv_packed_simd.h b/clang/lib/Headers/riscv_packed_simd.h
index ded18175b7453..bcaa3e0f29c0e 100644
--- a/clang/lib/Headers/riscv_packed_simd.h
+++ b/clang/lib/Headers/riscv_packed_simd.h
@@ -742,6 +742,20 @@ __packed_binary_builtin(pmulqr_i16x4, int16x4_t, __builtin_riscv_pmulqr_i16x4)
__packed_binary_builtin(pmulq_i32x2, int32x2_t, __builtin_riscv_pmulq_i32x2)
__packed_binary_builtin(pmulqr_i32x2, int32x2_t, __builtin_riscv_pmulqr_i32x2)
+/* Packed Narrowing Clip Pair (32-bit) */
+__packed_binary_builtin_cast(pnclipp_i8x4, int16x2_t, int8x4_t, __builtin_riscv_pnclipp_i8x4)
+__packed_binary_builtin_cast(pnclipup_u8x4, uint16x2_t, uint8x4_t, __builtin_riscv_pnclipup_u8x4)
+__packed_binary_builtin_cast(pnclipp_i16x2, int, int16x2_t, __builtin_riscv_pnclipp_i16x2)
+__packed_binary_builtin_cast(pnclipup_u16x2, unsigned int, uint16x2_t, __builtin_riscv_pnclipup_u16x2)
+
+/* Packed Narrowing Clip Pair (64-bit) */
+__packed_binary_builtin_cast(pnclipp_i8x8, int16x4_t, int8x8_t, __builtin_riscv_pnclipp_i8x8)
+__packed_binary_builtin_cast(pnclipup_u8x8, uint16x4_t, uint8x8_t, __builtin_riscv_pnclipup_u8x8)
+__packed_binary_builtin_cast(pnclipp_i16x4, int32x2_t, int16x4_t, __builtin_riscv_pnclipp_i16x4)
+__packed_binary_builtin_cast(pnclipup_u16x4, uint32x2_t, uint16x4_t, __builtin_riscv_pnclipup_u16x4)
+__packed_binary_builtin_cast(pnclipp_i32x2, int64_t, int32x2_t, __builtin_riscv_pnclipp_i32x2)
+__packed_binary_builtin_cast(pnclipup_u32x2, uint64_t, uint32x2_t, __builtin_riscv_pnclipup_u32x2)
+
/* Reinterpret Casts, Packed <-> Scalar (32-bit) */
__packed_reinterpret(u8x4_u32, uint32_t, uint8x4_t)
__packed_reinterpret(u16x2_u32, uint32_t, uint16x2_t)
diff --git a/clang/test/CodeGen/RISCV/rvp-intrinsics.c b/clang/test/CodeGen/RISCV/rvp-intrinsics.c
index 9ba0428e192f0..4fd28e5919ff6 100644
--- a/clang/test/CodeGen/RISCV/rvp-intrinsics.c
+++ b/clang/test/CodeGen/RISCV/rvp-intrinsics.c
@@ -9353,3 +9353,211 @@ int16x4_t test_pnziph_i16x4(int32x2_t rs1, int32x2_t rs2) {
uint16x4_t test_pnziph_u16x4(uint32x2_t rs1, uint32x2_t rs2) {
return __riscv_pnziph_u16x4(rs1, rs2);
}
+
+/* Packed Narrowing Clip Pair (32-bit) */
+
+// RV32-LABEL: define dso_local i32 @test_pnclipp_i8x4(
+// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
+// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
+// RV32-NEXT: [[TMP2:%.*]] = call <4 x i8> @llvm.riscv.pnclipp.v4i8.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// RV32-NEXT: [[TMP3:%.*]] = bitcast <4 x i8> [[TMP2]] to i32
+// RV32-NEXT: ret i32 [[TMP3]]
+//
+// RV64-LABEL: define dso_local i32 @test_pnclipp_i8x4(
+// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
+// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
+// RV64-NEXT: [[TMP2:%.*]] = call <4 x i8> @llvm.riscv.pnclipp.v4i8.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// RV64-NEXT: [[TMP3:%.*]] = bitcast <4 x i8> [[TMP2]] to i32
+// RV64-NEXT: ret i32 [[TMP3]]
+//
+int8x4_t test_pnclipp_i8x4(int16x2_t rs1, int16x2_t rs2) {
+ return __riscv_pnclipp_i8x4(rs1, rs2);
+}
+
+// RV32-LABEL: define dso_local i32 @test_pnclipup_u8x4(
+// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
+// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
+// RV32-NEXT: [[TMP2:%.*]] = call <4 x i8> @llvm.riscv.pnclipup.v4i8.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// RV32-NEXT: [[TMP3:%.*]] = bitcast <4 x i8> [[TMP2]] to i32
+// RV32-NEXT: ret i32 [[TMP3]]
+//
+// RV64-LABEL: define dso_local i32 @test_pnclipup_u8x4(
+// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16>
+// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16>
+// RV64-NEXT: [[TMP2:%.*]] = call <4 x i8> @llvm.riscv.pnclipup.v4i8.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+// RV64-NEXT: [[TMP3:%.*]] = bitcast <4 x i8> [[TMP2]] to i32
+// RV64-NEXT: ret i32 [[TMP3]]
+//
+uint8x4_t test_pnclipup_u8x4(uint16x2_t rs1, uint16x2_t rs2) {
+ return __riscv_pnclipup_u8x4(rs1, rs2);
+}
+
+// RV32-LABEL: define dso_local i32 @test_pnclipp_i16x2(
+// RV32-SAME: i32 noundef [[RS1:%.*]], i32 noundef [[RS2:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[TMP0:%.*]] = call <2 x i16> @llvm.riscv.pnclipp.v2i16.i32(i32 [[RS1]], i32 [[RS2]])
+// RV32-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[TMP0]] to i32
+// RV32-NEXT: ret i32 [[TMP1]]
+//
+// RV64-LABEL: define dso_local i32 @test_pnclipp_i16x2(
+// RV64-SAME: i32 noundef signext [[RS1:%.*]], i32 noundef signext [[RS2:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[TMP0:%.*]] = call <2 x i16> @llvm.riscv.pnclipp.v2i16.i32(i32 [[RS1]], i32 [[RS2]])
+// RV64-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[TMP0]] to i32
+// RV64-NEXT: ret i32 [[TMP1]]
+//
+int16x2_t test_pnclipp_i16x2(int32_t rs1, int32_t rs2) {
+ return __riscv_pnclipp_i16x2(rs1, rs2);
+}
+
+// RV32-LABEL: define dso_local i32 @test_pnclipup_u16x2(
+// RV32-SAME: i32 noundef [[RS1:%.*]], i32 noundef [[RS2:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[TMP0:%.*]] = call <2 x i16> @llvm.riscv.pnclipup.v2i16.i32(i32 [[RS1]], i32 [[RS2]])
+// RV32-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[TMP0]] to i32
+// RV32-NEXT: ret i32 [[TMP1]]
+//
+// RV64-LABEL: define dso_local i32 @test_pnclipup_u16x2(
+// RV64-SAME: i32 noundef signext [[RS1:%.*]], i32 noundef signext [[RS2:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[TMP0:%.*]] = call <2 x i16> @llvm.riscv.pnclipup.v2i16.i32(i32 [[RS1]], i32 [[RS2]])
+// RV64-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[TMP0]] to i32
+// RV64-NEXT: ret i32 [[TMP1]]
+//
+uint16x2_t test_pnclipup_u16x2(uint32_t rs1, uint32_t rs2) {
+ return __riscv_pnclipup_u16x2(rs1, rs2);
+}
+
+/* Packed Narrowing Clip Pair (64-bit) */
+
+// RV32-LABEL: define dso_local i64 @test_pnclipp_i8x8(
+// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
+// RV32-NEXT: [[TMP2:%.*]] = call <8 x i8> @llvm.riscv.pnclipp.v8i8.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
+// RV32-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to i64
+// RV32-NEXT: ret i64 [[TMP3]]
+//
+// RV64-LABEL: define dso_local i64 @test_pnclipp_i8x8(
+// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
+// RV64-NEXT: [[TMP2:%.*]] = call <8 x i8> @llvm.riscv.pnclipp.v8i8.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
+// RV64-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to i64
+// RV64-NEXT: ret i64 [[TMP3]]
+//
+int8x8_t test_pnclipp_i8x8(int16x4_t rs1, int16x4_t rs2) {
+ return __riscv_pnclipp_i8x8(rs1, rs2);
+}
+
+// RV32-LABEL: define dso_local i64 @test_pnclipup_u8x8(
+// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
+// RV32-NEXT: [[TMP2:%.*]] = call <8 x i8> @llvm.riscv.pnclipup.v8i8.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
+// RV32-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to i64
+// RV32-NEXT: ret i64 [[TMP3]]
+//
+// RV64-LABEL: define dso_local i64 @test_pnclipup_u8x8(
+// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16>
+// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16>
+// RV64-NEXT: [[TMP2:%.*]] = call <8 x i8> @llvm.riscv.pnclipup.v8i8.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
+// RV64-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to i64
+// RV64-NEXT: ret i64 [[TMP3]]
+//
+uint8x8_t test_pnclipup_u8x8(uint16x4_t rs1, uint16x4_t rs2) {
+ return __riscv_pnclipup_u8x8(rs1, rs2);
+}
+
+// RV32-LABEL: define dso_local i64 @test_pnclipp_i16x4(
+// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
+// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32>
+// RV32-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pnclipp.v4i16.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
+// RV32-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
+// RV32-NEXT: ret i64 [[TMP3]]
+//
+// RV64-LABEL: define dso_local i64 @test_pnclipp_i16x4(
+// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
+// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32>
+// RV64-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pnclipp.v4i16.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
+// RV64-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
+// RV64-NEXT: ret i64 [[TMP3]]
+//
+int16x4_t test_pnclipp_i16x4(int32x2_t rs1, int32x2_t rs2) {
+ return __riscv_pnclipp_i16x4(rs1, rs2);
+}
+
+// RV32-LABEL: define dso_local i64 @test_pnclipup_u16x4(
+// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
+// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32>
+// RV32-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pnclipup.v4i16.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
+// RV32-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
+// RV32-NEXT: ret i64 [[TMP3]]
+//
+// RV64-LABEL: define dso_local i64 @test_pnclipup_u16x4(
+// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32>
+// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32>
+// RV64-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pnclipup.v4i16.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]])
+// RV64-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
+// RV64-NEXT: ret i64 [[TMP3]]
+//
+uint16x4_t test_pnclipup_u16x4(uint32x2_t rs1, uint32x2_t rs2) {
+ return __riscv_pnclipup_u16x4(rs1, rs2);
+}
+
+// RV32-LABEL: define dso_local i64 @test_pnclipp_i32x2(
+// RV32-SAME: i64 noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[TMP0:%.*]] = call <2 x i32> @llvm.riscv.pnclipp.v2i32.i64(i64 [[RS1]], i64 [[RS2]])
+// RV32-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to i64
+// RV32-NEXT: ret i64 [[TMP1]]
+//
+// RV64-LABEL: define dso_local i64 @test_pnclipp_i32x2(
+// RV64-SAME: i64 noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[TMP0:%.*]] = call <2 x i32> @llvm.riscv.pnclipp.v2i32.i64(i64 [[RS1]], i64 [[RS2]])
+// RV64-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to i64
+// RV64-NEXT: ret i64 [[TMP1]]
+//
+int32x2_t test_pnclipp_i32x2(int64_t rs1, int64_t rs2) {
+ return __riscv_pnclipp_i32x2(rs1, rs2);
+}
+
+// RV32-LABEL: define dso_local i64 @test_pnclipup_u32x2(
+// RV32-SAME: i64 noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]]) #[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[TMP0:%.*]] = call <2 x i32> @llvm.riscv.pnclipup.v2i32.i64(i64 [[RS1]], i64 [[RS2]])
+// RV32-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to i64
+// RV32-NEXT: ret i64 [[TMP1]]
+//
+// RV64-LABEL: define dso_local i64 @test_pnclipup_u32x2(
+// RV64-SAME: i64 noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]]) #[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[TMP0:%.*]] = call <2 x i32> @llvm.riscv.pnclipup.v2i32.i64(i64 [[RS1]], i64 [[RS2]])
+// RV64-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to i64
+// RV64-NEXT: ret i64 [[TMP1]]
+//
+uint32x2_t test_pnclipup_u32x2(uint64_t rs1, uint64_t rs2) {
+ return __riscv_pnclipup_u32x2(rs1, rs2);
+}
diff --git a/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c b/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
index 874ae879ae488..6c225288756af 100644
--- a/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
+++ b/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
@@ -2847,3 +2847,79 @@ uint16x2_t test_punzipe_u16x2(uint16x4_t a) { return __riscv_punzipe_u16x2(a); }
// RV32: pncvth.h
// RV64: pncvth.wh
uint16x2_t test_punzipo_u16x2(uint16x4_t a) { return __riscv_punzipo_u16x2(a); }
+
+// CHECK-LABEL: test_pnclipp_i8x4:
+// RV32: pnclipi.b
+// RV64: pnclipp.b
+int8x4_t test_pnclipp_i8x4(int16x2_t a, int16x2_t b) {
+ return __riscv_pnclipp_i8x4(a, b);
+}
+
+// CHECK-LABEL: test_pnclipup_u8x4:
+// RV32: pnclipiu.b
+// RV64: pnclipup.b
+uint8x4_t test_pnclipup_u8x4(uint16x2_t a, uint16x2_t b) {
+ return __riscv_pnclipup_u8x4(a, b);
+}
+
+// CHECK-LABEL: test_pnclipp_i16x2:
+// RV32: pnclipi.h
+// RV64: pnclipp.h
+int16x2_t test_pnclipp_i16x2(int32_t a, int32_t b) {
+ return __riscv_pnclipp_i16x2(a, b);
+}
+
+// CHECK-LABEL: test_pnclipup_u16x2:
+// RV32: pnclipiu.h
+// RV64: pnclipup.h
+uint16x2_t test_pnclipup_u16x2(uint32_t a, uint32_t b) {
+ return __riscv_pnclipup_u16x2(a, b);
+}
+
+// CHECK-LABEL: test_pnclipp_i8x8:
+// RV32: pnclipi.b
+// RV32: pnclipi.b
+// RV64: pnclipp.b
+int8x8_t test_pnclipp_i8x8(int16x4_t a, int16x4_t b) {
+ return __riscv_pnclipp_i8x8(a, b);
+}
+
+// CHECK-LABEL: test_pnclipup_u8x8:
+// RV32: pnclipiu.b
+// RV32: pnclipiu.b
+// RV64: pnclipup.b
+uint8x8_t test_pnclipup_u8x8(uint16x4_t a, uint16x4_t b) {
+ return __riscv_pnclipup_u8x8(a, b);
+}
+
+// CHECK-LABEL: test_pnclipp_i16x4:
+// RV32: pnclipi.h
+// RV32: pnclipi.h
+// RV64: pnclipp.h
+int16x4_t test_pnclipp_i16x4(int32x2_t a, int32x2_t b) {
+ return __riscv_pnclipp_i16x4(a, b);
+}
+
+// CHECK-LABEL: test_pnclipup_u16x4:
+// RV32: pnclipiu.h
+// RV32: pnclipiu.h
+// RV64: pnclipup.h
+uint16x4_t test_pnclipup_u16x4(uint32x2_t a, uint32x2_t b) {
+ return __riscv_pnclipup_u16x4(a, b);
+}
+
+// CHECK-LABEL: test_pnclipp_i32x2:
+// RV32: nclipi
+// RV32: nclipi
+// RV64: pnclipp.w
+int32x2_t test_pnclipp_i32x2(int64_t a, int64_t b) {
+ return __riscv_pnclipp_i32x2(a, b);
+}
+
+// CHECK-LABEL: test_pnclipup_u32x2:
+// RV32: nclipiu
+// RV32: nclipiu
+// RV64: pnclipup.w
+uint32x2_t test_pnclipup_u32x2(uint64_t a, uint64_t b) {
+ return __riscv_pnclipup_u32x2(a, b);
+}
diff --git a/llvm/include/llvm/IR/IntrinsicsRISCV.td b/llvm/include/llvm/IR/IntrinsicsRISCV.td
index 6e3de3bfbc309..81fa98bf5bda5 100644
--- a/llvm/include/llvm/IR/IntrinsicsRISCV.td
+++ b/llvm/include/llvm/IR/IntrinsicsRISCV.td
@@ -2126,6 +2126,14 @@ class RVPBinaryIntrinsic
[LLVMMatchType<0>],
[IntrNoMem, IntrSpeculatable]>;
def int_riscv_psabs : RVPUnaryIntrinsic;
+
+ // Packed Narrowing Clip Pair
+ class RVPNarrowingClipIntrinsic
+ : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
+ [llvm_any_ty, LLVMMatchType<1>],
+ [IntrNoMem, IntrSpeculatable]>;
+ def int_riscv_pnclipp : RVPNarrowingClipIntrinsic;
+ def int_riscv_pnclipup : RVPNarrowingClipIntrinsic;
} // TargetPrefix = "riscv"
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index ea4803e59ebc1..ef7b4ce4b786e 100644
--- a/llvm/lib/Target/RISCV/RISCVISel...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/215779
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