[llvm] [NVVM][NVPTX] Add tensor map override support in S2G and Reduce intrinsics (PR #215503)

[Rajat Bajpai via llvm-commits]

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+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_107f | FileCheck %s
+; RUN: %if ptxas-sm_107f && ptxas-isa-9.4 %{ llc < %s -mtriple=nvptx64 -mcpu=sm_107f -mattr=+ptx94| %ptxas-verify -arch=sm_94 %}
+
+; RUN: llvm-as < %s | llvm-dis | FileCheck %s --check-prefixes=CHECK-FORMAT
+
+define void @cp_async_bulk_tensor_reduce_tile_override_addr(ptr addrspace(3) %src, ptr %tmap, ptr addrspace(1) %ogbl_addr, i32 %d0, i32 %d1, i32 %d2, i32 %d3, i32 %d4, i64 %ch) {
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rajatbajpai wrote:

sure, done.

https://github.com/llvm/llvm-project/pull/215503