[clang] [llvm] [mlir] [AMDGPU] Fix missing cache bypass scope on seq_cst buffer fat pointer atomics (PR #213585)

[Arseniy Obolenskiy via llvm-commits]

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@@ -4937,6 +5019,81 @@ static Value *upgradeAMDGCNIntrinsicCall(StringRef Name, CallBase *CI,
     return UpgradeLegacyWMMAIUIntrinsicCall(F, CI, Builder, {T1, T2, T3, T4});
   }
 
+  // Legacy buffer atomic/store/atomic-load intrinsics missed the trailing
+  // syncscope metadata operand. Append an empty MDNode, meaning "no scope
+  // info", matching the behavior of these calls before the operand existed.
+  auto UpgradeBufferScopeIntrinsicCall =
+      [](Function *F, CallBase *CI, IRBuilder<> &Builder,
+         ArrayRef<Type *> OverloadTys) -> Value * {
+    SmallVector<Value *, 8> Args(CI->args());
+    Args.push_back(MetadataAsValue::get(Builder.getContext(),
+                                        MDNode::get(Builder.getContext(), {})));
+
+    Function *NewDecl = Intrinsic::getOrInsertDeclaration(
+        F->getParent(), F->getIntrinsicID(), OverloadTys);
+
+    SmallVector<OperandBundleDef, 1> Bundles;
+    CI->getOperandBundlesAsDefs(Bundles);
+
+    auto *NewCall = cast<CallInst>(Builder.CreateCall(NewDecl, Args, Bundles));
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aobolensk wrote:

CallInst operands are fixed size at creation, so adding the trailing scope argument required to build a new call :(

https://github.com/llvm/llvm-project/pull/213585