[llvm] [RISCV][MC] Prioritize features in MultiMismatchFallback (PR #215737)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Aug 11 23:52:17 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-tablegen
Author: saloni-shinde-Q
<details>
<summary>Changes</summary>
## Summary
Add the `PrioritizeFeatureInMultipleNearMisses` AsmParser option and enable
it for RISCV.
When an instruction has both missing features and multiple invalid operands,
prioritize the feature entry when populating `MultiMismatchFallback` so that
diagnostics identify the missing extension.
Keep the existing `MultiMismatchFallback` behavior unchanged for targets that
do not enable the option.
This change was assisted by AI.
---
Patch is 52.51 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/215737.diff
27 Files Affected:
- (modified) llvm/include/llvm/Target/Target.td (+9)
- (modified) llvm/lib/Target/RISCV/RISCV.td (+1)
- (modified) llvm/test/MC/RISCV/priv-invalid.s (+4-4)
- (modified) llvm/test/MC/RISCV/rv32d-invalid.s (+10-5)
- (modified) llvm/test/MC/RISCV/rv32zclsd-invalid.s (+6-6)
- (modified) llvm/test/MC/RISCV/rv32zdinx-invalid.s (+1-1)
- (modified) llvm/test/MC/RISCV/rv32zfh-invalid.s (+4-2)
- (modified) llvm/test/MC/RISCV/rv32zfinx-invalid.s (+1-1)
- (modified) llvm/test/MC/RISCV/rv32zhinx-invalid.s (+1-1)
- (modified) llvm/test/MC/RISCV/rv32zhinxmin-invalid.s (+1-1)
- (modified) llvm/test/MC/RISCV/rv64d-invalid.s (+8-4)
- (modified) llvm/test/MC/RISCV/rv64f-invalid.s (+8-4)
- (modified) llvm/test/MC/RISCV/rv64xtheadmemidx-invalid.s (+34-12)
- (modified) llvm/test/MC/RISCV/rv64zdinx-invalid.s (+1-1)
- (modified) llvm/test/MC/RISCV/rv64zfh-invalid.s (+18-8)
- (modified) llvm/test/MC/RISCV/rv64zfinx-invalid.s (+1-1)
- (modified) llvm/test/MC/RISCV/rv64zhinx-invalid.s (+1-1)
- (modified) llvm/test/MC/RISCV/rv64zhinxmin-invalid.s (+2-2)
- (modified) llvm/test/MC/RISCV/tlsdesc.s (+10-6)
- (modified) llvm/test/MC/RISCV/xqcia-invalid.s (+1-1)
- (modified) llvm/test/MC/RISCV/xqciac-invalid.s (+2-2)
- (modified) llvm/test/MC/RISCV/xqciio-invalid.s (+3-7)
- (modified) llvm/test/MC/RISCV/xqcili-invalid.s (+1-1)
- (modified) llvm/test/MC/RISCV/xqcilo-invalid.s (+32-16)
- (modified) llvm/test/MC/RISCV/xqcilo-pseudos-invalid.s (+12-12)
- (modified) llvm/test/MC/RISCV/xqcilsm-invalid.s (+11-11)
- (modified) llvm/utils/TableGen/AsmMatcherEmitter.cpp (+73-33)
``````````diff
diff --git a/llvm/include/llvm/Target/Target.td b/llvm/include/llvm/Target/Target.td
index 7d1e7a28b7b6e..c8800177c2d77 100644
--- a/llvm/include/llvm/Target/Target.td
+++ b/llvm/include/llvm/Target/Target.td
@@ -1866,6 +1866,15 @@ class AsmParser {
// messages.
bit ReportMultipleNearMisses = false;
+ // PrioritizeFeatureInMultipleNearMisses -
+ // When 0, operand near-misses and feature near-misses are treated equally
+ // in the multiple near-miss reporting path.
+ // When 1, feature near-misses are prioritized over operand near-misses
+ // when multiple near-misses are recorded for the same instruction encoding,
+ // so that diagnostics point to the missing extension rather than a operand
+ // mismatch. Only effective when ReportMultipleNearMisses is also 1.
+ bit PrioritizeFeatureInMultipleNearMisses = false;
+
// OperandParserMethod - If non-empty, this is the name of a custom
// member function of the AsmParser class to call for every custom instruction
// operand to be parsed. If unset, this defaults to calling the generated
diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td
index bc56b3e059ca5..001207db1b251 100644
--- a/llvm/lib/Target/RISCV/RISCV.td
+++ b/llvm/lib/Target/RISCV/RISCV.td
@@ -93,6 +93,7 @@ def RISCVAsmParser : AsmParser {
let ShouldEmitMatchRegisterAltName = true;
let AllowDuplicateRegisterNames = true;
let ReportMultipleNearMisses = true;
+ let PrioritizeFeatureInMultipleNearMisses = true;
let EmitTokenDiagnosticTypes = true;
}
diff --git a/llvm/test/MC/RISCV/priv-invalid.s b/llvm/test/MC/RISCV/priv-invalid.s
index a3346ace3da28..c4bd1e8d74135 100644
--- a/llvm/test/MC/RISCV/priv-invalid.s
+++ b/llvm/test/MC/RISCV/priv-invalid.s
@@ -17,13 +17,13 @@ sfence.w.inval 0x10 # CHECK: :[[@LINE]]:1: error: invalid instruction
sfence.inval.ir 0x10 # CHECK: :[[@LINE]]:1: error: invalid instruction
-hfence.vvma zero, a1, a2 # CHECK: :[[@LINE]]:13: error: unexpected extra operand for instruction
+hfence.vvma zero, a1, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'H' (Hypervisor)
-hfence.vvma a0, 0x10 # CHECK: :[[@LINE]]:13: error: unexpected extra operand for instruction
+hfence.vvma a0, 0x10 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'H' (Hypervisor)
-hfence.gvma zero, a1, a2 # CHECK: :[[@LINE]]:13: error: unexpected extra operand for instruction
+hfence.gvma zero, a1, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'H' (Hypervisor)
-hfence.gvma a0, 0x10 # CHECK: :[[@LINE]]:13: error: unexpected extra operand for instruction
+hfence.gvma a0, 0x10 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'H' (Hypervisor)
hinval.vvma zero, a1, a2 # CHECK: :[[@LINE]]:1: error: invalid instruction
diff --git a/llvm/test/MC/RISCV/rv32d-invalid.s b/llvm/test/MC/RISCV/rv32d-invalid.s
index 4bcb342f7b2e6..f0ac4aca1e118 100644
--- a/llvm/test/MC/RISCV/rv32d-invalid.s
+++ b/llvm/test/MC/RISCV/rv32d-invalid.s
@@ -15,10 +15,15 @@ fld ft1, 100(a10) # CHECK: :[[@LINE]]:14: error: expected register
fsgnjn.d fa100, fa2, fa3 # CHECK: :[[@LINE]]:10: error: register must be a FPR
# Integer registers where FP regs are expected
-fadd.d a2, a1, a0 # CHECK: :[[@LINE]]:1: error: invalid instruction, any one of the following would fix this:
-# CHECK: :[[@LINE-1]]:8: note: register must be a FPR
-# CHECK: :[[@LINE-2]]:8: note: register must be a GPR when used as an FP operand
-# CHECK: :[[@LINE-3]]:8: note: register must be an even-numbered GPR when used as an FP operand
+fadd.d a2, a1, a0
+# CHECK: :[[@LINE-1]]:1: error: invalid instruction, any one of the following would fix this:
+# CHECK: :[[@LINE-2]]:8: note: register must be a FPR
+# CHECK: :[[@LINE-3]]:1: note: instruction requires the following: 'Zdinx' (Double in Integer), RV64I Base Instruction Set
+# CHECK: :[[@LINE-4]]:1: note: instruction requires the following: 'Zdinx' (Double in Integer)
# FP registers where integer regs are expected
-fcvt.wu.d ft2, a1 # CHECK: :[[@LINE]]:11: error: register must be a GPR
+fcvt.wu.d ft2, a1
+# CHECK: :[[@LINE-1]]:1: error: invalid instruction, any one of the following would fix this:
+# CHECK: :[[@LINE-2]]:11: note: register must be a GPR
+# CHECK: :[[@LINE-3]]:1: note: instruction requires the following: 'Zdinx' (Double in Integer), RV64I Base Instruction Set
+# CHECK: :[[@LINE-4]]:1: note: instruction requires the following: 'Zdinx' (Double in Integer)
diff --git a/llvm/test/MC/RISCV/rv32zclsd-invalid.s b/llvm/test/MC/RISCV/rv32zclsd-invalid.s
index 3337e6dd4a029..011a0d72c867a 100644
--- a/llvm/test/MC/RISCV/rv32zclsd-invalid.s
+++ b/llvm/test/MC/RISCV/rv32zclsd-invalid.s
@@ -3,23 +3,23 @@
## GPRPairC
c.ld t1, 4(sp)
# CHECK: :[[@LINE-1]]:1: error: invalid instruction, any one of the following would fix this:
-# CHECK: :[[@LINE-2]]:6: note: register must be a GPR from x8 to x15
+# CHECK: :[[@LINE-2]]:1: note: instruction requires the following: RV64I Base Instruction Set
# CHECK: :[[@LINE-3]]:6: note: register pair must start with x8, x10, x12, or x14
c.sd s2, 4(sp)
# CHECK: :[[@LINE-1]]:1: error: invalid instruction, any one of the following would fix this:
-# CHECK: :[[@LINE-2]]:6: note: register must be a GPR from x8 to x15
+# CHECK: :[[@LINE-2]]:1: note: instruction requires the following: RV64I Base Instruction Set
# CHECK: :[[@LINE-3]]:6: note: register pair must start with x8, x10, x12, or x14
## GPRPairNoX0
c.ldsp x0, 4(sp)
# CHECK: :[[@LINE-1]]:1: error: invalid instruction, any one of the following would fix this:
-# CHECK: :[[@LINE-2]]:9: note: register must be a GPR excluding zero (x0)
+# CHECK: :[[@LINE-2]]:1: note: instruction requires the following: RV64I Base Instruction Set
# CHECK: :[[@LINE-3]]:9: note: register pair must start with an even GPR other than x0
c.ldsp zero, 4(sp)
# CHECK: :[[@LINE-1]]:1: error: invalid instruction, any one of the following would fix this:
-# CHECK: :[[@LINE-2]]:9: note: register must be a GPR excluding zero (x0)
+# CHECK: :[[@LINE-2]]:1: note: instruction requires the following: RV64I Base Instruction Set
# CHECK: :[[@LINE-3]]:9: note: register pair must start with an even GPR other than x0
## uimm9_lsb000
@@ -29,12 +29,12 @@ c.sdsp t1, -8(sp) # CHECK: :[[@LINE]]:12: error: immediate must be a multiple of
## uimm8_lsb000
c.ld s0, -8(sp)
# CHECK: :[[@LINE-1]]:1: error: invalid instruction, any one of the following would fix this:
-# CHECK: :[[@LINE-2]]:7: note: register must be a GPR from x8 to x15
+# CHECK: :[[@LINE-2]]:1: note: instruction requires the following: RV64I Base Instruction Set
# CHECK: :[[@LINE-3]]:11: note: immediate must be a multiple of 8 bytes in the range [0, 248]
c.sd s0, 256(sp)
# CHECK: :[[@LINE-1]]:1: error: invalid instruction, any one of the following would fix this:
-# CHECK: :[[@LINE-2]]:7: note: register must be a GPR from x8 to x15
+# CHECK: :[[@LINE-2]]:1: note: instruction requires the following: RV64I Base Instruction Set
# CHECK: :[[@LINE-3]]:11: note: immediate must be a multiple of 8 bytes in the range [0, 248]
# Invalid register names
diff --git a/llvm/test/MC/RISCV/rv32zdinx-invalid.s b/llvm/test/MC/RISCV/rv32zdinx-invalid.s
index 172f4d6940e91..7aa49c9bcee9b 100644
--- a/llvm/test/MC/RISCV/rv32zdinx-invalid.s
+++ b/llvm/test/MC/RISCV/rv32zdinx-invalid.s
@@ -8,7 +8,7 @@ flw fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following
fadd.d fa0, fa1, fa2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'D' (Double-Precision Floating-Point){{$}}
# Invalid instructions
-fsw a5, 12(sp) # CHECK: :[[@LINE]]:5: error: register must be a FPR
+fsw a5, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'F' (Single-Precision Floating-Point)
fmv.x.w s0, s1 # CHECK: :[[@LINE]]:1: error: invalid instruction
# Invalid register names
diff --git a/llvm/test/MC/RISCV/rv32zfh-invalid.s b/llvm/test/MC/RISCV/rv32zfh-invalid.s
index 5cdca074f469c..139b8af37b46a 100644
--- a/llvm/test/MC/RISCV/rv32zfh-invalid.s
+++ b/llvm/test/MC/RISCV/rv32zfh-invalid.s
@@ -32,7 +32,9 @@ fnmsub.h f18, f19, f20, f21, 0b111 # CHECK: :[[@LINE]]:30: error: operand must b
# Integer registers where FP regs are expected
fadd.h a2, a1, a0 # CHECK: :[[@LINE]]:1: error: invalid instruction, any one of the following would fix this:
# CHECK: :[[@LINE-1]]:8: note: register must be a FPR
-# CHECK: :[[@LINE-2]]:8: note: register must be a GPR when used as an FP operand
+# CHECK: :[[@LINE-2]]:1: note: instruction requires the following: 'Zhinx' (Half Float in Integer)
# FP registers where integer regs are expected
-fcvt.wu.h ft2, a1 # CHECK: :[[@LINE]]:11: error: register must be a GPR
+fcvt.wu.h ft2, a1 # CHECK: :[[@LINE]]:1: error: invalid instruction, any one of the following would fix this:
+# CHECK: :[[@LINE-1]]:11: note: register must be a GPR
+# CHECK: :[[@LINE-2]]:1: note: instruction requires the following: 'Zhinx' (Half Float in Integer)
diff --git a/llvm/test/MC/RISCV/rv32zfinx-invalid.s b/llvm/test/MC/RISCV/rv32zfinx-invalid.s
index 5c47ad769f659..ec2335e3e7e2a 100644
--- a/llvm/test/MC/RISCV/rv32zfinx-invalid.s
+++ b/llvm/test/MC/RISCV/rv32zfinx-invalid.s
@@ -5,7 +5,7 @@ flw fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following
fadd.s fa0, fa1, fa2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'F' (Single-Precision Floating-Point){{$}}
# Invalid instructions
-fsw a5, 12(sp) # CHECK: :[[@LINE]]:5: error: register must be a FPR
+fsw a5, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'F' (Single-Precision Floating-Point)
fmv.x.w s0, s1 # CHECK: :[[@LINE]]:1: error: invalid instruction
fadd.d t1, t3, t5 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zdinx' (Double in Integer){{$}}
diff --git a/llvm/test/MC/RISCV/rv32zhinx-invalid.s b/llvm/test/MC/RISCV/rv32zhinx-invalid.s
index 7077b41cba368..a1bd3116d6d1c 100644
--- a/llvm/test/MC/RISCV/rv32zhinx-invalid.s
+++ b/llvm/test/MC/RISCV/rv32zhinx-invalid.s
@@ -5,7 +5,7 @@ flw fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following
fadd.h fa0, fa1, fa2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point){{$}}
# Invalid instructions
-fsw a5, 12(sp) # CHECK: :[[@LINE]]:5: error: register must be a FPR
+fsw a5, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'F' (Single-Precision Floating-Point)
fmv.x.h s0, s1 # CHECK: :[[@LINE]]:1: error: invalid instruction
# Invalid register names
diff --git a/llvm/test/MC/RISCV/rv32zhinxmin-invalid.s b/llvm/test/MC/RISCV/rv32zhinxmin-invalid.s
index 94bede5c4b46a..86eacff480885 100644
--- a/llvm/test/MC/RISCV/rv32zhinxmin-invalid.s
+++ b/llvm/test/MC/RISCV/rv32zhinxmin-invalid.s
@@ -5,7 +5,7 @@ flw fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following
fcvt.h.s fa0, fa1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal){{$}}
# Invalid instructions
-fsw a5, 12(sp) # CHECK: :[[@LINE]]:5: error: register must be a FPR
+fsw a5, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'F' (Single-Precision Floating-Point)
fmv.x.h s0, s1 # CHECK: :[[@LINE]]:1: error: invalid instruction
# Invalid register names
diff --git a/llvm/test/MC/RISCV/rv64d-invalid.s b/llvm/test/MC/RISCV/rv64d-invalid.s
index 9a211986f6765..79a8bcbf41d8c 100644
--- a/llvm/test/MC/RISCV/rv64d-invalid.s
+++ b/llvm/test/MC/RISCV/rv64d-invalid.s
@@ -1,17 +1,21 @@
# RUN: not llvm-mc -triple riscv64 -mattr=+d < %s 2>&1 | FileCheck %s
# Integer registers where FP regs are expected
-fcvt.l.d ft0, a0 # CHECK: :[[@LINE]]:10: error: register must be a GPR
-fcvt.lu.d ft1, a1 # CHECK: :[[@LINE]]:11: error: register must be a GPR
+fcvt.l.d ft0, a0 # CHECK: :[[@LINE]]:1: error: invalid instruction, any one of the following would fix this:
+# CHECK: :[[@LINE-1]]:10: note: register must be a GPR
+# CHECK: :[[@LINE-2]]:1: note: instruction requires the following: 'Zdinx' (Double in Integer)
+fcvt.lu.d ft1, a1 # CHECK: :[[@LINE]]:1: error: invalid instruction, any one of the following would fix this:
+# CHECK: :[[@LINE-1]]:11: note: register must be a GPR
+# CHECK: :[[@LINE-2]]:1: note: instruction requires the following: 'Zdinx' (Double in Integer)
fmv.x.d ft2, a2 # CHECK: :[[@LINE]]:9: error: register must be a GPR
# FP registers where integer regs are expected
fcvt.d.l a3, ft3 # CHECK: :[[@LINE]]:1: error: invalid instruction, any one of the following would fix this:
# CHECK: :[[@LINE-1]]:10: note: register must be a FPR
-# CHECK: :[[@LINE-2]]:10: note: register must be a GPR when used as an FP operand
+# CHECK: :[[@LINE-2]]:1: note: instruction requires the following: 'Zdinx' (Double in Integer)
fcvt.d.lu a4, ft4 # CHECK: :[[@LINE]]:1: error: invalid instruction, any one of the following would fix this:
# CHECK: :[[@LINE-1]]:11: note: register must be a FPR
-# CHECK: :[[@LINE-2]]:11: note: register must be a GPR when used as an FP operand
+# CHECK: :[[@LINE-2]]:1: note: instruction requires the following: 'Zdinx' (Double in Integer)
fmv.d.x a5, ft5 # CHECK: :[[@LINE]]:9: error: register must be a FPR
diff --git a/llvm/test/MC/RISCV/rv64f-invalid.s b/llvm/test/MC/RISCV/rv64f-invalid.s
index d547a27ee497d..b11e124712781 100644
--- a/llvm/test/MC/RISCV/rv64f-invalid.s
+++ b/llvm/test/MC/RISCV/rv64f-invalid.s
@@ -1,14 +1,18 @@
# RUN: not llvm-mc -triple riscv64 -mattr=+f < %s 2>&1 | FileCheck %s
# Integer registers where FP regs are expected
-fcvt.l.s ft0, a0 # CHECK: :[[@LINE]]:10: error: register must be a GPR
-fcvt.lu.s ft1, a1 # CHECK: :[[@LINE]]:11: error: register must be a GPR
+fcvt.l.s ft0, a0 # CHECK: :[[@LINE]]:1: error: invalid instruction, any one of the following would fix this:
+# CHECK: :[[@LINE-1]]:10: note: register must be a GPR
+# CHECK: :[[@LINE-2]]:1: note: instruction requires the following: 'Zfinx' (Float in Integer)
+fcvt.lu.s ft1, a1 # CHECK: :[[@LINE]]:1: error: invalid instruction, any one of the following would fix this:
+# CHECK: :[[@LINE-1]]:11: note: register must be a GPR
+# CHECK: :[[@LINE-2]]:1: note: instruction requires the following: 'Zfinx' (Float in Integer)
# FP registers where integer regs are expected
fcvt.s.l a2, ft2 # CHECK: :[[@LINE]]:1: error: invalid instruction, any one of the following would fix this:
# CHECK: :[[@LINE-1]]:10: note: register must be a FPR
-# CHECK: :[[@LINE-2]]:10: note: register must be a GPR when used as an FP operand
+# CHECK: :[[@LINE-2]]:1: note: instruction requires the following: 'Zfinx' (Float in Integer)
fcvt.s.lu a3, ft3 # CHECK: :[[@LINE]]:1: error: invalid instruction, any one of the following would fix this:
# CHECK: :[[@LINE-1]]:11: note: register must be a FPR
-# CHECK: :[[@LINE-2]]:11: note: register must be a GPR when used as an FP operand
+# CHECK: :[[@LINE-2]]:1: note: instruction requires the following: 'Zfinx' (Float in Integer)
diff --git a/llvm/test/MC/RISCV/rv64xtheadmemidx-invalid.s b/llvm/test/MC/RISCV/rv64xtheadmemidx-invalid.s
index 0b3d8a7040e78..5e38d155f5840 100644
--- a/llvm/test/MC/RISCV/rv64xtheadmemidx-invalid.s
+++ b/llvm/test/MC/RISCV/rv64xtheadmemidx-invalid.s
@@ -1,13 +1,35 @@
-# RUN: not llvm-mc -triple riscv32 -mattr=+xtheadmemidx < %s 2>&1 | FileCheck %s
-# RUN: not llvm-mc -triple riscv64 -mattr=+xtheadmemidx < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv32 -mattr=+xtheadmemidx < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-RV32 %s
+# RUN: not llvm-mc -triple riscv64 -mattr=+xtheadmemidx < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-RV64 %s
-th.ldia 0(a0), (a1), 0, 0 # CHECK: :[[@LINE]]:10: error: register must be a GPR
-th.ldib a0, 2(a1), 15, 1 # CHECK: :[[@LINE]]:14: error: expected '('
-th.lwia a0, (a1), 30, 2 # CHECK: :[[@LINE]]:20: error: immediate must be an integer in the range [-16, 15]
-th.lwib a0, (a1), -16, 43 # CHECK: :[[@LINE]]:25: error: immediate must be an integer in the range [0, 3]
-th.lhib a0, (a1), -17, 3 # CHECK: :[[@LINE]]:20: error: immediate must be an integer in the range [-16, 15]
-th.lrb -2(a0), a1, a2, 0 # CHECK: :[[@LINE]]:9: error: register must be a GPR
-th.lrw a0, 3(a1), a2, 1 # CHECK: :[[@LINE]]:13: error: register must be a GPR
-th.lrw a0, a1, 4(a2), 2 # CHECK: :[[@LINE]]:17: error: register must be a GPR
-th.lrh a0, a1, a2, 5 # CHECK: :[[@LINE]]:21: error: immediate must be an integer in the range [0, 3]
-th.lrhu a0, a1, a2, -1 # CHECK: :[[@LINE]]:22: error: immediate must be an integer in the range [0, 3]
+# CHECK-RV32: :[[@LINE+2]]:1: error: instruction requires the following: RV64I Base Instruction Set
+# CHECK-RV64: :[[@LINE+1]]:9: error: register must be a GPR
+th.ldia 0(a0), (a1), 0, 0
+# CHECK-RV32: :[[@LINE+2]]:1: error: instruction requires the following: RV64I Base Instruction Set
+# CHECK-RV64: :[[@LINE+1]]:14: error: expected '('
+th.ldib a0, 2(a1), 15, 1
+# CHECK-RV32: :[[@LINE+2]]:20: error: immediate must be an integer in the range [-16, 15]
+# CHECK-RV64: :[[@LINE+1]]:20: error: immediate must be an integer in the range [-16, 15]
+th.lwia a0, (a1), 30, 2
+# CHECK-RV32: :[[@LINE+2]]:25: error: immediate must be an integer in the range [0, 3]
+# CHECK-RV64: :[[@LINE+1]]:25: error: immediate must be an integer in the range [0, 3]
+th.lwib a0, (a1), -16, 43
+# CHECK-RV32: :[[@LINE+2]]:20: error: immediate must be an integer in the range [-16, 15]
+# CHECK-RV64: :[[@LINE+1]]:20: error: immediate must be an integer in the range [-16, 15]
+th.lhib a0, (a1), -17, 3
+# CHECK-RV32: :[[@LINE+2]]:9: error: register must be a GPR
+# CHECK-RV64: :[[@LINE+1]]:9: error: register must be a GPR
+th.lrb -2(a0), a1, a2, 0
+# CHECK-RV32: :[[@LINE+2]]:13: error: register must be a GPR
+# CHECK-RV64: :[[@LINE+1]]:13: error: register must be a GPR
+th.lrw a0, 3(a1), a2, 1
+# CHECK-RV32: :[[@LINE+2]]:17: error: register must be a GPR
+# CHECK-RV64: :[[@LINE+1]]:17: error: register must be a GPR
+th.lrw a0, a1, 4(a2), 2
+# CHECK-RV32: :[[@LINE+2]]:21: error: immediate must be an integer in the range [0, 3]
+# CHECK-RV64: :[[@LINE+1]]:21: error: immediate must be an integer in the range [0, 3]
+th.lrh a0, a1, a2, 5
+# CHECK-RV32: :[[@LINE+2]]:22: error: immediate must be an integer in the range [0, 3]
+# CHECK-RV64: :[[@LINE+1]]:22: error: immediate must be an integer in the range [0, 3]
+th.lrhu a0, a1, a2, -1
diff --git a/llvm/test/MC/RISCV/rv64zdinx-invalid.s b/llvm/test/MC/RISCV/rv64zdinx-invalid.s
index 9c2c38e8d10fa..9d1431bb30792 100644
--- a/llvm/test/MC/RISCV/rv64zdinx-invalid.s
+++ b/llvm/test/MC/RISCV/rv64zdinx-invalid.s
@@ -5,7 +5,7 @@ fld fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following
ld a0, -2049(a1) # CHECK: :[[@LINE]]:8: error: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo specifier or an integer in the range [-2048, 2047]
# Invalid instructions
-fsd a5, 12(sp) # CHECK: :[[@LINE]]:5: error: register must be a FPR
+fsd a5, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'D' (Double-Precision Floating-Point)
sd fa4, 64(sp) # CHECK: :[[@LINE]]:4: error: register must be a GPR
fmv.x.d t2, a2 # CHECK: :[[@LINE]]:1: error: invalid instruction
fmv.d.x a5, t5 # CHECK: :[[@LINE]]:1: error: invalid instruction
diff --git a/llvm/test/MC/RISCV/rv64zfh-invalid.s b/llvm/test/MC/RISCV/rv64zfh-invalid.s
index 4c5a21c690616..b2513d47e3727 100644
--- a/llvm/test/MC/RISCV/rv64zfh-invalid.s
+++ b/llvm/test/MC/RISCV/rv64zfh-invalid.s
@@ -7,13 +7,23 @@ flh ft1, -2049(a0) # CHECK: :[[@LINE]]:10: error: operand must be a symbol with
fsh ft2, 2048(a1) # CHECK: :[[@LINE]]:10: error: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo specifier or an integer in the range [-2048, 2047]
# Integer registers where FP regs are expected
-fcvt.l.h ft0, a0 # CHECK: :[[@LINE]]:10: error: register must be a GPR
-fcvt.lu.h ft1, a1 # CHECK: :[[@LINE]]:11: error: register must be a GPR
+fcvt.l.h ft0, a0
+# CHECK: :[[@LINE-1]]:1: error: invalid instruction, any one of the following would fix this:
+# CHECK: :[[@LINE-2]]:10: note: register must be a GPR
+# CHECK: :[[@LINE-3]]:1: note: instruction requires the following: 'Zhinx' (Half Float in Integer)
+
+fcvt.lu.h ft1, a1
+# CHECK: :[[@LINE-1]]:1: error: invalid instruction...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/215737
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