[llvm] [AtomicExpand] Let targets keep the release fence out of the reservation (PR #214867)

[Josef Schlehofer via llvm-commits]

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@@ -2315,6 +2315,13 @@ class LLVM_ABI TargetLoweringBase {
     return false;
   }
 
+  /// Whether a fence placed between the load-linked and the store-conditional
+  /// can clear the reservation on this target. When it can, AtomicExpandPass
+  /// must not sink the leading fence of a weak cmpxchg into the reservation
+  /// window: the store-conditional would fail, and a weak cmpxchg has no retry
+  /// to re-reserve and recover with. Defaults to false.
+  virtual bool fenceClearsLoadLinkedReservation() const { return false; }
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BKPepe wrote:

Thanks, but it looks like this is indeed the same shape of problem.

The issue is quite old, though, and I don't have any ARMv7 hardware to test this on. The only way I could really verify the ARM side would be to ask @zrzka if they could take a look and test it.

I'd rather focus on getting the PowerPC issue I reported resolved first. I can reproduce that one reliably on my Turris 1.0 and Turris 1.1, and I can also verify whether the fix actually works. Without that, I'm basically stuck. :)

https://github.com/llvm/llvm-project/pull/214867