[llvm] 035c725 - [NVPTX] Cleanup PTX ISA subtarget features (#214623)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Aug 11 20:14:07 PDT 2026
Author: Alex MacLean
Date: 2026-08-11T20:13:58-07:00
New Revision: 035c725dab7d89022fd6b837c0b5fca23d0be648
URL: https://github.com/llvm/llvm-project/commit/035c725dab7d89022fd6b837c0b5fca23d0be648
DIFF: https://github.com/llvm/llvm-project/commit/035c725dab7d89022fd6b837c0b5fca23d0be648.diff
LOG: [NVPTX] Cleanup PTX ISA subtarget features (#214623)
Added:
Modified:
llvm/lib/Target/NVPTX/NVPTX.td
llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
llvm/lib/Target/NVPTX/NVPTXDwarfDebug.cpp
llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
llvm/lib/Target/NVPTX/NVPTXSubtarget.cpp
llvm/lib/Target/NVPTX/NVPTXSubtarget.h
llvm/test/CodeGen/NVPTX/atomicrmw-allow-ftz-atomics.ll
llvm/test/CodeGen/NVPTX/atomicrmw-sm90.ll
llvm/test/CodeGen/NVPTX/atomics-b128.ll
llvm/test/CodeGen/NVPTX/clusterlaunchcontrol-multicast.ll
llvm/test/CodeGen/NVPTX/clusterlaunchcontrol.ll
llvm/test/CodeGen/NVPTX/cmpxchg-sm90.ll
llvm/test/CodeGen/NVPTX/convert-sm100.ll
llvm/test/CodeGen/NVPTX/convert-sm100a.ll
llvm/test/CodeGen/NVPTX/convert-sm103a.ll
llvm/test/CodeGen/NVPTX/convert-ue5m3x2.ll
llvm/test/CodeGen/NVPTX/convert_fp4x2_sm_100f.ll
llvm/test/CodeGen/NVPTX/convert_fp4x2_to_bf16x2.ll
llvm/test/CodeGen/NVPTX/convert_fp6x2_sm_100f.ll
llvm/test/CodeGen/NVPTX/convert_fp6x2_to_bf16x2.ll
llvm/test/CodeGen/NVPTX/convert_fp8x2_sm_100f.ll
llvm/test/CodeGen/NVPTX/convert_fp8x2_to_bf16x2.ll
llvm/test/CodeGen/NVPTX/convert_s2f6x2_sm_100a.ll
llvm/test/CodeGen/NVPTX/cp-async-bulk-ptx86.ll
llvm/test/CodeGen/NVPTX/cp-async-bulk-s2g-sm100.ll
llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-1cta.ll
llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-2cta.ll
llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-cta-sm100.ll
llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-cta-sm100a.ll
llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-cta-sm90.ll
llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-gather4.ll
llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-im2colw.ll
llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-im2colw128.ll
llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s.ll
llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-prefetch-sm100a.ll
llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-reduce-im2colw.ll
llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-s2g-im2colw.ll
llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-s2g-scatter4.ll
llvm/test/CodeGen/NVPTX/f32x2-convert-i32x2.ll
llvm/test/CodeGen/NVPTX/f32x2-instructions.ll
llvm/test/CodeGen/NVPTX/fmax3.ll
llvm/test/CodeGen/NVPTX/fold-movs.ll
llvm/test/CodeGen/NVPTX/fp-contract-f32x2.ll
llvm/test/CodeGen/NVPTX/gvn-scalar-pre-reg-pressure.ll
llvm/test/CodeGen/NVPTX/i32x2-instructions.ll
llvm/test/CodeGen/NVPTX/ldg-invariant-256.ll
llvm/test/CodeGen/NVPTX/load-store-256-addressing-invariant.ll
llvm/test/CodeGen/NVPTX/load-store-256-addressing.ll
llvm/test/CodeGen/NVPTX/load-store-vectors-256.ll
llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-multiple-users.ll
llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-vector-float.ll
llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion.ll
llvm/test/CodeGen/NVPTX/machine-cse-predicate-no-inversion.ll
llvm/test/CodeGen/NVPTX/masked-load-3xhalf.ll
llvm/test/CodeGen/NVPTX/masked-load-vectors.ll
llvm/test/CodeGen/NVPTX/masked-store-variable-mask.ll
llvm/test/CodeGen/NVPTX/masked-store-vectors-256.ll
llvm/test/CodeGen/NVPTX/mbarrier_arr_relaxed.ll
llvm/test/CodeGen/NVPTX/mbarrier_wait_sm90_ptx86.ll
llvm/test/CodeGen/NVPTX/mixed-precision-fp.ll
llvm/test/CodeGen/NVPTX/no-f32x2.ll
llvm/test/CodeGen/NVPTX/reduction-intrinsics.ll
llvm/test/CodeGen/NVPTX/redux-sync-f32.ll
llvm/test/CodeGen/NVPTX/scalarize-non-coalescable-v2f32.ll
llvm/test/CodeGen/NVPTX/st_async_mbarrier_b128.ll
llvm/test/CodeGen/NVPTX/st_async_release.ll
llvm/test/CodeGen/NVPTX/st_async_release_multimem.ll
llvm/test/CodeGen/NVPTX/st_bulk.ll
llvm/test/CodeGen/NVPTX/sub-byte-constant-vector-convert.ll
llvm/test/CodeGen/NVPTX/tcgen05-alloc.ll
llvm/test/CodeGen/NVPTX/tcgen05-commit-sm107.ll
llvm/test/CodeGen/NVPTX/tcgen05-commit.ll
llvm/test/CodeGen/NVPTX/tcgen05-cp.ll
llvm/test/CodeGen/NVPTX/tcgen05-ld-red.ll
llvm/test/CodeGen/NVPTX/tcgen05-ld.ll
llvm/test/CodeGen/NVPTX/tcgen05-mma-block-scale-ptx88-aa.ll
llvm/test/CodeGen/NVPTX/tcgen05-mma-block-scale-ptx88.ll
llvm/test/CodeGen/NVPTX/tcgen05-mma-block-scale.ll
llvm/test/CodeGen/NVPTX/tcgen05-mma-collector-b.ll
llvm/test/CodeGen/NVPTX/tcgen05-mma-disable-output-lane-collector-b.ll
llvm/test/CodeGen/NVPTX/tcgen05-mma-disable-output-lane-i8.ll
llvm/test/CodeGen/NVPTX/tcgen05-mma-disable-output-lane.ll
llvm/test/CodeGen/NVPTX/tcgen05-mma-i8.ll
llvm/test/CodeGen/NVPTX/tcgen05-mma-scale-d.ll
llvm/test/CodeGen/NVPTX/tcgen05-mma-sp-collector-b.ll
llvm/test/CodeGen/NVPTX/tcgen05-mma-sp-disable-output-lane-collector-b.ll
llvm/test/CodeGen/NVPTX/tcgen05-mma-ws-i8.ll
llvm/test/CodeGen/NVPTX/tcgen05-mma-ws.ll
llvm/test/CodeGen/NVPTX/tcgen05-mma.ll
llvm/test/CodeGen/NVPTX/tcgen05-shift.ll
llvm/test/CodeGen/NVPTX/tcgen05-st.ll
llvm/test/CodeGen/NVPTX/tensormap_replace_sm_100a.ll
llvm/test/CodeGen/NVPTX/tensormap_replace_sm_103a.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/NVPTX/NVPTX.td b/llvm/lib/Target/NVPTX/NVPTX.td
index 8804e5c57e5fc..f9be7928ad102 100644
--- a/llvm/lib/Target/NVPTX/NVPTX.td
+++ b/llvm/lib/Target/NVPTX/NVPTX.td
@@ -18,15 +18,21 @@ include "llvm/Target/Target.td"
// PTX ISA versions.
//===----------------------------------------------------------------------===//
-class FeaturePTX<int version>:
- SubtargetFeature<"ptx"# version, "PTXVersion",
+class FeaturePTX<int version, list<SubtargetFeature> implies>:
+ SubtargetFeature<"ptx" # version, "PTXVersion",
"" # version,
- "Use PTX version " # version>;
-
-foreach version = [32, 40, 41, 42, 43, 50, 60, 61, 62, 63, 64, 65, 70, 71, 72,
- 73, 74, 75, 76, 77, 78, 80, 81, 82, 83, 84, 85, 86, 87, 88,
- 90, 91, 92, 93, 94] in
- def PTX#version : FeaturePTX<version>;
+ "Use PTX version " # version, implies>,
+ Predicate<"Subtarget->hasFeature(NVPTX::" # NAME # ")">;
+
+defvar PTXVersions = [32, 40, 41, 42, 43, 50, 60, 61, 62, 63, 64, 65, 70, 71,
+ 72, 73, 74, 75, 76, 77, 78, 80, 81, 82, 83, 84, 85, 86,
+ 87, 88, 90, 91, 92, 93, 94];
+
+foreach version = PTXVersions in
+ def PTX # version : FeaturePTX<version,
+ !foreach(earlier,
+ !filter(v, PTXVersions, !lt(v, version)),
+ !cast<SubtargetFeature>("PTX" # earlier))>;
//===----------------------------------------------------------------------===//
// Target architectures.
diff --git a/llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp b/llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
index 9f8051ebc2ed8..2486818493204 100644
--- a/llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
@@ -1021,7 +1021,7 @@ void NVPTXAsmPrinter::emitKernelFunctionDirectives(const Function &F,
Ctx.diagnose(DiagnosticInfoUnsupported(
F, "blocksareclusters requires reqntid and cluster_dim attributes",
F.getSubprogram()));
- else if (STI->getPTXVersion() < 90)
+ else if (!STI->hasFeature(NVPTX::PTX90))
Ctx.diagnose(DiagnosticInfoUnsupported(
F, "blocksareclusters requires PTX version >= 9.0",
F.getSubprogram()));
@@ -1236,7 +1236,7 @@ bool NVPTXAsmPrinter::doInitialization(Module &M) {
const NVPTXTargetMachine &NTM = static_cast<const NVPTXTargetMachine &>(TM);
const NVPTXSubtarget &STI = *NTM.getSubtargetImpl();
if (M.alias_size() &&
- (STI.getPTXVersion() < 63 || !STI.hasFeature(NVPTX::SM30)))
+ (!STI.hasFeature(NVPTX::PTX63) || !STI.hasFeature(NVPTX::SM30)))
report_fatal_error(".alias requires PTX version >= 6.3 and sm_30");
// We need to call the parent's one explicitly.
@@ -1420,7 +1420,7 @@ void NVPTXAsmPrinter::printModuleLevelGV(const GlobalVariable *GVar,
O << ".visible ";
else
O << ".extern ";
- } else if (STI.getPTXVersion() >= 50 && GVar->hasCommonLinkage() &&
+ } else if (STI.hasFeature(NVPTX::PTX50) && GVar->hasCommonLinkage() &&
GVar->getAddressSpace() == ADDRESS_SPACE_GLOBAL) {
O << ".common ";
} else if (GVar->hasLinkOnceLinkage() || GVar->hasWeakLinkage() ||
@@ -1544,7 +1544,7 @@ void NVPTXAsmPrinter::emitPTXGlobalVariableDefinition(
emitPTXAddressSpace(GVar->getAddressSpace(), O);
if (isManaged(*GVar)) {
- if (STI.getPTXVersion() < 40 || !STI.hasFeature(NVPTX::SM30))
+ if (!STI.hasFeature(NVPTX::PTX40) || !STI.hasFeature(NVPTX::SM30))
report_fatal_error(
".attribute(.managed) requires PTX version >= 4.0 and sm_30");
O << " .attribute(.managed)";
@@ -1843,7 +1843,7 @@ void NVPTXAsmPrinter::emitPTXGlobalVariable(const GlobalVariable *GVar,
O << ".";
emitPTXAddressSpace(GVar->getType()->getAddressSpace(), O);
if (isManaged(*GVar)) {
- if (STI.getPTXVersion() < 40 || !STI.hasFeature(NVPTX::SM30))
+ if (!STI.hasFeature(NVPTX::PTX40) || !STI.hasFeature(NVPTX::SM30))
report_fatal_error(
".attribute(.managed) requires PTX version >= 4.0 and sm_30");
diff --git a/llvm/lib/Target/NVPTX/NVPTXDwarfDebug.cpp b/llvm/lib/Target/NVPTX/NVPTXDwarfDebug.cpp
index 283641d1bf516..80e3f56922660 100644
--- a/llvm/lib/Target/NVPTX/NVPTXDwarfDebug.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXDwarfDebug.cpp
@@ -55,7 +55,7 @@ MCSymbol *NVPTXDwarfDebug::getOrCreateFuncNameSymbol(StringRef LinkageName) {
bool NVPTXDwarfDebug::isEnhancedLineinfo(const MachineFunction &MF) const {
const DISubprogram *SP = MF.getFunction().getSubprogram();
const NVPTXSubtarget &STI = MF.getSubtarget<NVPTXSubtarget>();
- return LineInfoWithInlinedAt && (STI.getPTXVersion() >= 72) && SP &&
+ return LineInfoWithInlinedAt && (STI.hasFeature(NVPTX::PTX72)) && SP &&
(SP->getUnit()->isDebugDirectivesOnly() ||
SP->getUnit()->getEmissionKind() == DICompileUnit::LineTablesOnly);
}
diff --git a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
index 88f7d9495a19c..b6c3a9dbe2078 100644
--- a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
@@ -560,11 +560,13 @@ NVPTXTargetLowering::NVPTXTargetLowering(const NVPTXTargetMachine &TM,
case ISD::FMINIMUM:
case ISD::FMAXIMUMNUM:
case ISD::FMINIMUMNUM:
- IsOpSupported &= STI.hasFeature(NVPTX::SM80) && STI.getPTXVersion() >= 70;
+ IsOpSupported &=
+ STI.hasFeature(NVPTX::SM80) && STI.hasFeature(NVPTX::PTX70);
break;
case ISD::FEXP2:
case ISD::FTANH:
- IsOpSupported &= STI.hasFeature(NVPTX::SM75) && STI.getPTXVersion() >= 70;
+ IsOpSupported &=
+ STI.hasFeature(NVPTX::SM75) && STI.hasFeature(NVPTX::PTX70);
break;
}
setOperationAction(Op, VT, IsOpSupported ? Action : NoF16Action);
@@ -587,7 +589,8 @@ NVPTXTargetLowering::NVPTXTargetLowering(const NVPTXTargetMachine &TM,
case ISD::SMIN:
case ISD::UMIN:
case ISD::UMAX:
- IsOpSupported = STI.hasFeature(NVPTX::SM90) && STI.getPTXVersion() >= 80;
+ IsOpSupported =
+ STI.hasFeature(NVPTX::SM90) && STI.hasFeature(NVPTX::PTX80);
break;
}
setOperationAction(Op, VT, IsOpSupported ? Action : NoI16x2Action);
@@ -618,7 +621,7 @@ NVPTXTargetLowering::NVPTXTargetLowering(const NVPTXTargetMachine &TM,
setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f16, Expand);
setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Legal);
- if (STI.hasFeature(NVPTX::SM30) && STI.getPTXVersion() > 31)
+ if (STI.hasFeature(NVPTX::SM30))
setOperationAction(ISD::READSTEADYCOUNTER, MVT::i64, Legal);
setFP16OperationAction(ISD::SETCC, MVT::f16, Legal, Promote);
@@ -861,7 +864,7 @@ NVPTXTargetLowering::NVPTXTargetLowering(const NVPTXTargetMachine &TM,
setOperationAction(ISD::ADDE, MVT::i32, Legal);
setOperationAction(ISD::SUBC, MVT::i32, Legal);
setOperationAction(ISD::SUBE, MVT::i32, Legal);
- if (STI.getPTXVersion() >= 43) {
+ if (STI.hasFeature(NVPTX::PTX43)) {
setOperationAction(ISD::ADDC, MVT::i64, Legal);
setOperationAction(ISD::ADDE, MVT::i64, Legal);
setOperationAction(ISD::SUBC, MVT::i64, Legal);
@@ -954,7 +957,7 @@ NVPTXTargetLowering::NVPTXTargetLowering(const NVPTXTargetMachine &TM,
// f16/f16x2 neg was introduced in PTX 60, SM_53.
const bool IsFP16FP16x2NegAvailable = STI.hasFeature(NVPTX::SM53) &&
- STI.getPTXVersion() >= 60 &&
+ STI.hasFeature(NVPTX::PTX60) &&
STI.allowFP16Math();
for (const auto &VT : {MVT::f16, MVT::v2f16})
setOperationAction(ISD::FNEG, VT,
@@ -979,10 +982,10 @@ NVPTXTargetLowering::NVPTXTargetLowering(const NVPTXTargetMachine &TM,
AddPromotedToType(Op, MVT::bf16, MVT::f32);
}
- if (!STI.hasFeature(NVPTX::SM80) || STI.getPTXVersion() < 71) {
+ if (!STI.hasFeature(NVPTX::SM80) || !STI.hasFeature(NVPTX::PTX71)) {
setOperationAction(ISD::BF16_TO_FP, MVT::f32, Expand);
}
- if (!STI.hasFeature(NVPTX::SM90) || STI.getPTXVersion() < 78) {
+ if (!STI.hasFeature(NVPTX::SM90) || !STI.hasFeature(NVPTX::PTX78)) {
for (MVT VT : {MVT::bf16, MVT::f32, MVT::f64}) {
setOperationAction(ISD::FP_EXTEND, VT, Custom);
setOperationAction(ISD::FP_ROUND, VT, Custom);
@@ -996,7 +999,7 @@ NVPTXTargetLowering::NVPTXTargetLowering(const NVPTXTargetMachine &TM,
// sm_80 only has conversions between f32 and bf16. Custom lower all other
// bf16 conversions.
- if (!STI.hasFeature(NVPTX::SM90) || STI.getPTXVersion() < 78) {
+ if (!STI.hasFeature(NVPTX::SM90) || !STI.hasFeature(NVPTX::PTX78)) {
for (MVT VT : {MVT::i1, MVT::i16, MVT::i32, MVT::i64}) {
setOperationAction(
{ISD::SINT_TO_FP, ISD::UINT_TO_FP, ISD::FP_TO_SINT, ISD::FP_TO_UINT},
@@ -1048,7 +1051,7 @@ NVPTXTargetLowering::NVPTXTargetLowering(const NVPTXTargetMachine &TM,
// - f16/f16x2 (sm_75+, PTX 7.0+)
// - bf16/bf16x2 (sm_90+, PTX 7.8+)
// When f16/bf16 types aren't supported, they are promoted/expanded to f32.
- if (STI.hasFeature(NVPTX::SM75) && STI.getPTXVersion() >= 70)
+ if (STI.hasFeature(NVPTX::SM75) && STI.hasFeature(NVPTX::PTX70))
setOperationAction(ISD::FTANH, MVT::f32, Legal);
setOperationAction(ISD::FTANH, MVT::v2f32, Expand);
@@ -1064,7 +1067,7 @@ NVPTXTargetLowering::NVPTXTargetLowering(const NVPTXTargetMachine &TM,
setOperationAction(ISD::FABS, {MVT::f32, MVT::f64}, Legal);
setOperationAction(ISD::FABS, MVT::v2f32, Expand);
- if (STI.getPTXVersion() >= 65) {
+ if (STI.hasFeature(NVPTX::PTX65)) {
setFP16OperationAction(ISD::FABS, MVT::f16, Legal, Promote);
setFP16OperationAction(ISD::FABS, MVT::v2f16, Legal, Expand);
} else {
@@ -1089,7 +1092,7 @@ NVPTXTargetLowering::NVPTXTargetLowering(const NVPTXTargetMachine &TM,
setOperationAction(Op, MVT::v2f32, Expand);
}
bool SupportsF32MinMaxNaN =
- STI.hasFeature(NVPTX::SM80) && STI.getPTXVersion() >= 70;
+ STI.hasFeature(NVPTX::SM80) && STI.hasFeature(NVPTX::PTX70);
for (const auto &Op : {ISD::FMINIMUM, ISD::FMAXIMUM}) {
setOperationAction(Op, MVT::f32, SupportsF32MinMaxNaN ? Legal : Expand);
setFP16OperationAction(Op, MVT::f16, Legal, Expand);
@@ -1279,7 +1282,7 @@ SDValue NVPTXTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
SmallVectorImpl<SDValue> &InVals) const {
if (CLI.IsVarArg &&
- (STI.getPTXVersion() < 60 || !STI.hasFeature(NVPTX::SM30)))
+ (!STI.hasFeature(NVPTX::PTX60) || !STI.hasFeature(NVPTX::SM30)))
report_fatal_error(
"Support for variadic functions (unsized array parameter) introduced "
"in PTX ISA version 6.0 and requires target sm_30.");
@@ -1682,7 +1685,7 @@ SDValue NVPTXTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
SDValue NVPTXTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
SelectionDAG &DAG) const {
- if (STI.getPTXVersion() < 73 || !STI.hasFeature(NVPTX::SM52)) {
+ if (!STI.hasFeature(NVPTX::PTX73) || !STI.hasFeature(NVPTX::SM52)) {
const Function &Fn = DAG.getMachineFunction().getFunction();
DAG.getContext()->diagnose(DiagnosticInfoUnsupported(
@@ -1723,7 +1726,7 @@ SDValue NVPTXTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
SDValue NVPTXTargetLowering::LowerSTACKRESTORE(SDValue Op,
SelectionDAG &DAG) const {
SDLoc DL(Op.getNode());
- if (STI.getPTXVersion() < 73 || !STI.hasFeature(NVPTX::SM52)) {
+ if (!STI.hasFeature(NVPTX::PTX73) || !STI.hasFeature(NVPTX::SM52)) {
const Function &Fn = DAG.getMachineFunction().getFunction();
DAG.getContext()->diagnose(DiagnosticInfoUnsupported(
@@ -1745,7 +1748,7 @@ SDValue NVPTXTargetLowering::LowerSTACKRESTORE(SDValue Op,
SDValue NVPTXTargetLowering::LowerSTACKSAVE(SDValue Op,
SelectionDAG &DAG) const {
SDLoc DL(Op.getNode());
- if (STI.getPTXVersion() < 73 || !STI.hasFeature(NVPTX::SM52)) {
+ if (!STI.hasFeature(NVPTX::PTX73) || !STI.hasFeature(NVPTX::SM52)) {
const Function &Fn = DAG.getMachineFunction().getFunction();
DAG.getContext()->diagnose(DiagnosticInfoUnsupported(
@@ -1902,7 +1905,7 @@ SDValue NVPTXTargetLowering::LowerVECREDUCE(SDValue Op,
// Whether we can use 3-input min/max when expanding the reduction.
const bool CanUseMinMax3 =
EltTy == MVT::f32 && STI.hasFeature(NVPTX::SM100) &&
- STI.getPTXVersion() >= 88 &&
+ STI.hasFeature(NVPTX::PTX88) &&
(Opcode == ISD::VECREDUCE_FMAX || Opcode == ISD::VECREDUCE_FMIN ||
Opcode == ISD::VECREDUCE_FMAXIMUM || Opcode == ISD::VECREDUCE_FMINIMUM);
@@ -2358,7 +2361,7 @@ SDValue NVPTXTargetLowering::PromoteBinOpIfF32FTZ(SDValue Op,
SDValue NVPTXTargetLowering::LowerINT_TO_FP(SDValue Op,
SelectionDAG &DAG) const {
- assert(!STI.hasFeature(NVPTX::SM90) || STI.getPTXVersion() < 78);
+ assert(!STI.hasFeature(NVPTX::SM90) || !STI.hasFeature(NVPTX::PTX78));
if (Op.getValueType() == MVT::bf16) {
SDLoc Loc(Op);
@@ -2374,7 +2377,7 @@ SDValue NVPTXTargetLowering::LowerINT_TO_FP(SDValue Op,
SDValue NVPTXTargetLowering::LowerFP_TO_INT(SDValue Op,
SelectionDAG &DAG) const {
- assert(!STI.hasFeature(NVPTX::SM90) || STI.getPTXVersion() < 78);
+ assert(!STI.hasFeature(NVPTX::SM90) || !STI.hasFeature(NVPTX::PTX78));
if (Op.getOperand(0).getValueType() == MVT::bf16) {
SDLoc Loc(Op);
@@ -2394,12 +2397,12 @@ SDValue NVPTXTargetLowering::LowerFP_ROUND(SDValue Op,
EVT WideVT = Wide.getValueType();
if (NarrowVT.getScalarType() == MVT::bf16) {
const TargetLowering *TLI = STI.getTargetLowering();
- if (!STI.hasFeature(NVPTX::SM80) || STI.getPTXVersion() < 70) {
+ if (!STI.hasFeature(NVPTX::SM80) || !STI.hasFeature(NVPTX::PTX70)) {
return TLI->expandFP_ROUND(Op.getNode(), DAG);
}
- if (!STI.hasFeature(NVPTX::SM90) || STI.getPTXVersion() < 78) {
+ if (!STI.hasFeature(NVPTX::SM90) || !STI.hasFeature(NVPTX::PTX78)) {
// This combination was the first to support f32 -> bf16.
- if (STI.hasFeature(NVPTX::SM80) && STI.getPTXVersion() >= 70) {
+ if (STI.hasFeature(NVPTX::SM80) && STI.hasFeature(NVPTX::PTX70)) {
if (WideVT.getScalarType() == MVT::f32) {
return Op;
}
@@ -2428,15 +2431,15 @@ SDValue NVPTXTargetLowering::LowerFP_EXTEND(SDValue Op,
EVT WideVT = Op.getValueType();
if (NarrowVT.getScalarType() == MVT::bf16) {
if (WideVT.getScalarType() == MVT::f32 &&
- (!STI.hasFeature(NVPTX::SM80) || STI.getPTXVersion() < 71)) {
+ (!STI.hasFeature(NVPTX::SM80) || !STI.hasFeature(NVPTX::PTX71))) {
SDLoc Loc(Op);
return DAG.getNode(ISD::BF16_TO_FP, Loc, WideVT, Narrow);
}
if (WideVT.getScalarType() == MVT::f64 &&
- (!STI.hasFeature(NVPTX::SM90) || STI.getPTXVersion() < 78)) {
+ (!STI.hasFeature(NVPTX::SM90) || !STI.hasFeature(NVPTX::PTX78))) {
EVT F32 = NarrowVT.changeElementType(*DAG.getContext(), MVT::f32);
SDLoc Loc(Op);
- if (STI.hasFeature(NVPTX::SM80) && STI.getPTXVersion() >= 71) {
+ if (STI.hasFeature(NVPTX::SM80) && STI.hasFeature(NVPTX::PTX71)) {
Op = DAG.getNode(ISD::FP_EXTEND, Loc, F32, Narrow);
} else {
Op = DAG.getNode(ISD::BF16_TO_FP, Loc, F32, Narrow);
@@ -6268,7 +6271,7 @@ static SDValue PerformFMinMaxCombine(SDNode *N,
// 3-input min/max requires PTX 8.8+ and SM_100+, and only supports f32s
EVT VT = N->getValueType(0);
- if (VT != MVT::f32 || STI.getPTXVersion() < 88 ||
+ if (VT != MVT::f32 || !STI.hasFeature(NVPTX::PTX88) ||
!STI.hasFeature(NVPTX::SM100))
return SDValue();
@@ -7505,11 +7508,11 @@ NVPTXTargetLowering::shouldExpandAtomicRMWInIR(const AtomicRMWInst *AI) const {
}
if (Ty->isHalfTy() && (!FTZ || AllowFTZAtomics) &&
- STI.hasFeature(NVPTX::SM70) && STI.getPTXVersion() >= 63)
+ STI.hasFeature(NVPTX::SM70) && STI.hasFeature(NVPTX::PTX63))
return AtomicExpansionKind::None;
if (Ty->isBFloatTy() && STI.hasFeature(NVPTX::SM90) &&
- STI.getPTXVersion() >= 78)
+ STI.hasFeature(NVPTX::PTX78))
return AtomicExpansionKind::None;
if (Ty->isDoubleTy() && STI.hasAtomAddF64())
diff --git a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
index 0df5831cce038..7e9506859318e 100644
--- a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
+++ b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
@@ -148,11 +148,9 @@ def noHWROT32 : Predicate<"!Subtarget->hasHWROT32()">;
def hasDotInstructions : Predicate<"Subtarget->hasDotInstructions()">;
def hasF32x2Instructions : Predicate<"Subtarget->hasF32x2Instructions()">;
-class hasPTX<int version>: Predicate<"Subtarget->getPTXVersion() >= " # version>;
-
// non-sync shfl instructions are not available on sm_70+ in PTX6.4+
def hasSHFL : Predicate<"!(Subtarget->hasFeature(NVPTX::SM70)"
- "&& Subtarget->getPTXVersion() >= 64)">;
+ "&& Subtarget->hasFeature(NVPTX::PTX64))">;
def useFP16Math: Predicate<"Subtarget->allowFP16Math()">;
def hasBF16Math: Predicate<"Subtarget->hasBF16Math()">;
@@ -298,7 +296,7 @@ class I16x2<string OpcStr, SDNode OpNode> :
BasicNVPTXInst<(outs B32:$dst), (ins B32:$a, B32:$b),
OpcStr # "16x2",
[(set v2i16:$dst, (OpNode v2i16:$a, v2i16:$b))]>,
- Requires<[hasPTX<80>, SM90]>;
+ Requires<[PTX80, SM90]>;
// Template for instructions which take 3 int args. The instructions are
// named "<OpcStr>.s32" (e.g. "addc.cc.s32").
@@ -306,7 +304,7 @@ multiclass ADD_SUB_INT_CARRY<string op_str, SDNode op_node, bit commutative> {
let hasSideEffects = 1 in {
defm i32 : I3Inst<op_str # ".s32", op_node, I32RT, commutative>;
defm i64 : I3Inst<op_str # ".s64", op_node, I64RT, commutative,
- requires = [hasPTX<43>]>;
+ requires = [PTX43]>;
}
}
@@ -355,19 +353,19 @@ multiclass FMINIMUMMAXIMUM<string OpcStr, bit NaN, SDPatternOperator OpNode> {
(ins FTZFlag:$ftz),
OpcStr # "$ftz" # nan_str # ".f16x2",
[(set v2f16:$dst, (OpNode v2f16:$a, v2f16:$b))]>,
- Requires<[useFP16Math, SM80, hasPTX<70>]>;
+ Requires<[useFP16Math, SM80, PTX70]>;
def _bf16_rr :
BasicNVPTXInst<(outs B16:$dst),
(ins B16:$a, B16:$b),
OpcStr # nan_str # ".bf16",
[(set bf16:$dst, (OpNode bf16:$a, bf16:$b))]>,
- Requires<[hasBF16Math, SM80, hasPTX<70>]>;
+ Requires<[hasBF16Math, SM80, PTX70]>;
def _bf16x2_rr :
BasicNVPTXInst<(outs B32:$dst),
(ins B32:$a, B32:$b),
OpcStr # nan_str # ".bf16x2",
[(set v2bf16:$dst, (OpNode v2bf16:$a, v2bf16:$b))]>,
- Requires<[hasBF16Math, SM80, hasPTX<70>]>;
+ Requires<[hasBF16Math, SM80, PTX70]>;
}
// Template for 3-input minimum/maximum instructions
@@ -383,21 +381,21 @@ multiclass FMINIMUMMAXIMUM3<string OpcStr, bit NaN, SDNode OpNode> {
(ins FTZFlag:$ftz),
OpcStr # "$ftz" # nan_str # ".f32",
[(set f32:$dst, (OpNode f32:$a, f32:$b, f32:$c))]>,
- Requires<[hasPTX<88>, SM100]>;
+ Requires<[PTX88, SM100]>;
def f32rri :
BasicFlagsNVPTXInst<(outs B32:$dst),
(ins B32:$a, B32:$b, f32imm:$c),
(ins FTZFlag:$ftz),
OpcStr # "$ftz" # nan_str # ".f32",
[(set f32:$dst, (OpNode f32:$a, f32:$b, fpimm:$c))]>,
- Requires<[hasPTX<88>, SM100]>;
+ Requires<[PTX88, SM100]>;
def f32rii :
BasicFlagsNVPTXInst<(outs B32:$dst),
(ins B32:$a, f32imm:$b, f32imm:$c),
(ins FTZFlag:$ftz),
OpcStr # "$ftz" # nan_str # ".f32",
[(set f32:$dst, (OpNode f32:$a, fpimm:$b, fpimm:$c))]>,
- Requires<[hasPTX<88>, SM100]>;
+ Requires<[PTX88, SM100]>;
}
// Template for instructions which take three FP args. The
@@ -497,21 +495,21 @@ multiclass F2_Support_Half<string OpcStr, SDNode OpNode> {
def bf16 : BasicNVPTXInst<(outs B16:$dst), (ins B16:$a),
OpcStr # ".bf16",
[(set bf16:$dst, (OpNode bf16:$a))]>,
- Requires<[SM80, hasPTX<70>]>;
+ Requires<[SM80, PTX70]>;
def bf16x2 : BasicNVPTXInst<(outs B32:$dst), (ins B32:$a),
OpcStr # ".bf16x2",
[(set v2bf16:$dst, (OpNode v2bf16:$a))]>,
- Requires<[SM80, hasPTX<70>]>;
+ Requires<[SM80, PTX70]>;
def f16 : BasicFlagsNVPTXInst<(outs B16:$dst), (ins B16:$a),
(ins FTZFlag:$ftz),
OpcStr # "$ftz.f16",
[(set f16:$dst, (OpNode f16:$a))]>,
- Requires<[SM53, hasPTX<65>]>;
+ Requires<[SM53, PTX65]>;
def f16x2 : BasicFlagsNVPTXInst<(outs B32:$dst), (ins B32:$a),
(ins FTZFlag:$ftz),
OpcStr # "$ftz.f16x2",
[(set v2f16:$dst, (OpNode v2f16:$a))]>,
- Requires<[SM53, hasPTX<65>]>;
+ Requires<[SM53, PTX65]>;
}
@@ -561,16 +559,16 @@ let hasSideEffects = false in {
"cvt${mode:base}${mode:ftz}${mode:relu}${mode:sat}." # ToType # ".bf16">,
Requires<!if(!eq(ToType, "f32"),
// bf16->f32 was introduced early.
- [hasPTX<71>, SM80],
+ [PTX71, SM80],
// bf16->everything else needs sm90/ptx78
- [hasPTX<78>, SM90])>;
+ [PTX78, SM90])>;
def _f32 :
BasicFlagsNVPTXInst<(outs RC:$dst),
(ins B32:$src), (ins CvtMode:$mode),
"cvt${mode:base}${mode:ftz}${mode:relu}${mode:sat}." # ToType # ".f32">,
Requires<!if(!eq(ToType, "bf16"),
// f32->bf16 was introduced early.
- [hasPTX<70>, SM80],
+ [PTX70, SM80],
Preds)>;
def _f64 :
BasicFlagsNVPTXInst<(outs RC:$dst),
@@ -587,7 +585,7 @@ let hasSideEffects = false in {
defm CVT_ # sign # "64" : CVT_FROM_ALL<sign # "64", B64>;
}
defm CVT_f16 : CVT_FROM_ALL<"f16", B16>;
- defm CVT_bf16 : CVT_FROM_ALL<"bf16", B16, [hasPTX<78>, SM90]>;
+ defm CVT_bf16 : CVT_FROM_ALL<"bf16", B16, [PTX78, SM90]>;
defm CVT_f32 : CVT_FROM_ALL<"f32", B32>;
defm CVT_f64 : CVT_FROM_ALL<"f64", B64>;
@@ -614,7 +612,7 @@ let hasSideEffects = false in {
BasicFlagsNVPTXInst<(outs RC:$dst),
(ins B32:$src1, B32:$src2), (ins CvtMode:$mode),
"cvt${mode:base}${mode:relu}." # FromName # ".f32">,
- Requires<[hasPTX<70>, SM80]>;
+ Requires<[PTX70, SM80]>;
def _f32_sf :
BasicFlagsNVPTXInst<(outs RC:$dst),
@@ -648,12 +646,12 @@ let hasSideEffects = false in {
BasicFlagsNVPTXInst<(outs B16:$dst),
(ins B32:$src1, B32:$src2), (ins CvtMode:$mode),
"cvt${mode:base}.satfinite${mode:relu}." # F8Name # "x2.f32">,
- Requires<[hasPTX<81>, SM89]>;
+ Requires<[PTX81, SM89]>;
def _f16x2 :
BasicFlagsNVPTXInst<(outs B16:$dst),
(ins B32:$src), (ins CvtMode:$mode),
"cvt${mode:base}.satfinite${mode:relu}." # F8Name # "x2.f16x2">,
- Requires<[hasPTX<81>, SM89]>;
+ Requires<[PTX81, SM89]>;
def _bf16x2 :
BasicFlagsNVPTXInst<(outs B16:$dst), (ins B32:$src), (ins CvtMode:$mode),
"cvt${mode:base}.satfinite${mode:relu}." # F8Name # "x2.bf16x2">,
@@ -668,7 +666,7 @@ let hasSideEffects = false in {
BasicFlagsNVPTXInst<(outs B32:$dst),
(ins B16:$src), (ins CvtMode:$mode),
"cvt${mode:base}${mode:relu}.f16x2." # F8Name # "x2">,
- Requires<[hasPTX<81>, SM89]>;
+ Requires<[PTX81, SM89]>;
def bf16x2_ # F8Name # x2_scale :
BasicFlagsNVPTXInst<(outs B32:$dst),
(ins B16:$src, B16:$src2), (ins CvtMode:$mode),
@@ -689,7 +687,7 @@ let hasSideEffects = false in {
def CVT_e5m2x4_f32x4_rs_sf : CVT_TO_FP8X4<"e5m2">;
// Float to TF32 conversions
- multiclass CVT_TO_TF32<string Modifier, list<Predicate> Preds = [hasPTX<78>, SM90]> {
+ multiclass CVT_TO_TF32<string Modifier, list<Predicate> Preds = [PTX78, SM90]> {
defvar Intr = !cast<Intrinsic>("int_nvvm_f2tf32_" # !subst(".", "_", Modifier));
def NAME : BasicNVPTXInst<(outs B32:$dst), (ins B32:$src),
@@ -702,13 +700,13 @@ let hasSideEffects = false in {
defm CVT_to_tf32_rz : CVT_TO_TF32<"rz">;
defm CVT_to_tf32_rn_relu : CVT_TO_TF32<"rn.relu">;
defm CVT_to_tf32_rz_relu : CVT_TO_TF32<"rz.relu">;
- defm CVT_to_tf32_rna : CVT_TO_TF32<"rna", [hasPTX<70>, SM80]>;
- defm CVT_to_tf32_rna_satf : CVT_TO_TF32<"rna.satfinite", [hasPTX<81>, SM80]>;
+ defm CVT_to_tf32_rna : CVT_TO_TF32<"rna", [PTX70, SM80]>;
+ defm CVT_to_tf32_rna_satf : CVT_TO_TF32<"rna.satfinite", [PTX81, SM80]>;
- defm CVT_to_tf32_rn_satf : CVT_TO_TF32<"rn.satfinite", [hasPTX<86>, SM100]>;
- defm CVT_to_tf32_rz_satf : CVT_TO_TF32<"rz.satfinite", [hasPTX<86>, SM100]>;
- defm CVT_to_tf32_rn_relu_satf : CVT_TO_TF32<"rn.relu.satfinite", [hasPTX<86>, SM100]>;
- defm CVT_to_tf32_rz_relu_satf : CVT_TO_TF32<"rz.relu.satfinite", [hasPTX<86>, SM100]>;
+ defm CVT_to_tf32_rn_satf : CVT_TO_TF32<"rn.satfinite", [PTX86, SM100]>;
+ defm CVT_to_tf32_rz_satf : CVT_TO_TF32<"rz.satfinite", [PTX86, SM100]>;
+ defm CVT_to_tf32_rn_relu_satf : CVT_TO_TF32<"rn.relu.satfinite", [PTX86, SM100]>;
+ defm CVT_to_tf32_rz_relu_satf : CVT_TO_TF32<"rz.relu.satfinite", [PTX86, SM100]>;
let Predicates = [callSubtarget<"hasS2F6X2ConversionSupport">] in {
def CVT_s2f6x2_f32_sf_scale : BasicFlagsNVPTXInst<(outs B16:$dst),
@@ -861,12 +859,12 @@ def fpround_oneuse : OneUse1<fpround>;
def : Pat<(v2bf16 (build_vector (bf16 (fpround_oneuse f32:$lo)),
(bf16 (fpround_oneuse f32:$hi)))),
(CVT_bf16x2_f32 $hi, $lo, CvtRN)>,
- Requires<[hasPTX<70>, SM80, hasBF16Math]>;
+ Requires<[PTX70, SM80, hasBF16Math]>;
def : Pat<(v2f16 (build_vector (f16 (fpround_oneuse f32:$lo)),
(f16 (fpround_oneuse f32:$hi)))),
(CVT_f16x2_f32 $hi, $lo, CvtRN)>,
- Requires<[hasPTX<70>, SM80, useFP16Math]>;
+ Requires<[PTX70, SM80, useFP16Math]>;
//-----------------------------------
// Selection instructions (selp)
@@ -997,7 +995,7 @@ def UMAX16x2 : I16x2<"max.u", umax>;
def SMIN16x2 : I16x2<"min.s", smin>;
def UMIN16x2 : I16x2<"min.u", umin>;
-let Predicates = [hasPTX<80>, SM90] in {
+let Predicates = [PTX80, SM90] in {
def MIN_RELU_S32 : BasicNVPTXInst<(outs B32:$dst), (ins B32:$a, B32:$b),
"min.relu.s32",
@@ -1131,7 +1129,7 @@ class FNEG16<RegTyInfo t> :
"neg$ftz." # t.PtxType,
[(set t.Ty:$dst, (fneg t.Ty:$src))]>;
-let Predicates = [useFP16Math, hasPTX<60>, SM53] in {
+let Predicates = [useFP16Math, PTX60, SM53] in {
def NEG_F16 : FNEG16<F16RT>;
def NEG_F16x2 : FNEG16<F16X2RT>;
}
@@ -1147,11 +1145,11 @@ class FEXP2Inst<RegTyInfo t, dag flags, string flag_str> :
def EX2_APPROX_f32 : FEXP2Inst<F32RT, (ins FTZFlag:$ftz), "$ftz">;
-let Predicates = [useFP16Math, hasPTX<70>, SM75] in {
+let Predicates = [useFP16Math, PTX70, SM75] in {
def EX2_APPROX_f16 : FEXP2Inst<F16RT, (ins), "">;
def EX2_APPROX_f16x2 : FEXP2Inst<F16X2RT, (ins), "">;
}
-let Predicates = [hasPTX<78>, SM90] in {
+let Predicates = [PTX78, SM90] in {
def EX2_APPROX_bf16 : FEXP2Inst<BF16RT, (ins), ".ftz">;
def EX2_APPROX_bf16x2 : FEXP2Inst<BF16X2RT, (ins), ".ftz">;
}
@@ -1333,13 +1331,13 @@ class FTANHInst<RegTyInfo t> :
[(set t.Ty:$dst, (UnaryOpAllowsApproxFn<ftanh> t.Ty:$src))]>;
def TANH_APPROX_f32 : FTANHInst<F32RT>,
- Requires<[hasPTX<70>, SM75]>;
+ Requires<[PTX70, SM75]>;
-let Predicates = [useFP16Math, hasPTX<70>, SM75] in {
+let Predicates = [useFP16Math, PTX70, SM75] in {
def TANH_APPROX_f16 : FTANHInst<F16RT>;
def TANH_APPROX_f16x2 : FTANHInst<F16X2RT>;
}
-let Predicates = [hasPTX<78>, SM90] in {
+let Predicates = [PTX78, SM90] in {
def TANH_APPROX_bf16 : FTANHInst<BF16RT>;
def TANH_APPROX_bf16x2 : FTANHInst<BF16X2RT>;
}
@@ -1670,7 +1668,7 @@ defm SETP_f32 : FSETP<F32RT>;
defm SETP_f64 : FSETP<F64RT, allow_ftz = false>;
let Predicates = [useFP16Math] in
defm SETP_f16 : FSETP<F16RT>;
-let Predicates = [hasBF16Math, hasPTX<78>, SM90] in
+let Predicates = [hasBF16Math, PTX78, SM90] in
defm SETP_bf16 : FSETP<BF16RT, allow_ftz = false>;
def SETP_f16x2rr :
@@ -1683,7 +1681,7 @@ def SETP_bf16x2rr :
BasicFlagsNVPTXInst<(outs B1:$p, B1:$q),
(ins B32:$a, B32:$b), (ins CmpMode:$cmp),
"setp.${cmp:FCmp}.bf16x2">,
- Requires<[hasBF16Math, hasPTX<78>, SM90]>;
+ Requires<[hasBF16Math, PTX78, SM90]>;
//-----------------------------------
// Data Movement (Load / Store, Move)
@@ -2104,7 +2102,7 @@ def : Pat<(f16 (uint_to_fp i32:$a)), (CVT_f16_u32 $a, CvtRN)>;
def : Pat<(f16 (uint_to_fp i64:$a)), (CVT_f16_u64 $a, CvtRN)>;
// sint -> bf16
-let Predicates = [hasPTX<78>, SM90] in {
+let Predicates = [PTX78, SM90] in {
def : Pat<(bf16 (sint_to_fp i1:$a)), (CVT_bf16_s32 (SELP_b32ii -1, 0, $a), CvtRN)>;
def : Pat<(bf16 (sint_to_fp i16:$a)), (CVT_bf16_s16 $a, CvtRN)>;
def : Pat<(bf16 (sint_to_fp i32:$a)), (CVT_bf16_s32 $a, CvtRN)>;
@@ -2112,7 +2110,7 @@ let Predicates = [hasPTX<78>, SM90] in {
}
// uint -> bf16
-let Predicates = [hasPTX<78>, SM90] in {
+let Predicates = [PTX78, SM90] in {
def : Pat<(bf16 (uint_to_fp i1:$a)), (CVT_bf16_u32 (SELP_b32ii 1, 0, $a), CvtRN)>;
def : Pat<(bf16 (uint_to_fp i16:$a)), (CVT_bf16_u16 $a, CvtRN)>;
def : Pat<(bf16 (uint_to_fp i32:$a)), (CVT_bf16_u32 $a, CvtRN)>;
@@ -2295,7 +2293,7 @@ let hasSideEffects = false in {
// PTX 7.1 lets you avoid a temp register and just use _ as a "sink" for the
// unused high/low part.
- let Predicates = [hasPTX<71>] in {
+ let Predicates = [PTX71] in {
def I32toI16H_Sink : NVPTXInst<(outs B16:$high), (ins B32:$s),
"mov.b32 \t{{_, $high}}, $s;">;
def I32toI16L_Sink : NVPTXInst<(outs B16:$low), (ins B32:$s),
@@ -2307,7 +2305,7 @@ let hasSideEffects = false in {
}
}
-let Predicates = [hasPTX<71>] in {
+let Predicates = [PTX71] in {
def : Pat<(i16 (trunc (srl i32:$s, (i32 16)))), (I32toI16H_Sink i32:$s)>;
def : Pat<(i16 (trunc (sra i32:$s, (i32 16)))), (I32toI16H_Sink i32:$s)>;
def : Pat<(i32 (trunc (srl i64:$s, (i32 32)))), (I64toI32H_Sink i64:$s)>;
@@ -2325,8 +2323,8 @@ def: Pat<(i32 (sext (extractelt v2i16:$src, 0))),
// Handle extracting one element from the pair (32-bit types)
foreach vt = [v2f16, v2bf16, v2i16] in {
- def : Pat<(extractelt vt:$src, 0), (I32toI16L_Sink $src)>, Requires<[hasPTX<71>]>;
- def : Pat<(extractelt vt:$src, 1), (I32toI16H_Sink $src)>, Requires<[hasPTX<71>]>;
+ def : Pat<(extractelt vt:$src, 0), (I32toI16L_Sink $src)>, Requires<[PTX71]>;
+ def : Pat<(extractelt vt:$src, 1), (I32toI16H_Sink $src)>, Requires<[PTX71]>;
def : Pat<(extractelt vt:$src, 0), (I32toI16L $src)>;
def : Pat<(extractelt vt:$src, 1), (I32toI16H $src)>;
@@ -2337,8 +2335,8 @@ foreach vt = [v2f16, v2bf16, v2i16] in {
// Handle extracting one element from the pair (64-bit types)
foreach vt = [v2f32, v2i32] in {
- def : Pat<(extractelt vt:$src, 0), (I64toI32L_Sink $src)>, Requires<[hasPTX<71>]>;
- def : Pat<(extractelt vt:$src, 1), (I64toI32H_Sink $src)>, Requires<[hasPTX<71>]>;
+ def : Pat<(extractelt vt:$src, 0), (I64toI32L_Sink $src)>, Requires<[PTX71]>;
+ def : Pat<(extractelt vt:$src, 1), (I64toI32H_Sink $src)>, Requires<[PTX71]>;
def : Pat<(extractelt vt:$src, 0), (I64toI32L $src)>;
def : Pat<(extractelt vt:$src, 1), (I64toI32H $src)>;
@@ -2428,14 +2426,14 @@ def : Pat<(f16 (fpround f32:$a)), (CVT_f16_f32 $a, CvtRN)>;
// fpround f32 -> bf16
def : Pat<(bf16 (fpround f32:$a)), (CVT_bf16_f32 $a, CvtRN)>,
- Requires<[hasPTX<70>, SM80]>;
+ Requires<[PTX70, SM80]>;
// fpround f64 -> f16
def : Pat<(f16 (fpround f64:$a)), (CVT_f16_f64 $a, CvtRN)>;
// fpround f64 -> bf16
def : Pat<(bf16 (fpround f64:$a)), (CVT_bf16_f64 $a, CvtRN)>,
- Requires<[hasPTX<78>, SM90]>;
+ Requires<[PTX78, SM90]>;
// fpround f64 -> f32
def : Pat<(f32 (fpround f64:$a)), (CVT_f32_f64 $a, CvtRN_FTZ)>, Requires<[doF32FTZ]>;
@@ -2445,14 +2443,14 @@ def : Pat<(f32 (fpround f64:$a)), (CVT_f32_f64 $a, CvtRN)>;
def : Pat<(f32 (fpextend f16:$a)), (CVT_f32_f16 $a, CvtNONE_FTZ)>, Requires<[doF32FTZ]>;
def : Pat<(f32 (fpextend f16:$a)), (CVT_f32_f16 $a, CvtNONE)>;
// fpextend bf16 -> f32
-def : Pat<(f32 (fpextend bf16:$a)), (CVT_f32_bf16 $a, CvtNONE_FTZ)>, Requires<[doF32FTZ, hasPTX<78>, SM90]>;
-def : Pat<(f32 (fpextend bf16:$a)), (CVT_f32_bf16 $a, CvtNONE)>, Requires<[hasPTX<71>, SM80]>;
+def : Pat<(f32 (fpextend bf16:$a)), (CVT_f32_bf16 $a, CvtNONE_FTZ)>, Requires<[doF32FTZ, PTX78, SM90]>;
+def : Pat<(f32 (fpextend bf16:$a)), (CVT_f32_bf16 $a, CvtNONE)>, Requires<[PTX71, SM80]>;
// fpextend f16 -> f64
def : Pat<(f64 (fpextend f16:$a)), (CVT_f64_f16 $a, CvtNONE)>;
// fpextend bf16 -> f64
-def : Pat<(f64 (fpextend bf16:$a)), (CVT_f64_bf16 $a, CvtNONE)>, Requires<[hasPTX<78>, SM90]>;
+def : Pat<(f64 (fpextend bf16:$a)), (CVT_f64_bf16 $a, CvtNONE)>, Requires<[PTX78, SM90]>;
// fpextend f32 -> f64
def : Pat<(f64 (fpextend f32:$a)), (CVT_f64_f32 $a, CvtNONE_FTZ)>, Requires<[doF32FTZ]>;
@@ -2525,7 +2523,7 @@ foreach t = [I32RT, I64RT] in {
(ins t.RC:$size, i32imm:$align),
"alloca.u" # t.Size,
[(set t.Ty:$ptr, (dyn_alloca t.Ty:$size, timm:$align))]>,
- Requires<[hasPTX<73>, SM52]>;
+ Requires<[PTX73, SM52]>;
}
//
@@ -2584,7 +2582,7 @@ def stacksave :
SDNode<"NVPTXISD::STACKSAVE", SDTIntLeaf,
[SDNPHasChain, SDNPSideEffect]>;
-let Predicates = [hasPTX<73>, SM52] in {
+let Predicates = [PTX73, SM52] in {
foreach t = [I32RT, I64RT] in {
def STACKRESTORE_ # t.Size :
BasicNVPTXInst<(outs), (ins t.RC:$ptr),
@@ -2609,10 +2607,10 @@ class NVPTXFenceInst<string scope, string sem, Predicate ptx>:
Requires<[ptx, SM70]>;
foreach scope = ["sys", "gpu", "cluster", "cta"] in {
- def atomic_thread_fence_seq_cst_#scope: NVPTXFenceInst<scope, "sc", hasPTX<60>>;
- def atomic_thread_fence_acq_rel_#scope: NVPTXFenceInst<scope, "acq_rel", hasPTX<60>>;
- def atomic_thread_fence_acquire_#scope: NVPTXFenceInst<scope, "acquire", hasPTX<87>>;
- def atomic_thread_fence_release_#scope: NVPTXFenceInst<scope, "release", hasPTX<87>>;
+ def atomic_thread_fence_seq_cst_#scope: NVPTXFenceInst<scope, "sc", PTX60>;
+ def atomic_thread_fence_acq_rel_#scope: NVPTXFenceInst<scope, "acq_rel", PTX60>;
+ def atomic_thread_fence_acquire_#scope: NVPTXFenceInst<scope, "acquire", PTX87>;
+ def atomic_thread_fence_release_#scope: NVPTXFenceInst<scope, "release", PTX87>;
}
// Perform substitution if fma only has one use, and also if instruction has
@@ -2634,12 +2632,12 @@ class FMARELUInst<RegTyInfo t, bit allow_ftz, PatFrag zero_pat>
"fma.rn" # !if(allow_ftz, "$ftz", "") # ".relu." # t.PtxType,
[(set t.Ty:$dst, (NVPTX_fmaxnum_or_fmaximumnum_nsz (NVPTX_fma_oneuse_and_nnan t.Ty:$a, t.Ty:$b, t.Ty:$c), zero_pat))]>;
-let Predicates = [useFP16Math, hasPTX<70>, SM80] in {
+let Predicates = [useFP16Math, PTX70, SM80] in {
def FMARELU_F16 : FMARELUInst<F16RT, true, fpimm_0>;
def FMARELU_F16X2 : FMARELUInst<F16X2RT, true, zeroinitializer<v2f16>>;
}
-let Predicates = [hasBF16Math, hasPTX<70>, SM80] in {
+let Predicates = [hasBF16Math, PTX70, SM80] in {
def FMARELU_BF16 : FMARELUInst<BF16RT, false, fpimm_0>;
def FMARELU_BF16X2 : FMARELUInst<BF16X2RT, false, zeroinitializer<v2bf16>>;
}
diff --git a/llvm/lib/Target/NVPTX/NVPTXIntrinsics.td b/llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
index 48e036425079e..42fd451813f85 100644
--- a/llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
+++ b/llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
@@ -92,10 +92,10 @@ let isConvergent = true in {
def INT_BAR_WARP_SYNC_I : BasicNVPTXInst<(outs), (ins i32imm:$i), "bar.warp.sync",
[(int_nvvm_bar_warp_sync imm:$i)]>,
- Requires<[hasPTX<60>, SM30]>;
+ Requires<[PTX60, SM30]>;
def INT_BAR_WARP_SYNC_R : BasicNVPTXInst<(outs), (ins B32:$i), "bar.warp.sync",
[(int_nvvm_bar_warp_sync i32:$i)]>,
- Requires<[hasPTX<60>, SM30]>;
+ Requires<[PTX60, SM30]>;
multiclass BARRIER_ALL<string asmstr, Intrinsic intrinsic, list<Predicate> requires = []> {
let Predicates = requires in {
@@ -147,9 +147,9 @@ defm BARRIER_CTA_SYNC_ALIGNED_ALL : BARRIER_ALL<"bar.sync", int_nvvm_barrier_cta
defm BARRIER_CTA_SYNC_ALIGNED : BARRIER_COUNT<"bar.sync", int_nvvm_barrier_cta_sync_aligned_count>;
defm BARRIER_CTA_ARRIVE_ALIGNED : BARRIER_COUNT<"bar.arrive", int_nvvm_barrier_cta_arrive_aligned_count>;
-defm BARRIER_CTA_SYNC_ALL : BARRIER_ALL<"barrier.sync", int_nvvm_barrier_cta_sync_all, [hasPTX<60>]>;
-defm BARRIER_CTA_SYNC : BARRIER_COUNT<"barrier.sync", int_nvvm_barrier_cta_sync_count, [hasPTX<60>]>;
-defm BARRIER_CTA_ARRIVE : BARRIER_COUNT<"barrier.arrive", int_nvvm_barrier_cta_arrive_count, [hasPTX<60>]>;
+defm BARRIER_CTA_SYNC_ALL : BARRIER_ALL<"barrier.sync", int_nvvm_barrier_cta_sync_all, [PTX60]>;
+defm BARRIER_CTA_SYNC : BARRIER_COUNT<"barrier.sync", int_nvvm_barrier_cta_sync_count, [PTX60]>;
+defm BARRIER_CTA_ARRIVE : BARRIER_COUNT<"barrier.arrive", int_nvvm_barrier_cta_arrive_count, [PTX60]>;
defm BARRIER_CTA_RED_POPC_ALIGNED_ALL : BARRIER_RED_ALL<"bar.red.popc.u32", int_nvvm_barrier_cta_red_popc_aligned_all, I32RT>;
defm BARRIER_CTA_RED_AND_ALIGNED_ALL : BARRIER_RED_ALL<"bar.red.and.pred", int_nvvm_barrier_cta_red_and_aligned_all, I1RT>;
@@ -158,15 +158,15 @@ defm BARRIER_CTA_RED_POPC_ALIGNED : BARRIER_RED_COUNT<"bar.red.popc.u32", int_nv
defm BARRIER_CTA_RED_AND_ALIGNED : BARRIER_RED_COUNT<"bar.red.and.pred", int_nvvm_barrier_cta_red_and_aligned_count, I1RT>;
defm BARRIER_CTA_RED_OR_ALIGNED : BARRIER_RED_COUNT<"bar.red.or.pred", int_nvvm_barrier_cta_red_or_aligned_count, I1RT>;
-defm BARRIER_CTA_RED_POPC_ALL : BARRIER_RED_ALL<"barrier.red.popc.u32", int_nvvm_barrier_cta_red_popc_all, I32RT, [hasPTX<60>]>;
-defm BARRIER_CTA_RED_AND_ALL : BARRIER_RED_ALL<"barrier.red.and.pred", int_nvvm_barrier_cta_red_and_all, I1RT, [hasPTX<60>]>;
-defm BARRIER_CTA_RED_OR_ALL : BARRIER_RED_ALL<"barrier.red.or.pred", int_nvvm_barrier_cta_red_or_all, I1RT, [hasPTX<60>]>;
-defm BARRIER_CTA_RED_POPC_COUNT : BARRIER_RED_COUNT<"barrier.red.popc.u32", int_nvvm_barrier_cta_red_popc_count, I32RT, [hasPTX<60>]>;
-defm BARRIER_CTA_RED_AND_COUNT : BARRIER_RED_COUNT<"barrier.red.and.pred", int_nvvm_barrier_cta_red_and_count, I1RT, [hasPTX<60>]>;
-defm BARRIER_CTA_RED_OR_COUNT : BARRIER_RED_COUNT<"barrier.red.or.pred", int_nvvm_barrier_cta_red_or_count, I1RT, [hasPTX<60>]>;
+defm BARRIER_CTA_RED_POPC_ALL : BARRIER_RED_ALL<"barrier.red.popc.u32", int_nvvm_barrier_cta_red_popc_all, I32RT, [PTX60]>;
+defm BARRIER_CTA_RED_AND_ALL : BARRIER_RED_ALL<"barrier.red.and.pred", int_nvvm_barrier_cta_red_and_all, I1RT, [PTX60]>;
+defm BARRIER_CTA_RED_OR_ALL : BARRIER_RED_ALL<"barrier.red.or.pred", int_nvvm_barrier_cta_red_or_all, I1RT, [PTX60]>;
+defm BARRIER_CTA_RED_POPC_COUNT : BARRIER_RED_COUNT<"barrier.red.popc.u32", int_nvvm_barrier_cta_red_popc_count, I32RT, [PTX60]>;
+defm BARRIER_CTA_RED_AND_COUNT : BARRIER_RED_COUNT<"barrier.red.and.pred", int_nvvm_barrier_cta_red_and_count, I1RT, [PTX60]>;
+defm BARRIER_CTA_RED_OR_COUNT : BARRIER_RED_COUNT<"barrier.red.or.pred", int_nvvm_barrier_cta_red_or_count, I1RT, [PTX60]>;
class INT_BARRIER_CLUSTER<string variant, Intrinsic Intr,
- list<Predicate> Preds = [hasPTX<78>, SM90]>:
+ list<Predicate> Preds = [PTX78, SM90]>:
BasicNVPTXInst<(outs), (ins), "barrier.cluster."# variant, [(Intr)]>,
Requires<Preds>;
@@ -174,7 +174,7 @@ def barrier_cluster_arrive:
INT_BARRIER_CLUSTER<"arrive", int_nvvm_barrier_cluster_arrive>;
def barrier_cluster_arrive_relaxed:
INT_BARRIER_CLUSTER<"arrive.relaxed",
- int_nvvm_barrier_cluster_arrive_relaxed, [hasPTX<80>, SM90]>;
+ int_nvvm_barrier_cluster_arrive_relaxed, [PTX80, SM90]>;
def barrier_cluster_wait:
INT_BARRIER_CLUSTER<"wait", int_nvvm_barrier_cluster_wait>;
@@ -183,7 +183,7 @@ def barrier_cluster_arrive_aligned:
INT_BARRIER_CLUSTER<"arrive.aligned", int_nvvm_barrier_cluster_arrive_aligned>;
def barrier_cluster_arrive_relaxed_aligned:
INT_BARRIER_CLUSTER<"arrive.relaxed.aligned",
- int_nvvm_barrier_cluster_arrive_relaxed_aligned, [hasPTX<80>, SM90]>;
+ int_nvvm_barrier_cluster_arrive_relaxed_aligned, [PTX80, SM90]>;
def barrier_cluster_wait_aligned:
INT_BARRIER_CLUSTER<"wait.aligned", int_nvvm_barrier_cluster_wait_aligned>;
@@ -223,7 +223,7 @@ foreach sync = [false, true] in {
InOperandList,
"shfl." # !if(sync, "sync.", "") # mode # ".b32",
[Pattern]>,
- Requires<!if(sync, [SM30, hasPTX<60>], [SM30, hasSHFL])>;
+ Requires<!if(sync, [SM30, PTX60], [SM30, hasSHFL])>;
}
}
}
@@ -233,7 +233,7 @@ foreach sync = [false, true] in {
}
// vote.{all,any,uni,ballot}
-let Predicates = [hasPTX<60>, SM30] in {
+let Predicates = [PTX60, SM30] in {
multiclass VOTE<string mode, RegTyInfo t, Intrinsic op> {
def : BasicNVPTXInst<(outs t.RC:$dest), (ins B1:$pred),
"vote." # mode # "." # t.PtxType,
@@ -261,7 +261,7 @@ let Predicates = [hasPTX<60>, SM30] in {
defm VOTE_SYNC_BALLOT : VOTE_SYNC<"ballot", I32RT, int_nvvm_vote_ballot_sync>;
}
// elect.sync
-let Predicates = [hasPTX<80>, SM90] in {
+let Predicates = [PTX80, SM90] in {
def INT_ELECT_SYNC_I : BasicNVPTXInst<(outs B32:$dest, B1:$pred), (ins i32imm:$mask),
"elect.sync",
[(set i32:$dest, i1:$pred, (int_nvvm_elect_sync imm:$mask))]>;
@@ -270,7 +270,7 @@ def INT_ELECT_SYNC_R : BasicNVPTXInst<(outs B32:$dest, B1:$pred), (ins B32:$mask
[(set i32:$dest, i1:$pred, (int_nvvm_elect_sync i32:$mask))]>;
}
-let Predicates = [hasPTX<60>, SM70] in {
+let Predicates = [PTX60, SM70] in {
multiclass MATCH_ANY_SYNC<Intrinsic op, RegTyInfo t> {
def ii : BasicNVPTXInst<(outs B32:$dest), (ins t.Imm:$value, i32imm:$mask),
"match.any.sync." # t.PtxType,
@@ -315,13 +315,13 @@ let Predicates = [hasPTX<60>, SM70] in {
def ACTIVEMASK : BasicNVPTXInst<(outs B32:$dest), (ins),
"activemask.b32",
[(set i32:$dest, (int_nvvm_activemask))]>,
- Requires<[hasPTX<62>, SM30]>;
+ Requires<[PTX62, SM30]>;
multiclass REDUX_SYNC<string BinOp, string PTXType, Intrinsic Intrin> {
def : BasicNVPTXInst<(outs B32:$dst), (ins B32:$src, B32:$mask),
"redux.sync." # BinOp # "." # PTXType,
[(set i32:$dst, (Intrin i32:$src, B32:$mask))]>,
- Requires<[hasPTX<70>, SM80]>;
+ Requires<[PTX70, SM80]>;
}
defm REDUX_SYNC_UMIN : REDUX_SYNC<"min", "u32", int_nvvm_redux_sync_umin>;
@@ -366,14 +366,14 @@ def INT_MEMBAR_SYS : NullaryInst<"membar.sys", int_nvvm_membar_sys>;
def INT_FENCE_SC_CLUSTER:
NullaryInst<"fence.sc.cluster", int_nvvm_fence_sc_cluster>,
- Requires<[hasPTX<78>, SM90]>;
+ Requires<[PTX78, SM90]>;
def INT_FENCE_MBARRIER_INIT_RELEASE_CLUSTER:
NullaryInst<"fence.mbarrier_init.release.cluster",
int_nvvm_fence_mbarrier_init_release_cluster>,
- Requires<[hasPTX<80>, SM90]>;
+ Requires<[PTX80, SM90]>;
-let Predicates = [hasPTX<86>, SM90] in {
+let Predicates = [PTX86, SM90] in {
def INT_FENCE_ACQUIRE_SYNC_RESTRICT_CLUSTER_CLUSTER:
NullaryInst<"fence.acquire.sync_restrict::shared::cluster.cluster",
int_nvvm_fence_acquire_sync_restrict_space_cluster_scope_cluster>;
@@ -384,7 +384,7 @@ def INT_FENCE_RELEASE_SYNC_RESTRICT_CTA_CLUSTER:
}
// Proxy fence (uni-directional)
-let Predicates = [hasPTX<86>, SM90] in {
+let Predicates = [PTX86, SM90] in {
def INT_NVVM_FENCE_PROXY_ASYNC_GENERIC_ACQUIRE_SYNC_RESTRICT_SPACE_CLUSTER_SCOPE_CLUSTER:
NullaryInst<"fence.proxy.async::generic.acquire.sync_restrict::shared::cluster.cluster",
int_nvvm_fence_proxy_async_generic_acquire_sync_restrict_space_cluster_scope_cluster>;
@@ -397,8 +397,8 @@ def INT_NVVM_FENCE_PROXY_ASYNC_GENERIC_RELEASE_SYNC_RESTRICT_SPACE_CTA_SCOPE_CLU
// Proxy fence (bi-directional)
foreach proxykind = ["alias", "async", "async.global", "async.shared_cta",
"async.shared_cluster"] in {
- defvar Preds = !if(!eq(proxykind, "alias"), [hasPTX<75>, SM70],
- [hasPTX<80>, SM90]);
+ defvar Preds = !if(!eq(proxykind, "alias"), [PTX75, SM70],
+ [PTX80, SM90]);
defvar Intr = IntrinsicName<"llvm.nvvm.fence.proxy." # proxykind>;
def : NullaryInst<"fence.proxy." # !subst("_", "::", proxykind),
!cast<Intrinsic>(Intr.record_name)>, Requires<Preds>;
@@ -406,7 +406,7 @@ foreach proxykind = ["alias", "async", "async.global", "async.shared_cta",
class FENCE_PROXY_TENSORMAP_GENERIC_RELEASE<string Scope, Intrinsic Intr> :
NullaryInst<"fence.proxy.tensormap::generic.release." # Scope, Intr>,
- Requires<[hasPTX<83>, SM90]>;
+ Requires<[PTX83, SM90]>;
def INT_FENCE_PROXY_TENSORMAP_GENERIC_RELEASE_CTA:
FENCE_PROXY_TENSORMAP_GENERIC_RELEASE<"cta",
@@ -427,7 +427,7 @@ class FENCE_PROXY_TENSORMAP_GENERIC_ACQUIRE<string Scope, Intrinsic Intr> :
NVPTXInst<(outs), (ins B64:$addr),
"fence.proxy.tensormap::generic.acquire." # Scope # " [$addr], 128;",
[(Intr i64:$addr, (i32 128))]>,
- Requires<[hasPTX<83>, SM90]>;
+ Requires<[PTX83, SM90]>;
def INT_FENCE_PROXY_TENSORMAP_GENERIC_ACQUIRE_CTA :
FENCE_PROXY_TENSORMAP_GENERIC_ACQUIRE<"cta",
@@ -450,7 +450,7 @@ multiclass CP_ASYNC_MBARRIER_ARRIVE<string NoInc, string AddrSpace, Intrinsic In
def "" : BasicNVPTXInst<(outs), (ins ADDR:$addr),
"cp.async.mbarrier.arrive" # NoInc # AddrSpace # ".b64",
[(Intrin addr:$addr)]>,
- Requires<[hasPTX<70>, SM80]>;
+ Requires<[PTX70, SM80]>;
}
defm CP_ASYNC_MBARRIER_ARRIVE :
@@ -466,17 +466,17 @@ multiclass CP_ASYNC_SHARED_GLOBAL_I<string cc, string cpsize, Intrinsic Intrin,
def "" : NVPTXInst<(outs), (ins ADDR:$dst, ADDR:$src),
"cp.async." # cc # ".shared.global" # " [$dst], [$src], " # cpsize # ";",
[(Intrin addr:$dst, addr:$src)]>,
- Requires<[hasPTX<70>, SM80]>;
+ Requires<[PTX70, SM80]>;
// Variant with src_size parameter
def _s : NVPTXInst<(outs), (ins ADDR:$dst, ADDR:$src, B32:$src_size),
"cp.async." # cc # ".shared.global" # " [$dst], [$src], " # cpsize # ", $src_size;",
[(IntrinS addr:$dst, addr:$src, i32:$src_size)]>,
- Requires<[hasPTX<70>, SM80]>;
+ Requires<[PTX70, SM80]>;
def _si: NVPTXInst<(outs), (ins ADDR:$dst, ADDR:$src, i32imm:$src_size),
"cp.async." # cc # ".shared.global" # " [$dst], [$src], " # cpsize # ", $src_size;",
[(IntrinS addr:$dst, addr:$src, imm:$src_size)]>,
- Requires<[hasPTX<70>, SM80]>;
+ Requires<[PTX70, SM80]>;
}
defm CP_ASYNC_CA_SHARED_GLOBAL_4 :
@@ -495,7 +495,7 @@ defm CP_ASYNC_CG_SHARED_GLOBAL_16 :
CP_ASYNC_SHARED_GLOBAL_I<"cg", "16", int_nvvm_cp_async_cg_shared_global_16,
int_nvvm_cp_async_cg_shared_global_16_s>;
-let Predicates = [hasPTX<70>, SM80] in {
+let Predicates = [PTX70, SM80] in {
def CP_ASYNC_COMMIT_GROUP :
NullaryInst<"cp.async.commit_group", int_nvvm_cp_async_commit_group>;
@@ -507,7 +507,7 @@ let Predicates = [hasPTX<70>, SM80] in {
NullaryInst<"cp.async.wait_all", int_nvvm_cp_async_wait_all>;
}
-let Predicates = [hasPTX<80>, SM90] in {
+let Predicates = [PTX80, SM90] in {
// cp.async.bulk variants of the commit/wait group
def CP_ASYNC_BULK_COMMIT_GROUP :
NullaryInst<"cp.async.bulk.commit_group", int_nvvm_cp_async_bulk_commit_group>;
@@ -550,14 +550,14 @@ multiclass CP_ASYNC_BULK_S2G_INTR<bit has_ch> {
CpAsyncBulkStr<0, 1>.S2G # " [$dst], [$src], $size, $ch;",
CpAsyncBulkStr<0, 0>.S2G # " [$dst], [$src], $size;"),
[(int_nvvm_cp_async_bulk_shared_cta_to_global addr:$dst, addr:$src, i32:$size, i64:$ch, !if(has_ch, -1, 0))]>,
- Requires<[hasPTX<80>, SM90]>;
+ Requires<[PTX80, SM90]>;
def _BM : NVPTXInst<(outs), (ins ADDR:$dst, ADDR:$src, B32:$size, B64:$ch, B16:$mask),
!if(has_ch,
CpAsyncBulkStr<0, 1, 1>.S2G # " [$dst], [$src], $size, $ch, $mask;",
CpAsyncBulkStr<0, 0, 1>.S2G # " [$dst], [$src], $size, $mask;"),
[(int_nvvm_cp_async_bulk_shared_cta_to_global_bytemask addr:$dst, addr:$src, i32:$size, i64:$ch, !if(has_ch, -1, 0), i16:$mask)]>,
- Requires<[hasPTX<86>, SM100]>;
+ Requires<[PTX86, SM100]>;
}
defm CP_ASYNC_BULK_S2G : CP_ASYNC_BULK_S2G_INTR<has_ch = 0>;
defm CP_ASYNC_BULK_S2G_CH : CP_ASYNC_BULK_S2G_INTR<has_ch = 1>;
@@ -572,7 +572,7 @@ multiclass CP_ASYNC_BULK_G2S_INTR<bit has_ch> {
CpAsyncBulkStr<0, 1>.G2S # " [$dst], [$src], $size, [$mbar], $ch;",
CpAsyncBulkStr<0, 0>.G2S # " [$dst], [$src], $size, [$mbar];"),
[(Intr addr:$dst, addr:$mbar, addr:$src, i32:$size, i16:$mask, i64:$ch, 0, !if(has_ch, -1, 0))]>,
- Requires<[hasPTX<80>, SM90]>;
+ Requires<[PTX80, SM90]>;
def _MC : NVPTXInst<(outs),
(ins ADDR:$dst, ADDR:$mbar, ADDR:$src,
@@ -581,7 +581,7 @@ multiclass CP_ASYNC_BULK_G2S_INTR<bit has_ch> {
CpAsyncBulkStr<1, 1>.G2S # " [$dst], [$src], $size, [$mbar], $mask, $ch;",
CpAsyncBulkStr<1, 0>.G2S # " [$dst], [$src], $size, [$mbar], $mask;"),
[(Intr addr:$dst, addr:$mbar, addr:$src, i32:$size, i16:$mask, i64:$ch, -1, !if(has_ch, -1, 0))]>,
- Requires<[hasPTX<80>, SM90]>;
+ Requires<[PTX80, SM90]>;
}
defm CP_ASYNC_BULK_G2S : CP_ASYNC_BULK_G2S_INTR<has_ch = 0>;
defm CP_ASYNC_BULK_G2S_CH : CP_ASYNC_BULK_G2S_INTR<has_ch = 1>;
@@ -596,7 +596,7 @@ multiclass CP_ASYNC_BULK_G2S_CTA_INTR<bit has_ch> {
CpAsyncBulkStr<0, 1>.G2S_CTA # " [$dst], [$src], $size, [$mbar], $ch;",
CpAsyncBulkStr<0, 0>.G2S_CTA # " [$dst], [$src], $size, [$mbar];"),
[(Intr addr:$dst, addr:$mbar, addr:$src, i32:$size, i64:$ch, !if(has_ch, -1, 0))]>,
- Requires<[hasPTX<86>, SM90]>;
+ Requires<[PTX86, SM90]>;
}
defm CP_ASYNC_BULK_G2S_CTA : CP_ASYNC_BULK_G2S_CTA_INTR<has_ch = 0>;
defm CP_ASYNC_BULK_G2S_CTA_CH : CP_ASYNC_BULK_G2S_CTA_INTR<has_ch = 1>;
@@ -605,7 +605,7 @@ def CP_ASYNC_BULK_CTA_TO_CLUSTER : NVPTXInst<(outs),
(ins ADDR:$dst, ADDR:$mbar, ADDR:$src, B32:$size),
CpAsyncBulkStr<0, 0>.C2C # " [$dst], [$src], $size, [$mbar];",
[(int_nvvm_cp_async_bulk_shared_cta_to_cluster addr:$dst, addr:$mbar, addr:$src, i32:$size)]>,
- Requires<[hasPTX<80>, SM90]>;
+ Requires<[PTX80, SM90]>;
multiclass CP_ASYNC_BULK_PREFETCH_INTR<bit has_ch> {
def "" : NVPTXInst<(outs), (ins ADDR:$src, B32:$size, B64:$ch),
@@ -613,7 +613,7 @@ multiclass CP_ASYNC_BULK_PREFETCH_INTR<bit has_ch> {
"cp.async.bulk.prefetch.L2.global.L2::cache_hint" # " [$src], $size, $ch;",
"cp.async.bulk.prefetch.L2.global" # " [$src], $size;"),
[(int_nvvm_cp_async_bulk_prefetch_L2 addr:$src, i32:$size, i64:$ch, !if(has_ch, -1, 0))]>,
- Requires<[hasPTX<80>, SM90]>;
+ Requires<[PTX80, SM90]>;
}
defm CP_ASYNC_BULK_PREFETCH : CP_ASYNC_BULK_PREFETCH_INTR<has_ch = 0>;
defm CP_ASYNC_BULK_PREFETCH_CH : CP_ASYNC_BULK_PREFETCH_INTR<has_ch = 1>;
@@ -720,7 +720,7 @@ multiclass TMA_TENSOR_G2S_INTR<int dim, string mode, list<Predicate> pred,
foreach dim = 1...5 in {
defm TMA_G2S_TILE_CG0_ # dim # "D"
- : TMA_TENSOR_G2S_INTR<dim, "tile", [hasPTX<80>, SM90],
+ : TMA_TENSOR_G2S_INTR<dim, "tile", [PTX80, SM90],
tma_cta_group_imm0>;
defm TMA_G2S_TILE_ # dim # "D"
: TMA_TENSOR_G2S_INTR<dim, "tile",
@@ -728,7 +728,7 @@ foreach dim = 1...5 in {
}
foreach dim = 3...5 in {
defm TMA_G2S_IM2COL_CG0_ # dim # "D"
- : TMA_TENSOR_G2S_INTR<dim, "im2col", [hasPTX<80>, SM90],
+ : TMA_TENSOR_G2S_INTR<dim, "im2col", [PTX80, SM90],
tma_cta_group_imm0>;
defm TMA_G2S_IM2COL_ # dim # "D"
: TMA_TENSOR_G2S_INTR<dim, "im2col",
@@ -788,24 +788,24 @@ multiclass TMA_TENSOR_G2S_CTA_INTR<int dim, string mode, list<Predicate> pred =
}
foreach dim = 1...5 in {
defm TMA_G2S_CTA_TILE_ # dim # "D"
- : TMA_TENSOR_G2S_CTA_INTR<dim, "tile", [hasPTX<86>, SM90]>;
+ : TMA_TENSOR_G2S_CTA_INTR<dim, "tile", [PTX86, SM90]>;
}
foreach dim = 3...5 in {
defm TMA_G2S_CTA_IM2COL_ # dim # "D"
- : TMA_TENSOR_G2S_CTA_INTR<dim, "im2col", [hasPTX<86>, SM90]>;
+ : TMA_TENSOR_G2S_CTA_INTR<dim, "im2col", [PTX86, SM90]>;
defm TMA_G2S_CTA_IM2COL_W_ # dim # "D"
- : TMA_TENSOR_G2S_CTA_INTR<dim, "im2col_w", [hasPTX<86>, SM100]>;
+ : TMA_TENSOR_G2S_CTA_INTR<dim, "im2col_w", [PTX86, SM100]>;
defm TMA_G2S_CTA_IM2COL_W_128_ # dim # "D"
: TMA_TENSOR_G2S_CTA_INTR<dim, "im2col_w_128",
[callSubtarget<"hasTMABlackwellSupport">]>;
}
defm TMA_G2S_CTA_TILE_GATHER4_2D : TMA_TENSOR_G2S_CTA_INTR<5, "tile_gather4",
- [hasPTX<86>, SM100]>;
+ [PTX86, SM100]>;
multiclass TMA_TENSOR_S2G_INTR<int dim, string mode,
- list<Predicate> pred = [hasPTX<80>, SM90]> {
+ list<Predicate> pred = [PTX80, SM90]> {
defvar dims_dag = TMA_DIMS_UTIL<dim>.ins_dag;
defvar dims_str = TMA_DIMS_UTIL<dim>.base_str;
defvar asm_str = " [$tmap, {{" # dims_str # "}}], [$src]";
@@ -867,7 +867,7 @@ def tma_tensor_reduction_imm :
// TMA Copy from Shared to Global memory with Reduction
multiclass CP_ASYNC_BULK_TENSOR_REDUCE_INTR<int dim, string mode,
- list<Predicate> pred = [hasPTX<80>, SM90]> {
+ list<Predicate> pred = [PTX80, SM90]> {
defvar dims_dag = TMA_DIMS_UTIL<dim>.ins_dag;
defvar dims_str = TMA_DIMS_UTIL<dim>.base_str;
defvar asm_str = " [$tmap, {{" # dims_str # "}}], [$src]";
@@ -927,7 +927,7 @@ foreach dim = 3...5 in {
// TMA Prefetch from Global memory to L2 cache
multiclass TMA_TENSOR_PREFETCH_INTR<int dim, string mode,
- list<Predicate> pred = [hasPTX<80>, SM90]> {
+ list<Predicate> pred = [PTX80, SM90]> {
defvar dims_dag = TMA_DIMS_UTIL<dim>.ins_dag;
defvar dims_str = TMA_DIMS_UTIL<dim>.base_str;
defvar asm_str_base = " [$tmap, {{" # dims_str # "}}]";
@@ -1001,7 +1001,7 @@ multiclass PREFETCH_TENSORMAP_INST<string addrspace_name, PatFrag pattern_frag>
def "" : BasicNVPTXInst<(outs), (ins ADDR:$addr),
"prefetch" # addrspace_name # ".tensormap",
[(pattern_frag addr:$addr)]>,
- Requires<[hasPTX<80>, SM90]>;
+ Requires<[PTX80, SM90]>;
}
defm PREFETCH_CONST_TENSORMAP : PREFETCH_TENSORMAP_INST<".const", prefetch_tensormap_const>;
@@ -1012,7 +1012,7 @@ class PREFETCH_INTRS<string InstName, Intrinsic Intr> :
BasicNVPTXInst<(outs), (ins ADDR:$addr),
InstName,
[(Intr addr:$addr)]>,
- Requires<[hasPTX<80>, SM90]>;
+ Requires<[PTX80, SM90]>;
def PREFETCHU_L1 : PREFETCH_INTRS<"prefetchu.L1", int_nvvm_prefetchu_L1>;
def PREFETCH_L1 : PREFETCH_INTRS<"prefetch.L1", int_nvvm_prefetch_L1>;
@@ -1032,7 +1032,7 @@ class APPLYPRIORITY_L2_INTRS<string addrspace> :
StrJoin<".", ["applypriority", addrspace , "L2::evict_normal"]>.ret,
[(!cast<Intrinsic>(StrJoin<"_", ["int_nvvm_applypriority", addrspace , "L2_evict_normal"]>.ret)
addr:$addr, i64:$size)]>,
- Requires<[hasPTX<74>, SM80]>;
+ Requires<[PTX74, SM80]>;
def APPLYPRIORITY_L2_EVICT_NORMAL : APPLYPRIORITY_L2_INTRS<"">;
def APPLYPRIORITY_GLOBAL_L2_EVICT_NORMAL : APPLYPRIORITY_L2_INTRS<"global">;
@@ -1046,7 +1046,7 @@ class DISCARD_L2_INTRS<string addrspace> :
StrJoin<".", ["discard", addrspace , "L2"]>.ret,
[(!cast<Intrinsic>(StrJoin<"_", ["int_nvvm_discard", addrspace , "L2"]>.ret)
addr:$addr, discard_size_imm:$size)]>,
- Requires<[hasPTX<74>, SM80]>;
+ Requires<[PTX74, SM80]>;
def DISCARD_L2 : DISCARD_L2_INTRS<"">;
def DISCARD_GLOBAL_L2 : DISCARD_L2_INTRS<"global">;
@@ -1055,7 +1055,7 @@ def DISCARD_GLOBAL_L2 : DISCARD_L2_INTRS<"global">;
// MBarrier Functions
//-----------------------------------
-let Predicates = [hasPTX<70>, SM80] in {
+let Predicates = [PTX70, SM80] in {
class MBARRIER_INIT<string AddrSpace, Intrinsic Intrin> :
BasicNVPTXInst<(outs), (ins ADDR:$addr, B32:$count),
"mbarrier.init" # AddrSpace # ".b64",
@@ -1182,11 +1182,11 @@ class MBAR_UTIL<string op, string scope,
!eq(sem, "relaxed")) : SM90,
true : SM80);
Predicate _ptx_pred = !cond(
- !eq(sem, "relaxed") : hasPTX<86>,
- !ne(_scope_asm, "") : hasPTX<80>,
- !eq(op, "try_wait") : hasPTX<78>,
- parity : hasPTX<71>,
- true : hasPTX<70>);
+ !eq(sem, "relaxed") : PTX86,
+ !ne(_scope_asm, "") : PTX80,
+ !eq(op, "try_wait") : PTX78,
+ parity : PTX71,
+ true : PTX70);
list<Predicate> preds = [_ptx_pred, _sm_pred];
}
@@ -1198,7 +1198,7 @@ foreach op = ["expect_tx", "complete_tx"] in {
def mbar_ # suffix : BasicNVPTXInst<(outs), (ins ADDR:$addr, B32:$tx_count),
MBAR_UTIL<op, scope, space, "relaxed">.asm_str,
[(intr addr:$addr, i32:$tx_count)]>,
- Requires<[hasPTX<80>, SM90]>;
+ Requires<[PTX80, SM90]>;
} // space
} // scope
} // op
@@ -1234,8 +1234,8 @@ foreach op = ["arrive", "arrive.expect_tx",
"arrive_drop", "arrive_drop.expect_tx"] in {
foreach scope = ["scope_cta", "scope_cluster"] in {
defvar suffix = !subst(".", "_", op) # scope;
- defm mbar_ # suffix # _release : MBAR_ARR_INTR<op, scope, "", [hasPTX<80>, SM90]>;
- defm mbar_ # suffix # _relaxed : MBAR_ARR_INTR<op, scope, "relaxed", [hasPTX<86>, SM90]>;
+ defm mbar_ # suffix # _release : MBAR_ARR_INTR<op, scope, "", [PTX80, SM90]>;
+ defm mbar_ # suffix # _relaxed : MBAR_ARR_INTR<op, scope, "relaxed", [PTX86, SM90]>;
} // scope
} // op
@@ -1360,10 +1360,10 @@ class F_MATH_3<string OpcStr, NVPTXRegClass t_regclass,
def INT_NVVM_NANOSLEEP_I : BasicNVPTXInst<(outs), (ins i32imm:$i), "nanosleep.u32",
[(int_nvvm_nanosleep imm:$i)]>,
- Requires<[hasPTX<63>, SM70]>;
+ Requires<[PTX63, SM70]>;
def INT_NVVM_NANOSLEEP_R : BasicNVPTXInst<(outs), (ins B32:$i), "nanosleep.u32",
[(int_nvvm_nanosleep i32:$i)]>,
- Requires<[hasPTX<63>, SM70]>;
+ Requires<[PTX63, SM70]>;
def Hexu16imm : Operand<i16> {
let PrintMethod = "printHexUImm<16>";
@@ -1375,7 +1375,7 @@ def INT_PM_EVENT_MASK : BasicNVPTXInst<(outs),
(ins Hexu16imm:$mask),
"pmevent.mask",
[(int_nvvm_pm_event_mask timm:$mask)]>,
- Requires<[SM20, hasPTX<30>]>;
+ Requires<[SM20]>;
} // hasSideEffects
//
@@ -1385,45 +1385,45 @@ def INT_PM_EVENT_MASK : BasicNVPTXInst<(outs),
def : Pat<(int_nvvm_fmin_f f32:$a, f32:$b), (MIN_f32_rr $a, $b, NoFTZ)>;
def : Pat<(int_nvvm_fmin_ftz_f f32:$a, f32:$b), (MIN_f32_rr $a, $b, FTZ)>;
-let Predicates = [hasPTX<70>, SM80] in {
+let Predicates = [PTX70, SM80] in {
def : Pat<(int_nvvm_fmin_nan_f f32:$a, f32:$b), (MIN_NAN_f32_rr $a, $b, NoFTZ)>;
def : Pat<(int_nvvm_fmin_ftz_nan_f f32:$a, f32:$b), (MIN_NAN_f32_rr $a, $b, FTZ)>;
}
def INT_NVVM_FMIN_XORSIGN_ABS_F :
F_MATH_2<"min.xorsign.abs.f32", B32, B32, B32, int_nvvm_fmin_xorsign_abs_f,
- [hasPTX<72>, SM86]>;
+ [PTX72, SM86]>;
def INT_NVVM_FMIN_FTZ_XORSIGN_ABS_F :
F_MATH_2<"min.ftz.xorsign.abs.f32", B32, B32, B32, int_nvvm_fmin_ftz_xorsign_abs_f,
- [hasPTX<72>, SM86]>;
+ [PTX72, SM86]>;
def INT_NVVM_FMIN_NAN_XORSIGN_ABS_F :
F_MATH_2<"min.NaN.xorsign.abs.f32", B32, B32, B32, int_nvvm_fmin_nan_xorsign_abs_f,
- [hasPTX<72>, SM86]>;
+ [PTX72, SM86]>;
def INT_NVVM_FMIN_FTZ_NAN_XORSIGN_ABS_F :
F_MATH_2<"min.ftz.NaN.xorsign.abs.f32", B32, B32, B32, int_nvvm_fmin_ftz_nan_xorsign_abs_f,
- [hasPTX<72>, SM86]>;
+ [PTX72, SM86]>;
def : Pat<(int_nvvm_fmax_f f32:$a, f32:$b), (MAX_f32_rr $a, $b, NoFTZ)>;
def : Pat<(int_nvvm_fmax_ftz_f f32:$a, f32:$b), (MAX_f32_rr $a, $b, FTZ)>;
-let Predicates = [hasPTX<70>, SM80] in {
+let Predicates = [PTX70, SM80] in {
def : Pat<(int_nvvm_fmax_nan_f f32:$a, f32:$b), (MAX_NAN_f32_rr $a, $b, NoFTZ)>;
def : Pat<(int_nvvm_fmax_ftz_nan_f f32:$a, f32:$b), (MAX_NAN_f32_rr $a, $b, FTZ)>;
}
def INT_NVVM_FMAX_XORSIGN_ABS_F :
F_MATH_2<"max.xorsign.abs.f32", B32, B32, B32, int_nvvm_fmax_xorsign_abs_f,
- [hasPTX<72>, SM86]>;
+ [PTX72, SM86]>;
def INT_NVVM_FMAX_FTZ_XORSIGN_ABS_F :
F_MATH_2<"max.ftz.xorsign.abs.f32", B32, B32, B32, int_nvvm_fmax_ftz_xorsign_abs_f,
- [hasPTX<72>, SM86]>;
+ [PTX72, SM86]>;
def INT_NVVM_FMAX_NAN_XORSIGN_ABS_F :
F_MATH_2<"max.NaN.xorsign.abs.f32", B32, B32, B32, int_nvvm_fmax_nan_xorsign_abs_f,
- [hasPTX<72>, SM86]>;
+ [PTX72, SM86]>;
def INT_NVVM_FMAX_FTZ_NAN_XORSIGN_ABS_F :
F_MATH_2<"max.ftz.NaN.xorsign.abs.f32", B32, B32, B32, int_nvvm_fmax_ftz_nan_xorsign_abs_f,
- [hasPTX<72>, SM86]>;
+ [PTX72, SM86]>;
def : Pat<(int_nvvm_fmin_d f64:$a, f64:$b), (MIN_f64_rr $a, $b)>;
def : Pat<(int_nvvm_fmax_d f64:$a, f64:$b), (MAX_f64_rr $a, $b)>;
@@ -1433,7 +1433,7 @@ def : Pat<(int_nvvm_fmax_d f64:$a, f64:$b), (MAX_f64_rr $a, $b)>;
//
class MIN_MAX_TUPLE<string V, Intrinsic I, NVPTXRegClass RC,
- list<Predicate> Preds = [hasPTX<70>, SM80]> {
+ list<Predicate> Preds = [PTX70, SM80]> {
string Variant = V;
Intrinsic Intr = I;
NVPTXRegClass RegClass = RC;
@@ -1452,16 +1452,16 @@ multiclass MIN_MAX<string IntName> {
int_nvvm_fmin_ftz_nan_f16, int_nvvm_fmax_ftz_nan_f16), B16>,
MIN_MAX_TUPLE<"_xorsign_abs_f16", !if(!eq(IntName, "min"),
int_nvvm_fmin_xorsign_abs_f16, int_nvvm_fmax_xorsign_abs_f16),
- B16, [hasPTX<72>, SM86]>,
+ B16, [PTX72, SM86]>,
MIN_MAX_TUPLE<"_ftz_xorsign_abs_f16", !if(!eq(IntName, "min"),
int_nvvm_fmin_ftz_xorsign_abs_f16, int_nvvm_fmax_ftz_xorsign_abs_f16),
- B16, [hasPTX<72>, SM86]>,
+ B16, [PTX72, SM86]>,
MIN_MAX_TUPLE<"_NaN_xorsign_abs_f16", !if(!eq(IntName, "min"),
int_nvvm_fmin_nan_xorsign_abs_f16, int_nvvm_fmax_nan_xorsign_abs_f16),
- B16, [hasPTX<72>, SM86]>,
+ B16, [PTX72, SM86]>,
MIN_MAX_TUPLE<"_ftz_NaN_xorsign_abs_f16", !if(!eq(IntName, "min"),
int_nvvm_fmin_ftz_nan_xorsign_abs_f16,
- int_nvvm_fmax_ftz_nan_xorsign_abs_f16), B16, [hasPTX<72>, SM86]>,
+ int_nvvm_fmax_ftz_nan_xorsign_abs_f16), B16, [PTX72, SM86]>,
MIN_MAX_TUPLE<"_f16x2", !if(!eq(IntName, "min"), int_nvvm_fmin_f16x2,
int_nvvm_fmax_f16x2), B32>,
MIN_MAX_TUPLE<"_ftz_f16x2", !if(!eq(IntName, "min"),
@@ -1472,38 +1472,38 @@ multiclass MIN_MAX<string IntName> {
int_nvvm_fmin_ftz_nan_f16x2, int_nvvm_fmax_ftz_nan_f16x2), B32>,
MIN_MAX_TUPLE<"_xorsign_abs_f16x2", !if(!eq(IntName, "min"),
int_nvvm_fmin_xorsign_abs_f16x2, int_nvvm_fmax_xorsign_abs_f16x2),
- B32, [hasPTX<72>, SM86]>,
+ B32, [PTX72, SM86]>,
MIN_MAX_TUPLE<"_ftz_xorsign_abs_f16x2", !if(!eq(IntName, "min"),
int_nvvm_fmin_ftz_xorsign_abs_f16x2, int_nvvm_fmax_ftz_xorsign_abs_f16x2),
- B32, [hasPTX<72>, SM86]>,
+ B32, [PTX72, SM86]>,
MIN_MAX_TUPLE<"_NaN_xorsign_abs_f16x2", !if(!eq(IntName, "min"),
int_nvvm_fmin_nan_xorsign_abs_f16x2, int_nvvm_fmax_nan_xorsign_abs_f16x2),
- B32, [hasPTX<72>, SM86]>,
+ B32, [PTX72, SM86]>,
MIN_MAX_TUPLE<"_ftz_NaN_xorsign_abs_f16x2", !if(!eq(IntName, "min"),
int_nvvm_fmin_ftz_nan_xorsign_abs_f16x2,
int_nvvm_fmax_ftz_nan_xorsign_abs_f16x2),
- B32, [hasPTX<72>, SM86]>,
+ B32, [PTX72, SM86]>,
MIN_MAX_TUPLE<"_bf16", !if(!eq(IntName, "min"),
int_nvvm_fmin_bf16, int_nvvm_fmax_bf16), B16>,
MIN_MAX_TUPLE<"_NaN_bf16", !if(!eq(IntName, "min"), int_nvvm_fmin_nan_bf16,
int_nvvm_fmax_nan_bf16), B16>,
MIN_MAX_TUPLE<"_xorsign_abs_bf16", !if(!eq(IntName, "min"),
int_nvvm_fmin_xorsign_abs_bf16, int_nvvm_fmax_xorsign_abs_bf16),
- B16, [hasPTX<72>, SM86]>,
+ B16, [PTX72, SM86]>,
MIN_MAX_TUPLE<"_NaN_xorsign_abs_bf16", !if(!eq(IntName, "min"),
int_nvvm_fmin_nan_xorsign_abs_bf16, int_nvvm_fmax_nan_xorsign_abs_bf16),
- B16, [hasPTX<72>, SM86]>,
+ B16, [PTX72, SM86]>,
MIN_MAX_TUPLE<"_bf16x2", !if(!eq(IntName, "min"), int_nvvm_fmin_bf16x2,
int_nvvm_fmax_bf16x2), B32>,
MIN_MAX_TUPLE<"_NaN_bf16x2", !if(!eq(IntName, "min"),
int_nvvm_fmin_nan_bf16x2, int_nvvm_fmax_nan_bf16x2), B32>,
MIN_MAX_TUPLE<"_xorsign_abs_bf16x2", !if(!eq(IntName, "min"),
int_nvvm_fmin_xorsign_abs_bf16x2, int_nvvm_fmax_xorsign_abs_bf16x2),
- B32, [hasPTX<72>, SM86]>,
+ B32, [PTX72, SM86]>,
MIN_MAX_TUPLE<"_NaN_xorsign_abs_bf16x2", !if(!eq(IntName, "min"),
int_nvvm_fmin_nan_xorsign_abs_bf16x2,
int_nvvm_fmax_nan_xorsign_abs_bf16x2),
- B32, [hasPTX<72>, SM86]>] in {
+ B32, [PTX72, SM86]>] in {
def P.Variant : F_MATH_2<!strconcat(
IntName, !subst("_", ".", P.Variant)),
P.RegClass, P.RegClass, P.RegClass, P.Intr, P.Predicates>;
@@ -1605,11 +1605,11 @@ multiclass F_ABS<string suffix, RegTyInfo RT, bit support_ftz, list<Predicate> p
def _FTZ : F_MATH_1<"abs.ftz." # suffix, RT, RT, int_nvvm_fabs_ftz, preds>;
}
-defm ABS_F16 : F_ABS<"f16", F16RT, support_ftz = true, preds = [hasPTX<65>, SM53]>;
-defm ABS_F16X2 : F_ABS<"f16x2", F16X2RT, support_ftz = true, preds = [hasPTX<65>, SM53]>;
+defm ABS_F16 : F_ABS<"f16", F16RT, support_ftz = true, preds = [PTX65, SM53]>;
+defm ABS_F16X2 : F_ABS<"f16x2", F16X2RT, support_ftz = true, preds = [PTX65, SM53]>;
-defm ABS_BF16 : F_ABS<"bf16", BF16RT, support_ftz = false, preds = [hasPTX<70>, SM80]>;
-defm ABS_BF16X2 : F_ABS<"bf16x2", BF16X2RT, support_ftz = false, preds = [hasPTX<70>, SM80]>;
+defm ABS_BF16 : F_ABS<"bf16", BF16RT, support_ftz = false, preds = [PTX70, SM80]>;
+defm ABS_BF16X2 : F_ABS<"bf16x2", BF16X2RT, support_ftz = false, preds = [PTX70, SM80]>;
defm ABS_F32 : F_ABS<"f32", F32RT, support_ftz = true>;
defm ABS_F64 : F_ABS<"f64", F64RT, support_ftz = false>;
@@ -1631,9 +1631,9 @@ foreach t = [F32RT, F64RT] in
//
def INT_NVVM_NEG_BF16 : F_MATH_1<"neg.bf16", BF16RT,
- BF16RT, int_nvvm_neg_bf16, [hasPTX<70>, SM80]>;
+ BF16RT, int_nvvm_neg_bf16, [PTX70, SM80]>;
def INT_NVVM_NEG_BF16X2 : F_MATH_1<"neg.bf16x2", BF16X2RT,
- BF16X2RT, int_nvvm_neg_bf16x2, [hasPTX<70>, SM80]>;
+ BF16X2RT, int_nvvm_neg_bf16x2, [PTX70, SM80]>;
//
// Round
@@ -1666,12 +1666,12 @@ def : Pat<(int_nvvm_saturate_d f64:$a), (CVT_f64_f64 $a, CvtSAT)>;
def : Pat<(f32 (int_nvvm_ex2_approx_ftz f32:$a)), (EX2_APPROX_f32 $a, FTZ)>;
def : Pat<(f32 (int_nvvm_ex2_approx f32:$a)), (EX2_APPROX_f32 $a, NoFTZ)>;
-let Predicates = [hasPTX<70>, SM75] in {
+let Predicates = [PTX70, SM75] in {
def : Pat<(f16 (int_nvvm_ex2_approx f16:$a)), (EX2_APPROX_f16 $a)>;
def : Pat<(v2f16 (int_nvvm_ex2_approx v2f16:$a)), (EX2_APPROX_f16x2 $a)>;
}
-let Predicates = [hasPTX<78>, SM90] in {
+let Predicates = [PTX78, SM90] in {
def : Pat<(bf16 (int_nvvm_ex2_approx_ftz bf16:$a)), (EX2_APPROX_bf16 $a)>;
def : Pat<(v2bf16 (int_nvvm_ex2_approx_ftz v2bf16:$a)), (EX2_APPROX_bf16x2 $a)>;
}
@@ -1735,39 +1735,39 @@ multiclass FMA_INST {
FMA_TUPLE<"_rp_ftz_f32", int_nvvm_fma_rp_ftz_f, B32>,
FMA_TUPLE<"_rp_ftz_sat_f32", int_nvvm_fma_rp_ftz_sat_f, B32>,
- FMA_TUPLE<"_rn_f16", int_nvvm_fma_rn_f16, B16, [hasPTX<42>, SM53]>,
+ FMA_TUPLE<"_rn_f16", int_nvvm_fma_rn_f16, B16, [PTX42, SM53]>,
FMA_TUPLE<"_rn_ftz_f16", int_nvvm_fma_rn_ftz_f16, B16,
- [hasPTX<42>, SM53]>,
+ [PTX42, SM53]>,
FMA_TUPLE<"_rn_sat_f16", int_nvvm_fma_rn_sat_f16, B16,
- [hasPTX<42>, SM53]>,
+ [PTX42, SM53]>,
FMA_TUPLE<"_rn_ftz_sat_f16", int_nvvm_fma_rn_ftz_sat_f16, B16,
- [hasPTX<42>, SM53]>,
+ [PTX42, SM53]>,
FMA_TUPLE<"_rn_relu_f16", int_nvvm_fma_rn_relu_f16, B16,
- [hasPTX<70>, SM80]>,
+ [PTX70, SM80]>,
FMA_TUPLE<"_rn_ftz_relu_f16", int_nvvm_fma_rn_ftz_relu_f16, B16,
- [hasPTX<70>, SM80]>,
+ [PTX70, SM80]>,
- FMA_TUPLE<"_rn_bf16", int_nvvm_fma_rn_bf16, B16, [hasPTX<70>, SM80]>,
+ FMA_TUPLE<"_rn_bf16", int_nvvm_fma_rn_bf16, B16, [PTX70, SM80]>,
FMA_TUPLE<"_rn_relu_bf16", int_nvvm_fma_rn_relu_bf16, B16,
- [hasPTX<70>, SM80]>,
+ [PTX70, SM80]>,
FMA_TUPLE<"_rn_f16x2", int_nvvm_fma_rn_f16x2, B32,
- [hasPTX<42>, SM53]>,
+ [PTX42, SM53]>,
FMA_TUPLE<"_rn_ftz_f16x2", int_nvvm_fma_rn_ftz_f16x2, B32,
- [hasPTX<42>, SM53]>,
+ [PTX42, SM53]>,
FMA_TUPLE<"_rn_sat_f16x2", int_nvvm_fma_rn_sat_f16x2, B32,
- [hasPTX<42>, SM53]>,
+ [PTX42, SM53]>,
FMA_TUPLE<"_rn_ftz_sat_f16x2", int_nvvm_fma_rn_ftz_sat_f16x2,
- B32, [hasPTX<42>, SM53]>,
+ B32, [PTX42, SM53]>,
FMA_TUPLE<"_rn_relu_f16x2", int_nvvm_fma_rn_relu_f16x2, B32,
- [hasPTX<70>, SM80]>,
+ [PTX70, SM80]>,
FMA_TUPLE<"_rn_ftz_relu_f16x2", int_nvvm_fma_rn_ftz_relu_f16x2,
- B32, [hasPTX<70>, SM80]>,
+ B32, [PTX70, SM80]>,
FMA_TUPLE<"_rn_bf16x2", int_nvvm_fma_rn_bf16x2, B32,
- [hasPTX<70>, SM80]>,
+ [PTX70, SM80]>,
FMA_TUPLE<"_rn_relu_bf16x2", int_nvvm_fma_rn_relu_bf16x2, B32,
- [hasPTX<70>, SM80]>,
+ [PTX70, SM80]>,
] in {
def P.Variant :
F_MATH_3<!strconcat("fma", !subst("_", ".", P.Variant)),
@@ -1788,13 +1788,13 @@ foreach rnd = ["_rn", "_rz", "_rm", "_rp"] in {
(f32 (fpextend type:$a)),
(f32 (fpextend type:$b)),
f32:$c))]>,
- Requires<[SM100, hasPTX<86>]>;
+ Requires<[SM100, PTX86]>;
}
}
}
// Pattern for llvm.fma.f32 intrinsic when there is no FTZ flag
-let Predicates = [SM100, hasPTX<86>, doNoF32FTZ] in {
+let Predicates = [SM100, PTX86, doNoF32FTZ] in {
def : Pat<(f32 (fma (f32 (fpextend f16:$a)),
(f32 (fpextend f16:$b)), f32:$c)),
(INT_NVVM_MIXED_FMA_rn_f32_f16 B16:$a, B16:$b, B32:$c)>;
@@ -1811,7 +1811,7 @@ foreach ty = [F16RT, F16X2RT, BF16RT, BF16X2RT] in {
BasicNVPTXInst<(outs ty.RC:$dst), (ins ty.RC:$a, ty.RC:$b, ty.RC:$c),
"fma.rn.oob" # suffix,
[(set ty.Ty:$dst, (Intr ty.Ty:$a, ty.Ty:$b, ty.Ty:$c))]>,
- Requires<[hasPTX<81>, SM90]>;
+ Requires<[PTX81, SM90]>;
}
}
@@ -1950,13 +1950,13 @@ foreach rnd = ["_rn", "_rz", "_rm", "_rp"] in {
(!cast<Intrinsic>("int_nvvm_add" # rnd # sat # "_f")
(f32 (fpextend type:$a)),
f32:$b))]>,
- Requires<[SM100, hasPTX<86>]>;
+ Requires<[SM100, PTX86]>;
}
}
}
// Pattern for fadd when there is no FTZ flag
-let Predicates = [SM100, hasPTX<86>, doNoF32FTZ] in {
+let Predicates = [SM100, PTX86, doNoF32FTZ] in {
def : Pat<(f32 (fadd (f32 (fpextend f16:$a)), f32:$b)),
(INT_NVVM_MIXED_ADD_rn_f32_f16 B16:$a, B32:$b)>;
def : Pat<(f32 (fadd (f32 (fpextend bf16:$a)), f32:$b)),
@@ -2010,13 +2010,13 @@ foreach rnd = ["_rn", "_rz", "_rm", "_rp"] in {
(!cast<Intrinsic>("int_nvvm_add" # rnd # sat # "_f")
(f32 (fpextend type:$a)),
(f32 (fneg f32:$b))))]>,
- Requires<[SM100, hasPTX<86>]>;
+ Requires<[SM100, PTX86]>;
}
}
}
// Pattern for fsub when there is no FTZ flag
-let Predicates = [SM100, hasPTX<86>, doNoF32FTZ] in {
+let Predicates = [SM100, PTX86, doNoF32FTZ] in {
def : Pat<(f32 (fsub (f32 (fpextend f16:$a)), f32:$b)),
(INT_NVVM_MIXED_SUB_rn_f32_f16 B16:$a, B32:$b)>;
def : Pat<(f32 (fsub (f32 (fpextend bf16:$a)), f32:$b)),
@@ -2053,7 +2053,7 @@ foreach sign = ["s", "u"] in {
defm SZEXT_ # sign # _ # mode
: I3Inst<"szext." # mode # "." # sign # "32",
intrin, I32RT, commutative = false,
- requires = [SM70, hasPTX<76>]>;
+ requires = [SM70, PTX76]>;
}
}
@@ -2066,7 +2066,7 @@ foreach mode = ["wrap", "clamp"] in {
defm BMSK_ # mode
: I3Inst<"bmsk." # mode # ".b32",
intrin, I32RT, commutative = false,
- requires = [SM70, hasPTX<76>]>;
+ requires = [SM70, PTX76]>;
}
//
@@ -2134,7 +2134,7 @@ def : Pat<(int_nvvm_ff2bf16x2_rn f32:$a, f32:$b), (CVT_bf16x2_f32 $a, $b, C
def : Pat<(int_nvvm_ff2bf16x2_rn_relu f32:$a, f32:$b), (CVT_bf16x2_f32 $a, $b, CvtRN_RELU)>;
def : Pat<(int_nvvm_ff2bf16x2_rz f32:$a, f32:$b), (CVT_bf16x2_f32 $a, $b, CvtRZ)>;
def : Pat<(int_nvvm_ff2bf16x2_rz_relu f32:$a, f32:$b), (CVT_bf16x2_f32 $a, $b, CvtRZ_RELU)>;
-let Predicates = [hasPTX<81>, SM80] in {
+let Predicates = [PTX81, SM80] in {
def : Pat<(int_nvvm_ff2bf16x2_rn_satfinite f32:$a, f32:$b), (CVT_bf16x2_f32_sf $a, $b, CvtRN)>;
def : Pat<(int_nvvm_ff2bf16x2_rn_relu_satfinite f32:$a, f32:$b), (CVT_bf16x2_f32_sf $a, $b, CvtRN_RELU)>;
def : Pat<(int_nvvm_ff2bf16x2_rz_satfinite f32:$a, f32:$b), (CVT_bf16x2_f32_sf $a, $b, CvtRZ)>;
@@ -2155,7 +2155,7 @@ def : Pat<(int_nvvm_ff2f16x2_rn f32:$a, f32:$b), (CVT_f16x2_f32 $a, $b, Cvt
def : Pat<(int_nvvm_ff2f16x2_rn_relu f32:$a, f32:$b), (CVT_f16x2_f32 $a, $b, CvtRN_RELU)>;
def : Pat<(int_nvvm_ff2f16x2_rz f32:$a, f32:$b), (CVT_f16x2_f32 $a, $b, CvtRZ)>;
def : Pat<(int_nvvm_ff2f16x2_rz_relu f32:$a, f32:$b), (CVT_f16x2_f32 $a, $b, CvtRZ_RELU)>;
-let Predicates = [hasPTX<81>, SM80] in {
+let Predicates = [PTX81, SM80] in {
def : Pat<(int_nvvm_ff2f16x2_rn_satfinite f32:$a, f32:$b), (CVT_f16x2_f32_sf $a, $b, CvtRN)>;
def : Pat<(int_nvvm_ff2f16x2_rn_relu_satfinite f32:$a, f32:$b), (CVT_f16x2_f32_sf $a, $b, CvtRN_RELU)>;
def : Pat<(int_nvvm_ff2f16x2_rz_satfinite f32:$a, f32:$b), (CVT_f16x2_f32_sf $a, $b, CvtRZ)>;
@@ -2176,7 +2176,7 @@ def : Pat<(int_nvvm_f2bf16_rn f32:$a), (CVT_bf16_f32 $a, CvtRN)>;
def : Pat<(int_nvvm_f2bf16_rn_relu f32:$a), (CVT_bf16_f32 $a, CvtRN_RELU)>;
def : Pat<(int_nvvm_f2bf16_rz f32:$a), (CVT_bf16_f32 $a, CvtRZ)>;
def : Pat<(int_nvvm_f2bf16_rz_relu f32:$a), (CVT_bf16_f32 $a, CvtRZ_RELU)>;
-let Predicates = [hasPTX<81>, SM80] in {
+let Predicates = [PTX81, SM80] in {
def : Pat<(int_nvvm_f2bf16_rz_satfinite f32:$a), (CVT_bf16_f32_sf $a, CvtRZ)>;
def : Pat<(int_nvvm_f2bf16_rz_relu_satfinite f32:$a), (CVT_bf16_f32_sf $a, CvtRZ_RELU)>;
def : Pat<(int_nvvm_f2bf16_rn_satfinite f32:$a), (CVT_bf16_f32_sf $a, CvtRN)>;
@@ -2187,7 +2187,7 @@ def : Pat<(int_nvvm_f2f16_rn f32:$a), (CVT_f16_f32 $a, CvtRN)>;
def : Pat<(int_nvvm_f2f16_rn_relu f32:$a), (CVT_f16_f32 $a, CvtRN_RELU)>;
def : Pat<(int_nvvm_f2f16_rz f32:$a), (CVT_f16_f32 $a, CvtRZ)>;
def : Pat<(int_nvvm_f2f16_rz_relu f32:$a), (CVT_f16_f32 $a, CvtRZ_RELU)>;
-let Predicates = [hasPTX<81>, SM80] in {
+let Predicates = [PTX81, SM80] in {
def : Pat<(int_nvvm_f2f16_rz_satfinite f32:$a), (CVT_f16_f32_sf $a, CvtRZ)>;
def : Pat<(int_nvvm_f2f16_rz_relu_satfinite f32:$a), (CVT_f16_f32_sf $a, CvtRZ_RELU)>;
def : Pat<(int_nvvm_f2f16_rn_satfinite f32:$a), (CVT_f16_f32_sf $a, CvtRN)>;
@@ -2198,8 +2198,8 @@ def : Pat<(int_nvvm_lohi_i2d i32:$a, i32:$b), (V2I32toI64 $a, $b)>;
def : Pat<(int_nvvm_d2i_lo f64:$a), (I64toI32L $a)>;
def : Pat<(int_nvvm_d2i_hi f64:$a), (I64toI32H $a)>;
-def : Pat<(int_nvvm_d2i_lo f64:$a), (I64toI32L_Sink $a)>, Requires<[hasPTX<71>]>;
-def : Pat<(int_nvvm_d2i_hi f64:$a), (I64toI32H_Sink $a)>, Requires<[hasPTX<71>]>;
+def : Pat<(int_nvvm_d2i_lo f64:$a), (I64toI32L_Sink $a)>, Requires<[PTX71]>;
+def : Pat<(int_nvvm_d2i_hi f64:$a), (I64toI32H_Sink $a)>, Requires<[PTX71]>;
def : Pat<(int_nvvm_f2ll_rn_ftz f32:$a), (CVT_s64_f32 $a, CvtRNI_FTZ)>;
def : Pat<(int_nvvm_f2ll_rn f32:$a), (CVT_s64_f32 $a, CvtRNI)>;
@@ -2508,7 +2508,7 @@ class INT_FNS_MBO<dag ins, dag Operands>
: BasicNVPTXInst<(outs B32:$dst), ins,
"fns.b32",
[(set i32:$dst, Operands)]>,
- Requires<[hasPTX<60>, SM30]>;
+ Requires<[PTX60, SM30]>;
def INT_FNS_rrr : INT_FNS_MBO<(ins B32:$mask, B32:$base, B32:$offset),
(int_nvvm_fns i32:$mask, i32:$base, i32:$offset)>;
@@ -2617,8 +2617,8 @@ defm atomic_load_fadd : binary_atomic_op_fp<atomic_load_fadd>;
defm INT_PTX_ATOM_ADD_32 : F_ATOMIC_2<I32RT, atomic_load_add_i32, "add.u32", atomic_load_add>;
defm INT_PTX_ATOM_ADD_64 : F_ATOMIC_2<I64RT, atomic_load_add_i64, "add.u64", atomic_load_add>;
-defm INT_PTX_ATOM_ADD_F16 : F_ATOMIC_2<F16RT, atomic_load_fadd, "add.noftz.f16", atomic_load_fadd, [SM70, hasPTX<63>]>;
-defm INT_PTX_ATOM_ADD_BF16 : F_ATOMIC_2<BF16RT, atomic_load_fadd, "add.noftz.bf16", atomic_load_fadd, [SM90, hasPTX<78>]>;
+defm INT_PTX_ATOM_ADD_F16 : F_ATOMIC_2<F16RT, atomic_load_fadd, "add.noftz.f16", atomic_load_fadd, [SM70, PTX63]>;
+defm INT_PTX_ATOM_ADD_BF16 : F_ATOMIC_2<BF16RT, atomic_load_fadd, "add.noftz.bf16", atomic_load_fadd, [SM90, PTX78]>;
defm INT_PTX_ATOM_ADD_F32 : F_ATOMIC_2<F32RT, atomic_load_fadd, "add.f32", atomic_load_fadd>;
defm INT_PTX_ATOM_ADD_F64 : F_ATOMIC_2<F64RT, atomic_load_fadd, "add.f64", atomic_load_fadd, [hasAtomAddF64]>;
@@ -2860,7 +2860,7 @@ multiclass CvtaInsts<NVPTXAddressSpace as, list<Predicate> preds = [],
foreach as = [AddrSpaceLocal, AddrSpaceShared, AddrSpaceGlobal, AddrSpaceConst] in
defm cvta : CvtaInsts<as>;
-defm cvta : CvtaInsts<AddrSpaceParam, [hasPTX<77>, SM70]>;
+defm cvta : CvtaInsts<AddrSpaceParam, [PTX77, SM70]>;
defm cvta : CvtaInsts<AddrSpaceSharedCluster, [hasClusters], supports_32=false>;
@@ -2942,13 +2942,13 @@ multiclass ISSPACEP<string suffix, Intrinsic Intr, list<Predicate> Preds = []> {
Requires<Preds>;
}
-defm isspace_const : ISSPACEP<"const", int_nvvm_isspacep_const, [hasPTX<31>]>;
+defm isspace_const : ISSPACEP<"const", int_nvvm_isspacep_const>;
defm isspace_global : ISSPACEP<"global", int_nvvm_isspacep_global>;
defm isspace_local : ISSPACEP<"local", int_nvvm_isspacep_local>;
defm isspace_shared : ISSPACEP<"shared", int_nvvm_isspacep_shared>;
defm isspace_shared_cluster : ISSPACEP<"shared::cluster",
int_nvvm_isspacep_shared_cluster,
- [hasPTX<78>, SM90]>;
+ [PTX78, SM90]>;
// Special register reads
def MOV_SPECIAL : BasicNVPTXInst<(outs B32:$d),
@@ -4868,22 +4868,22 @@ defm INT_PTX_SREG_CTAID : PTX_READ_SREG_R32V4<"ctaid">;
defm INT_PTX_SREG_NCTAID: PTX_READ_SREG_R32V4<"nctaid">;
defm INT_PTX_SREG_CLUSTERID :
- PTX_READ_SREG_R32V4<"clusterid", [SM90, hasPTX<78>]>;
+ PTX_READ_SREG_R32V4<"clusterid", [SM90, PTX78]>;
defm INT_PTX_SREG_NCLUSTERID :
- PTX_READ_SREG_R32V4<"nclusterid", [SM90, hasPTX<78>]>;
+ PTX_READ_SREG_R32V4<"nclusterid", [SM90, PTX78]>;
defm INT_PTX_SREG_CLUSTER_CTAID :
- PTX_READ_SREG_R32V4<"cluster_ctaid", [SM90, hasPTX<78>]>;
+ PTX_READ_SREG_R32V4<"cluster_ctaid", [SM90, PTX78]>;
defm INT_PTX_SREG_CLUSTER_NCTAID:
- PTX_READ_SREG_R32V4<"cluster_nctaid", [SM90, hasPTX<78>]>;
+ PTX_READ_SREG_R32V4<"cluster_nctaid", [SM90, PTX78]>;
def INT_PTX_SREG_CLUSTER_CTARANK :
PTX_READ_SREG_R32<"cluster_ctarank",
int_nvvm_read_ptx_sreg_cluster_ctarank,
- [SM90, hasPTX<78>]>;
+ [SM90, PTX78]>;
def INT_PTX_SREG_CLUSTER_NCTARANK:
PTX_READ_SREG_R32<"cluster_nctarank",
int_nvvm_read_ptx_sreg_cluster_nctarank,
- [SM90, hasPTX<78>]>;
+ [SM90, PTX78]>;
def INT_PTX_SREG_TOTAL_SMEM_SIZE :
PTX_READ_SREG_R32<"total_smem_size", int_nvvm_read_ptx_sreg_total_smem_size>;
@@ -4892,7 +4892,7 @@ def INT_PTX_SREG_DYNAMIC_SMEM_SIZE :
def INT_PTX_SREG_AGGR_SMEM_SIZE :
PTX_READ_SREG_R32<"aggr_smem_size",
int_nvvm_read_ptx_sreg_aggr_smem_size,
- [SM90, hasPTX<81>]>;
+ [SM90, PTX81]>;
def SREG_LANEID : PTX_READ_SREG_R32<"laneid", int_nvvm_read_ptx_sreg_laneid>;
def SREG_WARPID : PTX_READ_SREG_R32<"warpid", int_nvvm_read_ptx_sreg_warpid>;
@@ -4933,7 +4933,7 @@ foreach suffix = ["begin", "end", "cap", "0", "1"] in {
defvar regname = "reserved_smem_offset_" # suffix;
defvar intr = !cast<Intrinsic>("int_nvvm_read_ptx_sreg_" # regname);
def "INT_PTX_SREG_RESERVED_SMEM_OFFSET_" # !toupper(suffix) :
- PTX_READ_SREG_R32<regname, intr, [hasPTX<76>, SM80]>;
+ PTX_READ_SREG_R32<regname, intr, [PTX76, SM80]>;
}
// TODO: It would be nice to use PTX_READ_SREG here, but it doesn't
@@ -5015,33 +5015,33 @@ class WMMA_REGINFO<WMMA_REGS r, string op, string metadata = "",
!and(!or(!eq(ptx_elt_type,"e4m3"),
!eq(ptx_elt_type,"e5m2")),
- !eq(geom, "m16n8k16")) : [SM89, hasPTX<87>],
+ !eq(geom, "m16n8k16")) : [SM89, PTX87],
!or(!eq(ptx_elt_type, "e4m3"),
- !eq(ptx_elt_type, "e5m2")) : [SM89, hasPTX<84>],
+ !eq(ptx_elt_type, "e5m2")) : [SM89, PTX84],
!and(isSparse,
- !ne(metadata, "sp")) : [SM80, hasPTX<85>],
- isSparse : [SM80, hasPTX<71>],
+ !ne(metadata, "sp")) : [SM80, PTX85],
+ isSparse : [SM80, PTX71],
// fp16 -> fp16/fp32 @ m16n16k16
!and(!eq(geom, "m16n16k16"),
!or(!eq(ptx_elt_type, "f16"),
- !eq(ptx_elt_type, "f32"))) : [SM70, hasPTX<60>],
+ !eq(ptx_elt_type, "f32"))) : [SM70, PTX60],
!and(!eq(geom, "m8n8k4"),
- !eq(ptx_elt_type, "f64")) : [SM80, hasPTX<70>],
+ !eq(ptx_elt_type, "f64")) : [SM80, PTX70],
!and(!or(!eq(geom, "m16n8k4"),
!eq(geom, "m16n8k8"),
!eq(geom, "m16n8k16")),
- !eq(ptx_elt_type, "f64")) : [SM90, hasPTX<78>],
+ !eq(ptx_elt_type, "f64")) : [SM90, PTX78],
// fp16 -> fp16/fp32 @ m8n32k16/m32n8k16
!and(!or(!eq(geom, "m8n32k16"),
!eq(geom, "m32n8k16")),
!or(!eq(ptx_elt_type, "f16"),
- !eq(ptx_elt_type, "f32"))) : [SM70, hasPTX<61>],
+ !eq(ptx_elt_type, "f32"))) : [SM70, PTX61],
// u8/s8 -> s32 @ m16n16k16/m8n32k16/m32n8k16
!and(!or(!eq(geom, "m16n16k16"),
@@ -5049,39 +5049,39 @@ class WMMA_REGINFO<WMMA_REGS r, string op, string metadata = "",
!eq(geom, "m32n8k16")),
!or(!eq(ptx_elt_type, "u8"),
!eq(ptx_elt_type, "s8"),
- !eq(ptx_elt_type, "s32"))) : [SM72, hasPTX<63>],
+ !eq(ptx_elt_type, "s32"))) : [SM72, PTX63],
!and(!or(!eq(geom, "m16n16k16"),
!eq(geom, "m8n32k16"),
!eq(geom, "m32n8k16")),
- !eq(ptx_elt_type, "bf16")) : [SM80, hasPTX<70>],
+ !eq(ptx_elt_type, "bf16")) : [SM80, PTX70],
!and(!eq(geom, "m16n16k8"),
- !eq(ptx_elt_type, "tf32")) : [SM80, hasPTX<70>],
+ !eq(ptx_elt_type, "tf32")) : [SM80, PTX70],
!and(!eq(geom, "m16n16k8"),
- !eq(ptx_elt_type, "f32")) : [SM80, hasPTX<70>],
+ !eq(ptx_elt_type, "f32")) : [SM80, PTX70],
// b1 -> s32 @ m8n8k128(b1)
!and(!ne(op, "mma"),
- !eq(geom, "m8n8k128")) : [SM75, hasPTX<63>],
+ !eq(geom, "m8n8k128")) : [SM75, PTX63],
// u4/s4 -> s32 @ m8n8k32 (u4/s4)
!and(!ne(op, "mma"),
- !eq(geom, "m8n8k32")) : [SM75, hasPTX<63>],
+ !eq(geom, "m8n8k32")) : [SM75, PTX63],
!or(!eq(geom, "m16n8k8"),
- !eq(geom, "m8n8k16")) : [SM75, hasPTX<65>],
+ !eq(geom, "m8n8k16")) : [SM75, PTX65],
!and(!ne(ptx_elt_type, "f64"),
- !eq(geom, "m8n8k4")) : [SM70, hasPTX<64>],
+ !eq(geom, "m8n8k4")) : [SM70, PTX64],
// mma m8n8k32 requires higher PTX version
!and(!eq(op, "mma"),
- !eq(geom, "m8n8k32")) : [SM75, hasPTX<65>],
+ !eq(geom, "m8n8k32")) : [SM75, PTX65],
!and(!eq(ptx_elt_type, "f64"),
- !eq(geom, "m8n8k4")) : [SM80, hasPTX<70>],
+ !eq(geom, "m8n8k4")) : [SM80, PTX70],
!and(!eq(op, "mma"),
!or(!eq(geom, "m16n8k16"),
@@ -5090,11 +5090,11 @@ class WMMA_REGINFO<WMMA_REGS r, string op, string metadata = "",
!eq(geom, "m16n8k64"),
!eq(geom, "m8n8k128"),
!eq(geom, "m16n8k128"),
- !eq(geom, "m16n8k256"))) : [SM80, hasPTX<70>],
+ !eq(geom, "m16n8k256"))) : [SM80, PTX70],
!and(!eq(op, "ldmatrix"),
!eq(ptx_elt_type, "b16"),
- !eq(geom, "m8n8")) : [SM75, hasPTX<65>],
+ !eq(geom, "m8n8")) : [SM75, PTX65],
!and(!eq(op, "ldmatrix"),
!eq(ptx_elt_type, "b8"),
@@ -5117,7 +5117,7 @@ class WMMA_REGINFO<WMMA_REGS r, string op, string metadata = "",
!eq(geom, "m8n16")) : [callSubtarget<"hasLdStmatrixBlackwellSupport">],
!and(!eq(op, "stmatrix"),!eq(ptx_elt_type, "b16"),
- !eq(geom, "m8n8")) : [SM90, hasPTX<78>],
+ !eq(geom, "m8n8")) : [SM90, PTX78],
!and(!eq(op, "stmatrix"),
!eq(ptx_elt_type, "b8"),
@@ -5256,7 +5256,7 @@ class MMA_OP_PREDICATES<WMMA_REGINFO FragA, string b1op> {
WMMA_REGINFO Frag = FragA;
list<Predicate> ret = !listconcat(
FragA.Predicates,
- !if(!eq(b1op, ".and.popc"), [SM80, hasPTX<71>], [])
+ !if(!eq(b1op, ".and.popc"), [SM80, PTX71], [])
);
}
// WMMA.MMA
@@ -5641,7 +5641,7 @@ def MOVMATRIX_SYNC_ALIGNED_M8N8_TRANS_B16
"movmatrix.sync.aligned.m8n8.trans.b16",
[(set B32:$dst,
(int_nvvm_movmatrix_sync_aligned_m8n8_trans_b16 B32:$src))]>,
- Requires<[SM75, hasPTX<78>]>;
+ Requires<[SM75, PTX78]>;
} // isConvergent = true
// Constructing non-flat DAGs is still a pain. I can't !subst a dag node with a
@@ -5659,7 +5659,7 @@ foreach mma = !listconcat(MMAs, MMA_BLOCK_SCALEs, WMMAs, MMA_LDSTs, LDMATRIXs,
def : MMA_PAT<mma>;
multiclass MAPA<string suffix, Intrinsic Intr> {
- let Predicates = [SM90, hasPTX<78>] in {
+ let Predicates = [SM90, PTX78] in {
def _32: BasicNVPTXInst<(outs B32:$d), (ins B32:$a, B32:$b),
"mapa" # suffix # ".u32",
[(set i32:$d, (Intr i32:$a, i32:$b))]>;
@@ -5681,7 +5681,7 @@ defm mapa_shared_cluster : MAPA<".shared::cluster", int_nvvm_mapa_shared_cluste
multiclass GETCTARANK<string suffix, Intrinsic Intr> {
- let Predicates = [SM90, hasPTX<78>] in {
+ let Predicates = [SM90, PTX78] in {
def _32: BasicNVPTXInst<(outs B32:$d), (ins B32:$a),
"getctarank" # suffix # ".u32",
[(set i32:$d, (Intr i32:$a))]>;
@@ -5697,7 +5697,7 @@ defm getctarank_shared_cluster : GETCTARANK<".shared::cluster", int_nvvm_getcta
def is_explicit_cluster: NVPTXInst<(outs B1:$d), (ins),
"mov.pred\t$d, %is_explicit_cluster;",
[(set i1:$d, (int_nvvm_is_explicit_cluster))]>,
- Requires<[SM90, hasPTX<78>]>;
+ Requires<[SM90, PTX78]>;
// setmaxnreg inc/dec intrinsics
let isConvergent = true in {
@@ -5716,7 +5716,7 @@ defm INT_SET_MAXNREG_DEC : SET_MAXNREG<"dec", int_nvvm_setmaxnreg_dec_sync_align
//
// WGMMA fence instructions
//
-let isConvergent = true, Predicates = [SM90a, hasPTX<80>] in {
+let isConvergent = true, Predicates = [SM90a, PTX80] in {
def WGMMA_FENCE_SYNC_ALIGNED : NullaryInst<"wgmma.fence.sync.aligned", int_nvvm_wgmma_fence_sync_aligned>;
def WGMMA_COMMIT_GROUP_SYNC_ALIGNED : NullaryInst<"wgmma.commit_group.sync.aligned", int_nvvm_wgmma_commit_group_sync_aligned>;
@@ -5725,7 +5725,7 @@ let isConvergent = true, Predicates = [SM90a, hasPTX<80>] in {
[(int_nvvm_wgmma_wait_group_sync_aligned timm:$n)]>;
}
-let Predicates = [SM90, hasPTX<78>] in {
+let Predicates = [SM90, PTX78] in {
def GRIDDEPCONTROL_LAUNCH_DEPENDENTS :
NullaryInst<"griddepcontrol.launch_dependents", int_nvvm_griddepcontrol_launch_dependents>;
def GRIDDEPCONTROL_WAIT :
@@ -6056,7 +6056,7 @@ let isConvergent = true in {
// Bulk store instructions
def st_bulk_imm : TImmLeaf<i64, [{ return Imm == 0; }]>;
-let Predicates = [SM100, hasPTX<86>] in {
+let Predicates = [SM100, PTX86] in {
def INT_NVVM_ST_BULK_GENERIC :
BasicNVPTXInst<(outs), (ins ADDR:$dest_addr, B64:$size, i64imm:$value),
"st.bulk",
@@ -6092,7 +6092,7 @@ def ST_ASYNC_MBARRIER_B128 :
"st.async.shared::cluster.mbarrier::complete_tx::bytes.b128 \t[$dest_addr], %in_128, [$mbar];\n\t"
"}}">;
-let Predicates = [SM90, hasPTX<81>] in {
+let Predicates = [SM90, PTX81] in {
foreach size = ["32", "64"] in {
defvar valueType = !cast<ValueType>("i" # size);
defvar reg = !cast<NVPTXRegClass>("B" # size);
@@ -6104,7 +6104,7 @@ let Predicates = [SM90, hasPTX<81>] in {
}
}
-let Predicates = [SM90, hasPTX<92>] in {
+let Predicates = [SM90, PTX92] in {
def : Pat<(st_async_mbarrier_b128
addr:$dest_addr, i64:$value0, i64:$value1, addr:$mbar),
(ST_ASYNC_MBARRIER_B128
@@ -6161,7 +6161,7 @@ def ST_ASYNC_MMIO_SYS_B8 :
ST_ASYNC_RELEASE_B8_BODY<"st.async.mmio.release.sys.global", "">.body>;
-let Predicates = [SM100, hasPTX<87>] in {
+let Predicates = [SM100, PTX87] in {
foreach rti = [I16RT, I32RT, I64RT] in {
def : Pat<(int_nvvm_st_async_sys
addr:$dest_addr, rti.Ty:$value, timm:$is_multimem),
@@ -6196,7 +6196,7 @@ def CLUSTERLAUNCHCONTRL_TRY_CANCEL:
BasicNVPTXInst<(outs), (ins ADDR:$addr, ADDR:$mbar),
"clusterlaunchcontrol.try_cancel.async.shared::cta.mbarrier::complete_tx::bytes.b128",
[(int_nvvm_clusterlaunchcontrol_try_cancel_async_shared addr:$addr, addr:$mbar)]>,
- Requires<[SM100, hasPTX<86>]>;
+ Requires<[SM100, PTX86]>;
def CLUSTERLAUNCHCONTRL_TRY_CANCEL_MULTICAST:
BasicNVPTXInst<(outs), (ins ADDR:$addr, ADDR:$mbar),
@@ -6218,7 +6218,7 @@ def CLUSTERLAUNCHCONTROL_QUERY_CANCEL_IS_CANCELED:
"clusterlaunchcontrol.query_cancel.is_canceled.pred.b128 $pred, %clc_handle;\n\t" #
"}}", [(set i1:$pred,
(clusterlaunchcontrol_query_cancel_is_canceled i64:$try_cancel_response0, i64:$try_cancel_response1))]>,
- Requires<[SM100, hasPTX<86>]>;
+ Requires<[SM100, PTX86]>;
class CLUSTERLAUNCHCONTROL_QUERY_CANCEL_GET_FIRST_CTAID<string Dim>:
NVPTXInst<(outs B32:$reg), (ins B64:$try_cancel_response0, B64:$try_cancel_response1),
@@ -6229,7 +6229,7 @@ class CLUSTERLAUNCHCONTROL_QUERY_CANCEL_GET_FIRST_CTAID<string Dim>:
"}}", [(set i32:$reg,
(!cast<SDNode>("clusterlaunchcontrol_query_cancel_first_cta_id_" # Dim)
i64:$try_cancel_response0, i64:$try_cancel_response1))]>,
- Requires<[SM100, hasPTX<86>]>;
+ Requires<[SM100, PTX86]>;
foreach dim = ["x", "y", "z"] in {
def SDTClusterLaunchControlQueryCancelGetFirstCtaId # dim: SDTypeProfile<1, 2, []>;
@@ -6522,7 +6522,7 @@ class Tcgen05MMABlockScaleInst<bit IsSparse, string ASpace, string Kind,
!eq(Kind, "mxf4")) : [callSubtarget<"hasTcgen05MMASparseMxf4">],
!and(IsSparse,
!eq(Kind, "mxf4nvf4")) : [callSubtarget<"hasTcgen05MMASparseMxf4nvf4">],
- !ne(ScaleVecSize, "") : [callSubtarget<"hasTcgen05InstSupport">, hasPTX<88>],
+ !ne(ScaleVecSize, "") : [callSubtarget<"hasTcgen05InstSupport">, PTX88],
true : [callSubtarget<"hasTcgen05InstSupport">]
)
);
diff --git a/llvm/lib/Target/NVPTX/NVPTXSubtarget.cpp b/llvm/lib/Target/NVPTX/NVPTXSubtarget.cpp
index d3989455cdd43..52970aac22504 100644
--- a/llvm/lib/Target/NVPTX/NVPTXSubtarget.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXSubtarget.cpp
@@ -131,6 +131,7 @@ NVPTXSubtarget &NVPTXSubtarget::initializeSubtargetDependencies(StringRef CPU,
if (PTXVersion == 0) {
// User didn't request a specific PTX version; use the minimum for this SM.
+ ApplyFeatureFlag(("+ptx" + Twine(MinPTX)).str());
PTXVersion = MinPTX;
} else if (PTXVersion < MinPTX) {
// User explicitly requested an insufficient PTX version.
@@ -159,7 +160,7 @@ bool NVPTXSubtarget::allowFP16Math() const {
}
bool NVPTXSubtarget::hasF32x2Instructions() const {
- return hasFeature(NVPTX::SM100) && PTXVersion >= 86 && !NoF32x2;
+ return hasFeature(NVPTX::SM100) && hasFeature(NVPTX::PTX86) && !NoF32x2;
}
bool NVPTXSubtarget::hasNativeBF16Support(unsigned Opcode) const {
@@ -182,7 +183,7 @@ bool NVPTXSubtarget::hasNativeBF16Support(unsigned Opcode) const {
case ISD::FRINT:
case ISD::FROUNDEVEN:
case ISD::FTRUNC:
- return hasFeature(NVPTX::SM90) && getPTXVersion() >= 78;
+ return hasFeature(NVPTX::SM90) && hasFeature(NVPTX::PTX78);
// Several BF16 instructions are available on sm_80 only.
case ISD::FMINNUM:
case ISD::FMAXNUM:
@@ -190,7 +191,7 @@ bool NVPTXSubtarget::hasNativeBF16Support(unsigned Opcode) const {
case ISD::FMINNUM_IEEE:
case ISD::FMAXIMUM:
case ISD::FMINIMUM:
- return hasFeature(NVPTX::SM80) && getPTXVersion() >= 70;
+ return hasFeature(NVPTX::SM80) && hasFeature(NVPTX::PTX70);
}
return true;
}
diff --git a/llvm/lib/Target/NVPTX/NVPTXSubtarget.h b/llvm/lib/Target/NVPTX/NVPTXSubtarget.h
index 65107d57dae2b..a7c18c57f7a40 100644
--- a/llvm/lib/Target/NVPTX/NVPTXSubtarget.h
+++ b/llvm/lib/Target/NVPTX/NVPTXSubtarget.h
@@ -79,69 +79,71 @@ class NVPTXSubtarget : public NVPTXGenSubtargetInfo {
}
bool has256BitVectorLoadStore(unsigned AS) const {
- return hasFeature(NVPTX::SM100) && PTXVersion >= 88 &&
+ return hasFeature(NVPTX::SM100) && hasFeature(NVPTX::PTX88) &&
AS == NVPTXAS::ADDRESS_SPACE_GLOBAL;
}
bool hasUsedBytesMaskPragma() const {
- return hasFeature(NVPTX::SM50) && PTXVersion >= 83;
+ return hasFeature(NVPTX::SM50) && hasFeature(NVPTX::PTX83);
}
bool hasAtomAddF64() const { return hasFeature(NVPTX::SM60); }
bool hasAtomScope() const { return hasFeature(NVPTX::SM60); }
bool hasAtomBitwise64() const { return hasFeature(NVPTX::SM32); }
bool hasAtomMinMax64() const { return hasFeature(NVPTX::SM32); }
bool hasAtomCas16() const {
- return hasFeature(NVPTX::SM70) && PTXVersion >= 63;
+ return hasFeature(NVPTX::SM70) && hasFeature(NVPTX::PTX63);
}
bool hasAtomSwap128() const {
- return hasFeature(NVPTX::SM90) && PTXVersion >= 83;
+ return hasFeature(NVPTX::SM90) && hasFeature(NVPTX::PTX83);
}
bool hasClusters() const {
- return hasFeature(NVPTX::SM90) && PTXVersion >= 78;
+ return hasFeature(NVPTX::SM90) && hasFeature(NVPTX::PTX78);
}
bool hasLDG() const { return hasFeature(NVPTX::SM32); }
bool hasHWROT32() const { return hasFeature(NVPTX::SM32); }
- bool hasBrx() const { return hasFeature(NVPTX::SM30) && PTXVersion >= 60; }
+ bool hasBrx() const {
+ return hasFeature(NVPTX::SM30) && hasFeature(NVPTX::PTX60);
+ }
bool hasFP16Math() const { return hasFeature(NVPTX::SM53); }
bool hasBF16Math() const { return hasFeature(NVPTX::SM80); }
bool allowFP16Math() const;
- bool hasMaskOperator() const { return PTXVersion >= 71; }
+ bool hasMaskOperator() const { return hasFeature(NVPTX::PTX71); }
bool hasNoReturn() const {
- return hasFeature(NVPTX::SM30) && PTXVersion >= 64;
+ return hasFeature(NVPTX::SM30) && hasFeature(NVPTX::PTX64);
}
// Does SM & PTX support memory orderings (weak and atomic: relaxed, acquire,
// release, acq_rel, sc) ?
bool hasMemoryOrdering() const {
- return hasFeature(NVPTX::SM70) && PTXVersion >= 60;
+ return hasFeature(NVPTX::SM70) && hasFeature(NVPTX::PTX60);
}
// Does SM & PTX support .acquire and .release qualifiers for fence?
bool hasSplitAcquireAndReleaseFences() const {
- return hasFeature(NVPTX::SM90) && PTXVersion >= 86;
+ return hasFeature(NVPTX::SM90) && hasFeature(NVPTX::PTX86);
}
// Does SM & PTX support atomic relaxed MMIO operations ?
bool hasRelaxedMMIO() const {
- return hasFeature(NVPTX::SM70) && PTXVersion >= 82;
+ return hasFeature(NVPTX::SM70) && hasFeature(NVPTX::PTX82);
}
bool hasDotInstructions() const {
- return hasFeature(NVPTX::SM61) && PTXVersion >= 50;
+ return hasFeature(NVPTX::SM61) && hasFeature(NVPTX::PTX50);
}
// Cache hint SM/PTX version requirements
bool hasL1EvictionHint() const {
- return getSmVersion() >= 70 && PTXVersion >= 74;
+ return hasFeature(NVPTX::SM70) && hasFeature(NVPTX::PTX74);
}
bool hasL2EvictionHint() const {
- return getSmVersion() >= 100 && PTXVersion >= 88;
+ return hasFeature(NVPTX::SM100) && hasFeature(NVPTX::PTX88);
}
bool hasL2Prefetch64B() const {
- return getSmVersion() >= 75 && PTXVersion >= 74;
+ return hasFeature(NVPTX::SM75) && hasFeature(NVPTX::PTX74);
}
bool hasL2Prefetch128B() const {
- return getSmVersion() >= 75 && PTXVersion >= 74;
+ return hasFeature(NVPTX::SM75) && hasFeature(NVPTX::PTX74);
}
bool hasL2Prefetch256B() const {
- return getSmVersion() >= 80 && PTXVersion >= 74;
+ return hasFeature(NVPTX::SM80) && hasFeature(NVPTX::PTX74);
}
bool hasL2CacheHint() const {
- return getSmVersion() >= 80 && PTXVersion >= 74;
+ return hasFeature(NVPTX::SM80) && hasFeature(NVPTX::PTX74);
}
// Checks following instructions support:
@@ -174,7 +176,7 @@ class NVPTXSubtarget : public NVPTXGenSubtargetInfo {
}
bool hasTcgen05MMASparseMxf4nvf4() const {
- return PTXVersion >= 87 &&
+ return hasFeature(NVPTX::PTX87) &&
hasAnyFeature({NVPTX::SM100a, NVPTX::SM103a, NVPTX::SM110a});
}
@@ -183,7 +185,8 @@ class NVPTXSubtarget : public NVPTXGenSubtargetInfo {
}
bool hasTcgen05LdRedSupport() const {
- return PTXVersion >= 88 && hasAnyFeature({NVPTX::SM103f, NVPTX::SM110f});
+ return hasFeature(NVPTX::PTX88) &&
+ hasAnyFeature({NVPTX::SM103f, NVPTX::SM110f});
}
bool hasReduxSyncF32() const { return hasAnyFeature({NVPTX::SM100f}); }
@@ -195,11 +198,12 @@ class NVPTXSubtarget : public NVPTXGenSubtargetInfo {
}
bool hasMMAWithMXF4NVF4Scale4xE8M0() const {
- return PTXVersion >= 91 && hasAnyFeature({NVPTX::SM120f});
+ return hasFeature(NVPTX::PTX91) && hasAnyFeature({NVPTX::SM120f});
}
bool hasMMASparseWithMXF4NVF4Scale4xE8M0() const {
- return PTXVersion >= 91 && hasAnyFeature({NVPTX::SM120a, NVPTX::SM121a});
+ return hasFeature(NVPTX::PTX91) &&
+ hasAnyFeature({NVPTX::SM120a, NVPTX::SM121a});
}
// f32x2 instructions in Blackwell family
@@ -216,10 +220,10 @@ class NVPTXSubtarget : public NVPTXGenSubtargetInfo {
// Checks support for conversions involving e4m3x2 and e5m2x2.
bool hasFP8ConversionSupport() const {
- if (PTXVersion >= 81)
+ if (hasFeature(NVPTX::PTX81))
return hasFeature(NVPTX::SM89);
- if (PTXVersion >= 78)
+ if (hasFeature(NVPTX::PTX78))
return hasFeature(NVPTX::SM90);
return false;
@@ -240,46 +244,46 @@ class NVPTXSubtarget : public NVPTXGenSubtargetInfo {
// - f16x2 -> f4x2
// - bf16x2 -> f4x2
bool hasFP16X2ToNarrowFPConversionSupport() const {
- return PTXVersion >= 91 &&
+ return hasFeature(NVPTX::PTX91) &&
hasAnyFeature({NVPTX::SM100f, NVPTX::SM110f, NVPTX::SM120f});
}
bool hasS2F6X2ConversionSupport() const {
- return PTXVersion >= 91 &&
+ return hasFeature(NVPTX::PTX91) &&
hasAnyFeature({NVPTX::SM100a, NVPTX::SM103a, NVPTX::SM110a,
NVPTX::SM120a, NVPTX::SM121a});
}
// Checks support for conversions from narrow FP types to bf16x2.
bool hasNarrowFPToBF16x2ConversionSupport() const {
- return PTXVersion >= 92 &&
+ return hasFeature(NVPTX::PTX92) &&
hasAnyFeature({NVPTX::SM100f, NVPTX::SM110f, NVPTX::SM120f});
}
// Checks support for conversions involving ue5m3x2.
bool hasUE5M3TypeSupport() const {
- return PTXVersion >= 94 && hasAnyFeature({NVPTX::SM107f});
+ return hasFeature(NVPTX::PTX94) && hasAnyFeature({NVPTX::SM107f});
}
bool hasTensormapReplaceSupport() const {
return hasAnyFeature({NVPTX::SM100f, NVPTX::SM110f, NVPTX::SM120f}) ||
- (PTXVersion >= 83 && hasAnyFeature({NVPTX::SM90a}));
+ (hasFeature(NVPTX::PTX83) && hasAnyFeature({NVPTX::SM90a}));
}
bool hasTensormapReplaceElemtypeSupport(unsigned ElemType) const {
if (ElemType >= static_cast<unsigned>(nvvm::TensormapElemType::B4x16))
- return (PTXVersion >= 88 &&
+ return (hasFeature(NVPTX::PTX88) &&
hasAnyFeature({NVPTX::SM100f, NVPTX::SM110f, NVPTX::SM120f})) ||
- (PTXVersion >= 87 &&
+ (hasFeature(NVPTX::PTX87) &&
hasAnyFeature({NVPTX::SM100a, NVPTX::SM110a, NVPTX::SM120a}));
return hasTensormapReplaceSupport();
}
bool hasTensormapReplaceSwizzleAtomicitySupport() const {
- return (PTXVersion >= 88 &&
+ return (hasFeature(NVPTX::PTX88) &&
hasAnyFeature({NVPTX::SM100f, NVPTX::SM110f, NVPTX::SM120f})) ||
- (PTXVersion >= 87 &&
+ (hasFeature(NVPTX::PTX87) &&
hasAnyFeature({NVPTX::SM100a, NVPTX::SM110a, NVPTX::SM120a}));
}
@@ -311,12 +315,13 @@ class NVPTXSubtarget : public NVPTXGenSubtargetInfo {
// being created within ptxas. This issue was fixed in CUDA 12.3. Thus, when
// PTX ISA versions 8.3+ we can confidently say that the bug will not be
// present.
- bool hasPTXASUnreachableBug() const { return PTXVersion < 83; }
+ bool hasPTXASUnreachableBug() const { return !hasFeature(NVPTX::PTX83); }
bool hasCvtaParam() const {
- return hasFeature(NVPTX::SM70) && PTXVersion >= 77;
+ return hasFeature(NVPTX::SM70) && hasFeature(NVPTX::PTX77);
}
bool hasConvertWithStochasticRounding() const {
- return PTXVersion >= 87 && hasAnyFeature({NVPTX::SM100a, NVPTX::SM103a});
+ return hasFeature(NVPTX::PTX87) &&
+ hasAnyFeature({NVPTX::SM100a, NVPTX::SM103a});
}
// The compute capability as a number, for __CUDA_ARCH__. This is the one
// place an architecture needs to be a number, and it is not an identity:
diff --git a/llvm/test/CodeGen/NVPTX/atomicrmw-allow-ftz-atomics.ll b/llvm/test/CodeGen/NVPTX/atomicrmw-allow-ftz-atomics.ll
index c1d223082eb30..78c86bfb08e2f 100644
--- a/llvm/test/CodeGen/NVPTX/atomicrmw-allow-ftz-atomics.ll
+++ b/llvm/test/CodeGen/NVPTX/atomicrmw-allow-ftz-atomics.ll
@@ -21,8 +21,8 @@ define float @fadd_f32_global(ptr addrspace(1) %addr, float %val) {
; DISALLOW-NEXT: .reg .b64 %rd<2>;
; DISALLOW-EMPTY:
; DISALLOW-NEXT: // %bb.0:
-; DISALLOW-NEXT: ld.param.b32 %r2, [fadd_f32_global_param_1];
-; DISALLOW-NEXT: ld.param.b64 %rd1, [fadd_f32_global_param_0];
+; DISALLOW-NEXT: ld.param::func.b32 %r2, [fadd_f32_global_param_1];
+; DISALLOW-NEXT: ld.param::func.b64 %rd1, [fadd_f32_global_param_0];
; DISALLOW-NEXT: ld.relaxed.sys.global.b32 %r4, [%rd1];
; DISALLOW-NEXT: $L__BB0_1: // %atomicrmw.start
; DISALLOW-NEXT: // =>This Inner Loop Header: Depth=1
@@ -32,7 +32,7 @@ define float @fadd_f32_global(ptr addrspace(1) %addr, float %val) {
; DISALLOW-NEXT: mov.b32 %r4, %r1;
; DISALLOW-NEXT: @%p1 bra $L__BB0_1;
; DISALLOW-NEXT: // %bb.2: // %atomicrmw.end
-; DISALLOW-NEXT: st.param.b32 [func_retval0], %r1;
+; DISALLOW-NEXT: st.param::func.b32 [func_retval0], %r1;
; DISALLOW-NEXT: ret;
;
; ALLOW-LABEL: fadd_f32_global(
@@ -41,10 +41,10 @@ define float @fadd_f32_global(ptr addrspace(1) %addr, float %val) {
; ALLOW-NEXT: .reg .b64 %rd<2>;
; ALLOW-EMPTY:
; ALLOW-NEXT: // %bb.0:
-; ALLOW-NEXT: ld.param.b64 %rd1, [fadd_f32_global_param_0];
-; ALLOW-NEXT: ld.param.b32 %r1, [fadd_f32_global_param_1];
+; ALLOW-NEXT: ld.param::func.b64 %rd1, [fadd_f32_global_param_0];
+; ALLOW-NEXT: ld.param::func.b32 %r1, [fadd_f32_global_param_1];
; ALLOW-NEXT: atom.relaxed.sys.global.add.f32 %r2, [%rd1], %r1;
-; ALLOW-NEXT: st.param.b32 [func_retval0], %r2;
+; ALLOW-NEXT: st.param::func.b32 [func_retval0], %r2;
; ALLOW-NEXT: ret;
%r = atomicrmw fadd ptr addrspace(1) %addr, float %val monotonic
ret float %r
@@ -61,8 +61,8 @@ define float @fadd_f32_generic(ptr %addr, float %val) {
; DISALLOW-NEXT: .reg .b64 %rd<2>;
; DISALLOW-EMPTY:
; DISALLOW-NEXT: // %bb.0:
-; DISALLOW-NEXT: ld.param.b32 %r2, [fadd_f32_generic_param_1];
-; DISALLOW-NEXT: ld.param.b64 %rd1, [fadd_f32_generic_param_0];
+; DISALLOW-NEXT: ld.param::func.b32 %r2, [fadd_f32_generic_param_1];
+; DISALLOW-NEXT: ld.param::func.b64 %rd1, [fadd_f32_generic_param_0];
; DISALLOW-NEXT: ld.relaxed.sys.b32 %r4, [%rd1];
; DISALLOW-NEXT: $L__BB1_1: // %atomicrmw.start
; DISALLOW-NEXT: // =>This Inner Loop Header: Depth=1
@@ -72,7 +72,7 @@ define float @fadd_f32_generic(ptr %addr, float %val) {
; DISALLOW-NEXT: mov.b32 %r4, %r1;
; DISALLOW-NEXT: @%p1 bra $L__BB1_1;
; DISALLOW-NEXT: // %bb.2: // %atomicrmw.end
-; DISALLOW-NEXT: st.param.b32 [func_retval0], %r1;
+; DISALLOW-NEXT: st.param::func.b32 [func_retval0], %r1;
; DISALLOW-NEXT: ret;
;
; ALLOW-LABEL: fadd_f32_generic(
@@ -81,10 +81,10 @@ define float @fadd_f32_generic(ptr %addr, float %val) {
; ALLOW-NEXT: .reg .b64 %rd<2>;
; ALLOW-EMPTY:
; ALLOW-NEXT: // %bb.0:
-; ALLOW-NEXT: ld.param.b64 %rd1, [fadd_f32_generic_param_0];
-; ALLOW-NEXT: ld.param.b32 %r1, [fadd_f32_generic_param_1];
+; ALLOW-NEXT: ld.param::func.b64 %rd1, [fadd_f32_generic_param_0];
+; ALLOW-NEXT: ld.param::func.b32 %r1, [fadd_f32_generic_param_1];
; ALLOW-NEXT: atom.relaxed.sys.add.f32 %r2, [%rd1], %r1;
-; ALLOW-NEXT: st.param.b32 [func_retval0], %r2;
+; ALLOW-NEXT: st.param::func.b32 [func_retval0], %r2;
; ALLOW-NEXT: ret;
%r = atomicrmw fadd ptr %addr, float %val monotonic
ret float %r
@@ -99,10 +99,10 @@ define float @fadd_f32_shared(ptr addrspace(3) %addr, float %val) {
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [fadd_f32_shared_param_0];
-; CHECK-NEXT: ld.param.b32 %r1, [fadd_f32_shared_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [fadd_f32_shared_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r1, [fadd_f32_shared_param_1];
; CHECK-NEXT: atom.relaxed.sys.shared.add.f32 %r2, [%rd1], %r1;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r2;
; CHECK-NEXT: ret;
%r = atomicrmw fadd ptr addrspace(3) %addr, float %val monotonic
ret float %r
diff --git a/llvm/test/CodeGen/NVPTX/atomicrmw-sm90.ll b/llvm/test/CodeGen/NVPTX/atomicrmw-sm90.ll
index 65e9daef2165d..66071ffa8f45d 100644
--- a/llvm/test/CodeGen/NVPTX/atomicrmw-sm90.ll
+++ b/llvm/test/CodeGen/NVPTX/atomicrmw-sm90.ll
@@ -20,9 +20,9 @@ define i8 @xchg_acq_rel_i8_global_cta(ptr addrspace(1) %addr, i8 %val) {
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd2, [xchg_acq_rel_i8_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd2, [xchg_acq_rel_i8_global_cta_param_0];
; SM90-NEXT: fence.release.cta;
-; SM90-NEXT: ld.param.b8 %r5, [xchg_acq_rel_i8_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b8 %r5, [xchg_acq_rel_i8_global_cta_param_1];
; SM90-NEXT: and.b64 %rd1, %rd2, -4;
; SM90-NEXT: cvt.u32.u64 %r6, %rd2;
; SM90-NEXT: and.b32 %r7, %r6, 3;
@@ -43,7 +43,7 @@ define i8 @xchg_acq_rel_i8_global_cta(ptr addrspace(1) %addr, i8 %val) {
; SM90-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NEXT: shr.u32 %r12, %r4, %r1;
; SM90-NEXT: fence.acquire.cta;
-; SM90-NEXT: st.param.b32 [func_retval0], %r12;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r12;
; SM90-NEXT: ret;
%retval = atomicrmw xchg ptr addrspace(1) %addr, i8 %val syncscope("block") acq_rel
ret i8 %retval
@@ -57,9 +57,9 @@ define i16 @xchg_acq_rel_i16_global_cta(ptr addrspace(1) %addr, i16 %val) {
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd2, [xchg_acq_rel_i16_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd2, [xchg_acq_rel_i16_global_cta_param_0];
; SM90-NEXT: fence.release.cta;
-; SM90-NEXT: ld.param.b16 %r5, [xchg_acq_rel_i16_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b16 %r5, [xchg_acq_rel_i16_global_cta_param_1];
; SM90-NEXT: and.b64 %rd1, %rd2, -4;
; SM90-NEXT: cvt.u32.u64 %r6, %rd2;
; SM90-NEXT: and.b32 %r7, %r6, 3;
@@ -80,7 +80,7 @@ define i16 @xchg_acq_rel_i16_global_cta(ptr addrspace(1) %addr, i16 %val) {
; SM90-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NEXT: shr.u32 %r12, %r4, %r1;
; SM90-NEXT: fence.acquire.cta;
-; SM90-NEXT: st.param.b32 [func_retval0], %r12;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r12;
; SM90-NEXT: ret;
%retval = atomicrmw xchg ptr addrspace(1) %addr, i16 %val syncscope("block") acq_rel
ret i16 %retval
@@ -93,10 +93,10 @@ define i32 @xchg_acq_rel_i32_global_cta(ptr addrspace(1) %addr, i32 %val) {
; SM90-NEXT: .reg .b64 %rd<2>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [xchg_acq_rel_i32_global_cta_param_0];
-; SM90-NEXT: ld.param.b32 %r1, [xchg_acq_rel_i32_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd1, [xchg_acq_rel_i32_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b32 %r1, [xchg_acq_rel_i32_global_cta_param_1];
; SM90-NEXT: atom.acq_rel.cta.global.exch.b32 %r2, [%rd1], %r1;
-; SM90-NEXT: st.param.b32 [func_retval0], %r2;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r2;
; SM90-NEXT: ret;
%retval = atomicrmw xchg ptr addrspace(1) %addr, i32 %val syncscope("block") acq_rel
ret i32 %retval
@@ -108,10 +108,10 @@ define i64 @xchg_acq_rel_i64_global_cta(ptr addrspace(1) %addr, i64 %val) {
; SM90-NEXT: .reg .b64 %rd<4>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [xchg_acq_rel_i64_global_cta_param_0];
-; SM90-NEXT: ld.param.b64 %rd2, [xchg_acq_rel_i64_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd1, [xchg_acq_rel_i64_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd2, [xchg_acq_rel_i64_global_cta_param_1];
; SM90-NEXT: atom.acq_rel.cta.global.exch.b64 %rd3, [%rd1], %rd2;
-; SM90-NEXT: st.param.b64 [func_retval0], %rd3;
+; SM90-NEXT: st.param::func.b64 [func_retval0], %rd3;
; SM90-NEXT: ret;
%retval = atomicrmw xchg ptr addrspace(1) %addr, i64 %val syncscope("block") acq_rel
ret i64 %retval
@@ -125,9 +125,9 @@ define i8 @add_acq_rel_i8_global_cta(ptr addrspace(1) %addr, i8 %val) {
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd2, [add_acq_rel_i8_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd2, [add_acq_rel_i8_global_cta_param_0];
; SM90-NEXT: fence.release.cta;
-; SM90-NEXT: ld.param.b8 %r6, [add_acq_rel_i8_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b8 %r6, [add_acq_rel_i8_global_cta_param_1];
; SM90-NEXT: and.b64 %rd1, %rd2, -4;
; SM90-NEXT: cvt.u32.u64 %r7, %rd2;
; SM90-NEXT: and.b32 %r8, %r7, 3;
@@ -150,7 +150,7 @@ define i8 @add_acq_rel_i8_global_cta(ptr addrspace(1) %addr, i8 %val) {
; SM90-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NEXT: shr.u32 %r14, %r5, %r1;
; SM90-NEXT: fence.acquire.cta;
-; SM90-NEXT: st.param.b32 [func_retval0], %r14;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r14;
; SM90-NEXT: ret;
%retval = atomicrmw add ptr addrspace(1) %addr, i8 %val syncscope("block") acq_rel
ret i8 %retval
@@ -164,9 +164,9 @@ define i16 @add_acq_rel_i16_global_cta(ptr addrspace(1) %addr, i16 %val) {
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd2, [add_acq_rel_i16_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd2, [add_acq_rel_i16_global_cta_param_0];
; SM90-NEXT: fence.release.cta;
-; SM90-NEXT: ld.param.b16 %r6, [add_acq_rel_i16_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b16 %r6, [add_acq_rel_i16_global_cta_param_1];
; SM90-NEXT: and.b64 %rd1, %rd2, -4;
; SM90-NEXT: cvt.u32.u64 %r7, %rd2;
; SM90-NEXT: and.b32 %r8, %r7, 3;
@@ -189,7 +189,7 @@ define i16 @add_acq_rel_i16_global_cta(ptr addrspace(1) %addr, i16 %val) {
; SM90-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NEXT: shr.u32 %r14, %r5, %r1;
; SM90-NEXT: fence.acquire.cta;
-; SM90-NEXT: st.param.b32 [func_retval0], %r14;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r14;
; SM90-NEXT: ret;
%retval = atomicrmw add ptr addrspace(1) %addr, i16 %val syncscope("block") acq_rel
ret i16 %retval
@@ -202,10 +202,10 @@ define i32 @add_acq_rel_i32_global_cta(ptr addrspace(1) %addr, i32 %val) {
; SM90-NEXT: .reg .b64 %rd<2>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [add_acq_rel_i32_global_cta_param_0];
-; SM90-NEXT: ld.param.b32 %r1, [add_acq_rel_i32_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd1, [add_acq_rel_i32_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b32 %r1, [add_acq_rel_i32_global_cta_param_1];
; SM90-NEXT: atom.acq_rel.cta.global.add.u32 %r2, [%rd1], %r1;
-; SM90-NEXT: st.param.b32 [func_retval0], %r2;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r2;
; SM90-NEXT: ret;
%retval = atomicrmw add ptr addrspace(1) %addr, i32 %val syncscope("block") acq_rel
ret i32 %retval
@@ -217,10 +217,10 @@ define i64 @add_acq_rel_i64_global_cta(ptr addrspace(1) %addr, i64 %val) {
; SM90-NEXT: .reg .b64 %rd<4>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [add_acq_rel_i64_global_cta_param_0];
-; SM90-NEXT: ld.param.b64 %rd2, [add_acq_rel_i64_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd1, [add_acq_rel_i64_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd2, [add_acq_rel_i64_global_cta_param_1];
; SM90-NEXT: atom.acq_rel.cta.global.add.u64 %rd3, [%rd1], %rd2;
-; SM90-NEXT: st.param.b64 [func_retval0], %rd3;
+; SM90-NEXT: st.param::func.b64 [func_retval0], %rd3;
; SM90-NEXT: ret;
%retval = atomicrmw add ptr addrspace(1) %addr, i64 %val syncscope("block") acq_rel
ret i64 %retval
@@ -234,9 +234,9 @@ define i8 @sub_acq_rel_i8_global_cta(ptr addrspace(1) %addr, i8 %val) {
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd2, [sub_acq_rel_i8_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd2, [sub_acq_rel_i8_global_cta_param_0];
; SM90-NEXT: fence.release.cta;
-; SM90-NEXT: ld.param.b8 %r6, [sub_acq_rel_i8_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b8 %r6, [sub_acq_rel_i8_global_cta_param_1];
; SM90-NEXT: and.b64 %rd1, %rd2, -4;
; SM90-NEXT: cvt.u32.u64 %r7, %rd2;
; SM90-NEXT: and.b32 %r8, %r7, 3;
@@ -259,7 +259,7 @@ define i8 @sub_acq_rel_i8_global_cta(ptr addrspace(1) %addr, i8 %val) {
; SM90-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NEXT: shr.u32 %r14, %r5, %r1;
; SM90-NEXT: fence.acquire.cta;
-; SM90-NEXT: st.param.b32 [func_retval0], %r14;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r14;
; SM90-NEXT: ret;
%retval = atomicrmw sub ptr addrspace(1) %addr, i8 %val syncscope("block") acq_rel
ret i8 %retval
@@ -273,9 +273,9 @@ define i16 @sub_acq_rel_i16_global_cta(ptr addrspace(1) %addr, i16 %val) {
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd2, [sub_acq_rel_i16_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd2, [sub_acq_rel_i16_global_cta_param_0];
; SM90-NEXT: fence.release.cta;
-; SM90-NEXT: ld.param.b16 %r6, [sub_acq_rel_i16_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b16 %r6, [sub_acq_rel_i16_global_cta_param_1];
; SM90-NEXT: and.b64 %rd1, %rd2, -4;
; SM90-NEXT: cvt.u32.u64 %r7, %rd2;
; SM90-NEXT: and.b32 %r8, %r7, 3;
@@ -298,7 +298,7 @@ define i16 @sub_acq_rel_i16_global_cta(ptr addrspace(1) %addr, i16 %val) {
; SM90-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NEXT: shr.u32 %r14, %r5, %r1;
; SM90-NEXT: fence.acquire.cta;
-; SM90-NEXT: st.param.b32 [func_retval0], %r14;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r14;
; SM90-NEXT: ret;
%retval = atomicrmw sub ptr addrspace(1) %addr, i16 %val syncscope("block") acq_rel
ret i16 %retval
@@ -311,11 +311,11 @@ define i32 @sub_acq_rel_i32_global_cta(ptr addrspace(1) %addr, i32 %val) {
; SM90-NEXT: .reg .b64 %rd<2>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [sub_acq_rel_i32_global_cta_param_0];
-; SM90-NEXT: ld.param.b32 %r1, [sub_acq_rel_i32_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd1, [sub_acq_rel_i32_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b32 %r1, [sub_acq_rel_i32_global_cta_param_1];
; SM90-NEXT: neg.s32 %r2, %r1;
; SM90-NEXT: atom.acq_rel.cta.global.add.u32 %r3, [%rd1], %r2;
-; SM90-NEXT: st.param.b32 [func_retval0], %r3;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r3;
; SM90-NEXT: ret;
%retval = atomicrmw sub ptr addrspace(1) %addr, i32 %val syncscope("block") acq_rel
ret i32 %retval
@@ -327,11 +327,11 @@ define i64 @sub_acq_rel_i64_global_cta(ptr addrspace(1) %addr, i64 %val) {
; SM90-NEXT: .reg .b64 %rd<5>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [sub_acq_rel_i64_global_cta_param_0];
-; SM90-NEXT: ld.param.b64 %rd2, [sub_acq_rel_i64_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd1, [sub_acq_rel_i64_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd2, [sub_acq_rel_i64_global_cta_param_1];
; SM90-NEXT: neg.s64 %rd3, %rd2;
; SM90-NEXT: atom.acq_rel.cta.global.add.u64 %rd4, [%rd1], %rd3;
-; SM90-NEXT: st.param.b64 [func_retval0], %rd4;
+; SM90-NEXT: st.param::func.b64 [func_retval0], %rd4;
; SM90-NEXT: ret;
%retval = atomicrmw sub ptr addrspace(1) %addr, i64 %val syncscope("block") acq_rel
ret i64 %retval
@@ -344,9 +344,9 @@ define i8 @and_acq_rel_i8_global_cta(ptr addrspace(1) %addr, i8 %val) {
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [and_acq_rel_i8_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd1, [and_acq_rel_i8_global_cta_param_0];
; SM90-NEXT: fence.release.cta;
-; SM90-NEXT: ld.param.b8 %r1, [and_acq_rel_i8_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b8 %r1, [and_acq_rel_i8_global_cta_param_1];
; SM90-NEXT: and.b64 %rd2, %rd1, -4;
; SM90-NEXT: cvt.u32.u64 %r2, %rd1;
; SM90-NEXT: and.b32 %r3, %r2, 3;
@@ -359,7 +359,7 @@ define i8 @and_acq_rel_i8_global_cta(ptr addrspace(1) %addr, i8 %val) {
; SM90-NEXT: atom.relaxed.cta.global.and.b32 %r10, [%rd2], %r9;
; SM90-NEXT: shr.u32 %r11, %r10, %r4;
; SM90-NEXT: fence.acquire.cta;
-; SM90-NEXT: st.param.b32 [func_retval0], %r11;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r11;
; SM90-NEXT: ret;
%retval = atomicrmw and ptr addrspace(1) %addr, i8 %val syncscope("block") acq_rel
ret i8 %retval
@@ -372,9 +372,9 @@ define i16 @and_acq_rel_i16_global_cta(ptr addrspace(1) %addr, i16 %val) {
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [and_acq_rel_i16_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd1, [and_acq_rel_i16_global_cta_param_0];
; SM90-NEXT: fence.release.cta;
-; SM90-NEXT: ld.param.b16 %r1, [and_acq_rel_i16_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b16 %r1, [and_acq_rel_i16_global_cta_param_1];
; SM90-NEXT: and.b64 %rd2, %rd1, -4;
; SM90-NEXT: cvt.u32.u64 %r2, %rd1;
; SM90-NEXT: and.b32 %r3, %r2, 3;
@@ -387,7 +387,7 @@ define i16 @and_acq_rel_i16_global_cta(ptr addrspace(1) %addr, i16 %val) {
; SM90-NEXT: atom.relaxed.cta.global.and.b32 %r10, [%rd2], %r9;
; SM90-NEXT: shr.u32 %r11, %r10, %r4;
; SM90-NEXT: fence.acquire.cta;
-; SM90-NEXT: st.param.b32 [func_retval0], %r11;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r11;
; SM90-NEXT: ret;
%retval = atomicrmw and ptr addrspace(1) %addr, i16 %val syncscope("block") acq_rel
ret i16 %retval
@@ -400,10 +400,10 @@ define i32 @and_acq_rel_i32_global_cta(ptr addrspace(1) %addr, i32 %val) {
; SM90-NEXT: .reg .b64 %rd<2>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [and_acq_rel_i32_global_cta_param_0];
-; SM90-NEXT: ld.param.b32 %r1, [and_acq_rel_i32_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd1, [and_acq_rel_i32_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b32 %r1, [and_acq_rel_i32_global_cta_param_1];
; SM90-NEXT: atom.acq_rel.cta.global.and.b32 %r2, [%rd1], %r1;
-; SM90-NEXT: st.param.b32 [func_retval0], %r2;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r2;
; SM90-NEXT: ret;
%retval = atomicrmw and ptr addrspace(1) %addr, i32 %val syncscope("block") acq_rel
ret i32 %retval
@@ -415,10 +415,10 @@ define i64 @and_acq_rel_i64_global_cta(ptr addrspace(1) %addr, i64 %val) {
; SM90-NEXT: .reg .b64 %rd<4>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [and_acq_rel_i64_global_cta_param_0];
-; SM90-NEXT: ld.param.b64 %rd2, [and_acq_rel_i64_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd1, [and_acq_rel_i64_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd2, [and_acq_rel_i64_global_cta_param_1];
; SM90-NEXT: atom.acq_rel.cta.global.and.b64 %rd3, [%rd1], %rd2;
-; SM90-NEXT: st.param.b64 [func_retval0], %rd3;
+; SM90-NEXT: st.param::func.b64 [func_retval0], %rd3;
; SM90-NEXT: ret;
%retval = atomicrmw and ptr addrspace(1) %addr, i64 %val syncscope("block") acq_rel
ret i64 %retval
@@ -432,9 +432,9 @@ define i8 @nand_acq_rel_i8_global_cta(ptr addrspace(1) %addr, i8 %val) {
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd2, [nand_acq_rel_i8_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd2, [nand_acq_rel_i8_global_cta_param_0];
; SM90-NEXT: fence.release.cta;
-; SM90-NEXT: ld.param.b8 %r6, [nand_acq_rel_i8_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b8 %r6, [nand_acq_rel_i8_global_cta_param_1];
; SM90-NEXT: and.b64 %rd1, %rd2, -4;
; SM90-NEXT: cvt.u32.u64 %r7, %rd2;
; SM90-NEXT: and.b32 %r8, %r7, 3;
@@ -458,7 +458,7 @@ define i8 @nand_acq_rel_i8_global_cta(ptr addrspace(1) %addr, i8 %val) {
; SM90-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NEXT: shr.u32 %r15, %r5, %r1;
; SM90-NEXT: fence.acquire.cta;
-; SM90-NEXT: st.param.b32 [func_retval0], %r15;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r15;
; SM90-NEXT: ret;
%retval = atomicrmw nand ptr addrspace(1) %addr, i8 %val syncscope("block") acq_rel
ret i8 %retval
@@ -472,9 +472,9 @@ define i16 @nand_acq_rel_i16_global_cta(ptr addrspace(1) %addr, i16 %val) {
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd2, [nand_acq_rel_i16_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd2, [nand_acq_rel_i16_global_cta_param_0];
; SM90-NEXT: fence.release.cta;
-; SM90-NEXT: ld.param.b16 %r6, [nand_acq_rel_i16_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b16 %r6, [nand_acq_rel_i16_global_cta_param_1];
; SM90-NEXT: and.b64 %rd1, %rd2, -4;
; SM90-NEXT: cvt.u32.u64 %r7, %rd2;
; SM90-NEXT: and.b32 %r8, %r7, 3;
@@ -498,7 +498,7 @@ define i16 @nand_acq_rel_i16_global_cta(ptr addrspace(1) %addr, i16 %val) {
; SM90-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NEXT: shr.u32 %r15, %r5, %r1;
; SM90-NEXT: fence.acquire.cta;
-; SM90-NEXT: st.param.b32 [func_retval0], %r15;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r15;
; SM90-NEXT: ret;
%retval = atomicrmw nand ptr addrspace(1) %addr, i16 %val syncscope("block") acq_rel
ret i16 %retval
@@ -512,8 +512,8 @@ define i32 @nand_acq_rel_i32_global_cta(ptr addrspace(1) %addr, i32 %val) {
; SM90-NEXT: .reg .b64 %rd<2>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b32 %r2, [nand_acq_rel_i32_global_cta_param_1];
-; SM90-NEXT: ld.param.b64 %rd1, [nand_acq_rel_i32_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b32 %r2, [nand_acq_rel_i32_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd1, [nand_acq_rel_i32_global_cta_param_0];
; SM90-NEXT: fence.release.cta;
; SM90-NEXT: ld.relaxed.cta.global.b32 %r5, [%rd1];
; SM90-NEXT: $L__BB18_1: // %atomicrmw.start
@@ -526,7 +526,7 @@ define i32 @nand_acq_rel_i32_global_cta(ptr addrspace(1) %addr, i32 %val) {
; SM90-NEXT: @%p1 bra $L__BB18_1;
; SM90-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NEXT: fence.acquire.cta;
-; SM90-NEXT: st.param.b32 [func_retval0], %r1;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r1;
; SM90-NEXT: ret;
%retval = atomicrmw nand ptr addrspace(1) %addr, i32 %val syncscope("block") acq_rel
ret i32 %retval
@@ -539,8 +539,8 @@ define i64 @nand_acq_rel_i64_global_cta(ptr addrspace(1) %addr, i64 %val) {
; SM90-NEXT: .reg .b64 %rd<7>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd3, [nand_acq_rel_i64_global_cta_param_1];
-; SM90-NEXT: ld.param.b64 %rd2, [nand_acq_rel_i64_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd3, [nand_acq_rel_i64_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd2, [nand_acq_rel_i64_global_cta_param_0];
; SM90-NEXT: fence.release.cta;
; SM90-NEXT: ld.relaxed.cta.global.b64 %rd6, [%rd2];
; SM90-NEXT: $L__BB19_1: // %atomicrmw.start
@@ -553,7 +553,7 @@ define i64 @nand_acq_rel_i64_global_cta(ptr addrspace(1) %addr, i64 %val) {
; SM90-NEXT: @%p1 bra $L__BB19_1;
; SM90-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NEXT: fence.acquire.cta;
-; SM90-NEXT: st.param.b64 [func_retval0], %rd1;
+; SM90-NEXT: st.param::func.b64 [func_retval0], %rd1;
; SM90-NEXT: ret;
%retval = atomicrmw nand ptr addrspace(1) %addr, i64 %val syncscope("block") acq_rel
ret i64 %retval
@@ -566,9 +566,9 @@ define i8 @or_acq_rel_i8_global_cta(ptr addrspace(1) %addr, i8 %val) {
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [or_acq_rel_i8_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd1, [or_acq_rel_i8_global_cta_param_0];
; SM90-NEXT: fence.release.cta;
-; SM90-NEXT: ld.param.b8 %r1, [or_acq_rel_i8_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b8 %r1, [or_acq_rel_i8_global_cta_param_1];
; SM90-NEXT: and.b64 %rd2, %rd1, -4;
; SM90-NEXT: cvt.u32.u64 %r2, %rd1;
; SM90-NEXT: and.b32 %r3, %r2, 3;
@@ -577,7 +577,7 @@ define i8 @or_acq_rel_i8_global_cta(ptr addrspace(1) %addr, i8 %val) {
; SM90-NEXT: atom.relaxed.cta.global.or.b32 %r6, [%rd2], %r5;
; SM90-NEXT: shr.u32 %r7, %r6, %r4;
; SM90-NEXT: fence.acquire.cta;
-; SM90-NEXT: st.param.b32 [func_retval0], %r7;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r7;
; SM90-NEXT: ret;
%retval = atomicrmw or ptr addrspace(1) %addr, i8 %val syncscope("block") acq_rel
ret i8 %retval
@@ -590,9 +590,9 @@ define i16 @or_acq_rel_i16_global_cta(ptr addrspace(1) %addr, i16 %val) {
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [or_acq_rel_i16_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd1, [or_acq_rel_i16_global_cta_param_0];
; SM90-NEXT: fence.release.cta;
-; SM90-NEXT: ld.param.b16 %r1, [or_acq_rel_i16_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b16 %r1, [or_acq_rel_i16_global_cta_param_1];
; SM90-NEXT: and.b64 %rd2, %rd1, -4;
; SM90-NEXT: cvt.u32.u64 %r2, %rd1;
; SM90-NEXT: and.b32 %r3, %r2, 3;
@@ -601,7 +601,7 @@ define i16 @or_acq_rel_i16_global_cta(ptr addrspace(1) %addr, i16 %val) {
; SM90-NEXT: atom.relaxed.cta.global.or.b32 %r6, [%rd2], %r5;
; SM90-NEXT: shr.u32 %r7, %r6, %r4;
; SM90-NEXT: fence.acquire.cta;
-; SM90-NEXT: st.param.b32 [func_retval0], %r7;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r7;
; SM90-NEXT: ret;
%retval = atomicrmw or ptr addrspace(1) %addr, i16 %val syncscope("block") acq_rel
ret i16 %retval
@@ -614,10 +614,10 @@ define i32 @or_acq_rel_i32_global_cta(ptr addrspace(1) %addr, i32 %val) {
; SM90-NEXT: .reg .b64 %rd<2>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [or_acq_rel_i32_global_cta_param_0];
-; SM90-NEXT: ld.param.b32 %r1, [or_acq_rel_i32_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd1, [or_acq_rel_i32_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b32 %r1, [or_acq_rel_i32_global_cta_param_1];
; SM90-NEXT: atom.acq_rel.cta.global.or.b32 %r2, [%rd1], %r1;
-; SM90-NEXT: st.param.b32 [func_retval0], %r2;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r2;
; SM90-NEXT: ret;
%retval = atomicrmw or ptr addrspace(1) %addr, i32 %val syncscope("block") acq_rel
ret i32 %retval
@@ -629,10 +629,10 @@ define i64 @or_acq_rel_i64_global_cta(ptr addrspace(1) %addr, i64 %val) {
; SM90-NEXT: .reg .b64 %rd<4>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [or_acq_rel_i64_global_cta_param_0];
-; SM90-NEXT: ld.param.b64 %rd2, [or_acq_rel_i64_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd1, [or_acq_rel_i64_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd2, [or_acq_rel_i64_global_cta_param_1];
; SM90-NEXT: atom.acq_rel.cta.global.or.b64 %rd3, [%rd1], %rd2;
-; SM90-NEXT: st.param.b64 [func_retval0], %rd3;
+; SM90-NEXT: st.param::func.b64 [func_retval0], %rd3;
; SM90-NEXT: ret;
%retval = atomicrmw or ptr addrspace(1) %addr, i64 %val syncscope("block") acq_rel
ret i64 %retval
@@ -645,9 +645,9 @@ define i8 @xor_acq_rel_i8_global_cta(ptr addrspace(1) %addr, i8 %val) {
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [xor_acq_rel_i8_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd1, [xor_acq_rel_i8_global_cta_param_0];
; SM90-NEXT: fence.release.cta;
-; SM90-NEXT: ld.param.b8 %r1, [xor_acq_rel_i8_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b8 %r1, [xor_acq_rel_i8_global_cta_param_1];
; SM90-NEXT: and.b64 %rd2, %rd1, -4;
; SM90-NEXT: cvt.u32.u64 %r2, %rd1;
; SM90-NEXT: and.b32 %r3, %r2, 3;
@@ -656,7 +656,7 @@ define i8 @xor_acq_rel_i8_global_cta(ptr addrspace(1) %addr, i8 %val) {
; SM90-NEXT: atom.relaxed.cta.global.xor.b32 %r6, [%rd2], %r5;
; SM90-NEXT: shr.u32 %r7, %r6, %r4;
; SM90-NEXT: fence.acquire.cta;
-; SM90-NEXT: st.param.b32 [func_retval0], %r7;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r7;
; SM90-NEXT: ret;
%retval = atomicrmw xor ptr addrspace(1) %addr, i8 %val syncscope("block") acq_rel
ret i8 %retval
@@ -669,9 +669,9 @@ define i16 @xor_acq_rel_i16_global_cta(ptr addrspace(1) %addr, i16 %val) {
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [xor_acq_rel_i16_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd1, [xor_acq_rel_i16_global_cta_param_0];
; SM90-NEXT: fence.release.cta;
-; SM90-NEXT: ld.param.b16 %r1, [xor_acq_rel_i16_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b16 %r1, [xor_acq_rel_i16_global_cta_param_1];
; SM90-NEXT: and.b64 %rd2, %rd1, -4;
; SM90-NEXT: cvt.u32.u64 %r2, %rd1;
; SM90-NEXT: and.b32 %r3, %r2, 3;
@@ -680,7 +680,7 @@ define i16 @xor_acq_rel_i16_global_cta(ptr addrspace(1) %addr, i16 %val) {
; SM90-NEXT: atom.relaxed.cta.global.xor.b32 %r6, [%rd2], %r5;
; SM90-NEXT: shr.u32 %r7, %r6, %r4;
; SM90-NEXT: fence.acquire.cta;
-; SM90-NEXT: st.param.b32 [func_retval0], %r7;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r7;
; SM90-NEXT: ret;
%retval = atomicrmw xor ptr addrspace(1) %addr, i16 %val syncscope("block") acq_rel
ret i16 %retval
@@ -693,10 +693,10 @@ define i32 @xor_acq_rel_i32_global_cta(ptr addrspace(1) %addr, i32 %val) {
; SM90-NEXT: .reg .b64 %rd<2>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [xor_acq_rel_i32_global_cta_param_0];
-; SM90-NEXT: ld.param.b32 %r1, [xor_acq_rel_i32_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd1, [xor_acq_rel_i32_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b32 %r1, [xor_acq_rel_i32_global_cta_param_1];
; SM90-NEXT: atom.acq_rel.cta.global.xor.b32 %r2, [%rd1], %r1;
-; SM90-NEXT: st.param.b32 [func_retval0], %r2;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r2;
; SM90-NEXT: ret;
%retval = atomicrmw xor ptr addrspace(1) %addr, i32 %val syncscope("block") acq_rel
ret i32 %retval
@@ -708,10 +708,10 @@ define i64 @xor_acq_rel_i64_global_cta(ptr addrspace(1) %addr, i64 %val) {
; SM90-NEXT: .reg .b64 %rd<4>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [xor_acq_rel_i64_global_cta_param_0];
-; SM90-NEXT: ld.param.b64 %rd2, [xor_acq_rel_i64_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd1, [xor_acq_rel_i64_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd2, [xor_acq_rel_i64_global_cta_param_1];
; SM90-NEXT: atom.acq_rel.cta.global.xor.b64 %rd3, [%rd1], %rd2;
-; SM90-NEXT: st.param.b64 [func_retval0], %rd3;
+; SM90-NEXT: st.param::func.b64 [func_retval0], %rd3;
; SM90-NEXT: ret;
%retval = atomicrmw xor ptr addrspace(1) %addr, i64 %val syncscope("block") acq_rel
ret i64 %retval
@@ -726,8 +726,8 @@ define i8 @max_acq_rel_i8_global_cta(ptr addrspace(1) %addr, i8 %val) {
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b8 %rs1, [max_acq_rel_i8_global_cta_param_1];
-; SM90-NEXT: ld.param.b64 %rd2, [max_acq_rel_i8_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b8 %rs1, [max_acq_rel_i8_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd2, [max_acq_rel_i8_global_cta_param_0];
; SM90-NEXT: fence.release.cta;
; SM90-NEXT: and.b64 %rd1, %rd2, -4;
; SM90-NEXT: cvt.u32.u64 %r4, %rd2;
@@ -755,7 +755,7 @@ define i8 @max_acq_rel_i8_global_cta(ptr addrspace(1) %addr, i8 %val) {
; SM90-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NEXT: shr.u32 %r14, %r3, %r1;
; SM90-NEXT: fence.acquire.cta;
-; SM90-NEXT: st.param.b32 [func_retval0], %r14;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r14;
; SM90-NEXT: ret;
%retval = atomicrmw max ptr addrspace(1) %addr, i8 %val syncscope("block") acq_rel
ret i8 %retval
@@ -770,8 +770,8 @@ define i16 @max_acq_rel_i16_global_cta(ptr addrspace(1) %addr, i16 %val) {
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b16 %rs1, [max_acq_rel_i16_global_cta_param_1];
-; SM90-NEXT: ld.param.b64 %rd2, [max_acq_rel_i16_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b16 %rs1, [max_acq_rel_i16_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd2, [max_acq_rel_i16_global_cta_param_0];
; SM90-NEXT: fence.release.cta;
; SM90-NEXT: and.b64 %rd1, %rd2, -4;
; SM90-NEXT: cvt.u32.u64 %r4, %rd2;
@@ -797,7 +797,7 @@ define i16 @max_acq_rel_i16_global_cta(ptr addrspace(1) %addr, i16 %val) {
; SM90-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NEXT: shr.u32 %r13, %r3, %r1;
; SM90-NEXT: fence.acquire.cta;
-; SM90-NEXT: st.param.b32 [func_retval0], %r13;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r13;
; SM90-NEXT: ret;
%retval = atomicrmw max ptr addrspace(1) %addr, i16 %val syncscope("block") acq_rel
ret i16 %retval
@@ -810,10 +810,10 @@ define i32 @max_acq_rel_i32_global_cta(ptr addrspace(1) %addr, i32 %val) {
; SM90-NEXT: .reg .b64 %rd<2>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [max_acq_rel_i32_global_cta_param_0];
-; SM90-NEXT: ld.param.b32 %r1, [max_acq_rel_i32_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd1, [max_acq_rel_i32_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b32 %r1, [max_acq_rel_i32_global_cta_param_1];
; SM90-NEXT: atom.acq_rel.cta.global.max.s32 %r2, [%rd1], %r1;
-; SM90-NEXT: st.param.b32 [func_retval0], %r2;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r2;
; SM90-NEXT: ret;
%retval = atomicrmw max ptr addrspace(1) %addr, i32 %val syncscope("block") acq_rel
ret i32 %retval
@@ -825,10 +825,10 @@ define i64 @max_acq_rel_i64_global_cta(ptr addrspace(1) %addr, i64 %val) {
; SM90-NEXT: .reg .b64 %rd<4>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [max_acq_rel_i64_global_cta_param_0];
-; SM90-NEXT: ld.param.b64 %rd2, [max_acq_rel_i64_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd1, [max_acq_rel_i64_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd2, [max_acq_rel_i64_global_cta_param_1];
; SM90-NEXT: atom.acq_rel.cta.global.max.s64 %rd3, [%rd1], %rd2;
-; SM90-NEXT: st.param.b64 [func_retval0], %rd3;
+; SM90-NEXT: st.param::func.b64 [func_retval0], %rd3;
; SM90-NEXT: ret;
%retval = atomicrmw max ptr addrspace(1) %addr, i64 %val syncscope("block") acq_rel
ret i64 %retval
@@ -843,8 +843,8 @@ define i8 @min_acq_rel_i8_global_cta(ptr addrspace(1) %addr, i8 %val) {
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b8 %rs1, [min_acq_rel_i8_global_cta_param_1];
-; SM90-NEXT: ld.param.b64 %rd2, [min_acq_rel_i8_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b8 %rs1, [min_acq_rel_i8_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd2, [min_acq_rel_i8_global_cta_param_0];
; SM90-NEXT: fence.release.cta;
; SM90-NEXT: and.b64 %rd1, %rd2, -4;
; SM90-NEXT: cvt.u32.u64 %r4, %rd2;
@@ -872,7 +872,7 @@ define i8 @min_acq_rel_i8_global_cta(ptr addrspace(1) %addr, i8 %val) {
; SM90-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NEXT: shr.u32 %r14, %r3, %r1;
; SM90-NEXT: fence.acquire.cta;
-; SM90-NEXT: st.param.b32 [func_retval0], %r14;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r14;
; SM90-NEXT: ret;
%retval = atomicrmw min ptr addrspace(1) %addr, i8 %val syncscope("block") acq_rel
ret i8 %retval
@@ -887,8 +887,8 @@ define i16 @min_acq_rel_i16_global_cta(ptr addrspace(1) %addr, i16 %val) {
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b16 %rs1, [min_acq_rel_i16_global_cta_param_1];
-; SM90-NEXT: ld.param.b64 %rd2, [min_acq_rel_i16_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b16 %rs1, [min_acq_rel_i16_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd2, [min_acq_rel_i16_global_cta_param_0];
; SM90-NEXT: fence.release.cta;
; SM90-NEXT: and.b64 %rd1, %rd2, -4;
; SM90-NEXT: cvt.u32.u64 %r4, %rd2;
@@ -914,7 +914,7 @@ define i16 @min_acq_rel_i16_global_cta(ptr addrspace(1) %addr, i16 %val) {
; SM90-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NEXT: shr.u32 %r13, %r3, %r1;
; SM90-NEXT: fence.acquire.cta;
-; SM90-NEXT: st.param.b32 [func_retval0], %r13;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r13;
; SM90-NEXT: ret;
%retval = atomicrmw min ptr addrspace(1) %addr, i16 %val syncscope("block") acq_rel
ret i16 %retval
@@ -927,10 +927,10 @@ define i32 @min_acq_rel_i32_global_cta(ptr addrspace(1) %addr, i32 %val) {
; SM90-NEXT: .reg .b64 %rd<2>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [min_acq_rel_i32_global_cta_param_0];
-; SM90-NEXT: ld.param.b32 %r1, [min_acq_rel_i32_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd1, [min_acq_rel_i32_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b32 %r1, [min_acq_rel_i32_global_cta_param_1];
; SM90-NEXT: atom.acq_rel.cta.global.min.s32 %r2, [%rd1], %r1;
-; SM90-NEXT: st.param.b32 [func_retval0], %r2;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r2;
; SM90-NEXT: ret;
%retval = atomicrmw min ptr addrspace(1) %addr, i32 %val syncscope("block") acq_rel
ret i32 %retval
@@ -942,10 +942,10 @@ define i64 @min_acq_rel_i64_global_cta(ptr addrspace(1) %addr, i64 %val) {
; SM90-NEXT: .reg .b64 %rd<4>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [min_acq_rel_i64_global_cta_param_0];
-; SM90-NEXT: ld.param.b64 %rd2, [min_acq_rel_i64_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd1, [min_acq_rel_i64_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd2, [min_acq_rel_i64_global_cta_param_1];
; SM90-NEXT: atom.acq_rel.cta.global.min.s64 %rd3, [%rd1], %rd2;
-; SM90-NEXT: st.param.b64 [func_retval0], %rd3;
+; SM90-NEXT: st.param::func.b64 [func_retval0], %rd3;
; SM90-NEXT: ret;
%retval = atomicrmw min ptr addrspace(1) %addr, i64 %val syncscope("block") acq_rel
ret i64 %retval
@@ -960,8 +960,8 @@ define i8 @umax_acq_rel_i8_global_cta(ptr addrspace(1) %addr, i8 %val) {
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b8 %rs1, [umax_acq_rel_i8_global_cta_param_1];
-; SM90-NEXT: ld.param.b64 %rd2, [umax_acq_rel_i8_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b8 %rs1, [umax_acq_rel_i8_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd2, [umax_acq_rel_i8_global_cta_param_0];
; SM90-NEXT: fence.release.cta;
; SM90-NEXT: and.b64 %rd1, %rd2, -4;
; SM90-NEXT: cvt.u32.u64 %r4, %rd2;
@@ -988,7 +988,7 @@ define i8 @umax_acq_rel_i8_global_cta(ptr addrspace(1) %addr, i8 %val) {
; SM90-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NEXT: shr.u32 %r13, %r3, %r1;
; SM90-NEXT: fence.acquire.cta;
-; SM90-NEXT: st.param.b32 [func_retval0], %r13;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r13;
; SM90-NEXT: ret;
%retval = atomicrmw umax ptr addrspace(1) %addr, i8 %val syncscope("block") acq_rel
ret i8 %retval
@@ -1003,8 +1003,8 @@ define i16 @umax_acq_rel_i16_global_cta(ptr addrspace(1) %addr, i16 %val) {
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b16 %rs1, [umax_acq_rel_i16_global_cta_param_1];
-; SM90-NEXT: ld.param.b64 %rd2, [umax_acq_rel_i16_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b16 %rs1, [umax_acq_rel_i16_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd2, [umax_acq_rel_i16_global_cta_param_0];
; SM90-NEXT: fence.release.cta;
; SM90-NEXT: and.b64 %rd1, %rd2, -4;
; SM90-NEXT: cvt.u32.u64 %r4, %rd2;
@@ -1030,7 +1030,7 @@ define i16 @umax_acq_rel_i16_global_cta(ptr addrspace(1) %addr, i16 %val) {
; SM90-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NEXT: shr.u32 %r13, %r3, %r1;
; SM90-NEXT: fence.acquire.cta;
-; SM90-NEXT: st.param.b32 [func_retval0], %r13;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r13;
; SM90-NEXT: ret;
%retval = atomicrmw umax ptr addrspace(1) %addr, i16 %val syncscope("block") acq_rel
ret i16 %retval
@@ -1043,10 +1043,10 @@ define i32 @umax_acq_rel_i32_global_cta(ptr addrspace(1) %addr, i32 %val) {
; SM90-NEXT: .reg .b64 %rd<2>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [umax_acq_rel_i32_global_cta_param_0];
-; SM90-NEXT: ld.param.b32 %r1, [umax_acq_rel_i32_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd1, [umax_acq_rel_i32_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b32 %r1, [umax_acq_rel_i32_global_cta_param_1];
; SM90-NEXT: atom.acq_rel.cta.global.max.u32 %r2, [%rd1], %r1;
-; SM90-NEXT: st.param.b32 [func_retval0], %r2;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r2;
; SM90-NEXT: ret;
%retval = atomicrmw umax ptr addrspace(1) %addr, i32 %val syncscope("block") acq_rel
ret i32 %retval
@@ -1058,10 +1058,10 @@ define i64 @umax_acq_rel_i64_global_cta(ptr addrspace(1) %addr, i64 %val) {
; SM90-NEXT: .reg .b64 %rd<4>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [umax_acq_rel_i64_global_cta_param_0];
-; SM90-NEXT: ld.param.b64 %rd2, [umax_acq_rel_i64_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd1, [umax_acq_rel_i64_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd2, [umax_acq_rel_i64_global_cta_param_1];
; SM90-NEXT: atom.acq_rel.cta.global.max.u64 %rd3, [%rd1], %rd2;
-; SM90-NEXT: st.param.b64 [func_retval0], %rd3;
+; SM90-NEXT: st.param::func.b64 [func_retval0], %rd3;
; SM90-NEXT: ret;
%retval = atomicrmw umax ptr addrspace(1) %addr, i64 %val syncscope("block") acq_rel
ret i64 %retval
@@ -1076,8 +1076,8 @@ define i8 @umin_acq_rel_i8_global_cta(ptr addrspace(1) %addr, i8 %val) {
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b8 %rs1, [umin_acq_rel_i8_global_cta_param_1];
-; SM90-NEXT: ld.param.b64 %rd2, [umin_acq_rel_i8_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b8 %rs1, [umin_acq_rel_i8_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd2, [umin_acq_rel_i8_global_cta_param_0];
; SM90-NEXT: fence.release.cta;
; SM90-NEXT: and.b64 %rd1, %rd2, -4;
; SM90-NEXT: cvt.u32.u64 %r4, %rd2;
@@ -1104,7 +1104,7 @@ define i8 @umin_acq_rel_i8_global_cta(ptr addrspace(1) %addr, i8 %val) {
; SM90-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NEXT: shr.u32 %r13, %r3, %r1;
; SM90-NEXT: fence.acquire.cta;
-; SM90-NEXT: st.param.b32 [func_retval0], %r13;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r13;
; SM90-NEXT: ret;
%retval = atomicrmw umin ptr addrspace(1) %addr, i8 %val syncscope("block") acq_rel
ret i8 %retval
@@ -1119,8 +1119,8 @@ define i16 @umin_acq_rel_i16_global_cta(ptr addrspace(1) %addr, i16 %val) {
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b16 %rs1, [umin_acq_rel_i16_global_cta_param_1];
-; SM90-NEXT: ld.param.b64 %rd2, [umin_acq_rel_i16_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b16 %rs1, [umin_acq_rel_i16_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd2, [umin_acq_rel_i16_global_cta_param_0];
; SM90-NEXT: fence.release.cta;
; SM90-NEXT: and.b64 %rd1, %rd2, -4;
; SM90-NEXT: cvt.u32.u64 %r4, %rd2;
@@ -1146,7 +1146,7 @@ define i16 @umin_acq_rel_i16_global_cta(ptr addrspace(1) %addr, i16 %val) {
; SM90-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NEXT: shr.u32 %r13, %r3, %r1;
; SM90-NEXT: fence.acquire.cta;
-; SM90-NEXT: st.param.b32 [func_retval0], %r13;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r13;
; SM90-NEXT: ret;
%retval = atomicrmw umin ptr addrspace(1) %addr, i16 %val syncscope("block") acq_rel
ret i16 %retval
@@ -1159,10 +1159,10 @@ define i32 @umin_acq_rel_i32_global_cta(ptr addrspace(1) %addr, i32 %val) {
; SM90-NEXT: .reg .b64 %rd<2>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [umin_acq_rel_i32_global_cta_param_0];
-; SM90-NEXT: ld.param.b32 %r1, [umin_acq_rel_i32_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd1, [umin_acq_rel_i32_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b32 %r1, [umin_acq_rel_i32_global_cta_param_1];
; SM90-NEXT: atom.acq_rel.cta.global.min.u32 %r2, [%rd1], %r1;
-; SM90-NEXT: st.param.b32 [func_retval0], %r2;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r2;
; SM90-NEXT: ret;
%retval = atomicrmw umin ptr addrspace(1) %addr, i32 %val syncscope("block") acq_rel
ret i32 %retval
@@ -1174,10 +1174,10 @@ define i64 @umin_acq_rel_i64_global_cta(ptr addrspace(1) %addr, i64 %val) {
; SM90-NEXT: .reg .b64 %rd<4>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [umin_acq_rel_i64_global_cta_param_0];
-; SM90-NEXT: ld.param.b64 %rd2, [umin_acq_rel_i64_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd1, [umin_acq_rel_i64_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd2, [umin_acq_rel_i64_global_cta_param_1];
; SM90-NEXT: atom.acq_rel.cta.global.min.u64 %rd3, [%rd1], %rd2;
-; SM90-NEXT: st.param.b64 [func_retval0], %rd3;
+; SM90-NEXT: st.param::func.b64 [func_retval0], %rd3;
; SM90-NEXT: ret;
%retval = atomicrmw umin ptr addrspace(1) %addr, i64 %val syncscope("block") acq_rel
ret i64 %retval
@@ -1192,8 +1192,8 @@ define i8 @uinc_wrap_acq_rel_i8_global_cta(ptr addrspace(1) %addr, i8 %val) {
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b8 %rs1, [uinc_wrap_acq_rel_i8_global_cta_param_1];
-; SM90-NEXT: ld.param.b64 %rd2, [uinc_wrap_acq_rel_i8_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b8 %rs1, [uinc_wrap_acq_rel_i8_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd2, [uinc_wrap_acq_rel_i8_global_cta_param_0];
; SM90-NEXT: fence.release.cta;
; SM90-NEXT: and.b64 %rd1, %rd2, -4;
; SM90-NEXT: cvt.u32.u64 %r4, %rd2;
@@ -1223,7 +1223,7 @@ define i8 @uinc_wrap_acq_rel_i8_global_cta(ptr addrspace(1) %addr, i8 %val) {
; SM90-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NEXT: shr.u32 %r14, %r3, %r1;
; SM90-NEXT: fence.acquire.cta;
-; SM90-NEXT: st.param.b32 [func_retval0], %r14;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r14;
; SM90-NEXT: ret;
%retval = atomicrmw uinc_wrap ptr addrspace(1) %addr, i8 %val syncscope("block") acq_rel
ret i8 %retval
@@ -1238,8 +1238,8 @@ define i16 @uinc_wrap_acq_rel_i16_global_cta(ptr addrspace(1) %addr, i16 %val) {
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b16 %rs1, [uinc_wrap_acq_rel_i16_global_cta_param_1];
-; SM90-NEXT: ld.param.b64 %rd2, [uinc_wrap_acq_rel_i16_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b16 %rs1, [uinc_wrap_acq_rel_i16_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd2, [uinc_wrap_acq_rel_i16_global_cta_param_0];
; SM90-NEXT: fence.release.cta;
; SM90-NEXT: and.b64 %rd1, %rd2, -4;
; SM90-NEXT: cvt.u32.u64 %r4, %rd2;
@@ -1267,7 +1267,7 @@ define i16 @uinc_wrap_acq_rel_i16_global_cta(ptr addrspace(1) %addr, i16 %val) {
; SM90-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NEXT: shr.u32 %r13, %r3, %r1;
; SM90-NEXT: fence.acquire.cta;
-; SM90-NEXT: st.param.b32 [func_retval0], %r13;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r13;
; SM90-NEXT: ret;
%retval = atomicrmw uinc_wrap ptr addrspace(1) %addr, i16 %val syncscope("block") acq_rel
ret i16 %retval
@@ -1280,10 +1280,10 @@ define i32 @uinc_wrap_acq_rel_i32_global_cta(ptr addrspace(1) %addr, i32 %val) {
; SM90-NEXT: .reg .b64 %rd<2>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [uinc_wrap_acq_rel_i32_global_cta_param_0];
-; SM90-NEXT: ld.param.b32 %r1, [uinc_wrap_acq_rel_i32_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd1, [uinc_wrap_acq_rel_i32_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b32 %r1, [uinc_wrap_acq_rel_i32_global_cta_param_1];
; SM90-NEXT: atom.acq_rel.cta.global.inc.u32 %r2, [%rd1], %r1;
-; SM90-NEXT: st.param.b32 [func_retval0], %r2;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r2;
; SM90-NEXT: ret;
%retval = atomicrmw uinc_wrap ptr addrspace(1) %addr, i32 %val syncscope("block") acq_rel
ret i32 %retval
@@ -1296,8 +1296,8 @@ define i64 @uinc_wrap_acq_rel_i64_global_cta(ptr addrspace(1) %addr, i64 %val) {
; SM90-NEXT: .reg .b64 %rd<7>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd3, [uinc_wrap_acq_rel_i64_global_cta_param_1];
-; SM90-NEXT: ld.param.b64 %rd2, [uinc_wrap_acq_rel_i64_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd3, [uinc_wrap_acq_rel_i64_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd2, [uinc_wrap_acq_rel_i64_global_cta_param_0];
; SM90-NEXT: fence.release.cta;
; SM90-NEXT: ld.relaxed.cta.global.b64 %rd6, [%rd2];
; SM90-NEXT: $L__BB47_1: // %atomicrmw.start
@@ -1311,7 +1311,7 @@ define i64 @uinc_wrap_acq_rel_i64_global_cta(ptr addrspace(1) %addr, i64 %val) {
; SM90-NEXT: @%p2 bra $L__BB47_1;
; SM90-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NEXT: fence.acquire.cta;
-; SM90-NEXT: st.param.b64 [func_retval0], %rd1;
+; SM90-NEXT: st.param::func.b64 [func_retval0], %rd1;
; SM90-NEXT: ret;
%retval = atomicrmw uinc_wrap ptr addrspace(1) %addr, i64 %val syncscope("block") acq_rel
ret i64 %retval
@@ -1326,8 +1326,8 @@ define i8 @udec_wrap_acq_rel_i8_global_cta(ptr addrspace(1) %addr, i8 %val) {
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b8 %rs1, [udec_wrap_acq_rel_i8_global_cta_param_1];
-; SM90-NEXT: ld.param.b64 %rd2, [udec_wrap_acq_rel_i8_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b8 %rs1, [udec_wrap_acq_rel_i8_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd2, [udec_wrap_acq_rel_i8_global_cta_param_0];
; SM90-NEXT: fence.release.cta;
; SM90-NEXT: and.b64 %rd1, %rd2, -4;
; SM90-NEXT: cvt.u32.u64 %r4, %rd2;
@@ -1359,7 +1359,7 @@ define i8 @udec_wrap_acq_rel_i8_global_cta(ptr addrspace(1) %addr, i8 %val) {
; SM90-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NEXT: shr.u32 %r14, %r3, %r1;
; SM90-NEXT: fence.acquire.cta;
-; SM90-NEXT: st.param.b32 [func_retval0], %r14;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r14;
; SM90-NEXT: ret;
%retval = atomicrmw udec_wrap ptr addrspace(1) %addr, i8 %val syncscope("block") acq_rel
ret i8 %retval
@@ -1374,8 +1374,8 @@ define i16 @udec_wrap_acq_rel_i16_global_cta(ptr addrspace(1) %addr, i16 %val) {
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b16 %rs1, [udec_wrap_acq_rel_i16_global_cta_param_1];
-; SM90-NEXT: ld.param.b64 %rd2, [udec_wrap_acq_rel_i16_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b16 %rs1, [udec_wrap_acq_rel_i16_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd2, [udec_wrap_acq_rel_i16_global_cta_param_0];
; SM90-NEXT: fence.release.cta;
; SM90-NEXT: and.b64 %rd1, %rd2, -4;
; SM90-NEXT: cvt.u32.u64 %r4, %rd2;
@@ -1405,7 +1405,7 @@ define i16 @udec_wrap_acq_rel_i16_global_cta(ptr addrspace(1) %addr, i16 %val) {
; SM90-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NEXT: shr.u32 %r13, %r3, %r1;
; SM90-NEXT: fence.acquire.cta;
-; SM90-NEXT: st.param.b32 [func_retval0], %r13;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r13;
; SM90-NEXT: ret;
%retval = atomicrmw udec_wrap ptr addrspace(1) %addr, i16 %val syncscope("block") acq_rel
ret i16 %retval
@@ -1418,10 +1418,10 @@ define i32 @udec_wrap_acq_rel_i32_global_cta(ptr addrspace(1) %addr, i32 %val) {
; SM90-NEXT: .reg .b64 %rd<2>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [udec_wrap_acq_rel_i32_global_cta_param_0];
-; SM90-NEXT: ld.param.b32 %r1, [udec_wrap_acq_rel_i32_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd1, [udec_wrap_acq_rel_i32_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b32 %r1, [udec_wrap_acq_rel_i32_global_cta_param_1];
; SM90-NEXT: atom.acq_rel.cta.global.dec.u32 %r2, [%rd1], %r1;
-; SM90-NEXT: st.param.b32 [func_retval0], %r2;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r2;
; SM90-NEXT: ret;
%retval = atomicrmw udec_wrap ptr addrspace(1) %addr, i32 %val syncscope("block") acq_rel
ret i32 %retval
@@ -1434,8 +1434,8 @@ define i64 @udec_wrap_acq_rel_i64_global_cta(ptr addrspace(1) %addr, i64 %val) {
; SM90-NEXT: .reg .b64 %rd<8>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd3, [udec_wrap_acq_rel_i64_global_cta_param_1];
-; SM90-NEXT: ld.param.b64 %rd2, [udec_wrap_acq_rel_i64_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd3, [udec_wrap_acq_rel_i64_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd2, [udec_wrap_acq_rel_i64_global_cta_param_0];
; SM90-NEXT: fence.release.cta;
; SM90-NEXT: ld.relaxed.cta.global.b64 %rd7, [%rd2];
; SM90-NEXT: $L__BB51_1: // %atomicrmw.start
@@ -1451,7 +1451,7 @@ define i64 @udec_wrap_acq_rel_i64_global_cta(ptr addrspace(1) %addr, i64 %val) {
; SM90-NEXT: @%p3 bra $L__BB51_1;
; SM90-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NEXT: fence.acquire.cta;
-; SM90-NEXT: st.param.b64 [func_retval0], %rd1;
+; SM90-NEXT: st.param::func.b64 [func_retval0], %rd1;
; SM90-NEXT: ret;
%retval = atomicrmw udec_wrap ptr addrspace(1) %addr, i64 %val syncscope("block") acq_rel
ret i64 %retval
@@ -1466,8 +1466,8 @@ define i8 @usub_cond_acq_rel_i8_global_cta(ptr addrspace(1) %addr, i8 %val) {
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b8 %rs1, [usub_cond_acq_rel_i8_global_cta_param_1];
-; SM90-NEXT: ld.param.b64 %rd2, [usub_cond_acq_rel_i8_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b8 %rs1, [usub_cond_acq_rel_i8_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd2, [usub_cond_acq_rel_i8_global_cta_param_0];
; SM90-NEXT: fence.release.cta;
; SM90-NEXT: and.b64 %rd1, %rd2, -4;
; SM90-NEXT: cvt.u32.u64 %r4, %rd2;
@@ -1497,7 +1497,7 @@ define i8 @usub_cond_acq_rel_i8_global_cta(ptr addrspace(1) %addr, i8 %val) {
; SM90-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NEXT: shr.u32 %r14, %r3, %r1;
; SM90-NEXT: fence.acquire.cta;
-; SM90-NEXT: st.param.b32 [func_retval0], %r14;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r14;
; SM90-NEXT: ret;
%retval = atomicrmw usub_cond ptr addrspace(1) %addr, i8 %val syncscope("block") acq_rel
ret i8 %retval
@@ -1512,8 +1512,8 @@ define i16 @usub_cond_acq_rel_i16_global_cta(ptr addrspace(1) %addr, i16 %val) {
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b16 %rs1, [usub_cond_acq_rel_i16_global_cta_param_1];
-; SM90-NEXT: ld.param.b64 %rd2, [usub_cond_acq_rel_i16_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b16 %rs1, [usub_cond_acq_rel_i16_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd2, [usub_cond_acq_rel_i16_global_cta_param_0];
; SM90-NEXT: fence.release.cta;
; SM90-NEXT: and.b64 %rd1, %rd2, -4;
; SM90-NEXT: cvt.u32.u64 %r4, %rd2;
@@ -1541,7 +1541,7 @@ define i16 @usub_cond_acq_rel_i16_global_cta(ptr addrspace(1) %addr, i16 %val) {
; SM90-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NEXT: shr.u32 %r13, %r3, %r1;
; SM90-NEXT: fence.acquire.cta;
-; SM90-NEXT: st.param.b32 [func_retval0], %r13;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r13;
; SM90-NEXT: ret;
%retval = atomicrmw usub_cond ptr addrspace(1) %addr, i16 %val syncscope("block") acq_rel
ret i16 %retval
@@ -1555,8 +1555,8 @@ define i32 @usub_cond_acq_rel_i32_global_cta(ptr addrspace(1) %addr, i32 %val) {
; SM90-NEXT: .reg .b64 %rd<2>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b32 %r2, [usub_cond_acq_rel_i32_global_cta_param_1];
-; SM90-NEXT: ld.param.b64 %rd1, [usub_cond_acq_rel_i32_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b32 %r2, [usub_cond_acq_rel_i32_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd1, [usub_cond_acq_rel_i32_global_cta_param_0];
; SM90-NEXT: fence.release.cta;
; SM90-NEXT: ld.relaxed.cta.global.b32 %r5, [%rd1];
; SM90-NEXT: $L__BB54_1: // %atomicrmw.start
@@ -1570,7 +1570,7 @@ define i32 @usub_cond_acq_rel_i32_global_cta(ptr addrspace(1) %addr, i32 %val) {
; SM90-NEXT: @%p2 bra $L__BB54_1;
; SM90-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NEXT: fence.acquire.cta;
-; SM90-NEXT: st.param.b32 [func_retval0], %r1;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r1;
; SM90-NEXT: ret;
%retval = atomicrmw usub_cond ptr addrspace(1) %addr, i32 %val syncscope("block") acq_rel
ret i32 %retval
@@ -1583,8 +1583,8 @@ define i64 @usub_cond_acq_rel_i64_global_cta(ptr addrspace(1) %addr, i64 %val) {
; SM90-NEXT: .reg .b64 %rd<7>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd3, [usub_cond_acq_rel_i64_global_cta_param_1];
-; SM90-NEXT: ld.param.b64 %rd2, [usub_cond_acq_rel_i64_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd3, [usub_cond_acq_rel_i64_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd2, [usub_cond_acq_rel_i64_global_cta_param_0];
; SM90-NEXT: fence.release.cta;
; SM90-NEXT: ld.relaxed.cta.global.b64 %rd6, [%rd2];
; SM90-NEXT: $L__BB55_1: // %atomicrmw.start
@@ -1598,7 +1598,7 @@ define i64 @usub_cond_acq_rel_i64_global_cta(ptr addrspace(1) %addr, i64 %val) {
; SM90-NEXT: @%p2 bra $L__BB55_1;
; SM90-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NEXT: fence.acquire.cta;
-; SM90-NEXT: st.param.b64 [func_retval0], %rd1;
+; SM90-NEXT: st.param::func.b64 [func_retval0], %rd1;
; SM90-NEXT: ret;
%retval = atomicrmw usub_cond ptr addrspace(1) %addr, i64 %val syncscope("block") acq_rel
ret i64 %retval
@@ -1613,8 +1613,8 @@ define i8 @usub_sat_acq_rel_i8_global_cta(ptr addrspace(1) %addr, i8 %val) {
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b8 %rs1, [usub_sat_acq_rel_i8_global_cta_param_1];
-; SM90-NEXT: ld.param.b64 %rd2, [usub_sat_acq_rel_i8_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b8 %rs1, [usub_sat_acq_rel_i8_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd2, [usub_sat_acq_rel_i8_global_cta_param_0];
; SM90-NEXT: fence.release.cta;
; SM90-NEXT: and.b64 %rd1, %rd2, -4;
; SM90-NEXT: cvt.u32.u64 %r4, %rd2;
@@ -1642,7 +1642,7 @@ define i8 @usub_sat_acq_rel_i8_global_cta(ptr addrspace(1) %addr, i8 %val) {
; SM90-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NEXT: shr.u32 %r13, %r3, %r1;
; SM90-NEXT: fence.acquire.cta;
-; SM90-NEXT: st.param.b32 [func_retval0], %r13;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r13;
; SM90-NEXT: ret;
%retval = atomicrmw usub_sat ptr addrspace(1) %addr, i8 %val syncscope("block") acq_rel
ret i8 %retval
@@ -1657,8 +1657,8 @@ define i16 @usub_sat_acq_rel_i16_global_cta(ptr addrspace(1) %addr, i16 %val) {
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b16 %rs1, [usub_sat_acq_rel_i16_global_cta_param_1];
-; SM90-NEXT: ld.param.b64 %rd2, [usub_sat_acq_rel_i16_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b16 %rs1, [usub_sat_acq_rel_i16_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd2, [usub_sat_acq_rel_i16_global_cta_param_0];
; SM90-NEXT: fence.release.cta;
; SM90-NEXT: and.b64 %rd1, %rd2, -4;
; SM90-NEXT: cvt.u32.u64 %r4, %rd2;
@@ -1685,7 +1685,7 @@ define i16 @usub_sat_acq_rel_i16_global_cta(ptr addrspace(1) %addr, i16 %val) {
; SM90-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NEXT: shr.u32 %r13, %r3, %r1;
; SM90-NEXT: fence.acquire.cta;
-; SM90-NEXT: st.param.b32 [func_retval0], %r13;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r13;
; SM90-NEXT: ret;
%retval = atomicrmw usub_sat ptr addrspace(1) %addr, i16 %val syncscope("block") acq_rel
ret i16 %retval
@@ -1699,8 +1699,8 @@ define i32 @usub_sat_acq_rel_i32_global_cta(ptr addrspace(1) %addr, i32 %val) {
; SM90-NEXT: .reg .b64 %rd<2>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b32 %r2, [usub_sat_acq_rel_i32_global_cta_param_1];
-; SM90-NEXT: ld.param.b64 %rd1, [usub_sat_acq_rel_i32_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b32 %r2, [usub_sat_acq_rel_i32_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd1, [usub_sat_acq_rel_i32_global_cta_param_0];
; SM90-NEXT: fence.release.cta;
; SM90-NEXT: ld.relaxed.cta.global.b32 %r5, [%rd1];
; SM90-NEXT: $L__BB58_1: // %atomicrmw.start
@@ -1713,7 +1713,7 @@ define i32 @usub_sat_acq_rel_i32_global_cta(ptr addrspace(1) %addr, i32 %val) {
; SM90-NEXT: @%p1 bra $L__BB58_1;
; SM90-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NEXT: fence.acquire.cta;
-; SM90-NEXT: st.param.b32 [func_retval0], %r1;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r1;
; SM90-NEXT: ret;
%retval = atomicrmw usub_sat ptr addrspace(1) %addr, i32 %val syncscope("block") acq_rel
ret i32 %retval
@@ -1726,8 +1726,8 @@ define i64 @usub_sat_acq_rel_i64_global_cta(ptr addrspace(1) %addr, i64 %val) {
; SM90-NEXT: .reg .b64 %rd<7>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd3, [usub_sat_acq_rel_i64_global_cta_param_1];
-; SM90-NEXT: ld.param.b64 %rd2, [usub_sat_acq_rel_i64_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd3, [usub_sat_acq_rel_i64_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd2, [usub_sat_acq_rel_i64_global_cta_param_0];
; SM90-NEXT: fence.release.cta;
; SM90-NEXT: ld.relaxed.cta.global.b64 %rd6, [%rd2];
; SM90-NEXT: $L__BB59_1: // %atomicrmw.start
@@ -1740,7 +1740,7 @@ define i64 @usub_sat_acq_rel_i64_global_cta(ptr addrspace(1) %addr, i64 %val) {
; SM90-NEXT: @%p1 bra $L__BB59_1;
; SM90-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NEXT: fence.acquire.cta;
-; SM90-NEXT: st.param.b64 [func_retval0], %rd1;
+; SM90-NEXT: st.param::func.b64 [func_retval0], %rd1;
; SM90-NEXT: ret;
%retval = atomicrmw usub_sat ptr addrspace(1) %addr, i64 %val syncscope("block") acq_rel
ret i64 %retval
@@ -1754,8 +1754,8 @@ define float @fadd_acq_rel_float_global_cta(ptr addrspace(1) %addr, float %val)
; SM90-NOFTZ-DISALLOW-NEXT: .reg .b64 %rd<2>;
; SM90-NOFTZ-DISALLOW-EMPTY:
; SM90-NOFTZ-DISALLOW-NEXT: // %bb.0:
-; SM90-NOFTZ-DISALLOW-NEXT: ld.param.b32 %r2, [fadd_acq_rel_float_global_cta_param_1];
-; SM90-NOFTZ-DISALLOW-NEXT: ld.param.b64 %rd1, [fadd_acq_rel_float_global_cta_param_0];
+; SM90-NOFTZ-DISALLOW-NEXT: ld.param::func.b32 %r2, [fadd_acq_rel_float_global_cta_param_1];
+; SM90-NOFTZ-DISALLOW-NEXT: ld.param::func.b64 %rd1, [fadd_acq_rel_float_global_cta_param_0];
; SM90-NOFTZ-DISALLOW-NEXT: fence.release.cta;
; SM90-NOFTZ-DISALLOW-NEXT: ld.relaxed.cta.global.b32 %r4, [%rd1];
; SM90-NOFTZ-DISALLOW-NEXT: $L__BB60_1: // %atomicrmw.start
@@ -1767,7 +1767,7 @@ define float @fadd_acq_rel_float_global_cta(ptr addrspace(1) %addr, float %val)
; SM90-NOFTZ-DISALLOW-NEXT: @%p1 bra $L__BB60_1;
; SM90-NOFTZ-DISALLOW-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NOFTZ-DISALLOW-NEXT: fence.acquire.cta;
-; SM90-NOFTZ-DISALLOW-NEXT: st.param.b32 [func_retval0], %r1;
+; SM90-NOFTZ-DISALLOW-NEXT: st.param::func.b32 [func_retval0], %r1;
; SM90-NOFTZ-DISALLOW-NEXT: ret;
;
; SM90-NOFTZ-ALLOW-LABEL: fadd_acq_rel_float_global_cta(
@@ -1776,10 +1776,10 @@ define float @fadd_acq_rel_float_global_cta(ptr addrspace(1) %addr, float %val)
; SM90-NOFTZ-ALLOW-NEXT: .reg .b64 %rd<2>;
; SM90-NOFTZ-ALLOW-EMPTY:
; SM90-NOFTZ-ALLOW-NEXT: // %bb.0:
-; SM90-NOFTZ-ALLOW-NEXT: ld.param.b64 %rd1, [fadd_acq_rel_float_global_cta_param_0];
-; SM90-NOFTZ-ALLOW-NEXT: ld.param.b32 %r1, [fadd_acq_rel_float_global_cta_param_1];
+; SM90-NOFTZ-ALLOW-NEXT: ld.param::func.b64 %rd1, [fadd_acq_rel_float_global_cta_param_0];
+; SM90-NOFTZ-ALLOW-NEXT: ld.param::func.b32 %r1, [fadd_acq_rel_float_global_cta_param_1];
; SM90-NOFTZ-ALLOW-NEXT: atom.acq_rel.cta.global.add.f32 %r2, [%rd1], %r1;
-; SM90-NOFTZ-ALLOW-NEXT: st.param.b32 [func_retval0], %r2;
+; SM90-NOFTZ-ALLOW-NEXT: st.param::func.b32 [func_retval0], %r2;
; SM90-NOFTZ-ALLOW-NEXT: ret;
;
; SM90-FTZ-DISALLOW-LABEL: fadd_acq_rel_float_global_cta(
@@ -1788,10 +1788,10 @@ define float @fadd_acq_rel_float_global_cta(ptr addrspace(1) %addr, float %val)
; SM90-FTZ-DISALLOW-NEXT: .reg .b64 %rd<2>;
; SM90-FTZ-DISALLOW-EMPTY:
; SM90-FTZ-DISALLOW-NEXT: // %bb.0:
-; SM90-FTZ-DISALLOW-NEXT: ld.param.b64 %rd1, [fadd_acq_rel_float_global_cta_param_0];
-; SM90-FTZ-DISALLOW-NEXT: ld.param.b32 %r1, [fadd_acq_rel_float_global_cta_param_1];
+; SM90-FTZ-DISALLOW-NEXT: ld.param::func.b64 %rd1, [fadd_acq_rel_float_global_cta_param_0];
+; SM90-FTZ-DISALLOW-NEXT: ld.param::func.b32 %r1, [fadd_acq_rel_float_global_cta_param_1];
; SM90-FTZ-DISALLOW-NEXT: atom.acq_rel.cta.global.add.f32 %r2, [%rd1], %r1;
-; SM90-FTZ-DISALLOW-NEXT: st.param.b32 [func_retval0], %r2;
+; SM90-FTZ-DISALLOW-NEXT: st.param::func.b32 [func_retval0], %r2;
; SM90-FTZ-DISALLOW-NEXT: ret;
;
; SM90-FTZ-ALLOW-LABEL: fadd_acq_rel_float_global_cta(
@@ -1800,10 +1800,10 @@ define float @fadd_acq_rel_float_global_cta(ptr addrspace(1) %addr, float %val)
; SM90-FTZ-ALLOW-NEXT: .reg .b64 %rd<2>;
; SM90-FTZ-ALLOW-EMPTY:
; SM90-FTZ-ALLOW-NEXT: // %bb.0:
-; SM90-FTZ-ALLOW-NEXT: ld.param.b64 %rd1, [fadd_acq_rel_float_global_cta_param_0];
-; SM90-FTZ-ALLOW-NEXT: ld.param.b32 %r1, [fadd_acq_rel_float_global_cta_param_1];
+; SM90-FTZ-ALLOW-NEXT: ld.param::func.b64 %rd1, [fadd_acq_rel_float_global_cta_param_0];
+; SM90-FTZ-ALLOW-NEXT: ld.param::func.b32 %r1, [fadd_acq_rel_float_global_cta_param_1];
; SM90-FTZ-ALLOW-NEXT: atom.acq_rel.cta.global.add.f32 %r2, [%rd1], %r1;
-; SM90-FTZ-ALLOW-NEXT: st.param.b32 [func_retval0], %r2;
+; SM90-FTZ-ALLOW-NEXT: st.param::func.b32 [func_retval0], %r2;
; SM90-FTZ-ALLOW-NEXT: ret;
%retval = atomicrmw fadd ptr addrspace(1) %addr, float %val syncscope("block") acq_rel
ret float %retval
@@ -1817,8 +1817,8 @@ define float @fsub_acq_rel_float_global_cta(ptr addrspace(1) %addr, float %val)
; SM90-NOFTZ-DISALLOW-NEXT: .reg .b64 %rd<2>;
; SM90-NOFTZ-DISALLOW-EMPTY:
; SM90-NOFTZ-DISALLOW-NEXT: // %bb.0:
-; SM90-NOFTZ-DISALLOW-NEXT: ld.param.b32 %r2, [fsub_acq_rel_float_global_cta_param_1];
-; SM90-NOFTZ-DISALLOW-NEXT: ld.param.b64 %rd1, [fsub_acq_rel_float_global_cta_param_0];
+; SM90-NOFTZ-DISALLOW-NEXT: ld.param::func.b32 %r2, [fsub_acq_rel_float_global_cta_param_1];
+; SM90-NOFTZ-DISALLOW-NEXT: ld.param::func.b64 %rd1, [fsub_acq_rel_float_global_cta_param_0];
; SM90-NOFTZ-DISALLOW-NEXT: fence.release.cta;
; SM90-NOFTZ-DISALLOW-NEXT: ld.relaxed.cta.global.b32 %r4, [%rd1];
; SM90-NOFTZ-DISALLOW-NEXT: $L__BB61_1: // %atomicrmw.start
@@ -1830,7 +1830,7 @@ define float @fsub_acq_rel_float_global_cta(ptr addrspace(1) %addr, float %val)
; SM90-NOFTZ-DISALLOW-NEXT: @%p1 bra $L__BB61_1;
; SM90-NOFTZ-DISALLOW-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NOFTZ-DISALLOW-NEXT: fence.acquire.cta;
-; SM90-NOFTZ-DISALLOW-NEXT: st.param.b32 [func_retval0], %r1;
+; SM90-NOFTZ-DISALLOW-NEXT: st.param::func.b32 [func_retval0], %r1;
; SM90-NOFTZ-DISALLOW-NEXT: ret;
;
; SM90-NOFTZ-ALLOW-LABEL: fsub_acq_rel_float_global_cta(
@@ -1840,8 +1840,8 @@ define float @fsub_acq_rel_float_global_cta(ptr addrspace(1) %addr, float %val)
; SM90-NOFTZ-ALLOW-NEXT: .reg .b64 %rd<2>;
; SM90-NOFTZ-ALLOW-EMPTY:
; SM90-NOFTZ-ALLOW-NEXT: // %bb.0:
-; SM90-NOFTZ-ALLOW-NEXT: ld.param.b32 %r2, [fsub_acq_rel_float_global_cta_param_1];
-; SM90-NOFTZ-ALLOW-NEXT: ld.param.b64 %rd1, [fsub_acq_rel_float_global_cta_param_0];
+; SM90-NOFTZ-ALLOW-NEXT: ld.param::func.b32 %r2, [fsub_acq_rel_float_global_cta_param_1];
+; SM90-NOFTZ-ALLOW-NEXT: ld.param::func.b64 %rd1, [fsub_acq_rel_float_global_cta_param_0];
; SM90-NOFTZ-ALLOW-NEXT: fence.release.cta;
; SM90-NOFTZ-ALLOW-NEXT: ld.relaxed.cta.global.b32 %r4, [%rd1];
; SM90-NOFTZ-ALLOW-NEXT: $L__BB61_1: // %atomicrmw.start
@@ -1853,7 +1853,7 @@ define float @fsub_acq_rel_float_global_cta(ptr addrspace(1) %addr, float %val)
; SM90-NOFTZ-ALLOW-NEXT: @%p1 bra $L__BB61_1;
; SM90-NOFTZ-ALLOW-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NOFTZ-ALLOW-NEXT: fence.acquire.cta;
-; SM90-NOFTZ-ALLOW-NEXT: st.param.b32 [func_retval0], %r1;
+; SM90-NOFTZ-ALLOW-NEXT: st.param::func.b32 [func_retval0], %r1;
; SM90-NOFTZ-ALLOW-NEXT: ret;
;
; SM90-FTZ-DISALLOW-LABEL: fsub_acq_rel_float_global_cta(
@@ -1863,8 +1863,8 @@ define float @fsub_acq_rel_float_global_cta(ptr addrspace(1) %addr, float %val)
; SM90-FTZ-DISALLOW-NEXT: .reg .b64 %rd<2>;
; SM90-FTZ-DISALLOW-EMPTY:
; SM90-FTZ-DISALLOW-NEXT: // %bb.0:
-; SM90-FTZ-DISALLOW-NEXT: ld.param.b32 %r2, [fsub_acq_rel_float_global_cta_param_1];
-; SM90-FTZ-DISALLOW-NEXT: ld.param.b64 %rd1, [fsub_acq_rel_float_global_cta_param_0];
+; SM90-FTZ-DISALLOW-NEXT: ld.param::func.b32 %r2, [fsub_acq_rel_float_global_cta_param_1];
+; SM90-FTZ-DISALLOW-NEXT: ld.param::func.b64 %rd1, [fsub_acq_rel_float_global_cta_param_0];
; SM90-FTZ-DISALLOW-NEXT: fence.release.cta;
; SM90-FTZ-DISALLOW-NEXT: ld.relaxed.cta.global.b32 %r4, [%rd1];
; SM90-FTZ-DISALLOW-NEXT: $L__BB61_1: // %atomicrmw.start
@@ -1876,7 +1876,7 @@ define float @fsub_acq_rel_float_global_cta(ptr addrspace(1) %addr, float %val)
; SM90-FTZ-DISALLOW-NEXT: @%p1 bra $L__BB61_1;
; SM90-FTZ-DISALLOW-NEXT: // %bb.2: // %atomicrmw.end
; SM90-FTZ-DISALLOW-NEXT: fence.acquire.cta;
-; SM90-FTZ-DISALLOW-NEXT: st.param.b32 [func_retval0], %r1;
+; SM90-FTZ-DISALLOW-NEXT: st.param::func.b32 [func_retval0], %r1;
; SM90-FTZ-DISALLOW-NEXT: ret;
;
; SM90-FTZ-ALLOW-LABEL: fsub_acq_rel_float_global_cta(
@@ -1886,8 +1886,8 @@ define float @fsub_acq_rel_float_global_cta(ptr addrspace(1) %addr, float %val)
; SM90-FTZ-ALLOW-NEXT: .reg .b64 %rd<2>;
; SM90-FTZ-ALLOW-EMPTY:
; SM90-FTZ-ALLOW-NEXT: // %bb.0:
-; SM90-FTZ-ALLOW-NEXT: ld.param.b32 %r2, [fsub_acq_rel_float_global_cta_param_1];
-; SM90-FTZ-ALLOW-NEXT: ld.param.b64 %rd1, [fsub_acq_rel_float_global_cta_param_0];
+; SM90-FTZ-ALLOW-NEXT: ld.param::func.b32 %r2, [fsub_acq_rel_float_global_cta_param_1];
+; SM90-FTZ-ALLOW-NEXT: ld.param::func.b64 %rd1, [fsub_acq_rel_float_global_cta_param_0];
; SM90-FTZ-ALLOW-NEXT: fence.release.cta;
; SM90-FTZ-ALLOW-NEXT: ld.relaxed.cta.global.b32 %r4, [%rd1];
; SM90-FTZ-ALLOW-NEXT: $L__BB61_1: // %atomicrmw.start
@@ -1899,7 +1899,7 @@ define float @fsub_acq_rel_float_global_cta(ptr addrspace(1) %addr, float %val)
; SM90-FTZ-ALLOW-NEXT: @%p1 bra $L__BB61_1;
; SM90-FTZ-ALLOW-NEXT: // %bb.2: // %atomicrmw.end
; SM90-FTZ-ALLOW-NEXT: fence.acquire.cta;
-; SM90-FTZ-ALLOW-NEXT: st.param.b32 [func_retval0], %r1;
+; SM90-FTZ-ALLOW-NEXT: st.param::func.b32 [func_retval0], %r1;
; SM90-FTZ-ALLOW-NEXT: ret;
%retval = atomicrmw fsub ptr addrspace(1) %addr, float %val syncscope("block") acq_rel
ret float %retval
@@ -1913,8 +1913,8 @@ define float @fmin_acq_rel_float_global_cta(ptr addrspace(1) %addr, float %val)
; SM90-NOFTZ-DISALLOW-NEXT: .reg .b64 %rd<2>;
; SM90-NOFTZ-DISALLOW-EMPTY:
; SM90-NOFTZ-DISALLOW-NEXT: // %bb.0:
-; SM90-NOFTZ-DISALLOW-NEXT: ld.param.b32 %r2, [fmin_acq_rel_float_global_cta_param_1];
-; SM90-NOFTZ-DISALLOW-NEXT: ld.param.b64 %rd1, [fmin_acq_rel_float_global_cta_param_0];
+; SM90-NOFTZ-DISALLOW-NEXT: ld.param::func.b32 %r2, [fmin_acq_rel_float_global_cta_param_1];
+; SM90-NOFTZ-DISALLOW-NEXT: ld.param::func.b64 %rd1, [fmin_acq_rel_float_global_cta_param_0];
; SM90-NOFTZ-DISALLOW-NEXT: fence.release.cta;
; SM90-NOFTZ-DISALLOW-NEXT: ld.relaxed.cta.global.b32 %r4, [%rd1];
; SM90-NOFTZ-DISALLOW-NEXT: $L__BB62_1: // %atomicrmw.start
@@ -1926,7 +1926,7 @@ define float @fmin_acq_rel_float_global_cta(ptr addrspace(1) %addr, float %val)
; SM90-NOFTZ-DISALLOW-NEXT: @%p1 bra $L__BB62_1;
; SM90-NOFTZ-DISALLOW-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NOFTZ-DISALLOW-NEXT: fence.acquire.cta;
-; SM90-NOFTZ-DISALLOW-NEXT: st.param.b32 [func_retval0], %r1;
+; SM90-NOFTZ-DISALLOW-NEXT: st.param::func.b32 [func_retval0], %r1;
; SM90-NOFTZ-DISALLOW-NEXT: ret;
;
; SM90-NOFTZ-ALLOW-LABEL: fmin_acq_rel_float_global_cta(
@@ -1936,8 +1936,8 @@ define float @fmin_acq_rel_float_global_cta(ptr addrspace(1) %addr, float %val)
; SM90-NOFTZ-ALLOW-NEXT: .reg .b64 %rd<2>;
; SM90-NOFTZ-ALLOW-EMPTY:
; SM90-NOFTZ-ALLOW-NEXT: // %bb.0:
-; SM90-NOFTZ-ALLOW-NEXT: ld.param.b32 %r2, [fmin_acq_rel_float_global_cta_param_1];
-; SM90-NOFTZ-ALLOW-NEXT: ld.param.b64 %rd1, [fmin_acq_rel_float_global_cta_param_0];
+; SM90-NOFTZ-ALLOW-NEXT: ld.param::func.b32 %r2, [fmin_acq_rel_float_global_cta_param_1];
+; SM90-NOFTZ-ALLOW-NEXT: ld.param::func.b64 %rd1, [fmin_acq_rel_float_global_cta_param_0];
; SM90-NOFTZ-ALLOW-NEXT: fence.release.cta;
; SM90-NOFTZ-ALLOW-NEXT: ld.relaxed.cta.global.b32 %r4, [%rd1];
; SM90-NOFTZ-ALLOW-NEXT: $L__BB62_1: // %atomicrmw.start
@@ -1949,7 +1949,7 @@ define float @fmin_acq_rel_float_global_cta(ptr addrspace(1) %addr, float %val)
; SM90-NOFTZ-ALLOW-NEXT: @%p1 bra $L__BB62_1;
; SM90-NOFTZ-ALLOW-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NOFTZ-ALLOW-NEXT: fence.acquire.cta;
-; SM90-NOFTZ-ALLOW-NEXT: st.param.b32 [func_retval0], %r1;
+; SM90-NOFTZ-ALLOW-NEXT: st.param::func.b32 [func_retval0], %r1;
; SM90-NOFTZ-ALLOW-NEXT: ret;
;
; SM90-FTZ-DISALLOW-LABEL: fmin_acq_rel_float_global_cta(
@@ -1959,8 +1959,8 @@ define float @fmin_acq_rel_float_global_cta(ptr addrspace(1) %addr, float %val)
; SM90-FTZ-DISALLOW-NEXT: .reg .b64 %rd<2>;
; SM90-FTZ-DISALLOW-EMPTY:
; SM90-FTZ-DISALLOW-NEXT: // %bb.0:
-; SM90-FTZ-DISALLOW-NEXT: ld.param.b32 %r2, [fmin_acq_rel_float_global_cta_param_1];
-; SM90-FTZ-DISALLOW-NEXT: ld.param.b64 %rd1, [fmin_acq_rel_float_global_cta_param_0];
+; SM90-FTZ-DISALLOW-NEXT: ld.param::func.b32 %r2, [fmin_acq_rel_float_global_cta_param_1];
+; SM90-FTZ-DISALLOW-NEXT: ld.param::func.b64 %rd1, [fmin_acq_rel_float_global_cta_param_0];
; SM90-FTZ-DISALLOW-NEXT: fence.release.cta;
; SM90-FTZ-DISALLOW-NEXT: ld.relaxed.cta.global.b32 %r4, [%rd1];
; SM90-FTZ-DISALLOW-NEXT: $L__BB62_1: // %atomicrmw.start
@@ -1972,7 +1972,7 @@ define float @fmin_acq_rel_float_global_cta(ptr addrspace(1) %addr, float %val)
; SM90-FTZ-DISALLOW-NEXT: @%p1 bra $L__BB62_1;
; SM90-FTZ-DISALLOW-NEXT: // %bb.2: // %atomicrmw.end
; SM90-FTZ-DISALLOW-NEXT: fence.acquire.cta;
-; SM90-FTZ-DISALLOW-NEXT: st.param.b32 [func_retval0], %r1;
+; SM90-FTZ-DISALLOW-NEXT: st.param::func.b32 [func_retval0], %r1;
; SM90-FTZ-DISALLOW-NEXT: ret;
;
; SM90-FTZ-ALLOW-LABEL: fmin_acq_rel_float_global_cta(
@@ -1982,8 +1982,8 @@ define float @fmin_acq_rel_float_global_cta(ptr addrspace(1) %addr, float %val)
; SM90-FTZ-ALLOW-NEXT: .reg .b64 %rd<2>;
; SM90-FTZ-ALLOW-EMPTY:
; SM90-FTZ-ALLOW-NEXT: // %bb.0:
-; SM90-FTZ-ALLOW-NEXT: ld.param.b32 %r2, [fmin_acq_rel_float_global_cta_param_1];
-; SM90-FTZ-ALLOW-NEXT: ld.param.b64 %rd1, [fmin_acq_rel_float_global_cta_param_0];
+; SM90-FTZ-ALLOW-NEXT: ld.param::func.b32 %r2, [fmin_acq_rel_float_global_cta_param_1];
+; SM90-FTZ-ALLOW-NEXT: ld.param::func.b64 %rd1, [fmin_acq_rel_float_global_cta_param_0];
; SM90-FTZ-ALLOW-NEXT: fence.release.cta;
; SM90-FTZ-ALLOW-NEXT: ld.relaxed.cta.global.b32 %r4, [%rd1];
; SM90-FTZ-ALLOW-NEXT: $L__BB62_1: // %atomicrmw.start
@@ -1995,7 +1995,7 @@ define float @fmin_acq_rel_float_global_cta(ptr addrspace(1) %addr, float %val)
; SM90-FTZ-ALLOW-NEXT: @%p1 bra $L__BB62_1;
; SM90-FTZ-ALLOW-NEXT: // %bb.2: // %atomicrmw.end
; SM90-FTZ-ALLOW-NEXT: fence.acquire.cta;
-; SM90-FTZ-ALLOW-NEXT: st.param.b32 [func_retval0], %r1;
+; SM90-FTZ-ALLOW-NEXT: st.param::func.b32 [func_retval0], %r1;
; SM90-FTZ-ALLOW-NEXT: ret;
%retval = atomicrmw fmin ptr addrspace(1) %addr, float %val syncscope("block") acq_rel
ret float %retval
@@ -2009,8 +2009,8 @@ define float @fmax_acq_rel_float_global_cta(ptr addrspace(1) %addr, float %val)
; SM90-NOFTZ-DISALLOW-NEXT: .reg .b64 %rd<2>;
; SM90-NOFTZ-DISALLOW-EMPTY:
; SM90-NOFTZ-DISALLOW-NEXT: // %bb.0:
-; SM90-NOFTZ-DISALLOW-NEXT: ld.param.b32 %r2, [fmax_acq_rel_float_global_cta_param_1];
-; SM90-NOFTZ-DISALLOW-NEXT: ld.param.b64 %rd1, [fmax_acq_rel_float_global_cta_param_0];
+; SM90-NOFTZ-DISALLOW-NEXT: ld.param::func.b32 %r2, [fmax_acq_rel_float_global_cta_param_1];
+; SM90-NOFTZ-DISALLOW-NEXT: ld.param::func.b64 %rd1, [fmax_acq_rel_float_global_cta_param_0];
; SM90-NOFTZ-DISALLOW-NEXT: fence.release.cta;
; SM90-NOFTZ-DISALLOW-NEXT: ld.relaxed.cta.global.b32 %r4, [%rd1];
; SM90-NOFTZ-DISALLOW-NEXT: $L__BB63_1: // %atomicrmw.start
@@ -2022,7 +2022,7 @@ define float @fmax_acq_rel_float_global_cta(ptr addrspace(1) %addr, float %val)
; SM90-NOFTZ-DISALLOW-NEXT: @%p1 bra $L__BB63_1;
; SM90-NOFTZ-DISALLOW-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NOFTZ-DISALLOW-NEXT: fence.acquire.cta;
-; SM90-NOFTZ-DISALLOW-NEXT: st.param.b32 [func_retval0], %r1;
+; SM90-NOFTZ-DISALLOW-NEXT: st.param::func.b32 [func_retval0], %r1;
; SM90-NOFTZ-DISALLOW-NEXT: ret;
;
; SM90-NOFTZ-ALLOW-LABEL: fmax_acq_rel_float_global_cta(
@@ -2032,8 +2032,8 @@ define float @fmax_acq_rel_float_global_cta(ptr addrspace(1) %addr, float %val)
; SM90-NOFTZ-ALLOW-NEXT: .reg .b64 %rd<2>;
; SM90-NOFTZ-ALLOW-EMPTY:
; SM90-NOFTZ-ALLOW-NEXT: // %bb.0:
-; SM90-NOFTZ-ALLOW-NEXT: ld.param.b32 %r2, [fmax_acq_rel_float_global_cta_param_1];
-; SM90-NOFTZ-ALLOW-NEXT: ld.param.b64 %rd1, [fmax_acq_rel_float_global_cta_param_0];
+; SM90-NOFTZ-ALLOW-NEXT: ld.param::func.b32 %r2, [fmax_acq_rel_float_global_cta_param_1];
+; SM90-NOFTZ-ALLOW-NEXT: ld.param::func.b64 %rd1, [fmax_acq_rel_float_global_cta_param_0];
; SM90-NOFTZ-ALLOW-NEXT: fence.release.cta;
; SM90-NOFTZ-ALLOW-NEXT: ld.relaxed.cta.global.b32 %r4, [%rd1];
; SM90-NOFTZ-ALLOW-NEXT: $L__BB63_1: // %atomicrmw.start
@@ -2045,7 +2045,7 @@ define float @fmax_acq_rel_float_global_cta(ptr addrspace(1) %addr, float %val)
; SM90-NOFTZ-ALLOW-NEXT: @%p1 bra $L__BB63_1;
; SM90-NOFTZ-ALLOW-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NOFTZ-ALLOW-NEXT: fence.acquire.cta;
-; SM90-NOFTZ-ALLOW-NEXT: st.param.b32 [func_retval0], %r1;
+; SM90-NOFTZ-ALLOW-NEXT: st.param::func.b32 [func_retval0], %r1;
; SM90-NOFTZ-ALLOW-NEXT: ret;
;
; SM90-FTZ-DISALLOW-LABEL: fmax_acq_rel_float_global_cta(
@@ -2055,8 +2055,8 @@ define float @fmax_acq_rel_float_global_cta(ptr addrspace(1) %addr, float %val)
; SM90-FTZ-DISALLOW-NEXT: .reg .b64 %rd<2>;
; SM90-FTZ-DISALLOW-EMPTY:
; SM90-FTZ-DISALLOW-NEXT: // %bb.0:
-; SM90-FTZ-DISALLOW-NEXT: ld.param.b32 %r2, [fmax_acq_rel_float_global_cta_param_1];
-; SM90-FTZ-DISALLOW-NEXT: ld.param.b64 %rd1, [fmax_acq_rel_float_global_cta_param_0];
+; SM90-FTZ-DISALLOW-NEXT: ld.param::func.b32 %r2, [fmax_acq_rel_float_global_cta_param_1];
+; SM90-FTZ-DISALLOW-NEXT: ld.param::func.b64 %rd1, [fmax_acq_rel_float_global_cta_param_0];
; SM90-FTZ-DISALLOW-NEXT: fence.release.cta;
; SM90-FTZ-DISALLOW-NEXT: ld.relaxed.cta.global.b32 %r4, [%rd1];
; SM90-FTZ-DISALLOW-NEXT: $L__BB63_1: // %atomicrmw.start
@@ -2068,7 +2068,7 @@ define float @fmax_acq_rel_float_global_cta(ptr addrspace(1) %addr, float %val)
; SM90-FTZ-DISALLOW-NEXT: @%p1 bra $L__BB63_1;
; SM90-FTZ-DISALLOW-NEXT: // %bb.2: // %atomicrmw.end
; SM90-FTZ-DISALLOW-NEXT: fence.acquire.cta;
-; SM90-FTZ-DISALLOW-NEXT: st.param.b32 [func_retval0], %r1;
+; SM90-FTZ-DISALLOW-NEXT: st.param::func.b32 [func_retval0], %r1;
; SM90-FTZ-DISALLOW-NEXT: ret;
;
; SM90-FTZ-ALLOW-LABEL: fmax_acq_rel_float_global_cta(
@@ -2078,8 +2078,8 @@ define float @fmax_acq_rel_float_global_cta(ptr addrspace(1) %addr, float %val)
; SM90-FTZ-ALLOW-NEXT: .reg .b64 %rd<2>;
; SM90-FTZ-ALLOW-EMPTY:
; SM90-FTZ-ALLOW-NEXT: // %bb.0:
-; SM90-FTZ-ALLOW-NEXT: ld.param.b32 %r2, [fmax_acq_rel_float_global_cta_param_1];
-; SM90-FTZ-ALLOW-NEXT: ld.param.b64 %rd1, [fmax_acq_rel_float_global_cta_param_0];
+; SM90-FTZ-ALLOW-NEXT: ld.param::func.b32 %r2, [fmax_acq_rel_float_global_cta_param_1];
+; SM90-FTZ-ALLOW-NEXT: ld.param::func.b64 %rd1, [fmax_acq_rel_float_global_cta_param_0];
; SM90-FTZ-ALLOW-NEXT: fence.release.cta;
; SM90-FTZ-ALLOW-NEXT: ld.relaxed.cta.global.b32 %r4, [%rd1];
; SM90-FTZ-ALLOW-NEXT: $L__BB63_1: // %atomicrmw.start
@@ -2091,7 +2091,7 @@ define float @fmax_acq_rel_float_global_cta(ptr addrspace(1) %addr, float %val)
; SM90-FTZ-ALLOW-NEXT: @%p1 bra $L__BB63_1;
; SM90-FTZ-ALLOW-NEXT: // %bb.2: // %atomicrmw.end
; SM90-FTZ-ALLOW-NEXT: fence.acquire.cta;
-; SM90-FTZ-ALLOW-NEXT: st.param.b32 [func_retval0], %r1;
+; SM90-FTZ-ALLOW-NEXT: st.param::func.b32 [func_retval0], %r1;
; SM90-FTZ-ALLOW-NEXT: ret;
%retval = atomicrmw fmax ptr addrspace(1) %addr, float %val syncscope("block") acq_rel
ret float %retval
@@ -2105,8 +2105,8 @@ define float @fminimum_acq_rel_float_global_cta(ptr addrspace(1) %addr, float %v
; SM90-NOFTZ-DISALLOW-NEXT: .reg .b64 %rd<2>;
; SM90-NOFTZ-DISALLOW-EMPTY:
; SM90-NOFTZ-DISALLOW-NEXT: // %bb.0:
-; SM90-NOFTZ-DISALLOW-NEXT: ld.param.b32 %r2, [fminimum_acq_rel_float_global_cta_param_1];
-; SM90-NOFTZ-DISALLOW-NEXT: ld.param.b64 %rd1, [fminimum_acq_rel_float_global_cta_param_0];
+; SM90-NOFTZ-DISALLOW-NEXT: ld.param::func.b32 %r2, [fminimum_acq_rel_float_global_cta_param_1];
+; SM90-NOFTZ-DISALLOW-NEXT: ld.param::func.b64 %rd1, [fminimum_acq_rel_float_global_cta_param_0];
; SM90-NOFTZ-DISALLOW-NEXT: fence.release.cta;
; SM90-NOFTZ-DISALLOW-NEXT: ld.relaxed.cta.global.b32 %r4, [%rd1];
; SM90-NOFTZ-DISALLOW-NEXT: $L__BB64_1: // %atomicrmw.start
@@ -2118,7 +2118,7 @@ define float @fminimum_acq_rel_float_global_cta(ptr addrspace(1) %addr, float %v
; SM90-NOFTZ-DISALLOW-NEXT: @%p1 bra $L__BB64_1;
; SM90-NOFTZ-DISALLOW-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NOFTZ-DISALLOW-NEXT: fence.acquire.cta;
-; SM90-NOFTZ-DISALLOW-NEXT: st.param.b32 [func_retval0], %r1;
+; SM90-NOFTZ-DISALLOW-NEXT: st.param::func.b32 [func_retval0], %r1;
; SM90-NOFTZ-DISALLOW-NEXT: ret;
;
; SM90-NOFTZ-ALLOW-LABEL: fminimum_acq_rel_float_global_cta(
@@ -2128,8 +2128,8 @@ define float @fminimum_acq_rel_float_global_cta(ptr addrspace(1) %addr, float %v
; SM90-NOFTZ-ALLOW-NEXT: .reg .b64 %rd<2>;
; SM90-NOFTZ-ALLOW-EMPTY:
; SM90-NOFTZ-ALLOW-NEXT: // %bb.0:
-; SM90-NOFTZ-ALLOW-NEXT: ld.param.b32 %r2, [fminimum_acq_rel_float_global_cta_param_1];
-; SM90-NOFTZ-ALLOW-NEXT: ld.param.b64 %rd1, [fminimum_acq_rel_float_global_cta_param_0];
+; SM90-NOFTZ-ALLOW-NEXT: ld.param::func.b32 %r2, [fminimum_acq_rel_float_global_cta_param_1];
+; SM90-NOFTZ-ALLOW-NEXT: ld.param::func.b64 %rd1, [fminimum_acq_rel_float_global_cta_param_0];
; SM90-NOFTZ-ALLOW-NEXT: fence.release.cta;
; SM90-NOFTZ-ALLOW-NEXT: ld.relaxed.cta.global.b32 %r4, [%rd1];
; SM90-NOFTZ-ALLOW-NEXT: $L__BB64_1: // %atomicrmw.start
@@ -2141,7 +2141,7 @@ define float @fminimum_acq_rel_float_global_cta(ptr addrspace(1) %addr, float %v
; SM90-NOFTZ-ALLOW-NEXT: @%p1 bra $L__BB64_1;
; SM90-NOFTZ-ALLOW-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NOFTZ-ALLOW-NEXT: fence.acquire.cta;
-; SM90-NOFTZ-ALLOW-NEXT: st.param.b32 [func_retval0], %r1;
+; SM90-NOFTZ-ALLOW-NEXT: st.param::func.b32 [func_retval0], %r1;
; SM90-NOFTZ-ALLOW-NEXT: ret;
;
; SM90-FTZ-DISALLOW-LABEL: fminimum_acq_rel_float_global_cta(
@@ -2151,8 +2151,8 @@ define float @fminimum_acq_rel_float_global_cta(ptr addrspace(1) %addr, float %v
; SM90-FTZ-DISALLOW-NEXT: .reg .b64 %rd<2>;
; SM90-FTZ-DISALLOW-EMPTY:
; SM90-FTZ-DISALLOW-NEXT: // %bb.0:
-; SM90-FTZ-DISALLOW-NEXT: ld.param.b32 %r2, [fminimum_acq_rel_float_global_cta_param_1];
-; SM90-FTZ-DISALLOW-NEXT: ld.param.b64 %rd1, [fminimum_acq_rel_float_global_cta_param_0];
+; SM90-FTZ-DISALLOW-NEXT: ld.param::func.b32 %r2, [fminimum_acq_rel_float_global_cta_param_1];
+; SM90-FTZ-DISALLOW-NEXT: ld.param::func.b64 %rd1, [fminimum_acq_rel_float_global_cta_param_0];
; SM90-FTZ-DISALLOW-NEXT: fence.release.cta;
; SM90-FTZ-DISALLOW-NEXT: ld.relaxed.cta.global.b32 %r4, [%rd1];
; SM90-FTZ-DISALLOW-NEXT: $L__BB64_1: // %atomicrmw.start
@@ -2164,7 +2164,7 @@ define float @fminimum_acq_rel_float_global_cta(ptr addrspace(1) %addr, float %v
; SM90-FTZ-DISALLOW-NEXT: @%p1 bra $L__BB64_1;
; SM90-FTZ-DISALLOW-NEXT: // %bb.2: // %atomicrmw.end
; SM90-FTZ-DISALLOW-NEXT: fence.acquire.cta;
-; SM90-FTZ-DISALLOW-NEXT: st.param.b32 [func_retval0], %r1;
+; SM90-FTZ-DISALLOW-NEXT: st.param::func.b32 [func_retval0], %r1;
; SM90-FTZ-DISALLOW-NEXT: ret;
;
; SM90-FTZ-ALLOW-LABEL: fminimum_acq_rel_float_global_cta(
@@ -2174,8 +2174,8 @@ define float @fminimum_acq_rel_float_global_cta(ptr addrspace(1) %addr, float %v
; SM90-FTZ-ALLOW-NEXT: .reg .b64 %rd<2>;
; SM90-FTZ-ALLOW-EMPTY:
; SM90-FTZ-ALLOW-NEXT: // %bb.0:
-; SM90-FTZ-ALLOW-NEXT: ld.param.b32 %r2, [fminimum_acq_rel_float_global_cta_param_1];
-; SM90-FTZ-ALLOW-NEXT: ld.param.b64 %rd1, [fminimum_acq_rel_float_global_cta_param_0];
+; SM90-FTZ-ALLOW-NEXT: ld.param::func.b32 %r2, [fminimum_acq_rel_float_global_cta_param_1];
+; SM90-FTZ-ALLOW-NEXT: ld.param::func.b64 %rd1, [fminimum_acq_rel_float_global_cta_param_0];
; SM90-FTZ-ALLOW-NEXT: fence.release.cta;
; SM90-FTZ-ALLOW-NEXT: ld.relaxed.cta.global.b32 %r4, [%rd1];
; SM90-FTZ-ALLOW-NEXT: $L__BB64_1: // %atomicrmw.start
@@ -2187,7 +2187,7 @@ define float @fminimum_acq_rel_float_global_cta(ptr addrspace(1) %addr, float %v
; SM90-FTZ-ALLOW-NEXT: @%p1 bra $L__BB64_1;
; SM90-FTZ-ALLOW-NEXT: // %bb.2: // %atomicrmw.end
; SM90-FTZ-ALLOW-NEXT: fence.acquire.cta;
-; SM90-FTZ-ALLOW-NEXT: st.param.b32 [func_retval0], %r1;
+; SM90-FTZ-ALLOW-NEXT: st.param::func.b32 [func_retval0], %r1;
; SM90-FTZ-ALLOW-NEXT: ret;
%retval = atomicrmw fminimum ptr addrspace(1) %addr, float %val syncscope("block") acq_rel
ret float %retval
@@ -2201,8 +2201,8 @@ define float @fmaximum_acq_rel_float_global_cta(ptr addrspace(1) %addr, float %v
; SM90-NOFTZ-DISALLOW-NEXT: .reg .b64 %rd<2>;
; SM90-NOFTZ-DISALLOW-EMPTY:
; SM90-NOFTZ-DISALLOW-NEXT: // %bb.0:
-; SM90-NOFTZ-DISALLOW-NEXT: ld.param.b32 %r2, [fmaximum_acq_rel_float_global_cta_param_1];
-; SM90-NOFTZ-DISALLOW-NEXT: ld.param.b64 %rd1, [fmaximum_acq_rel_float_global_cta_param_0];
+; SM90-NOFTZ-DISALLOW-NEXT: ld.param::func.b32 %r2, [fmaximum_acq_rel_float_global_cta_param_1];
+; SM90-NOFTZ-DISALLOW-NEXT: ld.param::func.b64 %rd1, [fmaximum_acq_rel_float_global_cta_param_0];
; SM90-NOFTZ-DISALLOW-NEXT: fence.release.cta;
; SM90-NOFTZ-DISALLOW-NEXT: ld.relaxed.cta.global.b32 %r4, [%rd1];
; SM90-NOFTZ-DISALLOW-NEXT: $L__BB65_1: // %atomicrmw.start
@@ -2214,7 +2214,7 @@ define float @fmaximum_acq_rel_float_global_cta(ptr addrspace(1) %addr, float %v
; SM90-NOFTZ-DISALLOW-NEXT: @%p1 bra $L__BB65_1;
; SM90-NOFTZ-DISALLOW-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NOFTZ-DISALLOW-NEXT: fence.acquire.cta;
-; SM90-NOFTZ-DISALLOW-NEXT: st.param.b32 [func_retval0], %r1;
+; SM90-NOFTZ-DISALLOW-NEXT: st.param::func.b32 [func_retval0], %r1;
; SM90-NOFTZ-DISALLOW-NEXT: ret;
;
; SM90-NOFTZ-ALLOW-LABEL: fmaximum_acq_rel_float_global_cta(
@@ -2224,8 +2224,8 @@ define float @fmaximum_acq_rel_float_global_cta(ptr addrspace(1) %addr, float %v
; SM90-NOFTZ-ALLOW-NEXT: .reg .b64 %rd<2>;
; SM90-NOFTZ-ALLOW-EMPTY:
; SM90-NOFTZ-ALLOW-NEXT: // %bb.0:
-; SM90-NOFTZ-ALLOW-NEXT: ld.param.b32 %r2, [fmaximum_acq_rel_float_global_cta_param_1];
-; SM90-NOFTZ-ALLOW-NEXT: ld.param.b64 %rd1, [fmaximum_acq_rel_float_global_cta_param_0];
+; SM90-NOFTZ-ALLOW-NEXT: ld.param::func.b32 %r2, [fmaximum_acq_rel_float_global_cta_param_1];
+; SM90-NOFTZ-ALLOW-NEXT: ld.param::func.b64 %rd1, [fmaximum_acq_rel_float_global_cta_param_0];
; SM90-NOFTZ-ALLOW-NEXT: fence.release.cta;
; SM90-NOFTZ-ALLOW-NEXT: ld.relaxed.cta.global.b32 %r4, [%rd1];
; SM90-NOFTZ-ALLOW-NEXT: $L__BB65_1: // %atomicrmw.start
@@ -2237,7 +2237,7 @@ define float @fmaximum_acq_rel_float_global_cta(ptr addrspace(1) %addr, float %v
; SM90-NOFTZ-ALLOW-NEXT: @%p1 bra $L__BB65_1;
; SM90-NOFTZ-ALLOW-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NOFTZ-ALLOW-NEXT: fence.acquire.cta;
-; SM90-NOFTZ-ALLOW-NEXT: st.param.b32 [func_retval0], %r1;
+; SM90-NOFTZ-ALLOW-NEXT: st.param::func.b32 [func_retval0], %r1;
; SM90-NOFTZ-ALLOW-NEXT: ret;
;
; SM90-FTZ-DISALLOW-LABEL: fmaximum_acq_rel_float_global_cta(
@@ -2247,8 +2247,8 @@ define float @fmaximum_acq_rel_float_global_cta(ptr addrspace(1) %addr, float %v
; SM90-FTZ-DISALLOW-NEXT: .reg .b64 %rd<2>;
; SM90-FTZ-DISALLOW-EMPTY:
; SM90-FTZ-DISALLOW-NEXT: // %bb.0:
-; SM90-FTZ-DISALLOW-NEXT: ld.param.b32 %r2, [fmaximum_acq_rel_float_global_cta_param_1];
-; SM90-FTZ-DISALLOW-NEXT: ld.param.b64 %rd1, [fmaximum_acq_rel_float_global_cta_param_0];
+; SM90-FTZ-DISALLOW-NEXT: ld.param::func.b32 %r2, [fmaximum_acq_rel_float_global_cta_param_1];
+; SM90-FTZ-DISALLOW-NEXT: ld.param::func.b64 %rd1, [fmaximum_acq_rel_float_global_cta_param_0];
; SM90-FTZ-DISALLOW-NEXT: fence.release.cta;
; SM90-FTZ-DISALLOW-NEXT: ld.relaxed.cta.global.b32 %r4, [%rd1];
; SM90-FTZ-DISALLOW-NEXT: $L__BB65_1: // %atomicrmw.start
@@ -2260,7 +2260,7 @@ define float @fmaximum_acq_rel_float_global_cta(ptr addrspace(1) %addr, float %v
; SM90-FTZ-DISALLOW-NEXT: @%p1 bra $L__BB65_1;
; SM90-FTZ-DISALLOW-NEXT: // %bb.2: // %atomicrmw.end
; SM90-FTZ-DISALLOW-NEXT: fence.acquire.cta;
-; SM90-FTZ-DISALLOW-NEXT: st.param.b32 [func_retval0], %r1;
+; SM90-FTZ-DISALLOW-NEXT: st.param::func.b32 [func_retval0], %r1;
; SM90-FTZ-DISALLOW-NEXT: ret;
;
; SM90-FTZ-ALLOW-LABEL: fmaximum_acq_rel_float_global_cta(
@@ -2270,8 +2270,8 @@ define float @fmaximum_acq_rel_float_global_cta(ptr addrspace(1) %addr, float %v
; SM90-FTZ-ALLOW-NEXT: .reg .b64 %rd<2>;
; SM90-FTZ-ALLOW-EMPTY:
; SM90-FTZ-ALLOW-NEXT: // %bb.0:
-; SM90-FTZ-ALLOW-NEXT: ld.param.b32 %r2, [fmaximum_acq_rel_float_global_cta_param_1];
-; SM90-FTZ-ALLOW-NEXT: ld.param.b64 %rd1, [fmaximum_acq_rel_float_global_cta_param_0];
+; SM90-FTZ-ALLOW-NEXT: ld.param::func.b32 %r2, [fmaximum_acq_rel_float_global_cta_param_1];
+; SM90-FTZ-ALLOW-NEXT: ld.param::func.b64 %rd1, [fmaximum_acq_rel_float_global_cta_param_0];
; SM90-FTZ-ALLOW-NEXT: fence.release.cta;
; SM90-FTZ-ALLOW-NEXT: ld.relaxed.cta.global.b32 %r4, [%rd1];
; SM90-FTZ-ALLOW-NEXT: $L__BB65_1: // %atomicrmw.start
@@ -2283,7 +2283,7 @@ define float @fmaximum_acq_rel_float_global_cta(ptr addrspace(1) %addr, float %v
; SM90-FTZ-ALLOW-NEXT: @%p1 bra $L__BB65_1;
; SM90-FTZ-ALLOW-NEXT: // %bb.2: // %atomicrmw.end
; SM90-FTZ-ALLOW-NEXT: fence.acquire.cta;
-; SM90-FTZ-ALLOW-NEXT: st.param.b32 [func_retval0], %r1;
+; SM90-FTZ-ALLOW-NEXT: st.param::func.b32 [func_retval0], %r1;
; SM90-FTZ-ALLOW-NEXT: ret;
%retval = atomicrmw fmaximum ptr addrspace(1) %addr, float %val syncscope("block") acq_rel
ret float %retval
@@ -2295,10 +2295,10 @@ define double @fadd_acq_rel_double_global_cta(ptr addrspace(1) %addr, double %va
; SM90-NEXT: .reg .b64 %rd<4>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [fadd_acq_rel_double_global_cta_param_0];
-; SM90-NEXT: ld.param.b64 %rd2, [fadd_acq_rel_double_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd1, [fadd_acq_rel_double_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd2, [fadd_acq_rel_double_global_cta_param_1];
; SM90-NEXT: atom.acq_rel.cta.global.add.f64 %rd3, [%rd1], %rd2;
-; SM90-NEXT: st.param.b64 [func_retval0], %rd3;
+; SM90-NEXT: st.param::func.b64 [func_retval0], %rd3;
; SM90-NEXT: ret;
%retval = atomicrmw fadd ptr addrspace(1) %addr, double %val syncscope("block") acq_rel
ret double %retval
@@ -2311,8 +2311,8 @@ define double @fsub_acq_rel_double_global_cta(ptr addrspace(1) %addr, double %va
; SM90-NEXT: .reg .b64 %rd<6>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd3, [fsub_acq_rel_double_global_cta_param_1];
-; SM90-NEXT: ld.param.b64 %rd2, [fsub_acq_rel_double_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd3, [fsub_acq_rel_double_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd2, [fsub_acq_rel_double_global_cta_param_0];
; SM90-NEXT: fence.release.cta;
; SM90-NEXT: ld.relaxed.cta.global.b64 %rd5, [%rd2];
; SM90-NEXT: $L__BB67_1: // %atomicrmw.start
@@ -2324,7 +2324,7 @@ define double @fsub_acq_rel_double_global_cta(ptr addrspace(1) %addr, double %va
; SM90-NEXT: @%p1 bra $L__BB67_1;
; SM90-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NEXT: fence.acquire.cta;
-; SM90-NEXT: st.param.b64 [func_retval0], %rd1;
+; SM90-NEXT: st.param::func.b64 [func_retval0], %rd1;
; SM90-NEXT: ret;
%retval = atomicrmw fsub ptr addrspace(1) %addr, double %val syncscope("block") acq_rel
ret double %retval
@@ -2337,8 +2337,8 @@ define double @fmin_acq_rel_double_global_cta(ptr addrspace(1) %addr, double %va
; SM90-NEXT: .reg .b64 %rd<6>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd3, [fmin_acq_rel_double_global_cta_param_1];
-; SM90-NEXT: ld.param.b64 %rd2, [fmin_acq_rel_double_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd3, [fmin_acq_rel_double_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd2, [fmin_acq_rel_double_global_cta_param_0];
; SM90-NEXT: fence.release.cta;
; SM90-NEXT: ld.relaxed.cta.global.b64 %rd5, [%rd2];
; SM90-NEXT: $L__BB68_1: // %atomicrmw.start
@@ -2350,7 +2350,7 @@ define double @fmin_acq_rel_double_global_cta(ptr addrspace(1) %addr, double %va
; SM90-NEXT: @%p1 bra $L__BB68_1;
; SM90-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NEXT: fence.acquire.cta;
-; SM90-NEXT: st.param.b64 [func_retval0], %rd1;
+; SM90-NEXT: st.param::func.b64 [func_retval0], %rd1;
; SM90-NEXT: ret;
%retval = atomicrmw fmin ptr addrspace(1) %addr, double %val syncscope("block") acq_rel
ret double %retval
@@ -2363,8 +2363,8 @@ define double @fmax_acq_rel_double_global_cta(ptr addrspace(1) %addr, double %va
; SM90-NEXT: .reg .b64 %rd<6>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd3, [fmax_acq_rel_double_global_cta_param_1];
-; SM90-NEXT: ld.param.b64 %rd2, [fmax_acq_rel_double_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd3, [fmax_acq_rel_double_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd2, [fmax_acq_rel_double_global_cta_param_0];
; SM90-NEXT: fence.release.cta;
; SM90-NEXT: ld.relaxed.cta.global.b64 %rd5, [%rd2];
; SM90-NEXT: $L__BB69_1: // %atomicrmw.start
@@ -2376,7 +2376,7 @@ define double @fmax_acq_rel_double_global_cta(ptr addrspace(1) %addr, double %va
; SM90-NEXT: @%p1 bra $L__BB69_1;
; SM90-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NEXT: fence.acquire.cta;
-; SM90-NEXT: st.param.b64 [func_retval0], %rd1;
+; SM90-NEXT: st.param::func.b64 [func_retval0], %rd1;
; SM90-NEXT: ret;
%retval = atomicrmw fmax ptr addrspace(1) %addr, double %val syncscope("block") acq_rel
ret double %retval
@@ -2389,8 +2389,8 @@ define double @fminimum_acq_rel_double_global_cta(ptr addrspace(1) %addr, double
; SM90-NEXT: .reg .b64 %rd<9>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd3, [fminimum_acq_rel_double_global_cta_param_1];
-; SM90-NEXT: ld.param.b64 %rd2, [fminimum_acq_rel_double_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd3, [fminimum_acq_rel_double_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd2, [fminimum_acq_rel_double_global_cta_param_0];
; SM90-NEXT: fence.release.cta;
; SM90-NEXT: ld.relaxed.cta.global.b64 %rd8, [%rd2];
; SM90-NEXT: $L__BB70_1: // %atomicrmw.start
@@ -2408,7 +2408,7 @@ define double @fminimum_acq_rel_double_global_cta(ptr addrspace(1) %addr, double
; SM90-NEXT: @%p4 bra $L__BB70_1;
; SM90-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NEXT: fence.acquire.cta;
-; SM90-NEXT: st.param.b64 [func_retval0], %rd1;
+; SM90-NEXT: st.param::func.b64 [func_retval0], %rd1;
; SM90-NEXT: ret;
%retval = atomicrmw fminimum ptr addrspace(1) %addr, double %val syncscope("block") acq_rel
ret double %retval
@@ -2421,8 +2421,8 @@ define double @fmaximum_acq_rel_double_global_cta(ptr addrspace(1) %addr, double
; SM90-NEXT: .reg .b64 %rd<9>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd3, [fmaximum_acq_rel_double_global_cta_param_1];
-; SM90-NEXT: ld.param.b64 %rd2, [fmaximum_acq_rel_double_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd3, [fmaximum_acq_rel_double_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd2, [fmaximum_acq_rel_double_global_cta_param_0];
; SM90-NEXT: fence.release.cta;
; SM90-NEXT: ld.relaxed.cta.global.b64 %rd8, [%rd2];
; SM90-NEXT: $L__BB71_1: // %atomicrmw.start
@@ -2440,7 +2440,7 @@ define double @fmaximum_acq_rel_double_global_cta(ptr addrspace(1) %addr, double
; SM90-NEXT: @%p4 bra $L__BB71_1;
; SM90-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NEXT: fence.acquire.cta;
-; SM90-NEXT: st.param.b64 [func_retval0], %rd1;
+; SM90-NEXT: st.param::func.b64 [func_retval0], %rd1;
; SM90-NEXT: ret;
%retval = atomicrmw fmaximum ptr addrspace(1) %addr, double %val syncscope("block") acq_rel
ret double %retval
@@ -2453,10 +2453,10 @@ define half @fadd_acq_rel_half_global_cta(ptr addrspace(1) %addr, half %val) {
; SM90-NOFTZ-DISALLOW-NEXT: .reg .b64 %rd<2>;
; SM90-NOFTZ-DISALLOW-EMPTY:
; SM90-NOFTZ-DISALLOW-NEXT: // %bb.0:
-; SM90-NOFTZ-DISALLOW-NEXT: ld.param.b64 %rd1, [fadd_acq_rel_half_global_cta_param_0];
-; SM90-NOFTZ-DISALLOW-NEXT: ld.param.b16 %rs1, [fadd_acq_rel_half_global_cta_param_1];
+; SM90-NOFTZ-DISALLOW-NEXT: ld.param::func.b64 %rd1, [fadd_acq_rel_half_global_cta_param_0];
+; SM90-NOFTZ-DISALLOW-NEXT: ld.param::func.b16 %rs1, [fadd_acq_rel_half_global_cta_param_1];
; SM90-NOFTZ-DISALLOW-NEXT: atom.acq_rel.cta.global.add.noftz.f16 %rs2, [%rd1], %rs1;
-; SM90-NOFTZ-DISALLOW-NEXT: st.param.b16 [func_retval0], %rs2;
+; SM90-NOFTZ-DISALLOW-NEXT: st.param::func.b16 [func_retval0], %rs2;
; SM90-NOFTZ-DISALLOW-NEXT: ret;
;
; SM90-NOFTZ-ALLOW-LABEL: fadd_acq_rel_half_global_cta(
@@ -2465,10 +2465,10 @@ define half @fadd_acq_rel_half_global_cta(ptr addrspace(1) %addr, half %val) {
; SM90-NOFTZ-ALLOW-NEXT: .reg .b64 %rd<2>;
; SM90-NOFTZ-ALLOW-EMPTY:
; SM90-NOFTZ-ALLOW-NEXT: // %bb.0:
-; SM90-NOFTZ-ALLOW-NEXT: ld.param.b64 %rd1, [fadd_acq_rel_half_global_cta_param_0];
-; SM90-NOFTZ-ALLOW-NEXT: ld.param.b16 %rs1, [fadd_acq_rel_half_global_cta_param_1];
+; SM90-NOFTZ-ALLOW-NEXT: ld.param::func.b64 %rd1, [fadd_acq_rel_half_global_cta_param_0];
+; SM90-NOFTZ-ALLOW-NEXT: ld.param::func.b16 %rs1, [fadd_acq_rel_half_global_cta_param_1];
; SM90-NOFTZ-ALLOW-NEXT: atom.acq_rel.cta.global.add.noftz.f16 %rs2, [%rd1], %rs1;
-; SM90-NOFTZ-ALLOW-NEXT: st.param.b16 [func_retval0], %rs2;
+; SM90-NOFTZ-ALLOW-NEXT: st.param::func.b16 [func_retval0], %rs2;
; SM90-NOFTZ-ALLOW-NEXT: ret;
;
; SM90-FTZ-DISALLOW-LABEL: fadd_acq_rel_half_global_cta(
@@ -2479,8 +2479,8 @@ define half @fadd_acq_rel_half_global_cta(ptr addrspace(1) %addr, half %val) {
; SM90-FTZ-DISALLOW-NEXT: .reg .b64 %rd<3>;
; SM90-FTZ-DISALLOW-EMPTY:
; SM90-FTZ-DISALLOW-NEXT: // %bb.0:
-; SM90-FTZ-DISALLOW-NEXT: ld.param.b16 %rs1, [fadd_acq_rel_half_global_cta_param_1];
-; SM90-FTZ-DISALLOW-NEXT: ld.param.b64 %rd2, [fadd_acq_rel_half_global_cta_param_0];
+; SM90-FTZ-DISALLOW-NEXT: ld.param::func.b16 %rs1, [fadd_acq_rel_half_global_cta_param_1];
+; SM90-FTZ-DISALLOW-NEXT: ld.param::func.b64 %rd2, [fadd_acq_rel_half_global_cta_param_0];
; SM90-FTZ-DISALLOW-NEXT: fence.release.cta;
; SM90-FTZ-DISALLOW-NEXT: and.b64 %rd1, %rd2, -4;
; SM90-FTZ-DISALLOW-NEXT: cvt.u32.u64 %r4, %rd2;
@@ -2506,7 +2506,7 @@ define half @fadd_acq_rel_half_global_cta(ptr addrspace(1) %addr, half %val) {
; SM90-FTZ-DISALLOW-NEXT: // %bb.2: // %atomicrmw.end
; SM90-FTZ-DISALLOW-NEXT: shr.u32 %r13, %r3, %r1;
; SM90-FTZ-DISALLOW-NEXT: fence.acquire.cta;
-; SM90-FTZ-DISALLOW-NEXT: st.param.b16 [func_retval0], %r13;
+; SM90-FTZ-DISALLOW-NEXT: st.param::func.b16 [func_retval0], %r13;
; SM90-FTZ-DISALLOW-NEXT: ret;
;
; SM90-FTZ-ALLOW-LABEL: fadd_acq_rel_half_global_cta(
@@ -2515,10 +2515,10 @@ define half @fadd_acq_rel_half_global_cta(ptr addrspace(1) %addr, half %val) {
; SM90-FTZ-ALLOW-NEXT: .reg .b64 %rd<2>;
; SM90-FTZ-ALLOW-EMPTY:
; SM90-FTZ-ALLOW-NEXT: // %bb.0:
-; SM90-FTZ-ALLOW-NEXT: ld.param.b64 %rd1, [fadd_acq_rel_half_global_cta_param_0];
-; SM90-FTZ-ALLOW-NEXT: ld.param.b16 %rs1, [fadd_acq_rel_half_global_cta_param_1];
+; SM90-FTZ-ALLOW-NEXT: ld.param::func.b64 %rd1, [fadd_acq_rel_half_global_cta_param_0];
+; SM90-FTZ-ALLOW-NEXT: ld.param::func.b16 %rs1, [fadd_acq_rel_half_global_cta_param_1];
; SM90-FTZ-ALLOW-NEXT: atom.acq_rel.cta.global.add.noftz.f16 %rs2, [%rd1], %rs1;
-; SM90-FTZ-ALLOW-NEXT: st.param.b16 [func_retval0], %rs2;
+; SM90-FTZ-ALLOW-NEXT: st.param::func.b16 [func_retval0], %rs2;
; SM90-FTZ-ALLOW-NEXT: ret;
%retval = atomicrmw fadd ptr addrspace(1) %addr, half %val syncscope("block") acq_rel
ret half %retval
@@ -2533,8 +2533,8 @@ define half @fsub_acq_rel_half_global_cta(ptr addrspace(1) %addr, half %val) {
; SM90-NOFTZ-DISALLOW-NEXT: .reg .b64 %rd<3>;
; SM90-NOFTZ-DISALLOW-EMPTY:
; SM90-NOFTZ-DISALLOW-NEXT: // %bb.0:
-; SM90-NOFTZ-DISALLOW-NEXT: ld.param.b16 %rs1, [fsub_acq_rel_half_global_cta_param_1];
-; SM90-NOFTZ-DISALLOW-NEXT: ld.param.b64 %rd2, [fsub_acq_rel_half_global_cta_param_0];
+; SM90-NOFTZ-DISALLOW-NEXT: ld.param::func.b16 %rs1, [fsub_acq_rel_half_global_cta_param_1];
+; SM90-NOFTZ-DISALLOW-NEXT: ld.param::func.b64 %rd2, [fsub_acq_rel_half_global_cta_param_0];
; SM90-NOFTZ-DISALLOW-NEXT: fence.release.cta;
; SM90-NOFTZ-DISALLOW-NEXT: and.b64 %rd1, %rd2, -4;
; SM90-NOFTZ-DISALLOW-NEXT: cvt.u32.u64 %r4, %rd2;
@@ -2560,7 +2560,7 @@ define half @fsub_acq_rel_half_global_cta(ptr addrspace(1) %addr, half %val) {
; SM90-NOFTZ-DISALLOW-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NOFTZ-DISALLOW-NEXT: shr.u32 %r13, %r3, %r1;
; SM90-NOFTZ-DISALLOW-NEXT: fence.acquire.cta;
-; SM90-NOFTZ-DISALLOW-NEXT: st.param.b16 [func_retval0], %r13;
+; SM90-NOFTZ-DISALLOW-NEXT: st.param::func.b16 [func_retval0], %r13;
; SM90-NOFTZ-DISALLOW-NEXT: ret;
;
; SM90-NOFTZ-ALLOW-LABEL: fsub_acq_rel_half_global_cta(
@@ -2571,8 +2571,8 @@ define half @fsub_acq_rel_half_global_cta(ptr addrspace(1) %addr, half %val) {
; SM90-NOFTZ-ALLOW-NEXT: .reg .b64 %rd<3>;
; SM90-NOFTZ-ALLOW-EMPTY:
; SM90-NOFTZ-ALLOW-NEXT: // %bb.0:
-; SM90-NOFTZ-ALLOW-NEXT: ld.param.b16 %rs1, [fsub_acq_rel_half_global_cta_param_1];
-; SM90-NOFTZ-ALLOW-NEXT: ld.param.b64 %rd2, [fsub_acq_rel_half_global_cta_param_0];
+; SM90-NOFTZ-ALLOW-NEXT: ld.param::func.b16 %rs1, [fsub_acq_rel_half_global_cta_param_1];
+; SM90-NOFTZ-ALLOW-NEXT: ld.param::func.b64 %rd2, [fsub_acq_rel_half_global_cta_param_0];
; SM90-NOFTZ-ALLOW-NEXT: fence.release.cta;
; SM90-NOFTZ-ALLOW-NEXT: and.b64 %rd1, %rd2, -4;
; SM90-NOFTZ-ALLOW-NEXT: cvt.u32.u64 %r4, %rd2;
@@ -2598,7 +2598,7 @@ define half @fsub_acq_rel_half_global_cta(ptr addrspace(1) %addr, half %val) {
; SM90-NOFTZ-ALLOW-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NOFTZ-ALLOW-NEXT: shr.u32 %r13, %r3, %r1;
; SM90-NOFTZ-ALLOW-NEXT: fence.acquire.cta;
-; SM90-NOFTZ-ALLOW-NEXT: st.param.b16 [func_retval0], %r13;
+; SM90-NOFTZ-ALLOW-NEXT: st.param::func.b16 [func_retval0], %r13;
; SM90-NOFTZ-ALLOW-NEXT: ret;
;
; SM90-FTZ-DISALLOW-LABEL: fsub_acq_rel_half_global_cta(
@@ -2609,8 +2609,8 @@ define half @fsub_acq_rel_half_global_cta(ptr addrspace(1) %addr, half %val) {
; SM90-FTZ-DISALLOW-NEXT: .reg .b64 %rd<3>;
; SM90-FTZ-DISALLOW-EMPTY:
; SM90-FTZ-DISALLOW-NEXT: // %bb.0:
-; SM90-FTZ-DISALLOW-NEXT: ld.param.b16 %rs1, [fsub_acq_rel_half_global_cta_param_1];
-; SM90-FTZ-DISALLOW-NEXT: ld.param.b64 %rd2, [fsub_acq_rel_half_global_cta_param_0];
+; SM90-FTZ-DISALLOW-NEXT: ld.param::func.b16 %rs1, [fsub_acq_rel_half_global_cta_param_1];
+; SM90-FTZ-DISALLOW-NEXT: ld.param::func.b64 %rd2, [fsub_acq_rel_half_global_cta_param_0];
; SM90-FTZ-DISALLOW-NEXT: fence.release.cta;
; SM90-FTZ-DISALLOW-NEXT: and.b64 %rd1, %rd2, -4;
; SM90-FTZ-DISALLOW-NEXT: cvt.u32.u64 %r4, %rd2;
@@ -2636,7 +2636,7 @@ define half @fsub_acq_rel_half_global_cta(ptr addrspace(1) %addr, half %val) {
; SM90-FTZ-DISALLOW-NEXT: // %bb.2: // %atomicrmw.end
; SM90-FTZ-DISALLOW-NEXT: shr.u32 %r13, %r3, %r1;
; SM90-FTZ-DISALLOW-NEXT: fence.acquire.cta;
-; SM90-FTZ-DISALLOW-NEXT: st.param.b16 [func_retval0], %r13;
+; SM90-FTZ-DISALLOW-NEXT: st.param::func.b16 [func_retval0], %r13;
; SM90-FTZ-DISALLOW-NEXT: ret;
;
; SM90-FTZ-ALLOW-LABEL: fsub_acq_rel_half_global_cta(
@@ -2647,8 +2647,8 @@ define half @fsub_acq_rel_half_global_cta(ptr addrspace(1) %addr, half %val) {
; SM90-FTZ-ALLOW-NEXT: .reg .b64 %rd<3>;
; SM90-FTZ-ALLOW-EMPTY:
; SM90-FTZ-ALLOW-NEXT: // %bb.0:
-; SM90-FTZ-ALLOW-NEXT: ld.param.b16 %rs1, [fsub_acq_rel_half_global_cta_param_1];
-; SM90-FTZ-ALLOW-NEXT: ld.param.b64 %rd2, [fsub_acq_rel_half_global_cta_param_0];
+; SM90-FTZ-ALLOW-NEXT: ld.param::func.b16 %rs1, [fsub_acq_rel_half_global_cta_param_1];
+; SM90-FTZ-ALLOW-NEXT: ld.param::func.b64 %rd2, [fsub_acq_rel_half_global_cta_param_0];
; SM90-FTZ-ALLOW-NEXT: fence.release.cta;
; SM90-FTZ-ALLOW-NEXT: and.b64 %rd1, %rd2, -4;
; SM90-FTZ-ALLOW-NEXT: cvt.u32.u64 %r4, %rd2;
@@ -2674,7 +2674,7 @@ define half @fsub_acq_rel_half_global_cta(ptr addrspace(1) %addr, half %val) {
; SM90-FTZ-ALLOW-NEXT: // %bb.2: // %atomicrmw.end
; SM90-FTZ-ALLOW-NEXT: shr.u32 %r13, %r3, %r1;
; SM90-FTZ-ALLOW-NEXT: fence.acquire.cta;
-; SM90-FTZ-ALLOW-NEXT: st.param.b16 [func_retval0], %r13;
+; SM90-FTZ-ALLOW-NEXT: st.param::func.b16 [func_retval0], %r13;
; SM90-FTZ-ALLOW-NEXT: ret;
%retval = atomicrmw fsub ptr addrspace(1) %addr, half %val syncscope("block") acq_rel
ret half %retval
@@ -2689,8 +2689,8 @@ define half @fmin_acq_rel_half_global_cta(ptr addrspace(1) %addr, half %val) {
; SM90-NOFTZ-DISALLOW-NEXT: .reg .b64 %rd<3>;
; SM90-NOFTZ-DISALLOW-EMPTY:
; SM90-NOFTZ-DISALLOW-NEXT: // %bb.0:
-; SM90-NOFTZ-DISALLOW-NEXT: ld.param.b16 %rs1, [fmin_acq_rel_half_global_cta_param_1];
-; SM90-NOFTZ-DISALLOW-NEXT: ld.param.b64 %rd2, [fmin_acq_rel_half_global_cta_param_0];
+; SM90-NOFTZ-DISALLOW-NEXT: ld.param::func.b16 %rs1, [fmin_acq_rel_half_global_cta_param_1];
+; SM90-NOFTZ-DISALLOW-NEXT: ld.param::func.b64 %rd2, [fmin_acq_rel_half_global_cta_param_0];
; SM90-NOFTZ-DISALLOW-NEXT: fence.release.cta;
; SM90-NOFTZ-DISALLOW-NEXT: and.b64 %rd1, %rd2, -4;
; SM90-NOFTZ-DISALLOW-NEXT: cvt.u32.u64 %r4, %rd2;
@@ -2716,7 +2716,7 @@ define half @fmin_acq_rel_half_global_cta(ptr addrspace(1) %addr, half %val) {
; SM90-NOFTZ-DISALLOW-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NOFTZ-DISALLOW-NEXT: shr.u32 %r13, %r3, %r1;
; SM90-NOFTZ-DISALLOW-NEXT: fence.acquire.cta;
-; SM90-NOFTZ-DISALLOW-NEXT: st.param.b16 [func_retval0], %r13;
+; SM90-NOFTZ-DISALLOW-NEXT: st.param::func.b16 [func_retval0], %r13;
; SM90-NOFTZ-DISALLOW-NEXT: ret;
;
; SM90-NOFTZ-ALLOW-LABEL: fmin_acq_rel_half_global_cta(
@@ -2727,8 +2727,8 @@ define half @fmin_acq_rel_half_global_cta(ptr addrspace(1) %addr, half %val) {
; SM90-NOFTZ-ALLOW-NEXT: .reg .b64 %rd<3>;
; SM90-NOFTZ-ALLOW-EMPTY:
; SM90-NOFTZ-ALLOW-NEXT: // %bb.0:
-; SM90-NOFTZ-ALLOW-NEXT: ld.param.b16 %rs1, [fmin_acq_rel_half_global_cta_param_1];
-; SM90-NOFTZ-ALLOW-NEXT: ld.param.b64 %rd2, [fmin_acq_rel_half_global_cta_param_0];
+; SM90-NOFTZ-ALLOW-NEXT: ld.param::func.b16 %rs1, [fmin_acq_rel_half_global_cta_param_1];
+; SM90-NOFTZ-ALLOW-NEXT: ld.param::func.b64 %rd2, [fmin_acq_rel_half_global_cta_param_0];
; SM90-NOFTZ-ALLOW-NEXT: fence.release.cta;
; SM90-NOFTZ-ALLOW-NEXT: and.b64 %rd1, %rd2, -4;
; SM90-NOFTZ-ALLOW-NEXT: cvt.u32.u64 %r4, %rd2;
@@ -2754,7 +2754,7 @@ define half @fmin_acq_rel_half_global_cta(ptr addrspace(1) %addr, half %val) {
; SM90-NOFTZ-ALLOW-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NOFTZ-ALLOW-NEXT: shr.u32 %r13, %r3, %r1;
; SM90-NOFTZ-ALLOW-NEXT: fence.acquire.cta;
-; SM90-NOFTZ-ALLOW-NEXT: st.param.b16 [func_retval0], %r13;
+; SM90-NOFTZ-ALLOW-NEXT: st.param::func.b16 [func_retval0], %r13;
; SM90-NOFTZ-ALLOW-NEXT: ret;
;
; SM90-FTZ-DISALLOW-LABEL: fmin_acq_rel_half_global_cta(
@@ -2765,8 +2765,8 @@ define half @fmin_acq_rel_half_global_cta(ptr addrspace(1) %addr, half %val) {
; SM90-FTZ-DISALLOW-NEXT: .reg .b64 %rd<3>;
; SM90-FTZ-DISALLOW-EMPTY:
; SM90-FTZ-DISALLOW-NEXT: // %bb.0:
-; SM90-FTZ-DISALLOW-NEXT: ld.param.b16 %rs1, [fmin_acq_rel_half_global_cta_param_1];
-; SM90-FTZ-DISALLOW-NEXT: ld.param.b64 %rd2, [fmin_acq_rel_half_global_cta_param_0];
+; SM90-FTZ-DISALLOW-NEXT: ld.param::func.b16 %rs1, [fmin_acq_rel_half_global_cta_param_1];
+; SM90-FTZ-DISALLOW-NEXT: ld.param::func.b64 %rd2, [fmin_acq_rel_half_global_cta_param_0];
; SM90-FTZ-DISALLOW-NEXT: fence.release.cta;
; SM90-FTZ-DISALLOW-NEXT: and.b64 %rd1, %rd2, -4;
; SM90-FTZ-DISALLOW-NEXT: cvt.u32.u64 %r4, %rd2;
@@ -2792,7 +2792,7 @@ define half @fmin_acq_rel_half_global_cta(ptr addrspace(1) %addr, half %val) {
; SM90-FTZ-DISALLOW-NEXT: // %bb.2: // %atomicrmw.end
; SM90-FTZ-DISALLOW-NEXT: shr.u32 %r13, %r3, %r1;
; SM90-FTZ-DISALLOW-NEXT: fence.acquire.cta;
-; SM90-FTZ-DISALLOW-NEXT: st.param.b16 [func_retval0], %r13;
+; SM90-FTZ-DISALLOW-NEXT: st.param::func.b16 [func_retval0], %r13;
; SM90-FTZ-DISALLOW-NEXT: ret;
;
; SM90-FTZ-ALLOW-LABEL: fmin_acq_rel_half_global_cta(
@@ -2803,8 +2803,8 @@ define half @fmin_acq_rel_half_global_cta(ptr addrspace(1) %addr, half %val) {
; SM90-FTZ-ALLOW-NEXT: .reg .b64 %rd<3>;
; SM90-FTZ-ALLOW-EMPTY:
; SM90-FTZ-ALLOW-NEXT: // %bb.0:
-; SM90-FTZ-ALLOW-NEXT: ld.param.b16 %rs1, [fmin_acq_rel_half_global_cta_param_1];
-; SM90-FTZ-ALLOW-NEXT: ld.param.b64 %rd2, [fmin_acq_rel_half_global_cta_param_0];
+; SM90-FTZ-ALLOW-NEXT: ld.param::func.b16 %rs1, [fmin_acq_rel_half_global_cta_param_1];
+; SM90-FTZ-ALLOW-NEXT: ld.param::func.b64 %rd2, [fmin_acq_rel_half_global_cta_param_0];
; SM90-FTZ-ALLOW-NEXT: fence.release.cta;
; SM90-FTZ-ALLOW-NEXT: and.b64 %rd1, %rd2, -4;
; SM90-FTZ-ALLOW-NEXT: cvt.u32.u64 %r4, %rd2;
@@ -2830,7 +2830,7 @@ define half @fmin_acq_rel_half_global_cta(ptr addrspace(1) %addr, half %val) {
; SM90-FTZ-ALLOW-NEXT: // %bb.2: // %atomicrmw.end
; SM90-FTZ-ALLOW-NEXT: shr.u32 %r13, %r3, %r1;
; SM90-FTZ-ALLOW-NEXT: fence.acquire.cta;
-; SM90-FTZ-ALLOW-NEXT: st.param.b16 [func_retval0], %r13;
+; SM90-FTZ-ALLOW-NEXT: st.param::func.b16 [func_retval0], %r13;
; SM90-FTZ-ALLOW-NEXT: ret;
%retval = atomicrmw fmin ptr addrspace(1) %addr, half %val syncscope("block") acq_rel
ret half %retval
@@ -2845,8 +2845,8 @@ define half @fmax_acq_rel_half_global_cta(ptr addrspace(1) %addr, half %val) {
; SM90-NOFTZ-DISALLOW-NEXT: .reg .b64 %rd<3>;
; SM90-NOFTZ-DISALLOW-EMPTY:
; SM90-NOFTZ-DISALLOW-NEXT: // %bb.0:
-; SM90-NOFTZ-DISALLOW-NEXT: ld.param.b16 %rs1, [fmax_acq_rel_half_global_cta_param_1];
-; SM90-NOFTZ-DISALLOW-NEXT: ld.param.b64 %rd2, [fmax_acq_rel_half_global_cta_param_0];
+; SM90-NOFTZ-DISALLOW-NEXT: ld.param::func.b16 %rs1, [fmax_acq_rel_half_global_cta_param_1];
+; SM90-NOFTZ-DISALLOW-NEXT: ld.param::func.b64 %rd2, [fmax_acq_rel_half_global_cta_param_0];
; SM90-NOFTZ-DISALLOW-NEXT: fence.release.cta;
; SM90-NOFTZ-DISALLOW-NEXT: and.b64 %rd1, %rd2, -4;
; SM90-NOFTZ-DISALLOW-NEXT: cvt.u32.u64 %r4, %rd2;
@@ -2872,7 +2872,7 @@ define half @fmax_acq_rel_half_global_cta(ptr addrspace(1) %addr, half %val) {
; SM90-NOFTZ-DISALLOW-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NOFTZ-DISALLOW-NEXT: shr.u32 %r13, %r3, %r1;
; SM90-NOFTZ-DISALLOW-NEXT: fence.acquire.cta;
-; SM90-NOFTZ-DISALLOW-NEXT: st.param.b16 [func_retval0], %r13;
+; SM90-NOFTZ-DISALLOW-NEXT: st.param::func.b16 [func_retval0], %r13;
; SM90-NOFTZ-DISALLOW-NEXT: ret;
;
; SM90-NOFTZ-ALLOW-LABEL: fmax_acq_rel_half_global_cta(
@@ -2883,8 +2883,8 @@ define half @fmax_acq_rel_half_global_cta(ptr addrspace(1) %addr, half %val) {
; SM90-NOFTZ-ALLOW-NEXT: .reg .b64 %rd<3>;
; SM90-NOFTZ-ALLOW-EMPTY:
; SM90-NOFTZ-ALLOW-NEXT: // %bb.0:
-; SM90-NOFTZ-ALLOW-NEXT: ld.param.b16 %rs1, [fmax_acq_rel_half_global_cta_param_1];
-; SM90-NOFTZ-ALLOW-NEXT: ld.param.b64 %rd2, [fmax_acq_rel_half_global_cta_param_0];
+; SM90-NOFTZ-ALLOW-NEXT: ld.param::func.b16 %rs1, [fmax_acq_rel_half_global_cta_param_1];
+; SM90-NOFTZ-ALLOW-NEXT: ld.param::func.b64 %rd2, [fmax_acq_rel_half_global_cta_param_0];
; SM90-NOFTZ-ALLOW-NEXT: fence.release.cta;
; SM90-NOFTZ-ALLOW-NEXT: and.b64 %rd1, %rd2, -4;
; SM90-NOFTZ-ALLOW-NEXT: cvt.u32.u64 %r4, %rd2;
@@ -2910,7 +2910,7 @@ define half @fmax_acq_rel_half_global_cta(ptr addrspace(1) %addr, half %val) {
; SM90-NOFTZ-ALLOW-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NOFTZ-ALLOW-NEXT: shr.u32 %r13, %r3, %r1;
; SM90-NOFTZ-ALLOW-NEXT: fence.acquire.cta;
-; SM90-NOFTZ-ALLOW-NEXT: st.param.b16 [func_retval0], %r13;
+; SM90-NOFTZ-ALLOW-NEXT: st.param::func.b16 [func_retval0], %r13;
; SM90-NOFTZ-ALLOW-NEXT: ret;
;
; SM90-FTZ-DISALLOW-LABEL: fmax_acq_rel_half_global_cta(
@@ -2921,8 +2921,8 @@ define half @fmax_acq_rel_half_global_cta(ptr addrspace(1) %addr, half %val) {
; SM90-FTZ-DISALLOW-NEXT: .reg .b64 %rd<3>;
; SM90-FTZ-DISALLOW-EMPTY:
; SM90-FTZ-DISALLOW-NEXT: // %bb.0:
-; SM90-FTZ-DISALLOW-NEXT: ld.param.b16 %rs1, [fmax_acq_rel_half_global_cta_param_1];
-; SM90-FTZ-DISALLOW-NEXT: ld.param.b64 %rd2, [fmax_acq_rel_half_global_cta_param_0];
+; SM90-FTZ-DISALLOW-NEXT: ld.param::func.b16 %rs1, [fmax_acq_rel_half_global_cta_param_1];
+; SM90-FTZ-DISALLOW-NEXT: ld.param::func.b64 %rd2, [fmax_acq_rel_half_global_cta_param_0];
; SM90-FTZ-DISALLOW-NEXT: fence.release.cta;
; SM90-FTZ-DISALLOW-NEXT: and.b64 %rd1, %rd2, -4;
; SM90-FTZ-DISALLOW-NEXT: cvt.u32.u64 %r4, %rd2;
@@ -2948,7 +2948,7 @@ define half @fmax_acq_rel_half_global_cta(ptr addrspace(1) %addr, half %val) {
; SM90-FTZ-DISALLOW-NEXT: // %bb.2: // %atomicrmw.end
; SM90-FTZ-DISALLOW-NEXT: shr.u32 %r13, %r3, %r1;
; SM90-FTZ-DISALLOW-NEXT: fence.acquire.cta;
-; SM90-FTZ-DISALLOW-NEXT: st.param.b16 [func_retval0], %r13;
+; SM90-FTZ-DISALLOW-NEXT: st.param::func.b16 [func_retval0], %r13;
; SM90-FTZ-DISALLOW-NEXT: ret;
;
; SM90-FTZ-ALLOW-LABEL: fmax_acq_rel_half_global_cta(
@@ -2959,8 +2959,8 @@ define half @fmax_acq_rel_half_global_cta(ptr addrspace(1) %addr, half %val) {
; SM90-FTZ-ALLOW-NEXT: .reg .b64 %rd<3>;
; SM90-FTZ-ALLOW-EMPTY:
; SM90-FTZ-ALLOW-NEXT: // %bb.0:
-; SM90-FTZ-ALLOW-NEXT: ld.param.b16 %rs1, [fmax_acq_rel_half_global_cta_param_1];
-; SM90-FTZ-ALLOW-NEXT: ld.param.b64 %rd2, [fmax_acq_rel_half_global_cta_param_0];
+; SM90-FTZ-ALLOW-NEXT: ld.param::func.b16 %rs1, [fmax_acq_rel_half_global_cta_param_1];
+; SM90-FTZ-ALLOW-NEXT: ld.param::func.b64 %rd2, [fmax_acq_rel_half_global_cta_param_0];
; SM90-FTZ-ALLOW-NEXT: fence.release.cta;
; SM90-FTZ-ALLOW-NEXT: and.b64 %rd1, %rd2, -4;
; SM90-FTZ-ALLOW-NEXT: cvt.u32.u64 %r4, %rd2;
@@ -2986,7 +2986,7 @@ define half @fmax_acq_rel_half_global_cta(ptr addrspace(1) %addr, half %val) {
; SM90-FTZ-ALLOW-NEXT: // %bb.2: // %atomicrmw.end
; SM90-FTZ-ALLOW-NEXT: shr.u32 %r13, %r3, %r1;
; SM90-FTZ-ALLOW-NEXT: fence.acquire.cta;
-; SM90-FTZ-ALLOW-NEXT: st.param.b16 [func_retval0], %r13;
+; SM90-FTZ-ALLOW-NEXT: st.param::func.b16 [func_retval0], %r13;
; SM90-FTZ-ALLOW-NEXT: ret;
%retval = atomicrmw fmax ptr addrspace(1) %addr, half %val syncscope("block") acq_rel
ret half %retval
@@ -3001,8 +3001,8 @@ define half @fminimum_acq_rel_half_global_cta(ptr addrspace(1) %addr, half %val)
; SM90-NOFTZ-DISALLOW-NEXT: .reg .b64 %rd<3>;
; SM90-NOFTZ-DISALLOW-EMPTY:
; SM90-NOFTZ-DISALLOW-NEXT: // %bb.0:
-; SM90-NOFTZ-DISALLOW-NEXT: ld.param.b16 %rs1, [fminimum_acq_rel_half_global_cta_param_1];
-; SM90-NOFTZ-DISALLOW-NEXT: ld.param.b64 %rd2, [fminimum_acq_rel_half_global_cta_param_0];
+; SM90-NOFTZ-DISALLOW-NEXT: ld.param::func.b16 %rs1, [fminimum_acq_rel_half_global_cta_param_1];
+; SM90-NOFTZ-DISALLOW-NEXT: ld.param::func.b64 %rd2, [fminimum_acq_rel_half_global_cta_param_0];
; SM90-NOFTZ-DISALLOW-NEXT: fence.release.cta;
; SM90-NOFTZ-DISALLOW-NEXT: and.b64 %rd1, %rd2, -4;
; SM90-NOFTZ-DISALLOW-NEXT: cvt.u32.u64 %r4, %rd2;
@@ -3028,7 +3028,7 @@ define half @fminimum_acq_rel_half_global_cta(ptr addrspace(1) %addr, half %val)
; SM90-NOFTZ-DISALLOW-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NOFTZ-DISALLOW-NEXT: shr.u32 %r13, %r3, %r1;
; SM90-NOFTZ-DISALLOW-NEXT: fence.acquire.cta;
-; SM90-NOFTZ-DISALLOW-NEXT: st.param.b16 [func_retval0], %r13;
+; SM90-NOFTZ-DISALLOW-NEXT: st.param::func.b16 [func_retval0], %r13;
; SM90-NOFTZ-DISALLOW-NEXT: ret;
;
; SM90-NOFTZ-ALLOW-LABEL: fminimum_acq_rel_half_global_cta(
@@ -3039,8 +3039,8 @@ define half @fminimum_acq_rel_half_global_cta(ptr addrspace(1) %addr, half %val)
; SM90-NOFTZ-ALLOW-NEXT: .reg .b64 %rd<3>;
; SM90-NOFTZ-ALLOW-EMPTY:
; SM90-NOFTZ-ALLOW-NEXT: // %bb.0:
-; SM90-NOFTZ-ALLOW-NEXT: ld.param.b16 %rs1, [fminimum_acq_rel_half_global_cta_param_1];
-; SM90-NOFTZ-ALLOW-NEXT: ld.param.b64 %rd2, [fminimum_acq_rel_half_global_cta_param_0];
+; SM90-NOFTZ-ALLOW-NEXT: ld.param::func.b16 %rs1, [fminimum_acq_rel_half_global_cta_param_1];
+; SM90-NOFTZ-ALLOW-NEXT: ld.param::func.b64 %rd2, [fminimum_acq_rel_half_global_cta_param_0];
; SM90-NOFTZ-ALLOW-NEXT: fence.release.cta;
; SM90-NOFTZ-ALLOW-NEXT: and.b64 %rd1, %rd2, -4;
; SM90-NOFTZ-ALLOW-NEXT: cvt.u32.u64 %r4, %rd2;
@@ -3066,7 +3066,7 @@ define half @fminimum_acq_rel_half_global_cta(ptr addrspace(1) %addr, half %val)
; SM90-NOFTZ-ALLOW-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NOFTZ-ALLOW-NEXT: shr.u32 %r13, %r3, %r1;
; SM90-NOFTZ-ALLOW-NEXT: fence.acquire.cta;
-; SM90-NOFTZ-ALLOW-NEXT: st.param.b16 [func_retval0], %r13;
+; SM90-NOFTZ-ALLOW-NEXT: st.param::func.b16 [func_retval0], %r13;
; SM90-NOFTZ-ALLOW-NEXT: ret;
;
; SM90-FTZ-DISALLOW-LABEL: fminimum_acq_rel_half_global_cta(
@@ -3077,8 +3077,8 @@ define half @fminimum_acq_rel_half_global_cta(ptr addrspace(1) %addr, half %val)
; SM90-FTZ-DISALLOW-NEXT: .reg .b64 %rd<3>;
; SM90-FTZ-DISALLOW-EMPTY:
; SM90-FTZ-DISALLOW-NEXT: // %bb.0:
-; SM90-FTZ-DISALLOW-NEXT: ld.param.b16 %rs1, [fminimum_acq_rel_half_global_cta_param_1];
-; SM90-FTZ-DISALLOW-NEXT: ld.param.b64 %rd2, [fminimum_acq_rel_half_global_cta_param_0];
+; SM90-FTZ-DISALLOW-NEXT: ld.param::func.b16 %rs1, [fminimum_acq_rel_half_global_cta_param_1];
+; SM90-FTZ-DISALLOW-NEXT: ld.param::func.b64 %rd2, [fminimum_acq_rel_half_global_cta_param_0];
; SM90-FTZ-DISALLOW-NEXT: fence.release.cta;
; SM90-FTZ-DISALLOW-NEXT: and.b64 %rd1, %rd2, -4;
; SM90-FTZ-DISALLOW-NEXT: cvt.u32.u64 %r4, %rd2;
@@ -3104,7 +3104,7 @@ define half @fminimum_acq_rel_half_global_cta(ptr addrspace(1) %addr, half %val)
; SM90-FTZ-DISALLOW-NEXT: // %bb.2: // %atomicrmw.end
; SM90-FTZ-DISALLOW-NEXT: shr.u32 %r13, %r3, %r1;
; SM90-FTZ-DISALLOW-NEXT: fence.acquire.cta;
-; SM90-FTZ-DISALLOW-NEXT: st.param.b16 [func_retval0], %r13;
+; SM90-FTZ-DISALLOW-NEXT: st.param::func.b16 [func_retval0], %r13;
; SM90-FTZ-DISALLOW-NEXT: ret;
;
; SM90-FTZ-ALLOW-LABEL: fminimum_acq_rel_half_global_cta(
@@ -3115,8 +3115,8 @@ define half @fminimum_acq_rel_half_global_cta(ptr addrspace(1) %addr, half %val)
; SM90-FTZ-ALLOW-NEXT: .reg .b64 %rd<3>;
; SM90-FTZ-ALLOW-EMPTY:
; SM90-FTZ-ALLOW-NEXT: // %bb.0:
-; SM90-FTZ-ALLOW-NEXT: ld.param.b16 %rs1, [fminimum_acq_rel_half_global_cta_param_1];
-; SM90-FTZ-ALLOW-NEXT: ld.param.b64 %rd2, [fminimum_acq_rel_half_global_cta_param_0];
+; SM90-FTZ-ALLOW-NEXT: ld.param::func.b16 %rs1, [fminimum_acq_rel_half_global_cta_param_1];
+; SM90-FTZ-ALLOW-NEXT: ld.param::func.b64 %rd2, [fminimum_acq_rel_half_global_cta_param_0];
; SM90-FTZ-ALLOW-NEXT: fence.release.cta;
; SM90-FTZ-ALLOW-NEXT: and.b64 %rd1, %rd2, -4;
; SM90-FTZ-ALLOW-NEXT: cvt.u32.u64 %r4, %rd2;
@@ -3142,7 +3142,7 @@ define half @fminimum_acq_rel_half_global_cta(ptr addrspace(1) %addr, half %val)
; SM90-FTZ-ALLOW-NEXT: // %bb.2: // %atomicrmw.end
; SM90-FTZ-ALLOW-NEXT: shr.u32 %r13, %r3, %r1;
; SM90-FTZ-ALLOW-NEXT: fence.acquire.cta;
-; SM90-FTZ-ALLOW-NEXT: st.param.b16 [func_retval0], %r13;
+; SM90-FTZ-ALLOW-NEXT: st.param::func.b16 [func_retval0], %r13;
; SM90-FTZ-ALLOW-NEXT: ret;
%retval = atomicrmw fminimum ptr addrspace(1) %addr, half %val syncscope("block") acq_rel
ret half %retval
@@ -3157,8 +3157,8 @@ define half @fmaximum_acq_rel_half_global_cta(ptr addrspace(1) %addr, half %val)
; SM90-NOFTZ-DISALLOW-NEXT: .reg .b64 %rd<3>;
; SM90-NOFTZ-DISALLOW-EMPTY:
; SM90-NOFTZ-DISALLOW-NEXT: // %bb.0:
-; SM90-NOFTZ-DISALLOW-NEXT: ld.param.b16 %rs1, [fmaximum_acq_rel_half_global_cta_param_1];
-; SM90-NOFTZ-DISALLOW-NEXT: ld.param.b64 %rd2, [fmaximum_acq_rel_half_global_cta_param_0];
+; SM90-NOFTZ-DISALLOW-NEXT: ld.param::func.b16 %rs1, [fmaximum_acq_rel_half_global_cta_param_1];
+; SM90-NOFTZ-DISALLOW-NEXT: ld.param::func.b64 %rd2, [fmaximum_acq_rel_half_global_cta_param_0];
; SM90-NOFTZ-DISALLOW-NEXT: fence.release.cta;
; SM90-NOFTZ-DISALLOW-NEXT: and.b64 %rd1, %rd2, -4;
; SM90-NOFTZ-DISALLOW-NEXT: cvt.u32.u64 %r4, %rd2;
@@ -3184,7 +3184,7 @@ define half @fmaximum_acq_rel_half_global_cta(ptr addrspace(1) %addr, half %val)
; SM90-NOFTZ-DISALLOW-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NOFTZ-DISALLOW-NEXT: shr.u32 %r13, %r3, %r1;
; SM90-NOFTZ-DISALLOW-NEXT: fence.acquire.cta;
-; SM90-NOFTZ-DISALLOW-NEXT: st.param.b16 [func_retval0], %r13;
+; SM90-NOFTZ-DISALLOW-NEXT: st.param::func.b16 [func_retval0], %r13;
; SM90-NOFTZ-DISALLOW-NEXT: ret;
;
; SM90-NOFTZ-ALLOW-LABEL: fmaximum_acq_rel_half_global_cta(
@@ -3195,8 +3195,8 @@ define half @fmaximum_acq_rel_half_global_cta(ptr addrspace(1) %addr, half %val)
; SM90-NOFTZ-ALLOW-NEXT: .reg .b64 %rd<3>;
; SM90-NOFTZ-ALLOW-EMPTY:
; SM90-NOFTZ-ALLOW-NEXT: // %bb.0:
-; SM90-NOFTZ-ALLOW-NEXT: ld.param.b16 %rs1, [fmaximum_acq_rel_half_global_cta_param_1];
-; SM90-NOFTZ-ALLOW-NEXT: ld.param.b64 %rd2, [fmaximum_acq_rel_half_global_cta_param_0];
+; SM90-NOFTZ-ALLOW-NEXT: ld.param::func.b16 %rs1, [fmaximum_acq_rel_half_global_cta_param_1];
+; SM90-NOFTZ-ALLOW-NEXT: ld.param::func.b64 %rd2, [fmaximum_acq_rel_half_global_cta_param_0];
; SM90-NOFTZ-ALLOW-NEXT: fence.release.cta;
; SM90-NOFTZ-ALLOW-NEXT: and.b64 %rd1, %rd2, -4;
; SM90-NOFTZ-ALLOW-NEXT: cvt.u32.u64 %r4, %rd2;
@@ -3222,7 +3222,7 @@ define half @fmaximum_acq_rel_half_global_cta(ptr addrspace(1) %addr, half %val)
; SM90-NOFTZ-ALLOW-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NOFTZ-ALLOW-NEXT: shr.u32 %r13, %r3, %r1;
; SM90-NOFTZ-ALLOW-NEXT: fence.acquire.cta;
-; SM90-NOFTZ-ALLOW-NEXT: st.param.b16 [func_retval0], %r13;
+; SM90-NOFTZ-ALLOW-NEXT: st.param::func.b16 [func_retval0], %r13;
; SM90-NOFTZ-ALLOW-NEXT: ret;
;
; SM90-FTZ-DISALLOW-LABEL: fmaximum_acq_rel_half_global_cta(
@@ -3233,8 +3233,8 @@ define half @fmaximum_acq_rel_half_global_cta(ptr addrspace(1) %addr, half %val)
; SM90-FTZ-DISALLOW-NEXT: .reg .b64 %rd<3>;
; SM90-FTZ-DISALLOW-EMPTY:
; SM90-FTZ-DISALLOW-NEXT: // %bb.0:
-; SM90-FTZ-DISALLOW-NEXT: ld.param.b16 %rs1, [fmaximum_acq_rel_half_global_cta_param_1];
-; SM90-FTZ-DISALLOW-NEXT: ld.param.b64 %rd2, [fmaximum_acq_rel_half_global_cta_param_0];
+; SM90-FTZ-DISALLOW-NEXT: ld.param::func.b16 %rs1, [fmaximum_acq_rel_half_global_cta_param_1];
+; SM90-FTZ-DISALLOW-NEXT: ld.param::func.b64 %rd2, [fmaximum_acq_rel_half_global_cta_param_0];
; SM90-FTZ-DISALLOW-NEXT: fence.release.cta;
; SM90-FTZ-DISALLOW-NEXT: and.b64 %rd1, %rd2, -4;
; SM90-FTZ-DISALLOW-NEXT: cvt.u32.u64 %r4, %rd2;
@@ -3260,7 +3260,7 @@ define half @fmaximum_acq_rel_half_global_cta(ptr addrspace(1) %addr, half %val)
; SM90-FTZ-DISALLOW-NEXT: // %bb.2: // %atomicrmw.end
; SM90-FTZ-DISALLOW-NEXT: shr.u32 %r13, %r3, %r1;
; SM90-FTZ-DISALLOW-NEXT: fence.acquire.cta;
-; SM90-FTZ-DISALLOW-NEXT: st.param.b16 [func_retval0], %r13;
+; SM90-FTZ-DISALLOW-NEXT: st.param::func.b16 [func_retval0], %r13;
; SM90-FTZ-DISALLOW-NEXT: ret;
;
; SM90-FTZ-ALLOW-LABEL: fmaximum_acq_rel_half_global_cta(
@@ -3271,8 +3271,8 @@ define half @fmaximum_acq_rel_half_global_cta(ptr addrspace(1) %addr, half %val)
; SM90-FTZ-ALLOW-NEXT: .reg .b64 %rd<3>;
; SM90-FTZ-ALLOW-EMPTY:
; SM90-FTZ-ALLOW-NEXT: // %bb.0:
-; SM90-FTZ-ALLOW-NEXT: ld.param.b16 %rs1, [fmaximum_acq_rel_half_global_cta_param_1];
-; SM90-FTZ-ALLOW-NEXT: ld.param.b64 %rd2, [fmaximum_acq_rel_half_global_cta_param_0];
+; SM90-FTZ-ALLOW-NEXT: ld.param::func.b16 %rs1, [fmaximum_acq_rel_half_global_cta_param_1];
+; SM90-FTZ-ALLOW-NEXT: ld.param::func.b64 %rd2, [fmaximum_acq_rel_half_global_cta_param_0];
; SM90-FTZ-ALLOW-NEXT: fence.release.cta;
; SM90-FTZ-ALLOW-NEXT: and.b64 %rd1, %rd2, -4;
; SM90-FTZ-ALLOW-NEXT: cvt.u32.u64 %r4, %rd2;
@@ -3298,7 +3298,7 @@ define half @fmaximum_acq_rel_half_global_cta(ptr addrspace(1) %addr, half %val)
; SM90-FTZ-ALLOW-NEXT: // %bb.2: // %atomicrmw.end
; SM90-FTZ-ALLOW-NEXT: shr.u32 %r13, %r3, %r1;
; SM90-FTZ-ALLOW-NEXT: fence.acquire.cta;
-; SM90-FTZ-ALLOW-NEXT: st.param.b16 [func_retval0], %r13;
+; SM90-FTZ-ALLOW-NEXT: st.param::func.b16 [func_retval0], %r13;
; SM90-FTZ-ALLOW-NEXT: ret;
%retval = atomicrmw fmaximum ptr addrspace(1) %addr, half %val syncscope("block") acq_rel
ret half %retval
@@ -3311,10 +3311,10 @@ define bfloat @fadd_acq_rel_bfloat_global_cta(ptr addrspace(1) %addr, bfloat %va
; SM90-NEXT: .reg .b64 %rd<2>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [fadd_acq_rel_bfloat_global_cta_param_0];
-; SM90-NEXT: ld.param.b16 %rs1, [fadd_acq_rel_bfloat_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd1, [fadd_acq_rel_bfloat_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b16 %rs1, [fadd_acq_rel_bfloat_global_cta_param_1];
; SM90-NEXT: atom.acq_rel.cta.global.add.noftz.bf16 %rs2, [%rd1], %rs1;
-; SM90-NEXT: st.param.b16 [func_retval0], %rs2;
+; SM90-NEXT: st.param::func.b16 [func_retval0], %rs2;
; SM90-NEXT: ret;
%retval = atomicrmw fadd ptr addrspace(1) %addr, bfloat %val syncscope("block") acq_rel
ret bfloat %retval
@@ -3329,8 +3329,8 @@ define bfloat @fsub_acq_rel_bfloat_global_cta(ptr addrspace(1) %addr, bfloat %va
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b16 %rs1, [fsub_acq_rel_bfloat_global_cta_param_1];
-; SM90-NEXT: ld.param.b64 %rd2, [fsub_acq_rel_bfloat_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b16 %rs1, [fsub_acq_rel_bfloat_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd2, [fsub_acq_rel_bfloat_global_cta_param_0];
; SM90-NEXT: fence.release.cta;
; SM90-NEXT: and.b64 %rd1, %rd2, -4;
; SM90-NEXT: cvt.u32.u64 %r4, %rd2;
@@ -3356,7 +3356,7 @@ define bfloat @fsub_acq_rel_bfloat_global_cta(ptr addrspace(1) %addr, bfloat %va
; SM90-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NEXT: shr.u32 %r13, %r3, %r1;
; SM90-NEXT: fence.acquire.cta;
-; SM90-NEXT: st.param.b16 [func_retval0], %r13;
+; SM90-NEXT: st.param::func.b16 [func_retval0], %r13;
; SM90-NEXT: ret;
%retval = atomicrmw fsub ptr addrspace(1) %addr, bfloat %val syncscope("block") acq_rel
ret bfloat %retval
@@ -3371,8 +3371,8 @@ define bfloat @fmin_acq_rel_bfloat_global_cta(ptr addrspace(1) %addr, bfloat %va
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b16 %rs1, [fmin_acq_rel_bfloat_global_cta_param_1];
-; SM90-NEXT: ld.param.b64 %rd2, [fmin_acq_rel_bfloat_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b16 %rs1, [fmin_acq_rel_bfloat_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd2, [fmin_acq_rel_bfloat_global_cta_param_0];
; SM90-NEXT: fence.release.cta;
; SM90-NEXT: and.b64 %rd1, %rd2, -4;
; SM90-NEXT: cvt.u32.u64 %r4, %rd2;
@@ -3398,7 +3398,7 @@ define bfloat @fmin_acq_rel_bfloat_global_cta(ptr addrspace(1) %addr, bfloat %va
; SM90-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NEXT: shr.u32 %r13, %r3, %r1;
; SM90-NEXT: fence.acquire.cta;
-; SM90-NEXT: st.param.b16 [func_retval0], %r13;
+; SM90-NEXT: st.param::func.b16 [func_retval0], %r13;
; SM90-NEXT: ret;
%retval = atomicrmw fmin ptr addrspace(1) %addr, bfloat %val syncscope("block") acq_rel
ret bfloat %retval
@@ -3413,8 +3413,8 @@ define bfloat @fmax_acq_rel_bfloat_global_cta(ptr addrspace(1) %addr, bfloat %va
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b16 %rs1, [fmax_acq_rel_bfloat_global_cta_param_1];
-; SM90-NEXT: ld.param.b64 %rd2, [fmax_acq_rel_bfloat_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b16 %rs1, [fmax_acq_rel_bfloat_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd2, [fmax_acq_rel_bfloat_global_cta_param_0];
; SM90-NEXT: fence.release.cta;
; SM90-NEXT: and.b64 %rd1, %rd2, -4;
; SM90-NEXT: cvt.u32.u64 %r4, %rd2;
@@ -3440,7 +3440,7 @@ define bfloat @fmax_acq_rel_bfloat_global_cta(ptr addrspace(1) %addr, bfloat %va
; SM90-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NEXT: shr.u32 %r13, %r3, %r1;
; SM90-NEXT: fence.acquire.cta;
-; SM90-NEXT: st.param.b16 [func_retval0], %r13;
+; SM90-NEXT: st.param::func.b16 [func_retval0], %r13;
; SM90-NEXT: ret;
%retval = atomicrmw fmax ptr addrspace(1) %addr, bfloat %val syncscope("block") acq_rel
ret bfloat %retval
@@ -3455,8 +3455,8 @@ define bfloat @fminimum_acq_rel_bfloat_global_cta(ptr addrspace(1) %addr, bfloat
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b16 %rs1, [fminimum_acq_rel_bfloat_global_cta_param_1];
-; SM90-NEXT: ld.param.b64 %rd2, [fminimum_acq_rel_bfloat_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b16 %rs1, [fminimum_acq_rel_bfloat_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd2, [fminimum_acq_rel_bfloat_global_cta_param_0];
; SM90-NEXT: fence.release.cta;
; SM90-NEXT: and.b64 %rd1, %rd2, -4;
; SM90-NEXT: cvt.u32.u64 %r4, %rd2;
@@ -3482,7 +3482,7 @@ define bfloat @fminimum_acq_rel_bfloat_global_cta(ptr addrspace(1) %addr, bfloat
; SM90-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NEXT: shr.u32 %r13, %r3, %r1;
; SM90-NEXT: fence.acquire.cta;
-; SM90-NEXT: st.param.b16 [func_retval0], %r13;
+; SM90-NEXT: st.param::func.b16 [func_retval0], %r13;
; SM90-NEXT: ret;
%retval = atomicrmw fminimum ptr addrspace(1) %addr, bfloat %val syncscope("block") acq_rel
ret bfloat %retval
@@ -3497,8 +3497,8 @@ define bfloat @fmaximum_acq_rel_bfloat_global_cta(ptr addrspace(1) %addr, bfloat
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b16 %rs1, [fmaximum_acq_rel_bfloat_global_cta_param_1];
-; SM90-NEXT: ld.param.b64 %rd2, [fmaximum_acq_rel_bfloat_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b16 %rs1, [fmaximum_acq_rel_bfloat_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd2, [fmaximum_acq_rel_bfloat_global_cta_param_0];
; SM90-NEXT: fence.release.cta;
; SM90-NEXT: and.b64 %rd1, %rd2, -4;
; SM90-NEXT: cvt.u32.u64 %r4, %rd2;
@@ -3524,7 +3524,7 @@ define bfloat @fmaximum_acq_rel_bfloat_global_cta(ptr addrspace(1) %addr, bfloat
; SM90-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NEXT: shr.u32 %r13, %r3, %r1;
; SM90-NEXT: fence.acquire.cta;
-; SM90-NEXT: st.param.b16 [func_retval0], %r13;
+; SM90-NEXT: st.param::func.b16 [func_retval0], %r13;
; SM90-NEXT: ret;
%retval = atomicrmw fmaximum ptr addrspace(1) %addr, bfloat %val syncscope("block") acq_rel
ret bfloat %retval
@@ -3538,9 +3538,9 @@ define i8 @add_monotonic_i8_global_cta(ptr addrspace(1) %addr, i8 %val) {
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd2, [add_monotonic_i8_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd2, [add_monotonic_i8_global_cta_param_0];
; SM90-NEXT: and.b64 %rd1, %rd2, -4;
-; SM90-NEXT: ld.param.b8 %r6, [add_monotonic_i8_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b8 %r6, [add_monotonic_i8_global_cta_param_1];
; SM90-NEXT: cvt.u32.u64 %r7, %rd2;
; SM90-NEXT: and.b32 %r8, %r7, 3;
; SM90-NEXT: shl.b32 %r1, %r8, 3;
@@ -3561,7 +3561,7 @@ define i8 @add_monotonic_i8_global_cta(ptr addrspace(1) %addr, i8 %val) {
; SM90-NEXT: @%p1 bra $L__BB84_1;
; SM90-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NEXT: shr.u32 %r14, %r5, %r1;
-; SM90-NEXT: st.param.b32 [func_retval0], %r14;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r14;
; SM90-NEXT: ret;
%retval = atomicrmw add ptr addrspace(1) %addr, i8 %val syncscope("block") monotonic
ret i8 %retval
@@ -3575,9 +3575,9 @@ define i8 @add_acquire_i8_global_cta(ptr addrspace(1) %addr, i8 %val) {
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd2, [add_acquire_i8_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd2, [add_acquire_i8_global_cta_param_0];
; SM90-NEXT: and.b64 %rd1, %rd2, -4;
-; SM90-NEXT: ld.param.b8 %r6, [add_acquire_i8_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b8 %r6, [add_acquire_i8_global_cta_param_1];
; SM90-NEXT: cvt.u32.u64 %r7, %rd2;
; SM90-NEXT: and.b32 %r8, %r7, 3;
; SM90-NEXT: shl.b32 %r1, %r8, 3;
@@ -3599,7 +3599,7 @@ define i8 @add_acquire_i8_global_cta(ptr addrspace(1) %addr, i8 %val) {
; SM90-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NEXT: shr.u32 %r14, %r5, %r1;
; SM90-NEXT: fence.acquire.cta;
-; SM90-NEXT: st.param.b32 [func_retval0], %r14;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r14;
; SM90-NEXT: ret;
%retval = atomicrmw add ptr addrspace(1) %addr, i8 %val syncscope("block") acquire
ret i8 %retval
@@ -3613,9 +3613,9 @@ define i8 @add_release_i8_global_cta(ptr addrspace(1) %addr, i8 %val) {
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd2, [add_release_i8_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd2, [add_release_i8_global_cta_param_0];
; SM90-NEXT: fence.release.cta;
-; SM90-NEXT: ld.param.b8 %r6, [add_release_i8_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b8 %r6, [add_release_i8_global_cta_param_1];
; SM90-NEXT: and.b64 %rd1, %rd2, -4;
; SM90-NEXT: cvt.u32.u64 %r7, %rd2;
; SM90-NEXT: and.b32 %r8, %r7, 3;
@@ -3637,7 +3637,7 @@ define i8 @add_release_i8_global_cta(ptr addrspace(1) %addr, i8 %val) {
; SM90-NEXT: @%p1 bra $L__BB86_1;
; SM90-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NEXT: shr.u32 %r14, %r5, %r1;
-; SM90-NEXT: st.param.b32 [func_retval0], %r14;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r14;
; SM90-NEXT: ret;
%retval = atomicrmw add ptr addrspace(1) %addr, i8 %val syncscope("block") release
ret i8 %retval
@@ -3651,9 +3651,9 @@ define i8 @add_seq_cst_i8_global_cta(ptr addrspace(1) %addr, i8 %val) {
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd2, [add_seq_cst_i8_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd2, [add_seq_cst_i8_global_cta_param_0];
; SM90-NEXT: fence.sc.cta;
-; SM90-NEXT: ld.param.b8 %r6, [add_seq_cst_i8_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b8 %r6, [add_seq_cst_i8_global_cta_param_1];
; SM90-NEXT: and.b64 %rd1, %rd2, -4;
; SM90-NEXT: cvt.u32.u64 %r7, %rd2;
; SM90-NEXT: and.b32 %r8, %r7, 3;
@@ -3676,7 +3676,7 @@ define i8 @add_seq_cst_i8_global_cta(ptr addrspace(1) %addr, i8 %val) {
; SM90-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NEXT: shr.u32 %r14, %r5, %r1;
; SM90-NEXT: fence.acquire.cta;
-; SM90-NEXT: st.param.b32 [func_retval0], %r14;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r14;
; SM90-NEXT: ret;
%retval = atomicrmw add ptr addrspace(1) %addr, i8 %val syncscope("block") seq_cst
ret i8 %retval
@@ -3689,10 +3689,10 @@ define i32 @add_monotonic_i32_global_cta(ptr addrspace(1) %addr, i32 %val) {
; SM90-NEXT: .reg .b64 %rd<2>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [add_monotonic_i32_global_cta_param_0];
-; SM90-NEXT: ld.param.b32 %r1, [add_monotonic_i32_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd1, [add_monotonic_i32_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b32 %r1, [add_monotonic_i32_global_cta_param_1];
; SM90-NEXT: atom.relaxed.cta.global.add.u32 %r2, [%rd1], %r1;
-; SM90-NEXT: st.param.b32 [func_retval0], %r2;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r2;
; SM90-NEXT: ret;
%retval = atomicrmw add ptr addrspace(1) %addr, i32 %val syncscope("block") monotonic
ret i32 %retval
@@ -3705,10 +3705,10 @@ define i32 @add_acquire_i32_global_cta(ptr addrspace(1) %addr, i32 %val) {
; SM90-NEXT: .reg .b64 %rd<2>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [add_acquire_i32_global_cta_param_0];
-; SM90-NEXT: ld.param.b32 %r1, [add_acquire_i32_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd1, [add_acquire_i32_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b32 %r1, [add_acquire_i32_global_cta_param_1];
; SM90-NEXT: atom.acquire.cta.global.add.u32 %r2, [%rd1], %r1;
-; SM90-NEXT: st.param.b32 [func_retval0], %r2;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r2;
; SM90-NEXT: ret;
%retval = atomicrmw add ptr addrspace(1) %addr, i32 %val syncscope("block") acquire
ret i32 %retval
@@ -3721,10 +3721,10 @@ define i32 @add_release_i32_global_cta(ptr addrspace(1) %addr, i32 %val) {
; SM90-NEXT: .reg .b64 %rd<2>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [add_release_i32_global_cta_param_0];
-; SM90-NEXT: ld.param.b32 %r1, [add_release_i32_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd1, [add_release_i32_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b32 %r1, [add_release_i32_global_cta_param_1];
; SM90-NEXT: atom.release.cta.global.add.u32 %r2, [%rd1], %r1;
-; SM90-NEXT: st.param.b32 [func_retval0], %r2;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r2;
; SM90-NEXT: ret;
%retval = atomicrmw add ptr addrspace(1) %addr, i32 %val syncscope("block") release
ret i32 %retval
@@ -3737,11 +3737,11 @@ define i32 @add_seq_cst_i32_global_cta(ptr addrspace(1) %addr, i32 %val) {
; SM90-NEXT: .reg .b64 %rd<2>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [add_seq_cst_i32_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd1, [add_seq_cst_i32_global_cta_param_0];
; SM90-NEXT: fence.sc.cta;
-; SM90-NEXT: ld.param.b32 %r1, [add_seq_cst_i32_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b32 %r1, [add_seq_cst_i32_global_cta_param_1];
; SM90-NEXT: atom.acquire.cta.global.add.u32 %r2, [%rd1], %r1;
-; SM90-NEXT: st.param.b32 [func_retval0], %r2;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r2;
; SM90-NEXT: ret;
%retval = atomicrmw add ptr addrspace(1) %addr, i32 %val syncscope("block") seq_cst
ret i32 %retval
@@ -3755,9 +3755,9 @@ define i8 @nand_monotonic_i8_global_cta(ptr addrspace(1) %addr, i8 %val) {
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd2, [nand_monotonic_i8_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd2, [nand_monotonic_i8_global_cta_param_0];
; SM90-NEXT: and.b64 %rd1, %rd2, -4;
-; SM90-NEXT: ld.param.b8 %r6, [nand_monotonic_i8_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b8 %r6, [nand_monotonic_i8_global_cta_param_1];
; SM90-NEXT: cvt.u32.u64 %r7, %rd2;
; SM90-NEXT: and.b32 %r8, %r7, 3;
; SM90-NEXT: shl.b32 %r1, %r8, 3;
@@ -3779,7 +3779,7 @@ define i8 @nand_monotonic_i8_global_cta(ptr addrspace(1) %addr, i8 %val) {
; SM90-NEXT: @%p1 bra $L__BB92_1;
; SM90-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NEXT: shr.u32 %r15, %r5, %r1;
-; SM90-NEXT: st.param.b32 [func_retval0], %r15;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r15;
; SM90-NEXT: ret;
%retval = atomicrmw nand ptr addrspace(1) %addr, i8 %val syncscope("block") monotonic
ret i8 %retval
@@ -3793,9 +3793,9 @@ define i8 @nand_acquire_i8_global_cta(ptr addrspace(1) %addr, i8 %val) {
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd2, [nand_acquire_i8_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd2, [nand_acquire_i8_global_cta_param_0];
; SM90-NEXT: and.b64 %rd1, %rd2, -4;
-; SM90-NEXT: ld.param.b8 %r6, [nand_acquire_i8_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b8 %r6, [nand_acquire_i8_global_cta_param_1];
; SM90-NEXT: cvt.u32.u64 %r7, %rd2;
; SM90-NEXT: and.b32 %r8, %r7, 3;
; SM90-NEXT: shl.b32 %r1, %r8, 3;
@@ -3818,7 +3818,7 @@ define i8 @nand_acquire_i8_global_cta(ptr addrspace(1) %addr, i8 %val) {
; SM90-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NEXT: shr.u32 %r15, %r5, %r1;
; SM90-NEXT: fence.acquire.cta;
-; SM90-NEXT: st.param.b32 [func_retval0], %r15;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r15;
; SM90-NEXT: ret;
%retval = atomicrmw nand ptr addrspace(1) %addr, i8 %val syncscope("block") acquire
ret i8 %retval
@@ -3832,9 +3832,9 @@ define i8 @nand_release_i8_global_cta(ptr addrspace(1) %addr, i8 %val) {
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd2, [nand_release_i8_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd2, [nand_release_i8_global_cta_param_0];
; SM90-NEXT: fence.release.cta;
-; SM90-NEXT: ld.param.b8 %r6, [nand_release_i8_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b8 %r6, [nand_release_i8_global_cta_param_1];
; SM90-NEXT: and.b64 %rd1, %rd2, -4;
; SM90-NEXT: cvt.u32.u64 %r7, %rd2;
; SM90-NEXT: and.b32 %r8, %r7, 3;
@@ -3857,7 +3857,7 @@ define i8 @nand_release_i8_global_cta(ptr addrspace(1) %addr, i8 %val) {
; SM90-NEXT: @%p1 bra $L__BB94_1;
; SM90-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NEXT: shr.u32 %r15, %r5, %r1;
-; SM90-NEXT: st.param.b32 [func_retval0], %r15;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r15;
; SM90-NEXT: ret;
%retval = atomicrmw nand ptr addrspace(1) %addr, i8 %val syncscope("block") release
ret i8 %retval
@@ -3871,9 +3871,9 @@ define i8 @nand_seq_cst_i8_global_cta(ptr addrspace(1) %addr, i8 %val) {
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd2, [nand_seq_cst_i8_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd2, [nand_seq_cst_i8_global_cta_param_0];
; SM90-NEXT: fence.sc.cta;
-; SM90-NEXT: ld.param.b8 %r6, [nand_seq_cst_i8_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b8 %r6, [nand_seq_cst_i8_global_cta_param_1];
; SM90-NEXT: and.b64 %rd1, %rd2, -4;
; SM90-NEXT: cvt.u32.u64 %r7, %rd2;
; SM90-NEXT: and.b32 %r8, %r7, 3;
@@ -3897,7 +3897,7 @@ define i8 @nand_seq_cst_i8_global_cta(ptr addrspace(1) %addr, i8 %val) {
; SM90-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NEXT: shr.u32 %r15, %r5, %r1;
; SM90-NEXT: fence.acquire.cta;
-; SM90-NEXT: st.param.b32 [func_retval0], %r15;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r15;
; SM90-NEXT: ret;
%retval = atomicrmw nand ptr addrspace(1) %addr, i8 %val syncscope("block") seq_cst
ret i8 %retval
@@ -3911,8 +3911,8 @@ define i32 @nand_monotonic_i32_global_cta(ptr addrspace(1) %addr, i32 %val) {
; SM90-NEXT: .reg .b64 %rd<2>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b32 %r2, [nand_monotonic_i32_global_cta_param_1];
-; SM90-NEXT: ld.param.b64 %rd1, [nand_monotonic_i32_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b32 %r2, [nand_monotonic_i32_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd1, [nand_monotonic_i32_global_cta_param_0];
; SM90-NEXT: ld.relaxed.cta.global.b32 %r5, [%rd1];
; SM90-NEXT: $L__BB96_1: // %atomicrmw.start
; SM90-NEXT: // =>This Inner Loop Header: Depth=1
@@ -3923,7 +3923,7 @@ define i32 @nand_monotonic_i32_global_cta(ptr addrspace(1) %addr, i32 %val) {
; SM90-NEXT: mov.b32 %r5, %r1;
; SM90-NEXT: @%p1 bra $L__BB96_1;
; SM90-NEXT: // %bb.2: // %atomicrmw.end
-; SM90-NEXT: st.param.b32 [func_retval0], %r1;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r1;
; SM90-NEXT: ret;
%retval = atomicrmw nand ptr addrspace(1) %addr, i32 %val syncscope("block") monotonic
ret i32 %retval
@@ -3937,8 +3937,8 @@ define i32 @nand_acquire_i32_global_cta(ptr addrspace(1) %addr, i32 %val) {
; SM90-NEXT: .reg .b64 %rd<2>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b32 %r2, [nand_acquire_i32_global_cta_param_1];
-; SM90-NEXT: ld.param.b64 %rd1, [nand_acquire_i32_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b32 %r2, [nand_acquire_i32_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd1, [nand_acquire_i32_global_cta_param_0];
; SM90-NEXT: ld.relaxed.cta.global.b32 %r5, [%rd1];
; SM90-NEXT: $L__BB97_1: // %atomicrmw.start
; SM90-NEXT: // =>This Inner Loop Header: Depth=1
@@ -3950,7 +3950,7 @@ define i32 @nand_acquire_i32_global_cta(ptr addrspace(1) %addr, i32 %val) {
; SM90-NEXT: @%p1 bra $L__BB97_1;
; SM90-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NEXT: fence.acquire.cta;
-; SM90-NEXT: st.param.b32 [func_retval0], %r1;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r1;
; SM90-NEXT: ret;
%retval = atomicrmw nand ptr addrspace(1) %addr, i32 %val syncscope("block") acquire
ret i32 %retval
@@ -3964,8 +3964,8 @@ define i32 @nand_release_i32_global_cta(ptr addrspace(1) %addr, i32 %val) {
; SM90-NEXT: .reg .b64 %rd<2>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b32 %r2, [nand_release_i32_global_cta_param_1];
-; SM90-NEXT: ld.param.b64 %rd1, [nand_release_i32_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b32 %r2, [nand_release_i32_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd1, [nand_release_i32_global_cta_param_0];
; SM90-NEXT: fence.release.cta;
; SM90-NEXT: ld.relaxed.cta.global.b32 %r5, [%rd1];
; SM90-NEXT: $L__BB98_1: // %atomicrmw.start
@@ -3977,7 +3977,7 @@ define i32 @nand_release_i32_global_cta(ptr addrspace(1) %addr, i32 %val) {
; SM90-NEXT: mov.b32 %r5, %r1;
; SM90-NEXT: @%p1 bra $L__BB98_1;
; SM90-NEXT: // %bb.2: // %atomicrmw.end
-; SM90-NEXT: st.param.b32 [func_retval0], %r1;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r1;
; SM90-NEXT: ret;
%retval = atomicrmw nand ptr addrspace(1) %addr, i32 %val syncscope("block") release
ret i32 %retval
@@ -3991,8 +3991,8 @@ define i32 @nand_seq_cst_i32_global_cta(ptr addrspace(1) %addr, i32 %val) {
; SM90-NEXT: .reg .b64 %rd<2>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b32 %r2, [nand_seq_cst_i32_global_cta_param_1];
-; SM90-NEXT: ld.param.b64 %rd1, [nand_seq_cst_i32_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b32 %r2, [nand_seq_cst_i32_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd1, [nand_seq_cst_i32_global_cta_param_0];
; SM90-NEXT: fence.sc.cta;
; SM90-NEXT: ld.relaxed.cta.global.b32 %r5, [%rd1];
; SM90-NEXT: $L__BB99_1: // %atomicrmw.start
@@ -4005,7 +4005,7 @@ define i32 @nand_seq_cst_i32_global_cta(ptr addrspace(1) %addr, i32 %val) {
; SM90-NEXT: @%p1 bra $L__BB99_1;
; SM90-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NEXT: fence.acquire.cta;
-; SM90-NEXT: st.param.b32 [func_retval0], %r1;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r1;
; SM90-NEXT: ret;
%retval = atomicrmw nand ptr addrspace(1) %addr, i32 %val syncscope("block") seq_cst
ret i32 %retval
@@ -4018,10 +4018,10 @@ define i32 @add_acq_rel_i32_global_sys(ptr addrspace(1) %addr, i32 %val) {
; SM90-NEXT: .reg .b64 %rd<2>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [add_acq_rel_i32_global_sys_param_0];
-; SM90-NEXT: ld.param.b32 %r1, [add_acq_rel_i32_global_sys_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd1, [add_acq_rel_i32_global_sys_param_0];
+; SM90-NEXT: ld.param::func.b32 %r1, [add_acq_rel_i32_global_sys_param_1];
; SM90-NEXT: atom.acq_rel.sys.global.add.u32 %r2, [%rd1], %r1;
-; SM90-NEXT: st.param.b32 [func_retval0], %r2;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r2;
; SM90-NEXT: ret;
%retval = atomicrmw add ptr addrspace(1) %addr, i32 %val syncscope("") acq_rel
ret i32 %retval
@@ -4033,10 +4033,10 @@ define i64 @add_acq_rel_i64_global_sys(ptr addrspace(1) %addr, i64 %val) {
; SM90-NEXT: .reg .b64 %rd<4>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [add_acq_rel_i64_global_sys_param_0];
-; SM90-NEXT: ld.param.b64 %rd2, [add_acq_rel_i64_global_sys_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd1, [add_acq_rel_i64_global_sys_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd2, [add_acq_rel_i64_global_sys_param_1];
; SM90-NEXT: atom.acq_rel.sys.global.add.u64 %rd3, [%rd1], %rd2;
-; SM90-NEXT: st.param.b64 [func_retval0], %rd3;
+; SM90-NEXT: st.param::func.b64 [func_retval0], %rd3;
; SM90-NEXT: ret;
%retval = atomicrmw add ptr addrspace(1) %addr, i64 %val syncscope("") acq_rel
ret i64 %retval
@@ -4049,10 +4049,10 @@ define i32 @min_acq_rel_i32_global_sys(ptr addrspace(1) %addr, i32 %val) {
; SM90-NEXT: .reg .b64 %rd<2>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [min_acq_rel_i32_global_sys_param_0];
-; SM90-NEXT: ld.param.b32 %r1, [min_acq_rel_i32_global_sys_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd1, [min_acq_rel_i32_global_sys_param_0];
+; SM90-NEXT: ld.param::func.b32 %r1, [min_acq_rel_i32_global_sys_param_1];
; SM90-NEXT: atom.acq_rel.sys.global.min.s32 %r2, [%rd1], %r1;
-; SM90-NEXT: st.param.b32 [func_retval0], %r2;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r2;
; SM90-NEXT: ret;
%retval = atomicrmw min ptr addrspace(1) %addr, i32 %val syncscope("") acq_rel
ret i32 %retval
@@ -4065,10 +4065,10 @@ define i32 @umax_acq_rel_i32_global_sys(ptr addrspace(1) %addr, i32 %val) {
; SM90-NEXT: .reg .b64 %rd<2>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [umax_acq_rel_i32_global_sys_param_0];
-; SM90-NEXT: ld.param.b32 %r1, [umax_acq_rel_i32_global_sys_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd1, [umax_acq_rel_i32_global_sys_param_0];
+; SM90-NEXT: ld.param::func.b32 %r1, [umax_acq_rel_i32_global_sys_param_1];
; SM90-NEXT: atom.acq_rel.sys.global.max.u32 %r2, [%rd1], %r1;
-; SM90-NEXT: st.param.b32 [func_retval0], %r2;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r2;
; SM90-NEXT: ret;
%retval = atomicrmw umax ptr addrspace(1) %addr, i32 %val syncscope("") acq_rel
ret i32 %retval
@@ -4082,8 +4082,8 @@ define i32 @nand_acq_rel_i32_global_sys(ptr addrspace(1) %addr, i32 %val) {
; SM90-NEXT: .reg .b64 %rd<2>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b32 %r2, [nand_acq_rel_i32_global_sys_param_1];
-; SM90-NEXT: ld.param.b64 %rd1, [nand_acq_rel_i32_global_sys_param_0];
+; SM90-NEXT: ld.param::func.b32 %r2, [nand_acq_rel_i32_global_sys_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd1, [nand_acq_rel_i32_global_sys_param_0];
; SM90-NEXT: fence.release.sys;
; SM90-NEXT: ld.relaxed.sys.global.b32 %r5, [%rd1];
; SM90-NEXT: $L__BB104_1: // %atomicrmw.start
@@ -4096,7 +4096,7 @@ define i32 @nand_acq_rel_i32_global_sys(ptr addrspace(1) %addr, i32 %val) {
; SM90-NEXT: @%p1 bra $L__BB104_1;
; SM90-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NEXT: fence.acquire.sys;
-; SM90-NEXT: st.param.b32 [func_retval0], %r1;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r1;
; SM90-NEXT: ret;
%retval = atomicrmw nand ptr addrspace(1) %addr, i32 %val syncscope("") acq_rel
ret i32 %retval
@@ -4109,8 +4109,8 @@ define i64 @nand_acq_rel_i64_global_sys(ptr addrspace(1) %addr, i64 %val) {
; SM90-NEXT: .reg .b64 %rd<7>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd3, [nand_acq_rel_i64_global_sys_param_1];
-; SM90-NEXT: ld.param.b64 %rd2, [nand_acq_rel_i64_global_sys_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd3, [nand_acq_rel_i64_global_sys_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd2, [nand_acq_rel_i64_global_sys_param_0];
; SM90-NEXT: fence.release.sys;
; SM90-NEXT: ld.relaxed.sys.global.b64 %rd6, [%rd2];
; SM90-NEXT: $L__BB105_1: // %atomicrmw.start
@@ -4123,7 +4123,7 @@ define i64 @nand_acq_rel_i64_global_sys(ptr addrspace(1) %addr, i64 %val) {
; SM90-NEXT: @%p1 bra $L__BB105_1;
; SM90-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NEXT: fence.acquire.sys;
-; SM90-NEXT: st.param.b64 [func_retval0], %rd1;
+; SM90-NEXT: st.param::func.b64 [func_retval0], %rd1;
; SM90-NEXT: ret;
%retval = atomicrmw nand ptr addrspace(1) %addr, i64 %val syncscope("") acq_rel
ret i64 %retval
@@ -4137,8 +4137,8 @@ define float @fadd_acq_rel_float_global_sys(ptr addrspace(1) %addr, float %val)
; SM90-NOFTZ-DISALLOW-NEXT: .reg .b64 %rd<2>;
; SM90-NOFTZ-DISALLOW-EMPTY:
; SM90-NOFTZ-DISALLOW-NEXT: // %bb.0:
-; SM90-NOFTZ-DISALLOW-NEXT: ld.param.b32 %r2, [fadd_acq_rel_float_global_sys_param_1];
-; SM90-NOFTZ-DISALLOW-NEXT: ld.param.b64 %rd1, [fadd_acq_rel_float_global_sys_param_0];
+; SM90-NOFTZ-DISALLOW-NEXT: ld.param::func.b32 %r2, [fadd_acq_rel_float_global_sys_param_1];
+; SM90-NOFTZ-DISALLOW-NEXT: ld.param::func.b64 %rd1, [fadd_acq_rel_float_global_sys_param_0];
; SM90-NOFTZ-DISALLOW-NEXT: fence.release.sys;
; SM90-NOFTZ-DISALLOW-NEXT: ld.relaxed.sys.global.b32 %r4, [%rd1];
; SM90-NOFTZ-DISALLOW-NEXT: $L__BB106_1: // %atomicrmw.start
@@ -4150,7 +4150,7 @@ define float @fadd_acq_rel_float_global_sys(ptr addrspace(1) %addr, float %val)
; SM90-NOFTZ-DISALLOW-NEXT: @%p1 bra $L__BB106_1;
; SM90-NOFTZ-DISALLOW-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NOFTZ-DISALLOW-NEXT: fence.acquire.sys;
-; SM90-NOFTZ-DISALLOW-NEXT: st.param.b32 [func_retval0], %r1;
+; SM90-NOFTZ-DISALLOW-NEXT: st.param::func.b32 [func_retval0], %r1;
; SM90-NOFTZ-DISALLOW-NEXT: ret;
;
; SM90-NOFTZ-ALLOW-LABEL: fadd_acq_rel_float_global_sys(
@@ -4159,10 +4159,10 @@ define float @fadd_acq_rel_float_global_sys(ptr addrspace(1) %addr, float %val)
; SM90-NOFTZ-ALLOW-NEXT: .reg .b64 %rd<2>;
; SM90-NOFTZ-ALLOW-EMPTY:
; SM90-NOFTZ-ALLOW-NEXT: // %bb.0:
-; SM90-NOFTZ-ALLOW-NEXT: ld.param.b64 %rd1, [fadd_acq_rel_float_global_sys_param_0];
-; SM90-NOFTZ-ALLOW-NEXT: ld.param.b32 %r1, [fadd_acq_rel_float_global_sys_param_1];
+; SM90-NOFTZ-ALLOW-NEXT: ld.param::func.b64 %rd1, [fadd_acq_rel_float_global_sys_param_0];
+; SM90-NOFTZ-ALLOW-NEXT: ld.param::func.b32 %r1, [fadd_acq_rel_float_global_sys_param_1];
; SM90-NOFTZ-ALLOW-NEXT: atom.acq_rel.sys.global.add.f32 %r2, [%rd1], %r1;
-; SM90-NOFTZ-ALLOW-NEXT: st.param.b32 [func_retval0], %r2;
+; SM90-NOFTZ-ALLOW-NEXT: st.param::func.b32 [func_retval0], %r2;
; SM90-NOFTZ-ALLOW-NEXT: ret;
;
; SM90-FTZ-DISALLOW-LABEL: fadd_acq_rel_float_global_sys(
@@ -4171,10 +4171,10 @@ define float @fadd_acq_rel_float_global_sys(ptr addrspace(1) %addr, float %val)
; SM90-FTZ-DISALLOW-NEXT: .reg .b64 %rd<2>;
; SM90-FTZ-DISALLOW-EMPTY:
; SM90-FTZ-DISALLOW-NEXT: // %bb.0:
-; SM90-FTZ-DISALLOW-NEXT: ld.param.b64 %rd1, [fadd_acq_rel_float_global_sys_param_0];
-; SM90-FTZ-DISALLOW-NEXT: ld.param.b32 %r1, [fadd_acq_rel_float_global_sys_param_1];
+; SM90-FTZ-DISALLOW-NEXT: ld.param::func.b64 %rd1, [fadd_acq_rel_float_global_sys_param_0];
+; SM90-FTZ-DISALLOW-NEXT: ld.param::func.b32 %r1, [fadd_acq_rel_float_global_sys_param_1];
; SM90-FTZ-DISALLOW-NEXT: atom.acq_rel.sys.global.add.f32 %r2, [%rd1], %r1;
-; SM90-FTZ-DISALLOW-NEXT: st.param.b32 [func_retval0], %r2;
+; SM90-FTZ-DISALLOW-NEXT: st.param::func.b32 [func_retval0], %r2;
; SM90-FTZ-DISALLOW-NEXT: ret;
;
; SM90-FTZ-ALLOW-LABEL: fadd_acq_rel_float_global_sys(
@@ -4183,10 +4183,10 @@ define float @fadd_acq_rel_float_global_sys(ptr addrspace(1) %addr, float %val)
; SM90-FTZ-ALLOW-NEXT: .reg .b64 %rd<2>;
; SM90-FTZ-ALLOW-EMPTY:
; SM90-FTZ-ALLOW-NEXT: // %bb.0:
-; SM90-FTZ-ALLOW-NEXT: ld.param.b64 %rd1, [fadd_acq_rel_float_global_sys_param_0];
-; SM90-FTZ-ALLOW-NEXT: ld.param.b32 %r1, [fadd_acq_rel_float_global_sys_param_1];
+; SM90-FTZ-ALLOW-NEXT: ld.param::func.b64 %rd1, [fadd_acq_rel_float_global_sys_param_0];
+; SM90-FTZ-ALLOW-NEXT: ld.param::func.b32 %r1, [fadd_acq_rel_float_global_sys_param_1];
; SM90-FTZ-ALLOW-NEXT: atom.acq_rel.sys.global.add.f32 %r2, [%rd1], %r1;
-; SM90-FTZ-ALLOW-NEXT: st.param.b32 [func_retval0], %r2;
+; SM90-FTZ-ALLOW-NEXT: st.param::func.b32 [func_retval0], %r2;
; SM90-FTZ-ALLOW-NEXT: ret;
%retval = atomicrmw fadd ptr addrspace(1) %addr, float %val syncscope("") acq_rel
ret float %retval
@@ -4198,10 +4198,10 @@ define double @fadd_acq_rel_double_global_sys(ptr addrspace(1) %addr, double %va
; SM90-NEXT: .reg .b64 %rd<4>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [fadd_acq_rel_double_global_sys_param_0];
-; SM90-NEXT: ld.param.b64 %rd2, [fadd_acq_rel_double_global_sys_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd1, [fadd_acq_rel_double_global_sys_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd2, [fadd_acq_rel_double_global_sys_param_1];
; SM90-NEXT: atom.acq_rel.sys.global.add.f64 %rd3, [%rd1], %rd2;
-; SM90-NEXT: st.param.b64 [func_retval0], %rd3;
+; SM90-NEXT: st.param::func.b64 [func_retval0], %rd3;
; SM90-NEXT: ret;
%retval = atomicrmw fadd ptr addrspace(1) %addr, double %val syncscope("") acq_rel
ret double %retval
@@ -4214,10 +4214,10 @@ define i32 @add_acq_rel_i32_global_cluster(ptr addrspace(1) %addr, i32 %val) {
; SM90-NEXT: .reg .b64 %rd<2>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [add_acq_rel_i32_global_cluster_param_0];
-; SM90-NEXT: ld.param.b32 %r1, [add_acq_rel_i32_global_cluster_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd1, [add_acq_rel_i32_global_cluster_param_0];
+; SM90-NEXT: ld.param::func.b32 %r1, [add_acq_rel_i32_global_cluster_param_1];
; SM90-NEXT: atom.acq_rel.cluster.global.add.u32 %r2, [%rd1], %r1;
-; SM90-NEXT: st.param.b32 [func_retval0], %r2;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r2;
; SM90-NEXT: ret;
%retval = atomicrmw add ptr addrspace(1) %addr, i32 %val syncscope("cluster") acq_rel
ret i32 %retval
@@ -4229,10 +4229,10 @@ define i64 @add_acq_rel_i64_global_cluster(ptr addrspace(1) %addr, i64 %val) {
; SM90-NEXT: .reg .b64 %rd<4>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [add_acq_rel_i64_global_cluster_param_0];
-; SM90-NEXT: ld.param.b64 %rd2, [add_acq_rel_i64_global_cluster_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd1, [add_acq_rel_i64_global_cluster_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd2, [add_acq_rel_i64_global_cluster_param_1];
; SM90-NEXT: atom.acq_rel.cluster.global.add.u64 %rd3, [%rd1], %rd2;
-; SM90-NEXT: st.param.b64 [func_retval0], %rd3;
+; SM90-NEXT: st.param::func.b64 [func_retval0], %rd3;
; SM90-NEXT: ret;
%retval = atomicrmw add ptr addrspace(1) %addr, i64 %val syncscope("cluster") acq_rel
ret i64 %retval
@@ -4245,10 +4245,10 @@ define i32 @min_acq_rel_i32_global_cluster(ptr addrspace(1) %addr, i32 %val) {
; SM90-NEXT: .reg .b64 %rd<2>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [min_acq_rel_i32_global_cluster_param_0];
-; SM90-NEXT: ld.param.b32 %r1, [min_acq_rel_i32_global_cluster_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd1, [min_acq_rel_i32_global_cluster_param_0];
+; SM90-NEXT: ld.param::func.b32 %r1, [min_acq_rel_i32_global_cluster_param_1];
; SM90-NEXT: atom.acq_rel.cluster.global.min.s32 %r2, [%rd1], %r1;
-; SM90-NEXT: st.param.b32 [func_retval0], %r2;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r2;
; SM90-NEXT: ret;
%retval = atomicrmw min ptr addrspace(1) %addr, i32 %val syncscope("cluster") acq_rel
ret i32 %retval
@@ -4261,10 +4261,10 @@ define i32 @umax_acq_rel_i32_global_cluster(ptr addrspace(1) %addr, i32 %val) {
; SM90-NEXT: .reg .b64 %rd<2>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [umax_acq_rel_i32_global_cluster_param_0];
-; SM90-NEXT: ld.param.b32 %r1, [umax_acq_rel_i32_global_cluster_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd1, [umax_acq_rel_i32_global_cluster_param_0];
+; SM90-NEXT: ld.param::func.b32 %r1, [umax_acq_rel_i32_global_cluster_param_1];
; SM90-NEXT: atom.acq_rel.cluster.global.max.u32 %r2, [%rd1], %r1;
-; SM90-NEXT: st.param.b32 [func_retval0], %r2;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r2;
; SM90-NEXT: ret;
%retval = atomicrmw umax ptr addrspace(1) %addr, i32 %val syncscope("cluster") acq_rel
ret i32 %retval
@@ -4278,8 +4278,8 @@ define i32 @nand_acq_rel_i32_global_cluster(ptr addrspace(1) %addr, i32 %val) {
; SM90-NEXT: .reg .b64 %rd<2>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b32 %r2, [nand_acq_rel_i32_global_cluster_param_1];
-; SM90-NEXT: ld.param.b64 %rd1, [nand_acq_rel_i32_global_cluster_param_0];
+; SM90-NEXT: ld.param::func.b32 %r2, [nand_acq_rel_i32_global_cluster_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd1, [nand_acq_rel_i32_global_cluster_param_0];
; SM90-NEXT: fence.release.cluster;
; SM90-NEXT: ld.relaxed.cluster.global.b32 %r5, [%rd1];
; SM90-NEXT: $L__BB112_1: // %atomicrmw.start
@@ -4292,7 +4292,7 @@ define i32 @nand_acq_rel_i32_global_cluster(ptr addrspace(1) %addr, i32 %val) {
; SM90-NEXT: @%p1 bra $L__BB112_1;
; SM90-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NEXT: fence.acquire.cluster;
-; SM90-NEXT: st.param.b32 [func_retval0], %r1;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r1;
; SM90-NEXT: ret;
%retval = atomicrmw nand ptr addrspace(1) %addr, i32 %val syncscope("cluster") acq_rel
ret i32 %retval
@@ -4305,8 +4305,8 @@ define i64 @nand_acq_rel_i64_global_cluster(ptr addrspace(1) %addr, i64 %val) {
; SM90-NEXT: .reg .b64 %rd<7>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd3, [nand_acq_rel_i64_global_cluster_param_1];
-; SM90-NEXT: ld.param.b64 %rd2, [nand_acq_rel_i64_global_cluster_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd3, [nand_acq_rel_i64_global_cluster_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd2, [nand_acq_rel_i64_global_cluster_param_0];
; SM90-NEXT: fence.release.cluster;
; SM90-NEXT: ld.relaxed.cluster.global.b64 %rd6, [%rd2];
; SM90-NEXT: $L__BB113_1: // %atomicrmw.start
@@ -4319,7 +4319,7 @@ define i64 @nand_acq_rel_i64_global_cluster(ptr addrspace(1) %addr, i64 %val) {
; SM90-NEXT: @%p1 bra $L__BB113_1;
; SM90-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NEXT: fence.acquire.cluster;
-; SM90-NEXT: st.param.b64 [func_retval0], %rd1;
+; SM90-NEXT: st.param::func.b64 [func_retval0], %rd1;
; SM90-NEXT: ret;
%retval = atomicrmw nand ptr addrspace(1) %addr, i64 %val syncscope("cluster") acq_rel
ret i64 %retval
@@ -4333,8 +4333,8 @@ define float @fadd_acq_rel_float_global_cluster(ptr addrspace(1) %addr, float %v
; SM90-NOFTZ-DISALLOW-NEXT: .reg .b64 %rd<2>;
; SM90-NOFTZ-DISALLOW-EMPTY:
; SM90-NOFTZ-DISALLOW-NEXT: // %bb.0:
-; SM90-NOFTZ-DISALLOW-NEXT: ld.param.b32 %r2, [fadd_acq_rel_float_global_cluster_param_1];
-; SM90-NOFTZ-DISALLOW-NEXT: ld.param.b64 %rd1, [fadd_acq_rel_float_global_cluster_param_0];
+; SM90-NOFTZ-DISALLOW-NEXT: ld.param::func.b32 %r2, [fadd_acq_rel_float_global_cluster_param_1];
+; SM90-NOFTZ-DISALLOW-NEXT: ld.param::func.b64 %rd1, [fadd_acq_rel_float_global_cluster_param_0];
; SM90-NOFTZ-DISALLOW-NEXT: fence.release.cluster;
; SM90-NOFTZ-DISALLOW-NEXT: ld.relaxed.cluster.global.b32 %r4, [%rd1];
; SM90-NOFTZ-DISALLOW-NEXT: $L__BB114_1: // %atomicrmw.start
@@ -4346,7 +4346,7 @@ define float @fadd_acq_rel_float_global_cluster(ptr addrspace(1) %addr, float %v
; SM90-NOFTZ-DISALLOW-NEXT: @%p1 bra $L__BB114_1;
; SM90-NOFTZ-DISALLOW-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NOFTZ-DISALLOW-NEXT: fence.acquire.cluster;
-; SM90-NOFTZ-DISALLOW-NEXT: st.param.b32 [func_retval0], %r1;
+; SM90-NOFTZ-DISALLOW-NEXT: st.param::func.b32 [func_retval0], %r1;
; SM90-NOFTZ-DISALLOW-NEXT: ret;
;
; SM90-NOFTZ-ALLOW-LABEL: fadd_acq_rel_float_global_cluster(
@@ -4355,10 +4355,10 @@ define float @fadd_acq_rel_float_global_cluster(ptr addrspace(1) %addr, float %v
; SM90-NOFTZ-ALLOW-NEXT: .reg .b64 %rd<2>;
; SM90-NOFTZ-ALLOW-EMPTY:
; SM90-NOFTZ-ALLOW-NEXT: // %bb.0:
-; SM90-NOFTZ-ALLOW-NEXT: ld.param.b64 %rd1, [fadd_acq_rel_float_global_cluster_param_0];
-; SM90-NOFTZ-ALLOW-NEXT: ld.param.b32 %r1, [fadd_acq_rel_float_global_cluster_param_1];
+; SM90-NOFTZ-ALLOW-NEXT: ld.param::func.b64 %rd1, [fadd_acq_rel_float_global_cluster_param_0];
+; SM90-NOFTZ-ALLOW-NEXT: ld.param::func.b32 %r1, [fadd_acq_rel_float_global_cluster_param_1];
; SM90-NOFTZ-ALLOW-NEXT: atom.acq_rel.cluster.global.add.f32 %r2, [%rd1], %r1;
-; SM90-NOFTZ-ALLOW-NEXT: st.param.b32 [func_retval0], %r2;
+; SM90-NOFTZ-ALLOW-NEXT: st.param::func.b32 [func_retval0], %r2;
; SM90-NOFTZ-ALLOW-NEXT: ret;
;
; SM90-FTZ-DISALLOW-LABEL: fadd_acq_rel_float_global_cluster(
@@ -4367,10 +4367,10 @@ define float @fadd_acq_rel_float_global_cluster(ptr addrspace(1) %addr, float %v
; SM90-FTZ-DISALLOW-NEXT: .reg .b64 %rd<2>;
; SM90-FTZ-DISALLOW-EMPTY:
; SM90-FTZ-DISALLOW-NEXT: // %bb.0:
-; SM90-FTZ-DISALLOW-NEXT: ld.param.b64 %rd1, [fadd_acq_rel_float_global_cluster_param_0];
-; SM90-FTZ-DISALLOW-NEXT: ld.param.b32 %r1, [fadd_acq_rel_float_global_cluster_param_1];
+; SM90-FTZ-DISALLOW-NEXT: ld.param::func.b64 %rd1, [fadd_acq_rel_float_global_cluster_param_0];
+; SM90-FTZ-DISALLOW-NEXT: ld.param::func.b32 %r1, [fadd_acq_rel_float_global_cluster_param_1];
; SM90-FTZ-DISALLOW-NEXT: atom.acq_rel.cluster.global.add.f32 %r2, [%rd1], %r1;
-; SM90-FTZ-DISALLOW-NEXT: st.param.b32 [func_retval0], %r2;
+; SM90-FTZ-DISALLOW-NEXT: st.param::func.b32 [func_retval0], %r2;
; SM90-FTZ-DISALLOW-NEXT: ret;
;
; SM90-FTZ-ALLOW-LABEL: fadd_acq_rel_float_global_cluster(
@@ -4379,10 +4379,10 @@ define float @fadd_acq_rel_float_global_cluster(ptr addrspace(1) %addr, float %v
; SM90-FTZ-ALLOW-NEXT: .reg .b64 %rd<2>;
; SM90-FTZ-ALLOW-EMPTY:
; SM90-FTZ-ALLOW-NEXT: // %bb.0:
-; SM90-FTZ-ALLOW-NEXT: ld.param.b64 %rd1, [fadd_acq_rel_float_global_cluster_param_0];
-; SM90-FTZ-ALLOW-NEXT: ld.param.b32 %r1, [fadd_acq_rel_float_global_cluster_param_1];
+; SM90-FTZ-ALLOW-NEXT: ld.param::func.b64 %rd1, [fadd_acq_rel_float_global_cluster_param_0];
+; SM90-FTZ-ALLOW-NEXT: ld.param::func.b32 %r1, [fadd_acq_rel_float_global_cluster_param_1];
; SM90-FTZ-ALLOW-NEXT: atom.acq_rel.cluster.global.add.f32 %r2, [%rd1], %r1;
-; SM90-FTZ-ALLOW-NEXT: st.param.b32 [func_retval0], %r2;
+; SM90-FTZ-ALLOW-NEXT: st.param::func.b32 [func_retval0], %r2;
; SM90-FTZ-ALLOW-NEXT: ret;
%retval = atomicrmw fadd ptr addrspace(1) %addr, float %val syncscope("cluster") acq_rel
ret float %retval
@@ -4394,10 +4394,10 @@ define double @fadd_acq_rel_double_global_cluster(ptr addrspace(1) %addr, double
; SM90-NEXT: .reg .b64 %rd<4>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [fadd_acq_rel_double_global_cluster_param_0];
-; SM90-NEXT: ld.param.b64 %rd2, [fadd_acq_rel_double_global_cluster_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd1, [fadd_acq_rel_double_global_cluster_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd2, [fadd_acq_rel_double_global_cluster_param_1];
; SM90-NEXT: atom.acq_rel.cluster.global.add.f64 %rd3, [%rd1], %rd2;
-; SM90-NEXT: st.param.b64 [func_retval0], %rd3;
+; SM90-NEXT: st.param::func.b64 [func_retval0], %rd3;
; SM90-NEXT: ret;
%retval = atomicrmw fadd ptr addrspace(1) %addr, double %val syncscope("cluster") acq_rel
ret double %retval
@@ -4410,10 +4410,10 @@ define i32 @add_acq_rel_i32_global_gpu(ptr addrspace(1) %addr, i32 %val) {
; SM90-NEXT: .reg .b64 %rd<2>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [add_acq_rel_i32_global_gpu_param_0];
-; SM90-NEXT: ld.param.b32 %r1, [add_acq_rel_i32_global_gpu_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd1, [add_acq_rel_i32_global_gpu_param_0];
+; SM90-NEXT: ld.param::func.b32 %r1, [add_acq_rel_i32_global_gpu_param_1];
; SM90-NEXT: atom.acq_rel.gpu.global.add.u32 %r2, [%rd1], %r1;
-; SM90-NEXT: st.param.b32 [func_retval0], %r2;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r2;
; SM90-NEXT: ret;
%retval = atomicrmw add ptr addrspace(1) %addr, i32 %val syncscope("device") acq_rel
ret i32 %retval
@@ -4425,10 +4425,10 @@ define i64 @add_acq_rel_i64_global_gpu(ptr addrspace(1) %addr, i64 %val) {
; SM90-NEXT: .reg .b64 %rd<4>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [add_acq_rel_i64_global_gpu_param_0];
-; SM90-NEXT: ld.param.b64 %rd2, [add_acq_rel_i64_global_gpu_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd1, [add_acq_rel_i64_global_gpu_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd2, [add_acq_rel_i64_global_gpu_param_1];
; SM90-NEXT: atom.acq_rel.gpu.global.add.u64 %rd3, [%rd1], %rd2;
-; SM90-NEXT: st.param.b64 [func_retval0], %rd3;
+; SM90-NEXT: st.param::func.b64 [func_retval0], %rd3;
; SM90-NEXT: ret;
%retval = atomicrmw add ptr addrspace(1) %addr, i64 %val syncscope("device") acq_rel
ret i64 %retval
@@ -4441,10 +4441,10 @@ define i32 @min_acq_rel_i32_global_gpu(ptr addrspace(1) %addr, i32 %val) {
; SM90-NEXT: .reg .b64 %rd<2>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [min_acq_rel_i32_global_gpu_param_0];
-; SM90-NEXT: ld.param.b32 %r1, [min_acq_rel_i32_global_gpu_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd1, [min_acq_rel_i32_global_gpu_param_0];
+; SM90-NEXT: ld.param::func.b32 %r1, [min_acq_rel_i32_global_gpu_param_1];
; SM90-NEXT: atom.acq_rel.gpu.global.min.s32 %r2, [%rd1], %r1;
-; SM90-NEXT: st.param.b32 [func_retval0], %r2;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r2;
; SM90-NEXT: ret;
%retval = atomicrmw min ptr addrspace(1) %addr, i32 %val syncscope("device") acq_rel
ret i32 %retval
@@ -4457,10 +4457,10 @@ define i32 @umax_acq_rel_i32_global_gpu(ptr addrspace(1) %addr, i32 %val) {
; SM90-NEXT: .reg .b64 %rd<2>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [umax_acq_rel_i32_global_gpu_param_0];
-; SM90-NEXT: ld.param.b32 %r1, [umax_acq_rel_i32_global_gpu_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd1, [umax_acq_rel_i32_global_gpu_param_0];
+; SM90-NEXT: ld.param::func.b32 %r1, [umax_acq_rel_i32_global_gpu_param_1];
; SM90-NEXT: atom.acq_rel.gpu.global.max.u32 %r2, [%rd1], %r1;
-; SM90-NEXT: st.param.b32 [func_retval0], %r2;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r2;
; SM90-NEXT: ret;
%retval = atomicrmw umax ptr addrspace(1) %addr, i32 %val syncscope("device") acq_rel
ret i32 %retval
@@ -4474,8 +4474,8 @@ define i32 @nand_acq_rel_i32_global_gpu(ptr addrspace(1) %addr, i32 %val) {
; SM90-NEXT: .reg .b64 %rd<2>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b32 %r2, [nand_acq_rel_i32_global_gpu_param_1];
-; SM90-NEXT: ld.param.b64 %rd1, [nand_acq_rel_i32_global_gpu_param_0];
+; SM90-NEXT: ld.param::func.b32 %r2, [nand_acq_rel_i32_global_gpu_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd1, [nand_acq_rel_i32_global_gpu_param_0];
; SM90-NEXT: fence.release.gpu;
; SM90-NEXT: ld.relaxed.gpu.global.b32 %r5, [%rd1];
; SM90-NEXT: $L__BB120_1: // %atomicrmw.start
@@ -4488,7 +4488,7 @@ define i32 @nand_acq_rel_i32_global_gpu(ptr addrspace(1) %addr, i32 %val) {
; SM90-NEXT: @%p1 bra $L__BB120_1;
; SM90-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NEXT: fence.acquire.gpu;
-; SM90-NEXT: st.param.b32 [func_retval0], %r1;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r1;
; SM90-NEXT: ret;
%retval = atomicrmw nand ptr addrspace(1) %addr, i32 %val syncscope("device") acq_rel
ret i32 %retval
@@ -4501,8 +4501,8 @@ define i64 @nand_acq_rel_i64_global_gpu(ptr addrspace(1) %addr, i64 %val) {
; SM90-NEXT: .reg .b64 %rd<7>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd3, [nand_acq_rel_i64_global_gpu_param_1];
-; SM90-NEXT: ld.param.b64 %rd2, [nand_acq_rel_i64_global_gpu_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd3, [nand_acq_rel_i64_global_gpu_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd2, [nand_acq_rel_i64_global_gpu_param_0];
; SM90-NEXT: fence.release.gpu;
; SM90-NEXT: ld.relaxed.gpu.global.b64 %rd6, [%rd2];
; SM90-NEXT: $L__BB121_1: // %atomicrmw.start
@@ -4515,7 +4515,7 @@ define i64 @nand_acq_rel_i64_global_gpu(ptr addrspace(1) %addr, i64 %val) {
; SM90-NEXT: @%p1 bra $L__BB121_1;
; SM90-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NEXT: fence.acquire.gpu;
-; SM90-NEXT: st.param.b64 [func_retval0], %rd1;
+; SM90-NEXT: st.param::func.b64 [func_retval0], %rd1;
; SM90-NEXT: ret;
%retval = atomicrmw nand ptr addrspace(1) %addr, i64 %val syncscope("device") acq_rel
ret i64 %retval
@@ -4529,8 +4529,8 @@ define float @fadd_acq_rel_float_global_gpu(ptr addrspace(1) %addr, float %val)
; SM90-NOFTZ-DISALLOW-NEXT: .reg .b64 %rd<2>;
; SM90-NOFTZ-DISALLOW-EMPTY:
; SM90-NOFTZ-DISALLOW-NEXT: // %bb.0:
-; SM90-NOFTZ-DISALLOW-NEXT: ld.param.b32 %r2, [fadd_acq_rel_float_global_gpu_param_1];
-; SM90-NOFTZ-DISALLOW-NEXT: ld.param.b64 %rd1, [fadd_acq_rel_float_global_gpu_param_0];
+; SM90-NOFTZ-DISALLOW-NEXT: ld.param::func.b32 %r2, [fadd_acq_rel_float_global_gpu_param_1];
+; SM90-NOFTZ-DISALLOW-NEXT: ld.param::func.b64 %rd1, [fadd_acq_rel_float_global_gpu_param_0];
; SM90-NOFTZ-DISALLOW-NEXT: fence.release.gpu;
; SM90-NOFTZ-DISALLOW-NEXT: ld.relaxed.gpu.global.b32 %r4, [%rd1];
; SM90-NOFTZ-DISALLOW-NEXT: $L__BB122_1: // %atomicrmw.start
@@ -4542,7 +4542,7 @@ define float @fadd_acq_rel_float_global_gpu(ptr addrspace(1) %addr, float %val)
; SM90-NOFTZ-DISALLOW-NEXT: @%p1 bra $L__BB122_1;
; SM90-NOFTZ-DISALLOW-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NOFTZ-DISALLOW-NEXT: fence.acquire.gpu;
-; SM90-NOFTZ-DISALLOW-NEXT: st.param.b32 [func_retval0], %r1;
+; SM90-NOFTZ-DISALLOW-NEXT: st.param::func.b32 [func_retval0], %r1;
; SM90-NOFTZ-DISALLOW-NEXT: ret;
;
; SM90-NOFTZ-ALLOW-LABEL: fadd_acq_rel_float_global_gpu(
@@ -4551,10 +4551,10 @@ define float @fadd_acq_rel_float_global_gpu(ptr addrspace(1) %addr, float %val)
; SM90-NOFTZ-ALLOW-NEXT: .reg .b64 %rd<2>;
; SM90-NOFTZ-ALLOW-EMPTY:
; SM90-NOFTZ-ALLOW-NEXT: // %bb.0:
-; SM90-NOFTZ-ALLOW-NEXT: ld.param.b64 %rd1, [fadd_acq_rel_float_global_gpu_param_0];
-; SM90-NOFTZ-ALLOW-NEXT: ld.param.b32 %r1, [fadd_acq_rel_float_global_gpu_param_1];
+; SM90-NOFTZ-ALLOW-NEXT: ld.param::func.b64 %rd1, [fadd_acq_rel_float_global_gpu_param_0];
+; SM90-NOFTZ-ALLOW-NEXT: ld.param::func.b32 %r1, [fadd_acq_rel_float_global_gpu_param_1];
; SM90-NOFTZ-ALLOW-NEXT: atom.acq_rel.gpu.global.add.f32 %r2, [%rd1], %r1;
-; SM90-NOFTZ-ALLOW-NEXT: st.param.b32 [func_retval0], %r2;
+; SM90-NOFTZ-ALLOW-NEXT: st.param::func.b32 [func_retval0], %r2;
; SM90-NOFTZ-ALLOW-NEXT: ret;
;
; SM90-FTZ-DISALLOW-LABEL: fadd_acq_rel_float_global_gpu(
@@ -4563,10 +4563,10 @@ define float @fadd_acq_rel_float_global_gpu(ptr addrspace(1) %addr, float %val)
; SM90-FTZ-DISALLOW-NEXT: .reg .b64 %rd<2>;
; SM90-FTZ-DISALLOW-EMPTY:
; SM90-FTZ-DISALLOW-NEXT: // %bb.0:
-; SM90-FTZ-DISALLOW-NEXT: ld.param.b64 %rd1, [fadd_acq_rel_float_global_gpu_param_0];
-; SM90-FTZ-DISALLOW-NEXT: ld.param.b32 %r1, [fadd_acq_rel_float_global_gpu_param_1];
+; SM90-FTZ-DISALLOW-NEXT: ld.param::func.b64 %rd1, [fadd_acq_rel_float_global_gpu_param_0];
+; SM90-FTZ-DISALLOW-NEXT: ld.param::func.b32 %r1, [fadd_acq_rel_float_global_gpu_param_1];
; SM90-FTZ-DISALLOW-NEXT: atom.acq_rel.gpu.global.add.f32 %r2, [%rd1], %r1;
-; SM90-FTZ-DISALLOW-NEXT: st.param.b32 [func_retval0], %r2;
+; SM90-FTZ-DISALLOW-NEXT: st.param::func.b32 [func_retval0], %r2;
; SM90-FTZ-DISALLOW-NEXT: ret;
;
; SM90-FTZ-ALLOW-LABEL: fadd_acq_rel_float_global_gpu(
@@ -4575,10 +4575,10 @@ define float @fadd_acq_rel_float_global_gpu(ptr addrspace(1) %addr, float %val)
; SM90-FTZ-ALLOW-NEXT: .reg .b64 %rd<2>;
; SM90-FTZ-ALLOW-EMPTY:
; SM90-FTZ-ALLOW-NEXT: // %bb.0:
-; SM90-FTZ-ALLOW-NEXT: ld.param.b64 %rd1, [fadd_acq_rel_float_global_gpu_param_0];
-; SM90-FTZ-ALLOW-NEXT: ld.param.b32 %r1, [fadd_acq_rel_float_global_gpu_param_1];
+; SM90-FTZ-ALLOW-NEXT: ld.param::func.b64 %rd1, [fadd_acq_rel_float_global_gpu_param_0];
+; SM90-FTZ-ALLOW-NEXT: ld.param::func.b32 %r1, [fadd_acq_rel_float_global_gpu_param_1];
; SM90-FTZ-ALLOW-NEXT: atom.acq_rel.gpu.global.add.f32 %r2, [%rd1], %r1;
-; SM90-FTZ-ALLOW-NEXT: st.param.b32 [func_retval0], %r2;
+; SM90-FTZ-ALLOW-NEXT: st.param::func.b32 [func_retval0], %r2;
; SM90-FTZ-ALLOW-NEXT: ret;
%retval = atomicrmw fadd ptr addrspace(1) %addr, float %val syncscope("device") acq_rel
ret float %retval
@@ -4590,10 +4590,10 @@ define double @fadd_acq_rel_double_global_gpu(ptr addrspace(1) %addr, double %va
; SM90-NEXT: .reg .b64 %rd<4>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [fadd_acq_rel_double_global_gpu_param_0];
-; SM90-NEXT: ld.param.b64 %rd2, [fadd_acq_rel_double_global_gpu_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd1, [fadd_acq_rel_double_global_gpu_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd2, [fadd_acq_rel_double_global_gpu_param_1];
; SM90-NEXT: atom.acq_rel.gpu.global.add.f64 %rd3, [%rd1], %rd2;
-; SM90-NEXT: st.param.b64 [func_retval0], %rd3;
+; SM90-NEXT: st.param::func.b64 [func_retval0], %rd3;
; SM90-NEXT: ret;
%retval = atomicrmw fadd ptr addrspace(1) %addr, double %val syncscope("device") acq_rel
ret double %retval
@@ -4606,10 +4606,10 @@ define i32 @add_acq_rel_i32_generic_cta(ptr %addr, i32 %val) {
; SM90-NEXT: .reg .b64 %rd<2>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [add_acq_rel_i32_generic_cta_param_0];
-; SM90-NEXT: ld.param.b32 %r1, [add_acq_rel_i32_generic_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd1, [add_acq_rel_i32_generic_cta_param_0];
+; SM90-NEXT: ld.param::func.b32 %r1, [add_acq_rel_i32_generic_cta_param_1];
; SM90-NEXT: atom.acq_rel.cta.add.u32 %r2, [%rd1], %r1;
-; SM90-NEXT: st.param.b32 [func_retval0], %r2;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r2;
; SM90-NEXT: ret;
%retval = atomicrmw add ptr %addr, i32 %val syncscope("block") acq_rel
ret i32 %retval
@@ -4621,10 +4621,10 @@ define i64 @add_acq_rel_i64_generic_cta(ptr %addr, i64 %val) {
; SM90-NEXT: .reg .b64 %rd<4>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [add_acq_rel_i64_generic_cta_param_0];
-; SM90-NEXT: ld.param.b64 %rd2, [add_acq_rel_i64_generic_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd1, [add_acq_rel_i64_generic_cta_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd2, [add_acq_rel_i64_generic_cta_param_1];
; SM90-NEXT: atom.acq_rel.cta.add.u64 %rd3, [%rd1], %rd2;
-; SM90-NEXT: st.param.b64 [func_retval0], %rd3;
+; SM90-NEXT: st.param::func.b64 [func_retval0], %rd3;
; SM90-NEXT: ret;
%retval = atomicrmw add ptr %addr, i64 %val syncscope("block") acq_rel
ret i64 %retval
@@ -4637,10 +4637,10 @@ define i32 @min_acq_rel_i32_generic_cta(ptr %addr, i32 %val) {
; SM90-NEXT: .reg .b64 %rd<2>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [min_acq_rel_i32_generic_cta_param_0];
-; SM90-NEXT: ld.param.b32 %r1, [min_acq_rel_i32_generic_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd1, [min_acq_rel_i32_generic_cta_param_0];
+; SM90-NEXT: ld.param::func.b32 %r1, [min_acq_rel_i32_generic_cta_param_1];
; SM90-NEXT: atom.acq_rel.cta.min.s32 %r2, [%rd1], %r1;
-; SM90-NEXT: st.param.b32 [func_retval0], %r2;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r2;
; SM90-NEXT: ret;
%retval = atomicrmw min ptr %addr, i32 %val syncscope("block") acq_rel
ret i32 %retval
@@ -4653,10 +4653,10 @@ define i32 @umax_acq_rel_i32_generic_cta(ptr %addr, i32 %val) {
; SM90-NEXT: .reg .b64 %rd<2>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [umax_acq_rel_i32_generic_cta_param_0];
-; SM90-NEXT: ld.param.b32 %r1, [umax_acq_rel_i32_generic_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd1, [umax_acq_rel_i32_generic_cta_param_0];
+; SM90-NEXT: ld.param::func.b32 %r1, [umax_acq_rel_i32_generic_cta_param_1];
; SM90-NEXT: atom.acq_rel.cta.max.u32 %r2, [%rd1], %r1;
-; SM90-NEXT: st.param.b32 [func_retval0], %r2;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r2;
; SM90-NEXT: ret;
%retval = atomicrmw umax ptr %addr, i32 %val syncscope("block") acq_rel
ret i32 %retval
@@ -4670,8 +4670,8 @@ define i32 @nand_acq_rel_i32_generic_cta(ptr %addr, i32 %val) {
; SM90-NEXT: .reg .b64 %rd<2>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b32 %r2, [nand_acq_rel_i32_generic_cta_param_1];
-; SM90-NEXT: ld.param.b64 %rd1, [nand_acq_rel_i32_generic_cta_param_0];
+; SM90-NEXT: ld.param::func.b32 %r2, [nand_acq_rel_i32_generic_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd1, [nand_acq_rel_i32_generic_cta_param_0];
; SM90-NEXT: fence.release.cta;
; SM90-NEXT: ld.relaxed.cta.b32 %r5, [%rd1];
; SM90-NEXT: $L__BB128_1: // %atomicrmw.start
@@ -4684,7 +4684,7 @@ define i32 @nand_acq_rel_i32_generic_cta(ptr %addr, i32 %val) {
; SM90-NEXT: @%p1 bra $L__BB128_1;
; SM90-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NEXT: fence.acquire.cta;
-; SM90-NEXT: st.param.b32 [func_retval0], %r1;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r1;
; SM90-NEXT: ret;
%retval = atomicrmw nand ptr %addr, i32 %val syncscope("block") acq_rel
ret i32 %retval
@@ -4697,8 +4697,8 @@ define i64 @nand_acq_rel_i64_generic_cta(ptr %addr, i64 %val) {
; SM90-NEXT: .reg .b64 %rd<7>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd3, [nand_acq_rel_i64_generic_cta_param_1];
-; SM90-NEXT: ld.param.b64 %rd2, [nand_acq_rel_i64_generic_cta_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd3, [nand_acq_rel_i64_generic_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd2, [nand_acq_rel_i64_generic_cta_param_0];
; SM90-NEXT: fence.release.cta;
; SM90-NEXT: ld.relaxed.cta.b64 %rd6, [%rd2];
; SM90-NEXT: $L__BB129_1: // %atomicrmw.start
@@ -4711,7 +4711,7 @@ define i64 @nand_acq_rel_i64_generic_cta(ptr %addr, i64 %val) {
; SM90-NEXT: @%p1 bra $L__BB129_1;
; SM90-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NEXT: fence.acquire.cta;
-; SM90-NEXT: st.param.b64 [func_retval0], %rd1;
+; SM90-NEXT: st.param::func.b64 [func_retval0], %rd1;
; SM90-NEXT: ret;
%retval = atomicrmw nand ptr %addr, i64 %val syncscope("block") acq_rel
ret i64 %retval
@@ -4725,8 +4725,8 @@ define float @fadd_acq_rel_float_generic_cta(ptr %addr, float %val) {
; SM90-NOFTZ-DISALLOW-NEXT: .reg .b64 %rd<2>;
; SM90-NOFTZ-DISALLOW-EMPTY:
; SM90-NOFTZ-DISALLOW-NEXT: // %bb.0:
-; SM90-NOFTZ-DISALLOW-NEXT: ld.param.b32 %r2, [fadd_acq_rel_float_generic_cta_param_1];
-; SM90-NOFTZ-DISALLOW-NEXT: ld.param.b64 %rd1, [fadd_acq_rel_float_generic_cta_param_0];
+; SM90-NOFTZ-DISALLOW-NEXT: ld.param::func.b32 %r2, [fadd_acq_rel_float_generic_cta_param_1];
+; SM90-NOFTZ-DISALLOW-NEXT: ld.param::func.b64 %rd1, [fadd_acq_rel_float_generic_cta_param_0];
; SM90-NOFTZ-DISALLOW-NEXT: fence.release.cta;
; SM90-NOFTZ-DISALLOW-NEXT: ld.relaxed.cta.b32 %r4, [%rd1];
; SM90-NOFTZ-DISALLOW-NEXT: $L__BB130_1: // %atomicrmw.start
@@ -4738,7 +4738,7 @@ define float @fadd_acq_rel_float_generic_cta(ptr %addr, float %val) {
; SM90-NOFTZ-DISALLOW-NEXT: @%p1 bra $L__BB130_1;
; SM90-NOFTZ-DISALLOW-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NOFTZ-DISALLOW-NEXT: fence.acquire.cta;
-; SM90-NOFTZ-DISALLOW-NEXT: st.param.b32 [func_retval0], %r1;
+; SM90-NOFTZ-DISALLOW-NEXT: st.param::func.b32 [func_retval0], %r1;
; SM90-NOFTZ-DISALLOW-NEXT: ret;
;
; SM90-NOFTZ-ALLOW-LABEL: fadd_acq_rel_float_generic_cta(
@@ -4747,10 +4747,10 @@ define float @fadd_acq_rel_float_generic_cta(ptr %addr, float %val) {
; SM90-NOFTZ-ALLOW-NEXT: .reg .b64 %rd<2>;
; SM90-NOFTZ-ALLOW-EMPTY:
; SM90-NOFTZ-ALLOW-NEXT: // %bb.0:
-; SM90-NOFTZ-ALLOW-NEXT: ld.param.b64 %rd1, [fadd_acq_rel_float_generic_cta_param_0];
-; SM90-NOFTZ-ALLOW-NEXT: ld.param.b32 %r1, [fadd_acq_rel_float_generic_cta_param_1];
+; SM90-NOFTZ-ALLOW-NEXT: ld.param::func.b64 %rd1, [fadd_acq_rel_float_generic_cta_param_0];
+; SM90-NOFTZ-ALLOW-NEXT: ld.param::func.b32 %r1, [fadd_acq_rel_float_generic_cta_param_1];
; SM90-NOFTZ-ALLOW-NEXT: atom.acq_rel.cta.add.f32 %r2, [%rd1], %r1;
-; SM90-NOFTZ-ALLOW-NEXT: st.param.b32 [func_retval0], %r2;
+; SM90-NOFTZ-ALLOW-NEXT: st.param::func.b32 [func_retval0], %r2;
; SM90-NOFTZ-ALLOW-NEXT: ret;
;
; SM90-FTZ-DISALLOW-LABEL: fadd_acq_rel_float_generic_cta(
@@ -4760,8 +4760,8 @@ define float @fadd_acq_rel_float_generic_cta(ptr %addr, float %val) {
; SM90-FTZ-DISALLOW-NEXT: .reg .b64 %rd<2>;
; SM90-FTZ-DISALLOW-EMPTY:
; SM90-FTZ-DISALLOW-NEXT: // %bb.0:
-; SM90-FTZ-DISALLOW-NEXT: ld.param.b32 %r2, [fadd_acq_rel_float_generic_cta_param_1];
-; SM90-FTZ-DISALLOW-NEXT: ld.param.b64 %rd1, [fadd_acq_rel_float_generic_cta_param_0];
+; SM90-FTZ-DISALLOW-NEXT: ld.param::func.b32 %r2, [fadd_acq_rel_float_generic_cta_param_1];
+; SM90-FTZ-DISALLOW-NEXT: ld.param::func.b64 %rd1, [fadd_acq_rel_float_generic_cta_param_0];
; SM90-FTZ-DISALLOW-NEXT: fence.release.cta;
; SM90-FTZ-DISALLOW-NEXT: ld.relaxed.cta.b32 %r4, [%rd1];
; SM90-FTZ-DISALLOW-NEXT: $L__BB130_1: // %atomicrmw.start
@@ -4773,7 +4773,7 @@ define float @fadd_acq_rel_float_generic_cta(ptr %addr, float %val) {
; SM90-FTZ-DISALLOW-NEXT: @%p1 bra $L__BB130_1;
; SM90-FTZ-DISALLOW-NEXT: // %bb.2: // %atomicrmw.end
; SM90-FTZ-DISALLOW-NEXT: fence.acquire.cta;
-; SM90-FTZ-DISALLOW-NEXT: st.param.b32 [func_retval0], %r1;
+; SM90-FTZ-DISALLOW-NEXT: st.param::func.b32 [func_retval0], %r1;
; SM90-FTZ-DISALLOW-NEXT: ret;
;
; SM90-FTZ-ALLOW-LABEL: fadd_acq_rel_float_generic_cta(
@@ -4782,10 +4782,10 @@ define float @fadd_acq_rel_float_generic_cta(ptr %addr, float %val) {
; SM90-FTZ-ALLOW-NEXT: .reg .b64 %rd<2>;
; SM90-FTZ-ALLOW-EMPTY:
; SM90-FTZ-ALLOW-NEXT: // %bb.0:
-; SM90-FTZ-ALLOW-NEXT: ld.param.b64 %rd1, [fadd_acq_rel_float_generic_cta_param_0];
-; SM90-FTZ-ALLOW-NEXT: ld.param.b32 %r1, [fadd_acq_rel_float_generic_cta_param_1];
+; SM90-FTZ-ALLOW-NEXT: ld.param::func.b64 %rd1, [fadd_acq_rel_float_generic_cta_param_0];
+; SM90-FTZ-ALLOW-NEXT: ld.param::func.b32 %r1, [fadd_acq_rel_float_generic_cta_param_1];
; SM90-FTZ-ALLOW-NEXT: atom.acq_rel.cta.add.f32 %r2, [%rd1], %r1;
-; SM90-FTZ-ALLOW-NEXT: st.param.b32 [func_retval0], %r2;
+; SM90-FTZ-ALLOW-NEXT: st.param::func.b32 [func_retval0], %r2;
; SM90-FTZ-ALLOW-NEXT: ret;
%retval = atomicrmw fadd ptr %addr, float %val syncscope("block") acq_rel
ret float %retval
@@ -4797,10 +4797,10 @@ define double @fadd_acq_rel_double_generic_cta(ptr %addr, double %val) {
; SM90-NEXT: .reg .b64 %rd<4>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [fadd_acq_rel_double_generic_cta_param_0];
-; SM90-NEXT: ld.param.b64 %rd2, [fadd_acq_rel_double_generic_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd1, [fadd_acq_rel_double_generic_cta_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd2, [fadd_acq_rel_double_generic_cta_param_1];
; SM90-NEXT: atom.acq_rel.cta.add.f64 %rd3, [%rd1], %rd2;
-; SM90-NEXT: st.param.b64 [func_retval0], %rd3;
+; SM90-NEXT: st.param::func.b64 [func_retval0], %rd3;
; SM90-NEXT: ret;
%retval = atomicrmw fadd ptr %addr, double %val syncscope("block") acq_rel
ret double %retval
@@ -4813,10 +4813,10 @@ define i32 @add_acq_rel_i32_shared_cta(ptr addrspace(3) %addr, i32 %val) {
; SM90-NEXT: .reg .b64 %rd<2>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [add_acq_rel_i32_shared_cta_param_0];
-; SM90-NEXT: ld.param.b32 %r1, [add_acq_rel_i32_shared_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd1, [add_acq_rel_i32_shared_cta_param_0];
+; SM90-NEXT: ld.param::func.b32 %r1, [add_acq_rel_i32_shared_cta_param_1];
; SM90-NEXT: atom.acq_rel.cta.shared.add.u32 %r2, [%rd1], %r1;
-; SM90-NEXT: st.param.b32 [func_retval0], %r2;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r2;
; SM90-NEXT: ret;
%retval = atomicrmw add ptr addrspace(3) %addr, i32 %val syncscope("block") acq_rel
ret i32 %retval
@@ -4828,10 +4828,10 @@ define i64 @add_acq_rel_i64_shared_cta(ptr addrspace(3) %addr, i64 %val) {
; SM90-NEXT: .reg .b64 %rd<4>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [add_acq_rel_i64_shared_cta_param_0];
-; SM90-NEXT: ld.param.b64 %rd2, [add_acq_rel_i64_shared_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd1, [add_acq_rel_i64_shared_cta_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd2, [add_acq_rel_i64_shared_cta_param_1];
; SM90-NEXT: atom.acq_rel.cta.shared.add.u64 %rd3, [%rd1], %rd2;
-; SM90-NEXT: st.param.b64 [func_retval0], %rd3;
+; SM90-NEXT: st.param::func.b64 [func_retval0], %rd3;
; SM90-NEXT: ret;
%retval = atomicrmw add ptr addrspace(3) %addr, i64 %val syncscope("block") acq_rel
ret i64 %retval
@@ -4844,10 +4844,10 @@ define i32 @min_acq_rel_i32_shared_cta(ptr addrspace(3) %addr, i32 %val) {
; SM90-NEXT: .reg .b64 %rd<2>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [min_acq_rel_i32_shared_cta_param_0];
-; SM90-NEXT: ld.param.b32 %r1, [min_acq_rel_i32_shared_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd1, [min_acq_rel_i32_shared_cta_param_0];
+; SM90-NEXT: ld.param::func.b32 %r1, [min_acq_rel_i32_shared_cta_param_1];
; SM90-NEXT: atom.acq_rel.cta.shared.min.s32 %r2, [%rd1], %r1;
-; SM90-NEXT: st.param.b32 [func_retval0], %r2;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r2;
; SM90-NEXT: ret;
%retval = atomicrmw min ptr addrspace(3) %addr, i32 %val syncscope("block") acq_rel
ret i32 %retval
@@ -4860,10 +4860,10 @@ define i32 @umax_acq_rel_i32_shared_cta(ptr addrspace(3) %addr, i32 %val) {
; SM90-NEXT: .reg .b64 %rd<2>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [umax_acq_rel_i32_shared_cta_param_0];
-; SM90-NEXT: ld.param.b32 %r1, [umax_acq_rel_i32_shared_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd1, [umax_acq_rel_i32_shared_cta_param_0];
+; SM90-NEXT: ld.param::func.b32 %r1, [umax_acq_rel_i32_shared_cta_param_1];
; SM90-NEXT: atom.acq_rel.cta.shared.max.u32 %r2, [%rd1], %r1;
-; SM90-NEXT: st.param.b32 [func_retval0], %r2;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r2;
; SM90-NEXT: ret;
%retval = atomicrmw umax ptr addrspace(3) %addr, i32 %val syncscope("block") acq_rel
ret i32 %retval
@@ -4877,8 +4877,8 @@ define i32 @nand_acq_rel_i32_shared_cta(ptr addrspace(3) %addr, i32 %val) {
; SM90-NEXT: .reg .b64 %rd<2>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b32 %r2, [nand_acq_rel_i32_shared_cta_param_1];
-; SM90-NEXT: ld.param.b64 %rd1, [nand_acq_rel_i32_shared_cta_param_0];
+; SM90-NEXT: ld.param::func.b32 %r2, [nand_acq_rel_i32_shared_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd1, [nand_acq_rel_i32_shared_cta_param_0];
; SM90-NEXT: fence.release.cta;
; SM90-NEXT: ld.relaxed.cta.shared.b32 %r5, [%rd1];
; SM90-NEXT: $L__BB136_1: // %atomicrmw.start
@@ -4891,7 +4891,7 @@ define i32 @nand_acq_rel_i32_shared_cta(ptr addrspace(3) %addr, i32 %val) {
; SM90-NEXT: @%p1 bra $L__BB136_1;
; SM90-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NEXT: fence.acquire.cta;
-; SM90-NEXT: st.param.b32 [func_retval0], %r1;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r1;
; SM90-NEXT: ret;
%retval = atomicrmw nand ptr addrspace(3) %addr, i32 %val syncscope("block") acq_rel
ret i32 %retval
@@ -4904,8 +4904,8 @@ define i64 @nand_acq_rel_i64_shared_cta(ptr addrspace(3) %addr, i64 %val) {
; SM90-NEXT: .reg .b64 %rd<7>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd3, [nand_acq_rel_i64_shared_cta_param_1];
-; SM90-NEXT: ld.param.b64 %rd2, [nand_acq_rel_i64_shared_cta_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd3, [nand_acq_rel_i64_shared_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd2, [nand_acq_rel_i64_shared_cta_param_0];
; SM90-NEXT: fence.release.cta;
; SM90-NEXT: ld.relaxed.cta.shared.b64 %rd6, [%rd2];
; SM90-NEXT: $L__BB137_1: // %atomicrmw.start
@@ -4918,7 +4918,7 @@ define i64 @nand_acq_rel_i64_shared_cta(ptr addrspace(3) %addr, i64 %val) {
; SM90-NEXT: @%p1 bra $L__BB137_1;
; SM90-NEXT: // %bb.2: // %atomicrmw.end
; SM90-NEXT: fence.acquire.cta;
-; SM90-NEXT: st.param.b64 [func_retval0], %rd1;
+; SM90-NEXT: st.param::func.b64 [func_retval0], %rd1;
; SM90-NEXT: ret;
%retval = atomicrmw nand ptr addrspace(3) %addr, i64 %val syncscope("block") acq_rel
ret i64 %retval
@@ -4931,10 +4931,10 @@ define float @fadd_acq_rel_float_shared_cta(ptr addrspace(3) %addr, float %val)
; SM90-NOFTZ-DISALLOW-NEXT: .reg .b64 %rd<2>;
; SM90-NOFTZ-DISALLOW-EMPTY:
; SM90-NOFTZ-DISALLOW-NEXT: // %bb.0:
-; SM90-NOFTZ-DISALLOW-NEXT: ld.param.b64 %rd1, [fadd_acq_rel_float_shared_cta_param_0];
-; SM90-NOFTZ-DISALLOW-NEXT: ld.param.b32 %r1, [fadd_acq_rel_float_shared_cta_param_1];
+; SM90-NOFTZ-DISALLOW-NEXT: ld.param::func.b64 %rd1, [fadd_acq_rel_float_shared_cta_param_0];
+; SM90-NOFTZ-DISALLOW-NEXT: ld.param::func.b32 %r1, [fadd_acq_rel_float_shared_cta_param_1];
; SM90-NOFTZ-DISALLOW-NEXT: atom.acq_rel.cta.shared.add.f32 %r2, [%rd1], %r1;
-; SM90-NOFTZ-DISALLOW-NEXT: st.param.b32 [func_retval0], %r2;
+; SM90-NOFTZ-DISALLOW-NEXT: st.param::func.b32 [func_retval0], %r2;
; SM90-NOFTZ-DISALLOW-NEXT: ret;
;
; SM90-NOFTZ-ALLOW-LABEL: fadd_acq_rel_float_shared_cta(
@@ -4943,10 +4943,10 @@ define float @fadd_acq_rel_float_shared_cta(ptr addrspace(3) %addr, float %val)
; SM90-NOFTZ-ALLOW-NEXT: .reg .b64 %rd<2>;
; SM90-NOFTZ-ALLOW-EMPTY:
; SM90-NOFTZ-ALLOW-NEXT: // %bb.0:
-; SM90-NOFTZ-ALLOW-NEXT: ld.param.b64 %rd1, [fadd_acq_rel_float_shared_cta_param_0];
-; SM90-NOFTZ-ALLOW-NEXT: ld.param.b32 %r1, [fadd_acq_rel_float_shared_cta_param_1];
+; SM90-NOFTZ-ALLOW-NEXT: ld.param::func.b64 %rd1, [fadd_acq_rel_float_shared_cta_param_0];
+; SM90-NOFTZ-ALLOW-NEXT: ld.param::func.b32 %r1, [fadd_acq_rel_float_shared_cta_param_1];
; SM90-NOFTZ-ALLOW-NEXT: atom.acq_rel.cta.shared.add.f32 %r2, [%rd1], %r1;
-; SM90-NOFTZ-ALLOW-NEXT: st.param.b32 [func_retval0], %r2;
+; SM90-NOFTZ-ALLOW-NEXT: st.param::func.b32 [func_retval0], %r2;
; SM90-NOFTZ-ALLOW-NEXT: ret;
;
; SM90-FTZ-DISALLOW-LABEL: fadd_acq_rel_float_shared_cta(
@@ -4956,8 +4956,8 @@ define float @fadd_acq_rel_float_shared_cta(ptr addrspace(3) %addr, float %val)
; SM90-FTZ-DISALLOW-NEXT: .reg .b64 %rd<2>;
; SM90-FTZ-DISALLOW-EMPTY:
; SM90-FTZ-DISALLOW-NEXT: // %bb.0:
-; SM90-FTZ-DISALLOW-NEXT: ld.param.b32 %r2, [fadd_acq_rel_float_shared_cta_param_1];
-; SM90-FTZ-DISALLOW-NEXT: ld.param.b64 %rd1, [fadd_acq_rel_float_shared_cta_param_0];
+; SM90-FTZ-DISALLOW-NEXT: ld.param::func.b32 %r2, [fadd_acq_rel_float_shared_cta_param_1];
+; SM90-FTZ-DISALLOW-NEXT: ld.param::func.b64 %rd1, [fadd_acq_rel_float_shared_cta_param_0];
; SM90-FTZ-DISALLOW-NEXT: fence.release.cta;
; SM90-FTZ-DISALLOW-NEXT: ld.relaxed.cta.shared.b32 %r4, [%rd1];
; SM90-FTZ-DISALLOW-NEXT: $L__BB138_1: // %atomicrmw.start
@@ -4969,7 +4969,7 @@ define float @fadd_acq_rel_float_shared_cta(ptr addrspace(3) %addr, float %val)
; SM90-FTZ-DISALLOW-NEXT: @%p1 bra $L__BB138_1;
; SM90-FTZ-DISALLOW-NEXT: // %bb.2: // %atomicrmw.end
; SM90-FTZ-DISALLOW-NEXT: fence.acquire.cta;
-; SM90-FTZ-DISALLOW-NEXT: st.param.b32 [func_retval0], %r1;
+; SM90-FTZ-DISALLOW-NEXT: st.param::func.b32 [func_retval0], %r1;
; SM90-FTZ-DISALLOW-NEXT: ret;
;
; SM90-FTZ-ALLOW-LABEL: fadd_acq_rel_float_shared_cta(
@@ -4978,10 +4978,10 @@ define float @fadd_acq_rel_float_shared_cta(ptr addrspace(3) %addr, float %val)
; SM90-FTZ-ALLOW-NEXT: .reg .b64 %rd<2>;
; SM90-FTZ-ALLOW-EMPTY:
; SM90-FTZ-ALLOW-NEXT: // %bb.0:
-; SM90-FTZ-ALLOW-NEXT: ld.param.b64 %rd1, [fadd_acq_rel_float_shared_cta_param_0];
-; SM90-FTZ-ALLOW-NEXT: ld.param.b32 %r1, [fadd_acq_rel_float_shared_cta_param_1];
+; SM90-FTZ-ALLOW-NEXT: ld.param::func.b64 %rd1, [fadd_acq_rel_float_shared_cta_param_0];
+; SM90-FTZ-ALLOW-NEXT: ld.param::func.b32 %r1, [fadd_acq_rel_float_shared_cta_param_1];
; SM90-FTZ-ALLOW-NEXT: atom.acq_rel.cta.shared.add.f32 %r2, [%rd1], %r1;
-; SM90-FTZ-ALLOW-NEXT: st.param.b32 [func_retval0], %r2;
+; SM90-FTZ-ALLOW-NEXT: st.param::func.b32 [func_retval0], %r2;
; SM90-FTZ-ALLOW-NEXT: ret;
%retval = atomicrmw fadd ptr addrspace(3) %addr, float %val syncscope("block") acq_rel
ret float %retval
@@ -4993,10 +4993,10 @@ define double @fadd_acq_rel_double_shared_cta(ptr addrspace(3) %addr, double %va
; SM90-NEXT: .reg .b64 %rd<4>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [fadd_acq_rel_double_shared_cta_param_0];
-; SM90-NEXT: ld.param.b64 %rd2, [fadd_acq_rel_double_shared_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd1, [fadd_acq_rel_double_shared_cta_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd2, [fadd_acq_rel_double_shared_cta_param_1];
; SM90-NEXT: atom.acq_rel.cta.shared.add.f64 %rd3, [%rd1], %rd2;
-; SM90-NEXT: st.param.b64 [func_retval0], %rd3;
+; SM90-NEXT: st.param::func.b64 [func_retval0], %rd3;
; SM90-NEXT: ret;
%retval = atomicrmw fadd ptr addrspace(3) %addr, double %val syncscope("block") acq_rel
ret double %retval
diff --git a/llvm/test/CodeGen/NVPTX/atomics-b128.ll b/llvm/test/CodeGen/NVPTX/atomics-b128.ll
index 170222a7c5f2e..bb1e800ef7a6d 100644
--- a/llvm/test/CodeGen/NVPTX/atomics-b128.ll
+++ b/llvm/test/CodeGen/NVPTX/atomics-b128.ll
@@ -19,15 +19,15 @@ define i128 @test_xchg_generic(ptr %addr, i128 %amt) {
; CHECK-NEXT: .reg .b64 %rd<6>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [test_xchg_generic_param_0];
-; CHECK-NEXT: ld.param.v2.b64 {%rd2, %rd3}, [test_xchg_generic_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_xchg_generic_param_0];
+; CHECK-NEXT: ld.param::func.v2.b64 {%rd2, %rd3}, [test_xchg_generic_param_1];
; CHECK-NEXT: {
; CHECK-NEXT: .reg .b128 amt, dst;
; CHECK-NEXT: mov.b128 amt, {%rd2, %rd3};
; CHECK-NEXT: atom.release.sys.exch.b128 dst, [%rd1], amt;
; CHECK-NEXT: mov.b128 {%rd4, %rd5}, dst;
; CHECK-NEXT: }
-; CHECK-NEXT: st.param.v2.b64 [func_retval0], {%rd4, %rd5};
+; CHECK-NEXT: st.param::func.v2.b64 [func_retval0], {%rd4, %rd5};
; CHECK-NEXT: ret;
%old = atomicrmw xchg ptr %addr, i128 %amt release
ret i128 %old
@@ -39,15 +39,15 @@ define i128 @test_xchg_global(ptr addrspace(1) %addr, i128 %amt) {
; CHECK-NEXT: .reg .b64 %rd<6>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [test_xchg_global_param_0];
-; CHECK-NEXT: ld.param.v2.b64 {%rd2, %rd3}, [test_xchg_global_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_xchg_global_param_0];
+; CHECK-NEXT: ld.param::func.v2.b64 {%rd2, %rd3}, [test_xchg_global_param_1];
; CHECK-NEXT: {
; CHECK-NEXT: .reg .b128 amt, dst;
; CHECK-NEXT: mov.b128 amt, {%rd2, %rd3};
; CHECK-NEXT: atom.release.sys.global.exch.b128 dst, [%rd1], amt;
; CHECK-NEXT: mov.b128 {%rd4, %rd5}, dst;
; CHECK-NEXT: }
-; CHECK-NEXT: st.param.v2.b64 [func_retval0], {%rd4, %rd5};
+; CHECK-NEXT: st.param::func.v2.b64 [func_retval0], {%rd4, %rd5};
; CHECK-NEXT: ret;
%old = atomicrmw xchg ptr addrspace(1) %addr, i128 %amt release
ret i128 %old
@@ -59,15 +59,15 @@ define i128 @test_xchg_shared(ptr addrspace(3) %addr, i128 %amt) {
; CHECK-NEXT: .reg .b64 %rd<6>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [test_xchg_shared_param_0];
-; CHECK-NEXT: ld.param.v2.b64 {%rd2, %rd3}, [test_xchg_shared_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_xchg_shared_param_0];
+; CHECK-NEXT: ld.param::func.v2.b64 {%rd2, %rd3}, [test_xchg_shared_param_1];
; CHECK-NEXT: {
; CHECK-NEXT: .reg .b128 amt, dst;
; CHECK-NEXT: mov.b128 amt, {%rd2, %rd3};
; CHECK-NEXT: atom.release.sys.shared.exch.b128 dst, [%rd1], amt;
; CHECK-NEXT: mov.b128 {%rd4, %rd5}, dst;
; CHECK-NEXT: }
-; CHECK-NEXT: st.param.v2.b64 [func_retval0], {%rd4, %rd5};
+; CHECK-NEXT: st.param::func.v2.b64 [func_retval0], {%rd4, %rd5};
; CHECK-NEXT: ret;
%old = atomicrmw xchg ptr addrspace(3) %addr, i128 %amt release
ret i128 %old
@@ -79,15 +79,15 @@ define i128 @test_xchg_shared_cluster(ptr addrspace(7) %addr, i128 %amt) {
; CHECK-NEXT: .reg .b64 %rd<6>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [test_xchg_shared_cluster_param_0];
-; CHECK-NEXT: ld.param.v2.b64 {%rd2, %rd3}, [test_xchg_shared_cluster_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_xchg_shared_cluster_param_0];
+; CHECK-NEXT: ld.param::func.v2.b64 {%rd2, %rd3}, [test_xchg_shared_cluster_param_1];
; CHECK-NEXT: {
; CHECK-NEXT: .reg .b128 amt, dst;
; CHECK-NEXT: mov.b128 amt, {%rd2, %rd3};
; CHECK-NEXT: atom.release.sys.shared::cluster.exch.b128 dst, [%rd1], amt;
; CHECK-NEXT: mov.b128 {%rd4, %rd5}, dst;
; CHECK-NEXT: }
-; CHECK-NEXT: st.param.v2.b64 [func_retval0], {%rd4, %rd5};
+; CHECK-NEXT: st.param::func.v2.b64 [func_retval0], {%rd4, %rd5};
; CHECK-NEXT: ret;
%old = atomicrmw xchg ptr addrspace(7) %addr, i128 %amt release
ret i128 %old
@@ -99,15 +99,15 @@ define i128 @test_xchg_block(ptr %addr, i128 %amt) {
; CHECK-NEXT: .reg .b64 %rd<6>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [test_xchg_block_param_0];
-; CHECK-NEXT: ld.param.v2.b64 {%rd2, %rd3}, [test_xchg_block_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_xchg_block_param_0];
+; CHECK-NEXT: ld.param::func.v2.b64 {%rd2, %rd3}, [test_xchg_block_param_1];
; CHECK-NEXT: {
; CHECK-NEXT: .reg .b128 amt, dst;
; CHECK-NEXT: mov.b128 amt, {%rd2, %rd3};
; CHECK-NEXT: atom.release.cta.exch.b128 dst, [%rd1], amt;
; CHECK-NEXT: mov.b128 {%rd4, %rd5}, dst;
; CHECK-NEXT: }
-; CHECK-NEXT: st.param.v2.b64 [func_retval0], {%rd4, %rd5};
+; CHECK-NEXT: st.param::func.v2.b64 [func_retval0], {%rd4, %rd5};
; CHECK-NEXT: ret;
%old = atomicrmw xchg ptr %addr, i128 %amt syncscope("block") release
ret i128 %old
@@ -119,15 +119,15 @@ define i128 @test_xchg_cluster(ptr %addr, i128 %amt) {
; CHECK-NEXT: .reg .b64 %rd<6>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [test_xchg_cluster_param_0];
-; CHECK-NEXT: ld.param.v2.b64 {%rd2, %rd3}, [test_xchg_cluster_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_xchg_cluster_param_0];
+; CHECK-NEXT: ld.param::func.v2.b64 {%rd2, %rd3}, [test_xchg_cluster_param_1];
; CHECK-NEXT: {
; CHECK-NEXT: .reg .b128 amt, dst;
; CHECK-NEXT: mov.b128 amt, {%rd2, %rd3};
; CHECK-NEXT: atom.release.cluster.exch.b128 dst, [%rd1], amt;
; CHECK-NEXT: mov.b128 {%rd4, %rd5}, dst;
; CHECK-NEXT: }
-; CHECK-NEXT: st.param.v2.b64 [func_retval0], {%rd4, %rd5};
+; CHECK-NEXT: st.param::func.v2.b64 [func_retval0], {%rd4, %rd5};
; CHECK-NEXT: ret;
%old = atomicrmw xchg ptr %addr, i128 %amt syncscope("cluster") release
ret i128 %old
@@ -139,15 +139,15 @@ define i128 @test_xchg_gpu(ptr %addr, i128 %amt) {
; CHECK-NEXT: .reg .b64 %rd<6>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [test_xchg_gpu_param_0];
-; CHECK-NEXT: ld.param.v2.b64 {%rd2, %rd3}, [test_xchg_gpu_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_xchg_gpu_param_0];
+; CHECK-NEXT: ld.param::func.v2.b64 {%rd2, %rd3}, [test_xchg_gpu_param_1];
; CHECK-NEXT: {
; CHECK-NEXT: .reg .b128 amt, dst;
; CHECK-NEXT: mov.b128 amt, {%rd2, %rd3};
; CHECK-NEXT: atom.release.gpu.exch.b128 dst, [%rd1], amt;
; CHECK-NEXT: mov.b128 {%rd4, %rd5}, dst;
; CHECK-NEXT: }
-; CHECK-NEXT: st.param.v2.b64 [func_retval0], {%rd4, %rd5};
+; CHECK-NEXT: st.param::func.v2.b64 [func_retval0], {%rd4, %rd5};
; CHECK-NEXT: ret;
%old = atomicrmw xchg ptr %addr, i128 %amt syncscope("device") release
ret i128 %old
@@ -159,15 +159,15 @@ define i128 @test_xchg_sys(ptr %addr, i128 %amt) {
; CHECK-NEXT: .reg .b64 %rd<6>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [test_xchg_sys_param_0];
-; CHECK-NEXT: ld.param.v2.b64 {%rd2, %rd3}, [test_xchg_sys_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_xchg_sys_param_0];
+; CHECK-NEXT: ld.param::func.v2.b64 {%rd2, %rd3}, [test_xchg_sys_param_1];
; CHECK-NEXT: {
; CHECK-NEXT: .reg .b128 amt, dst;
; CHECK-NEXT: mov.b128 amt, {%rd2, %rd3};
; CHECK-NEXT: atom.release.sys.exch.b128 dst, [%rd1], amt;
; CHECK-NEXT: mov.b128 {%rd4, %rd5}, dst;
; CHECK-NEXT: }
-; CHECK-NEXT: st.param.v2.b64 [func_retval0], {%rd4, %rd5};
+; CHECK-NEXT: st.param::func.v2.b64 [func_retval0], {%rd4, %rd5};
; CHECK-NEXT: ret;
%old = atomicrmw xchg ptr %addr, i128 %amt release
ret i128 %old
@@ -179,15 +179,15 @@ define i128 @test_xchg_relaxed(ptr %addr, i128 %amt) {
; CHECK-NEXT: .reg .b64 %rd<6>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [test_xchg_relaxed_param_0];
-; CHECK-NEXT: ld.param.v2.b64 {%rd2, %rd3}, [test_xchg_relaxed_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_xchg_relaxed_param_0];
+; CHECK-NEXT: ld.param::func.v2.b64 {%rd2, %rd3}, [test_xchg_relaxed_param_1];
; CHECK-NEXT: {
; CHECK-NEXT: .reg .b128 amt, dst;
; CHECK-NEXT: mov.b128 amt, {%rd2, %rd3};
; CHECK-NEXT: atom.relaxed.sys.exch.b128 dst, [%rd1], amt;
; CHECK-NEXT: mov.b128 {%rd4, %rd5}, dst;
; CHECK-NEXT: }
-; CHECK-NEXT: st.param.v2.b64 [func_retval0], {%rd4, %rd5};
+; CHECK-NEXT: st.param::func.v2.b64 [func_retval0], {%rd4, %rd5};
; CHECK-NEXT: ret;
%old = atomicrmw xchg ptr %addr, i128 %amt monotonic
ret i128 %old
@@ -199,15 +199,15 @@ define i128 @test_xchg_acquire(ptr %addr, i128 %amt) {
; CHECK-NEXT: .reg .b64 %rd<6>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [test_xchg_acquire_param_0];
-; CHECK-NEXT: ld.param.v2.b64 {%rd2, %rd3}, [test_xchg_acquire_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_xchg_acquire_param_0];
+; CHECK-NEXT: ld.param::func.v2.b64 {%rd2, %rd3}, [test_xchg_acquire_param_1];
; CHECK-NEXT: {
; CHECK-NEXT: .reg .b128 amt, dst;
; CHECK-NEXT: mov.b128 amt, {%rd2, %rd3};
; CHECK-NEXT: atom.acquire.sys.exch.b128 dst, [%rd1], amt;
; CHECK-NEXT: mov.b128 {%rd4, %rd5}, dst;
; CHECK-NEXT: }
-; CHECK-NEXT: st.param.v2.b64 [func_retval0], {%rd4, %rd5};
+; CHECK-NEXT: st.param::func.v2.b64 [func_retval0], {%rd4, %rd5};
; CHECK-NEXT: ret;
%old = atomicrmw xchg ptr %addr, i128 %amt acquire
ret i128 %old
@@ -219,15 +219,15 @@ define i128 @test_xchg_release(ptr %addr, i128 %amt) {
; CHECK-NEXT: .reg .b64 %rd<6>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [test_xchg_release_param_0];
-; CHECK-NEXT: ld.param.v2.b64 {%rd2, %rd3}, [test_xchg_release_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_xchg_release_param_0];
+; CHECK-NEXT: ld.param::func.v2.b64 {%rd2, %rd3}, [test_xchg_release_param_1];
; CHECK-NEXT: {
; CHECK-NEXT: .reg .b128 amt, dst;
; CHECK-NEXT: mov.b128 amt, {%rd2, %rd3};
; CHECK-NEXT: atom.release.sys.exch.b128 dst, [%rd1], amt;
; CHECK-NEXT: mov.b128 {%rd4, %rd5}, dst;
; CHECK-NEXT: }
-; CHECK-NEXT: st.param.v2.b64 [func_retval0], {%rd4, %rd5};
+; CHECK-NEXT: st.param::func.v2.b64 [func_retval0], {%rd4, %rd5};
; CHECK-NEXT: ret;
%old = atomicrmw xchg ptr %addr, i128 %amt release
ret i128 %old
@@ -239,15 +239,15 @@ define i128 @test_xchg_acq_rel(ptr %addr, i128 %amt) {
; CHECK-NEXT: .reg .b64 %rd<6>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [test_xchg_acq_rel_param_0];
-; CHECK-NEXT: ld.param.v2.b64 {%rd2, %rd3}, [test_xchg_acq_rel_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_xchg_acq_rel_param_0];
+; CHECK-NEXT: ld.param::func.v2.b64 {%rd2, %rd3}, [test_xchg_acq_rel_param_1];
; CHECK-NEXT: {
; CHECK-NEXT: .reg .b128 amt, dst;
; CHECK-NEXT: mov.b128 amt, {%rd2, %rd3};
; CHECK-NEXT: atom.acq_rel.sys.exch.b128 dst, [%rd1], amt;
; CHECK-NEXT: mov.b128 {%rd4, %rd5}, dst;
; CHECK-NEXT: }
-; CHECK-NEXT: st.param.v2.b64 [func_retval0], {%rd4, %rd5};
+; CHECK-NEXT: st.param::func.v2.b64 [func_retval0], {%rd4, %rd5};
; CHECK-NEXT: ret;
%old = atomicrmw xchg ptr %addr, i128 %amt acq_rel
ret i128 %old
@@ -259,9 +259,9 @@ define i128 @test_cmpxchg_generic(ptr %addr, i128 %cmp, i128 %new) {
; CHECK-NEXT: .reg .b64 %rd<8>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [test_cmpxchg_generic_param_0];
-; CHECK-NEXT: ld.param.v2.b64 {%rd2, %rd3}, [test_cmpxchg_generic_param_1];
-; CHECK-NEXT: ld.param.v2.b64 {%rd4, %rd5}, [test_cmpxchg_generic_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_cmpxchg_generic_param_0];
+; CHECK-NEXT: ld.param::func.v2.b64 {%rd2, %rd3}, [test_cmpxchg_generic_param_1];
+; CHECK-NEXT: ld.param::func.v2.b64 {%rd4, %rd5}, [test_cmpxchg_generic_param_2];
; CHECK-NEXT: {
; CHECK-NEXT: .reg .b128 cmp, swap, dst;
; CHECK-NEXT: mov.b128 cmp, {%rd2, %rd3};
@@ -269,7 +269,7 @@ define i128 @test_cmpxchg_generic(ptr %addr, i128 %cmp, i128 %new) {
; CHECK-NEXT: atom.relaxed.sys.cas.b128 dst, [%rd1], cmp, swap;
; CHECK-NEXT: mov.b128 {%rd6, %rd7}, dst;
; CHECK-NEXT: }
-; CHECK-NEXT: st.param.v2.b64 [func_retval0], {%rd4, %rd5};
+; CHECK-NEXT: st.param::func.v2.b64 [func_retval0], {%rd4, %rd5};
; CHECK-NEXT: ret;
%pairold = cmpxchg ptr %addr, i128 %cmp, i128 %new monotonic monotonic
ret i128 %new
@@ -281,9 +281,9 @@ define i128 @test_cmpxchg_global(ptr addrspace(1) %addr, i128 %cmp, i128 %new) {
; CHECK-NEXT: .reg .b64 %rd<8>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [test_cmpxchg_global_param_0];
-; CHECK-NEXT: ld.param.v2.b64 {%rd2, %rd3}, [test_cmpxchg_global_param_1];
-; CHECK-NEXT: ld.param.v2.b64 {%rd4, %rd5}, [test_cmpxchg_global_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_cmpxchg_global_param_0];
+; CHECK-NEXT: ld.param::func.v2.b64 {%rd2, %rd3}, [test_cmpxchg_global_param_1];
+; CHECK-NEXT: ld.param::func.v2.b64 {%rd4, %rd5}, [test_cmpxchg_global_param_2];
; CHECK-NEXT: {
; CHECK-NEXT: .reg .b128 cmp, swap, dst;
; CHECK-NEXT: mov.b128 cmp, {%rd2, %rd3};
@@ -291,7 +291,7 @@ define i128 @test_cmpxchg_global(ptr addrspace(1) %addr, i128 %cmp, i128 %new) {
; CHECK-NEXT: atom.relaxed.sys.global.cas.b128 dst, [%rd1], cmp, swap;
; CHECK-NEXT: mov.b128 {%rd6, %rd7}, dst;
; CHECK-NEXT: }
-; CHECK-NEXT: st.param.v2.b64 [func_retval0], {%rd4, %rd5};
+; CHECK-NEXT: st.param::func.v2.b64 [func_retval0], {%rd4, %rd5};
; CHECK-NEXT: ret;
%pairold = cmpxchg ptr addrspace(1) %addr, i128 %cmp, i128 %new monotonic monotonic
ret i128 %new
@@ -303,9 +303,9 @@ define i128 @test_cmpxchg_shared(ptr addrspace(3) %addr, i128 %cmp, i128 %new) {
; CHECK-NEXT: .reg .b64 %rd<8>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [test_cmpxchg_shared_param_0];
-; CHECK-NEXT: ld.param.v2.b64 {%rd2, %rd3}, [test_cmpxchg_shared_param_1];
-; CHECK-NEXT: ld.param.v2.b64 {%rd4, %rd5}, [test_cmpxchg_shared_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_cmpxchg_shared_param_0];
+; CHECK-NEXT: ld.param::func.v2.b64 {%rd2, %rd3}, [test_cmpxchg_shared_param_1];
+; CHECK-NEXT: ld.param::func.v2.b64 {%rd4, %rd5}, [test_cmpxchg_shared_param_2];
; CHECK-NEXT: {
; CHECK-NEXT: .reg .b128 cmp, swap, dst;
; CHECK-NEXT: mov.b128 cmp, {%rd2, %rd3};
@@ -313,7 +313,7 @@ define i128 @test_cmpxchg_shared(ptr addrspace(3) %addr, i128 %cmp, i128 %new) {
; CHECK-NEXT: atom.relaxed.sys.shared.cas.b128 dst, [%rd1], cmp, swap;
; CHECK-NEXT: mov.b128 {%rd6, %rd7}, dst;
; CHECK-NEXT: }
-; CHECK-NEXT: st.param.v2.b64 [func_retval0], {%rd4, %rd5};
+; CHECK-NEXT: st.param::func.v2.b64 [func_retval0], {%rd4, %rd5};
; CHECK-NEXT: ret;
%pairold = cmpxchg ptr addrspace(3) %addr, i128 %cmp, i128 %new monotonic monotonic
ret i128 %new
@@ -325,9 +325,9 @@ define i128 @test_cmpxchg_block(ptr %addr, i128 %cmp, i128 %new) {
; CHECK-NEXT: .reg .b64 %rd<8>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [test_cmpxchg_block_param_0];
-; CHECK-NEXT: ld.param.v2.b64 {%rd2, %rd3}, [test_cmpxchg_block_param_1];
-; CHECK-NEXT: ld.param.v2.b64 {%rd4, %rd5}, [test_cmpxchg_block_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_cmpxchg_block_param_0];
+; CHECK-NEXT: ld.param::func.v2.b64 {%rd2, %rd3}, [test_cmpxchg_block_param_1];
+; CHECK-NEXT: ld.param::func.v2.b64 {%rd4, %rd5}, [test_cmpxchg_block_param_2];
; CHECK-NEXT: {
; CHECK-NEXT: .reg .b128 cmp, swap, dst;
; CHECK-NEXT: mov.b128 cmp, {%rd2, %rd3};
@@ -335,7 +335,7 @@ define i128 @test_cmpxchg_block(ptr %addr, i128 %cmp, i128 %new) {
; CHECK-NEXT: atom.relaxed.cta.cas.b128 dst, [%rd1], cmp, swap;
; CHECK-NEXT: mov.b128 {%rd6, %rd7}, dst;
; CHECK-NEXT: }
-; CHECK-NEXT: st.param.v2.b64 [func_retval0], {%rd4, %rd5};
+; CHECK-NEXT: st.param::func.v2.b64 [func_retval0], {%rd4, %rd5};
; CHECK-NEXT: ret;
%pairold = cmpxchg ptr %addr, i128 %cmp, i128 %new syncscope("block") monotonic monotonic
ret i128 %new
@@ -347,9 +347,9 @@ define i128 @test_cmpxchg_cluster(ptr %addr, i128 %cmp, i128 %new) {
; CHECK-NEXT: .reg .b64 %rd<8>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [test_cmpxchg_cluster_param_0];
-; CHECK-NEXT: ld.param.v2.b64 {%rd2, %rd3}, [test_cmpxchg_cluster_param_1];
-; CHECK-NEXT: ld.param.v2.b64 {%rd4, %rd5}, [test_cmpxchg_cluster_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_cmpxchg_cluster_param_0];
+; CHECK-NEXT: ld.param::func.v2.b64 {%rd2, %rd3}, [test_cmpxchg_cluster_param_1];
+; CHECK-NEXT: ld.param::func.v2.b64 {%rd4, %rd5}, [test_cmpxchg_cluster_param_2];
; CHECK-NEXT: {
; CHECK-NEXT: .reg .b128 cmp, swap, dst;
; CHECK-NEXT: mov.b128 cmp, {%rd2, %rd3};
@@ -357,7 +357,7 @@ define i128 @test_cmpxchg_cluster(ptr %addr, i128 %cmp, i128 %new) {
; CHECK-NEXT: atom.relaxed.cluster.cas.b128 dst, [%rd1], cmp, swap;
; CHECK-NEXT: mov.b128 {%rd6, %rd7}, dst;
; CHECK-NEXT: }
-; CHECK-NEXT: st.param.v2.b64 [func_retval0], {%rd4, %rd5};
+; CHECK-NEXT: st.param::func.v2.b64 [func_retval0], {%rd4, %rd5};
; CHECK-NEXT: ret;
%pairold = cmpxchg ptr %addr, i128 %cmp, i128 %new syncscope("cluster") monotonic monotonic
ret i128 %new
@@ -369,9 +369,9 @@ define i128 @test_cmpxchg_gpu(ptr %addr, i128 %cmp, i128 %new) {
; CHECK-NEXT: .reg .b64 %rd<8>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [test_cmpxchg_gpu_param_0];
-; CHECK-NEXT: ld.param.v2.b64 {%rd2, %rd3}, [test_cmpxchg_gpu_param_1];
-; CHECK-NEXT: ld.param.v2.b64 {%rd4, %rd5}, [test_cmpxchg_gpu_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_cmpxchg_gpu_param_0];
+; CHECK-NEXT: ld.param::func.v2.b64 {%rd2, %rd3}, [test_cmpxchg_gpu_param_1];
+; CHECK-NEXT: ld.param::func.v2.b64 {%rd4, %rd5}, [test_cmpxchg_gpu_param_2];
; CHECK-NEXT: {
; CHECK-NEXT: .reg .b128 cmp, swap, dst;
; CHECK-NEXT: mov.b128 cmp, {%rd2, %rd3};
@@ -379,7 +379,7 @@ define i128 @test_cmpxchg_gpu(ptr %addr, i128 %cmp, i128 %new) {
; CHECK-NEXT: atom.relaxed.gpu.cas.b128 dst, [%rd1], cmp, swap;
; CHECK-NEXT: mov.b128 {%rd6, %rd7}, dst;
; CHECK-NEXT: }
-; CHECK-NEXT: st.param.v2.b64 [func_retval0], {%rd4, %rd5};
+; CHECK-NEXT: st.param::func.v2.b64 [func_retval0], {%rd4, %rd5};
; CHECK-NEXT: ret;
%pairold = cmpxchg ptr %addr, i128 %cmp, i128 %new syncscope("device") monotonic monotonic
ret i128 %new
@@ -391,9 +391,9 @@ define i128 @test_cmpxchg_shared_cluster(ptr addrspace(7) %addr, i128 %cmp, i128
; CHECK-NEXT: .reg .b64 %rd<8>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [test_cmpxchg_shared_cluster_param_0];
-; CHECK-NEXT: ld.param.v2.b64 {%rd2, %rd3}, [test_cmpxchg_shared_cluster_param_1];
-; CHECK-NEXT: ld.param.v2.b64 {%rd4, %rd5}, [test_cmpxchg_shared_cluster_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_cmpxchg_shared_cluster_param_0];
+; CHECK-NEXT: ld.param::func.v2.b64 {%rd2, %rd3}, [test_cmpxchg_shared_cluster_param_1];
+; CHECK-NEXT: ld.param::func.v2.b64 {%rd4, %rd5}, [test_cmpxchg_shared_cluster_param_2];
; CHECK-NEXT: {
; CHECK-NEXT: .reg .b128 cmp, swap, dst;
; CHECK-NEXT: mov.b128 cmp, {%rd2, %rd3};
@@ -401,7 +401,7 @@ define i128 @test_cmpxchg_shared_cluster(ptr addrspace(7) %addr, i128 %cmp, i128
; CHECK-NEXT: atom.relaxed.sys.shared::cluster.cas.b128 dst, [%rd1], cmp, swap;
; CHECK-NEXT: mov.b128 {%rd6, %rd7}, dst;
; CHECK-NEXT: }
-; CHECK-NEXT: st.param.v2.b64 [func_retval0], {%rd4, %rd5};
+; CHECK-NEXT: st.param::func.v2.b64 [func_retval0], {%rd4, %rd5};
; CHECK-NEXT: ret;
%pairold = cmpxchg ptr addrspace(7) %addr, i128 %cmp, i128 %new monotonic monotonic
ret i128 %new
@@ -413,9 +413,9 @@ define i128 @test_cmpxchg_monotonic_monotonic(ptr %addr, i128 %cmp, i128 %new) {
; CHECK-NEXT: .reg .b64 %rd<8>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [test_cmpxchg_monotonic_monotonic_param_0];
-; CHECK-NEXT: ld.param.v2.b64 {%rd2, %rd3}, [test_cmpxchg_monotonic_monotonic_param_1];
-; CHECK-NEXT: ld.param.v2.b64 {%rd4, %rd5}, [test_cmpxchg_monotonic_monotonic_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_cmpxchg_monotonic_monotonic_param_0];
+; CHECK-NEXT: ld.param::func.v2.b64 {%rd2, %rd3}, [test_cmpxchg_monotonic_monotonic_param_1];
+; CHECK-NEXT: ld.param::func.v2.b64 {%rd4, %rd5}, [test_cmpxchg_monotonic_monotonic_param_2];
; CHECK-NEXT: {
; CHECK-NEXT: .reg .b128 cmp, swap, dst;
; CHECK-NEXT: mov.b128 cmp, {%rd2, %rd3};
@@ -423,7 +423,7 @@ define i128 @test_cmpxchg_monotonic_monotonic(ptr %addr, i128 %cmp, i128 %new) {
; CHECK-NEXT: atom.relaxed.sys.cas.b128 dst, [%rd1], cmp, swap;
; CHECK-NEXT: mov.b128 {%rd6, %rd7}, dst;
; CHECK-NEXT: }
-; CHECK-NEXT: st.param.v2.b64 [func_retval0], {%rd4, %rd5};
+; CHECK-NEXT: st.param::func.v2.b64 [func_retval0], {%rd4, %rd5};
; CHECK-NEXT: ret;
%pairold = cmpxchg ptr %addr, i128 %cmp, i128 %new monotonic monotonic
ret i128 %new
@@ -435,9 +435,9 @@ define i128 @test_cmpxchg_monotonic_acquire(ptr %addr, i128 %cmp, i128 %new) {
; CHECK-NEXT: .reg .b64 %rd<8>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [test_cmpxchg_monotonic_acquire_param_0];
-; CHECK-NEXT: ld.param.v2.b64 {%rd2, %rd3}, [test_cmpxchg_monotonic_acquire_param_1];
-; CHECK-NEXT: ld.param.v2.b64 {%rd4, %rd5}, [test_cmpxchg_monotonic_acquire_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_cmpxchg_monotonic_acquire_param_0];
+; CHECK-NEXT: ld.param::func.v2.b64 {%rd2, %rd3}, [test_cmpxchg_monotonic_acquire_param_1];
+; CHECK-NEXT: ld.param::func.v2.b64 {%rd4, %rd5}, [test_cmpxchg_monotonic_acquire_param_2];
; CHECK-NEXT: {
; CHECK-NEXT: .reg .b128 cmp, swap, dst;
; CHECK-NEXT: mov.b128 cmp, {%rd2, %rd3};
@@ -445,7 +445,7 @@ define i128 @test_cmpxchg_monotonic_acquire(ptr %addr, i128 %cmp, i128 %new) {
; CHECK-NEXT: atom.acquire.sys.cas.b128 dst, [%rd1], cmp, swap;
; CHECK-NEXT: mov.b128 {%rd6, %rd7}, dst;
; CHECK-NEXT: }
-; CHECK-NEXT: st.param.v2.b64 [func_retval0], {%rd4, %rd5};
+; CHECK-NEXT: st.param::func.v2.b64 [func_retval0], {%rd4, %rd5};
; CHECK-NEXT: ret;
%pairold = cmpxchg ptr %addr, i128 %cmp, i128 %new monotonic acquire
ret i128 %new
@@ -457,10 +457,10 @@ define i128 @test_cmpxchg_monotonic_seq_cst(ptr %addr, i128 %cmp, i128 %new) {
; CHECK-NEXT: .reg .b64 %rd<8>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [test_cmpxchg_monotonic_seq_cst_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_cmpxchg_monotonic_seq_cst_param_0];
; CHECK-NEXT: fence.sc.sys;
-; CHECK-NEXT: ld.param.v2.b64 {%rd2, %rd3}, [test_cmpxchg_monotonic_seq_cst_param_1];
-; CHECK-NEXT: ld.param.v2.b64 {%rd4, %rd5}, [test_cmpxchg_monotonic_seq_cst_param_2];
+; CHECK-NEXT: ld.param::func.v2.b64 {%rd2, %rd3}, [test_cmpxchg_monotonic_seq_cst_param_1];
+; CHECK-NEXT: ld.param::func.v2.b64 {%rd4, %rd5}, [test_cmpxchg_monotonic_seq_cst_param_2];
; CHECK-NEXT: {
; CHECK-NEXT: .reg .b128 cmp, swap, dst;
; CHECK-NEXT: mov.b128 cmp, {%rd2, %rd3};
@@ -468,7 +468,7 @@ define i128 @test_cmpxchg_monotonic_seq_cst(ptr %addr, i128 %cmp, i128 %new) {
; CHECK-NEXT: atom.acquire.sys.cas.b128 dst, [%rd1], cmp, swap;
; CHECK-NEXT: mov.b128 {%rd6, %rd7}, dst;
; CHECK-NEXT: }
-; CHECK-NEXT: st.param.v2.b64 [func_retval0], {%rd4, %rd5};
+; CHECK-NEXT: st.param::func.v2.b64 [func_retval0], {%rd4, %rd5};
; CHECK-NEXT: ret;
%pairold = cmpxchg ptr %addr, i128 %cmp, i128 %new monotonic seq_cst
ret i128 %new
@@ -480,9 +480,9 @@ define i128 @test_cmpxchg_acquire_monotonic(ptr %addr, i128 %cmp, i128 %new) {
; CHECK-NEXT: .reg .b64 %rd<8>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [test_cmpxchg_acquire_monotonic_param_0];
-; CHECK-NEXT: ld.param.v2.b64 {%rd2, %rd3}, [test_cmpxchg_acquire_monotonic_param_1];
-; CHECK-NEXT: ld.param.v2.b64 {%rd4, %rd5}, [test_cmpxchg_acquire_monotonic_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_cmpxchg_acquire_monotonic_param_0];
+; CHECK-NEXT: ld.param::func.v2.b64 {%rd2, %rd3}, [test_cmpxchg_acquire_monotonic_param_1];
+; CHECK-NEXT: ld.param::func.v2.b64 {%rd4, %rd5}, [test_cmpxchg_acquire_monotonic_param_2];
; CHECK-NEXT: {
; CHECK-NEXT: .reg .b128 cmp, swap, dst;
; CHECK-NEXT: mov.b128 cmp, {%rd2, %rd3};
@@ -490,7 +490,7 @@ define i128 @test_cmpxchg_acquire_monotonic(ptr %addr, i128 %cmp, i128 %new) {
; CHECK-NEXT: atom.acquire.sys.cas.b128 dst, [%rd1], cmp, swap;
; CHECK-NEXT: mov.b128 {%rd6, %rd7}, dst;
; CHECK-NEXT: }
-; CHECK-NEXT: st.param.v2.b64 [func_retval0], {%rd4, %rd5};
+; CHECK-NEXT: st.param::func.v2.b64 [func_retval0], {%rd4, %rd5};
; CHECK-NEXT: ret;
%pairold = cmpxchg ptr %addr, i128 %cmp, i128 %new acquire monotonic
ret i128 %new
@@ -502,9 +502,9 @@ define i128 @test_cmpxchg_acquire_acquire(ptr %addr, i128 %cmp, i128 %new) {
; CHECK-NEXT: .reg .b64 %rd<8>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [test_cmpxchg_acquire_acquire_param_0];
-; CHECK-NEXT: ld.param.v2.b64 {%rd2, %rd3}, [test_cmpxchg_acquire_acquire_param_1];
-; CHECK-NEXT: ld.param.v2.b64 {%rd4, %rd5}, [test_cmpxchg_acquire_acquire_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_cmpxchg_acquire_acquire_param_0];
+; CHECK-NEXT: ld.param::func.v2.b64 {%rd2, %rd3}, [test_cmpxchg_acquire_acquire_param_1];
+; CHECK-NEXT: ld.param::func.v2.b64 {%rd4, %rd5}, [test_cmpxchg_acquire_acquire_param_2];
; CHECK-NEXT: {
; CHECK-NEXT: .reg .b128 cmp, swap, dst;
; CHECK-NEXT: mov.b128 cmp, {%rd2, %rd3};
@@ -512,7 +512,7 @@ define i128 @test_cmpxchg_acquire_acquire(ptr %addr, i128 %cmp, i128 %new) {
; CHECK-NEXT: atom.acquire.sys.cas.b128 dst, [%rd1], cmp, swap;
; CHECK-NEXT: mov.b128 {%rd6, %rd7}, dst;
; CHECK-NEXT: }
-; CHECK-NEXT: st.param.v2.b64 [func_retval0], {%rd4, %rd5};
+; CHECK-NEXT: st.param::func.v2.b64 [func_retval0], {%rd4, %rd5};
; CHECK-NEXT: ret;
%pairold = cmpxchg ptr %addr, i128 %cmp, i128 %new acquire acquire
ret i128 %new
@@ -524,10 +524,10 @@ define i128 @test_cmpxchg_acquire_seq_cst(ptr %addr, i128 %cmp, i128 %new) {
; CHECK-NEXT: .reg .b64 %rd<8>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [test_cmpxchg_acquire_seq_cst_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_cmpxchg_acquire_seq_cst_param_0];
; CHECK-NEXT: fence.sc.sys;
-; CHECK-NEXT: ld.param.v2.b64 {%rd2, %rd3}, [test_cmpxchg_acquire_seq_cst_param_1];
-; CHECK-NEXT: ld.param.v2.b64 {%rd4, %rd5}, [test_cmpxchg_acquire_seq_cst_param_2];
+; CHECK-NEXT: ld.param::func.v2.b64 {%rd2, %rd3}, [test_cmpxchg_acquire_seq_cst_param_1];
+; CHECK-NEXT: ld.param::func.v2.b64 {%rd4, %rd5}, [test_cmpxchg_acquire_seq_cst_param_2];
; CHECK-NEXT: {
; CHECK-NEXT: .reg .b128 cmp, swap, dst;
; CHECK-NEXT: mov.b128 cmp, {%rd2, %rd3};
@@ -535,7 +535,7 @@ define i128 @test_cmpxchg_acquire_seq_cst(ptr %addr, i128 %cmp, i128 %new) {
; CHECK-NEXT: atom.acquire.sys.cas.b128 dst, [%rd1], cmp, swap;
; CHECK-NEXT: mov.b128 {%rd6, %rd7}, dst;
; CHECK-NEXT: }
-; CHECK-NEXT: st.param.v2.b64 [func_retval0], {%rd4, %rd5};
+; CHECK-NEXT: st.param::func.v2.b64 [func_retval0], {%rd4, %rd5};
; CHECK-NEXT: ret;
%pairold = cmpxchg ptr %addr, i128 %cmp, i128 %new acquire seq_cst
ret i128 %new
@@ -547,9 +547,9 @@ define i128 @test_cmpxchg_release_monotonic(ptr %addr, i128 %cmp, i128 %new) {
; CHECK-NEXT: .reg .b64 %rd<8>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [test_cmpxchg_release_monotonic_param_0];
-; CHECK-NEXT: ld.param.v2.b64 {%rd2, %rd3}, [test_cmpxchg_release_monotonic_param_1];
-; CHECK-NEXT: ld.param.v2.b64 {%rd4, %rd5}, [test_cmpxchg_release_monotonic_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_cmpxchg_release_monotonic_param_0];
+; CHECK-NEXT: ld.param::func.v2.b64 {%rd2, %rd3}, [test_cmpxchg_release_monotonic_param_1];
+; CHECK-NEXT: ld.param::func.v2.b64 {%rd4, %rd5}, [test_cmpxchg_release_monotonic_param_2];
; CHECK-NEXT: {
; CHECK-NEXT: .reg .b128 cmp, swap, dst;
; CHECK-NEXT: mov.b128 cmp, {%rd2, %rd3};
@@ -557,7 +557,7 @@ define i128 @test_cmpxchg_release_monotonic(ptr %addr, i128 %cmp, i128 %new) {
; CHECK-NEXT: atom.release.sys.cas.b128 dst, [%rd1], cmp, swap;
; CHECK-NEXT: mov.b128 {%rd6, %rd7}, dst;
; CHECK-NEXT: }
-; CHECK-NEXT: st.param.v2.b64 [func_retval0], {%rd4, %rd5};
+; CHECK-NEXT: st.param::func.v2.b64 [func_retval0], {%rd4, %rd5};
; CHECK-NEXT: ret;
%pairold = cmpxchg ptr %addr, i128 %cmp, i128 %new release monotonic
ret i128 %new
@@ -569,9 +569,9 @@ define i128 @test_cmpxchg_release_acquire(ptr %addr, i128 %cmp, i128 %new) {
; CHECK-NEXT: .reg .b64 %rd<8>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [test_cmpxchg_release_acquire_param_0];
-; CHECK-NEXT: ld.param.v2.b64 {%rd2, %rd3}, [test_cmpxchg_release_acquire_param_1];
-; CHECK-NEXT: ld.param.v2.b64 {%rd4, %rd5}, [test_cmpxchg_release_acquire_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_cmpxchg_release_acquire_param_0];
+; CHECK-NEXT: ld.param::func.v2.b64 {%rd2, %rd3}, [test_cmpxchg_release_acquire_param_1];
+; CHECK-NEXT: ld.param::func.v2.b64 {%rd4, %rd5}, [test_cmpxchg_release_acquire_param_2];
; CHECK-NEXT: {
; CHECK-NEXT: .reg .b128 cmp, swap, dst;
; CHECK-NEXT: mov.b128 cmp, {%rd2, %rd3};
@@ -579,7 +579,7 @@ define i128 @test_cmpxchg_release_acquire(ptr %addr, i128 %cmp, i128 %new) {
; CHECK-NEXT: atom.acq_rel.sys.cas.b128 dst, [%rd1], cmp, swap;
; CHECK-NEXT: mov.b128 {%rd6, %rd7}, dst;
; CHECK-NEXT: }
-; CHECK-NEXT: st.param.v2.b64 [func_retval0], {%rd4, %rd5};
+; CHECK-NEXT: st.param::func.v2.b64 [func_retval0], {%rd4, %rd5};
; CHECK-NEXT: ret;
%pairold = cmpxchg ptr %addr, i128 %cmp, i128 %new release acquire
ret i128 %new
@@ -591,10 +591,10 @@ define i128 @test_cmpxchg_release_seq_cst(ptr %addr, i128 %cmp, i128 %new) {
; CHECK-NEXT: .reg .b64 %rd<8>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [test_cmpxchg_release_seq_cst_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_cmpxchg_release_seq_cst_param_0];
; CHECK-NEXT: fence.sc.sys;
-; CHECK-NEXT: ld.param.v2.b64 {%rd2, %rd3}, [test_cmpxchg_release_seq_cst_param_1];
-; CHECK-NEXT: ld.param.v2.b64 {%rd4, %rd5}, [test_cmpxchg_release_seq_cst_param_2];
+; CHECK-NEXT: ld.param::func.v2.b64 {%rd2, %rd3}, [test_cmpxchg_release_seq_cst_param_1];
+; CHECK-NEXT: ld.param::func.v2.b64 {%rd4, %rd5}, [test_cmpxchg_release_seq_cst_param_2];
; CHECK-NEXT: {
; CHECK-NEXT: .reg .b128 cmp, swap, dst;
; CHECK-NEXT: mov.b128 cmp, {%rd2, %rd3};
@@ -602,7 +602,7 @@ define i128 @test_cmpxchg_release_seq_cst(ptr %addr, i128 %cmp, i128 %new) {
; CHECK-NEXT: atom.acquire.sys.cas.b128 dst, [%rd1], cmp, swap;
; CHECK-NEXT: mov.b128 {%rd6, %rd7}, dst;
; CHECK-NEXT: }
-; CHECK-NEXT: st.param.v2.b64 [func_retval0], {%rd4, %rd5};
+; CHECK-NEXT: st.param::func.v2.b64 [func_retval0], {%rd4, %rd5};
; CHECK-NEXT: ret;
%pairold = cmpxchg ptr %addr, i128 %cmp, i128 %new release seq_cst
ret i128 %new
@@ -614,9 +614,9 @@ define i128 @test_cmpxchg_acq_rel_monotonic(ptr %addr, i128 %cmp, i128 %new) {
; CHECK-NEXT: .reg .b64 %rd<8>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [test_cmpxchg_acq_rel_monotonic_param_0];
-; CHECK-NEXT: ld.param.v2.b64 {%rd2, %rd3}, [test_cmpxchg_acq_rel_monotonic_param_1];
-; CHECK-NEXT: ld.param.v2.b64 {%rd4, %rd5}, [test_cmpxchg_acq_rel_monotonic_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_cmpxchg_acq_rel_monotonic_param_0];
+; CHECK-NEXT: ld.param::func.v2.b64 {%rd2, %rd3}, [test_cmpxchg_acq_rel_monotonic_param_1];
+; CHECK-NEXT: ld.param::func.v2.b64 {%rd4, %rd5}, [test_cmpxchg_acq_rel_monotonic_param_2];
; CHECK-NEXT: {
; CHECK-NEXT: .reg .b128 cmp, swap, dst;
; CHECK-NEXT: mov.b128 cmp, {%rd2, %rd3};
@@ -624,7 +624,7 @@ define i128 @test_cmpxchg_acq_rel_monotonic(ptr %addr, i128 %cmp, i128 %new) {
; CHECK-NEXT: atom.acq_rel.sys.cas.b128 dst, [%rd1], cmp, swap;
; CHECK-NEXT: mov.b128 {%rd6, %rd7}, dst;
; CHECK-NEXT: }
-; CHECK-NEXT: st.param.v2.b64 [func_retval0], {%rd4, %rd5};
+; CHECK-NEXT: st.param::func.v2.b64 [func_retval0], {%rd4, %rd5};
; CHECK-NEXT: ret;
%pairold = cmpxchg ptr %addr, i128 %cmp, i128 %new acq_rel monotonic
ret i128 %new
@@ -636,9 +636,9 @@ define i128 @test_cmpxchg_acq_rel_acquire(ptr %addr, i128 %cmp, i128 %new) {
; CHECK-NEXT: .reg .b64 %rd<8>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [test_cmpxchg_acq_rel_acquire_param_0];
-; CHECK-NEXT: ld.param.v2.b64 {%rd2, %rd3}, [test_cmpxchg_acq_rel_acquire_param_1];
-; CHECK-NEXT: ld.param.v2.b64 {%rd4, %rd5}, [test_cmpxchg_acq_rel_acquire_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_cmpxchg_acq_rel_acquire_param_0];
+; CHECK-NEXT: ld.param::func.v2.b64 {%rd2, %rd3}, [test_cmpxchg_acq_rel_acquire_param_1];
+; CHECK-NEXT: ld.param::func.v2.b64 {%rd4, %rd5}, [test_cmpxchg_acq_rel_acquire_param_2];
; CHECK-NEXT: {
; CHECK-NEXT: .reg .b128 cmp, swap, dst;
; CHECK-NEXT: mov.b128 cmp, {%rd2, %rd3};
@@ -646,7 +646,7 @@ define i128 @test_cmpxchg_acq_rel_acquire(ptr %addr, i128 %cmp, i128 %new) {
; CHECK-NEXT: atom.acq_rel.sys.cas.b128 dst, [%rd1], cmp, swap;
; CHECK-NEXT: mov.b128 {%rd6, %rd7}, dst;
; CHECK-NEXT: }
-; CHECK-NEXT: st.param.v2.b64 [func_retval0], {%rd4, %rd5};
+; CHECK-NEXT: st.param::func.v2.b64 [func_retval0], {%rd4, %rd5};
; CHECK-NEXT: ret;
%pairold = cmpxchg ptr %addr, i128 %cmp, i128 %new acq_rel acquire
ret i128 %new
@@ -658,10 +658,10 @@ define i128 @test_cmpxchg_acq_rel_seq_cst(ptr %addr, i128 %cmp, i128 %new) {
; CHECK-NEXT: .reg .b64 %rd<8>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [test_cmpxchg_acq_rel_seq_cst_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_cmpxchg_acq_rel_seq_cst_param_0];
; CHECK-NEXT: fence.sc.sys;
-; CHECK-NEXT: ld.param.v2.b64 {%rd2, %rd3}, [test_cmpxchg_acq_rel_seq_cst_param_1];
-; CHECK-NEXT: ld.param.v2.b64 {%rd4, %rd5}, [test_cmpxchg_acq_rel_seq_cst_param_2];
+; CHECK-NEXT: ld.param::func.v2.b64 {%rd2, %rd3}, [test_cmpxchg_acq_rel_seq_cst_param_1];
+; CHECK-NEXT: ld.param::func.v2.b64 {%rd4, %rd5}, [test_cmpxchg_acq_rel_seq_cst_param_2];
; CHECK-NEXT: {
; CHECK-NEXT: .reg .b128 cmp, swap, dst;
; CHECK-NEXT: mov.b128 cmp, {%rd2, %rd3};
@@ -669,7 +669,7 @@ define i128 @test_cmpxchg_acq_rel_seq_cst(ptr %addr, i128 %cmp, i128 %new) {
; CHECK-NEXT: atom.acquire.sys.cas.b128 dst, [%rd1], cmp, swap;
; CHECK-NEXT: mov.b128 {%rd6, %rd7}, dst;
; CHECK-NEXT: }
-; CHECK-NEXT: st.param.v2.b64 [func_retval0], {%rd4, %rd5};
+; CHECK-NEXT: st.param::func.v2.b64 [func_retval0], {%rd4, %rd5};
; CHECK-NEXT: ret;
%pairold = cmpxchg ptr %addr, i128 %cmp, i128 %new acq_rel seq_cst
ret i128 %new
@@ -681,10 +681,10 @@ define i128 @test_cmpxchg_seq_cst_monotonic(ptr %addr, i128 %cmp, i128 %new) {
; CHECK-NEXT: .reg .b64 %rd<8>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [test_cmpxchg_seq_cst_monotonic_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_cmpxchg_seq_cst_monotonic_param_0];
; CHECK-NEXT: fence.sc.sys;
-; CHECK-NEXT: ld.param.v2.b64 {%rd2, %rd3}, [test_cmpxchg_seq_cst_monotonic_param_1];
-; CHECK-NEXT: ld.param.v2.b64 {%rd4, %rd5}, [test_cmpxchg_seq_cst_monotonic_param_2];
+; CHECK-NEXT: ld.param::func.v2.b64 {%rd2, %rd3}, [test_cmpxchg_seq_cst_monotonic_param_1];
+; CHECK-NEXT: ld.param::func.v2.b64 {%rd4, %rd5}, [test_cmpxchg_seq_cst_monotonic_param_2];
; CHECK-NEXT: {
; CHECK-NEXT: .reg .b128 cmp, swap, dst;
; CHECK-NEXT: mov.b128 cmp, {%rd2, %rd3};
@@ -692,7 +692,7 @@ define i128 @test_cmpxchg_seq_cst_monotonic(ptr %addr, i128 %cmp, i128 %new) {
; CHECK-NEXT: atom.acquire.sys.cas.b128 dst, [%rd1], cmp, swap;
; CHECK-NEXT: mov.b128 {%rd6, %rd7}, dst;
; CHECK-NEXT: }
-; CHECK-NEXT: st.param.v2.b64 [func_retval0], {%rd4, %rd5};
+; CHECK-NEXT: st.param::func.v2.b64 [func_retval0], {%rd4, %rd5};
; CHECK-NEXT: ret;
%pairold = cmpxchg ptr %addr, i128 %cmp, i128 %new seq_cst monotonic
ret i128 %new
@@ -704,10 +704,10 @@ define i128 @test_cmpxchg_seq_cst_acquire(ptr %addr, i128 %cmp, i128 %new) {
; CHECK-NEXT: .reg .b64 %rd<8>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [test_cmpxchg_seq_cst_acquire_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_cmpxchg_seq_cst_acquire_param_0];
; CHECK-NEXT: fence.sc.sys;
-; CHECK-NEXT: ld.param.v2.b64 {%rd2, %rd3}, [test_cmpxchg_seq_cst_acquire_param_1];
-; CHECK-NEXT: ld.param.v2.b64 {%rd4, %rd5}, [test_cmpxchg_seq_cst_acquire_param_2];
+; CHECK-NEXT: ld.param::func.v2.b64 {%rd2, %rd3}, [test_cmpxchg_seq_cst_acquire_param_1];
+; CHECK-NEXT: ld.param::func.v2.b64 {%rd4, %rd5}, [test_cmpxchg_seq_cst_acquire_param_2];
; CHECK-NEXT: {
; CHECK-NEXT: .reg .b128 cmp, swap, dst;
; CHECK-NEXT: mov.b128 cmp, {%rd2, %rd3};
@@ -715,7 +715,7 @@ define i128 @test_cmpxchg_seq_cst_acquire(ptr %addr, i128 %cmp, i128 %new) {
; CHECK-NEXT: atom.acquire.sys.cas.b128 dst, [%rd1], cmp, swap;
; CHECK-NEXT: mov.b128 {%rd6, %rd7}, dst;
; CHECK-NEXT: }
-; CHECK-NEXT: st.param.v2.b64 [func_retval0], {%rd4, %rd5};
+; CHECK-NEXT: st.param::func.v2.b64 [func_retval0], {%rd4, %rd5};
; CHECK-NEXT: ret;
%pairold = cmpxchg ptr %addr, i128 %cmp, i128 %new seq_cst acquire
ret i128 %new
@@ -727,10 +727,10 @@ define i128 @test_cmpxchg_seq_cst_seq_cst(ptr %addr, i128 %cmp, i128 %new) {
; CHECK-NEXT: .reg .b64 %rd<8>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [test_cmpxchg_seq_cst_seq_cst_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_cmpxchg_seq_cst_seq_cst_param_0];
; CHECK-NEXT: fence.sc.sys;
-; CHECK-NEXT: ld.param.v2.b64 {%rd2, %rd3}, [test_cmpxchg_seq_cst_seq_cst_param_1];
-; CHECK-NEXT: ld.param.v2.b64 {%rd4, %rd5}, [test_cmpxchg_seq_cst_seq_cst_param_2];
+; CHECK-NEXT: ld.param::func.v2.b64 {%rd2, %rd3}, [test_cmpxchg_seq_cst_seq_cst_param_1];
+; CHECK-NEXT: ld.param::func.v2.b64 {%rd4, %rd5}, [test_cmpxchg_seq_cst_seq_cst_param_2];
; CHECK-NEXT: {
; CHECK-NEXT: .reg .b128 cmp, swap, dst;
; CHECK-NEXT: mov.b128 cmp, {%rd2, %rd3};
@@ -738,7 +738,7 @@ define i128 @test_cmpxchg_seq_cst_seq_cst(ptr %addr, i128 %cmp, i128 %new) {
; CHECK-NEXT: atom.acquire.sys.cas.b128 dst, [%rd1], cmp, swap;
; CHECK-NEXT: mov.b128 {%rd6, %rd7}, dst;
; CHECK-NEXT: }
-; CHECK-NEXT: st.param.v2.b64 [func_retval0], {%rd4, %rd5};
+; CHECK-NEXT: st.param::func.v2.b64 [func_retval0], {%rd4, %rd5};
; CHECK-NEXT: ret;
%pairold = cmpxchg ptr %addr, i128 %cmp, i128 %new seq_cst seq_cst
ret i128 %new
@@ -751,8 +751,8 @@ define i128 @test_atomicrmw_and(ptr %ptr, i128 %val) {
; CHECK-NEXT: .reg .b64 %rd<14>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.v2.b64 {%rd4, %rd5}, [test_atomicrmw_and_param_1];
-; CHECK-NEXT: ld.param.b64 %rd3, [test_atomicrmw_and_param_0];
+; CHECK-NEXT: ld.param::func.v2.b64 {%rd4, %rd5}, [test_atomicrmw_and_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd3, [test_atomicrmw_and_param_0];
; CHECK-NEXT: mov.b64 %rd6, 0;
; CHECK-NEXT: {
; CHECK-NEXT: .reg .b128 cmp, swap, dst;
@@ -780,7 +780,7 @@ define i128 @test_atomicrmw_and(ptr %ptr, i128 %val) {
; CHECK-NEXT: mov.b64 %rd13, %rd2;
; CHECK-NEXT: @%p1 bra $L__BB34_1;
; CHECK-NEXT: // %bb.2: // %atomicrmw.end
-; CHECK-NEXT: st.param.v2.b64 [func_retval0], {%rd1, %rd2};
+; CHECK-NEXT: st.param::func.v2.b64 [func_retval0], {%rd1, %rd2};
; CHECK-NEXT: ret;
%ret = atomicrmw and ptr %ptr, i128 %val monotonic
ret i128 %ret
@@ -793,8 +793,8 @@ define i128 @test_atomicrmw_or(ptr %ptr, i128 %val) {
; CHECK-NEXT: .reg .b64 %rd<14>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.v2.b64 {%rd4, %rd5}, [test_atomicrmw_or_param_1];
-; CHECK-NEXT: ld.param.b64 %rd3, [test_atomicrmw_or_param_0];
+; CHECK-NEXT: ld.param::func.v2.b64 {%rd4, %rd5}, [test_atomicrmw_or_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd3, [test_atomicrmw_or_param_0];
; CHECK-NEXT: mov.b64 %rd6, 0;
; CHECK-NEXT: {
; CHECK-NEXT: .reg .b128 cmp, swap, dst;
@@ -822,7 +822,7 @@ define i128 @test_atomicrmw_or(ptr %ptr, i128 %val) {
; CHECK-NEXT: mov.b64 %rd13, %rd2;
; CHECK-NEXT: @%p1 bra $L__BB35_1;
; CHECK-NEXT: // %bb.2: // %atomicrmw.end
-; CHECK-NEXT: st.param.v2.b64 [func_retval0], {%rd1, %rd2};
+; CHECK-NEXT: st.param::func.v2.b64 [func_retval0], {%rd1, %rd2};
; CHECK-NEXT: ret;
%ret = atomicrmw or ptr %ptr, i128 %val monotonic
ret i128 %ret
@@ -835,8 +835,8 @@ define i128 @test_atomicrmw_xor(ptr %ptr, i128 %val) {
; CHECK-NEXT: .reg .b64 %rd<14>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.v2.b64 {%rd4, %rd5}, [test_atomicrmw_xor_param_1];
-; CHECK-NEXT: ld.param.b64 %rd3, [test_atomicrmw_xor_param_0];
+; CHECK-NEXT: ld.param::func.v2.b64 {%rd4, %rd5}, [test_atomicrmw_xor_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd3, [test_atomicrmw_xor_param_0];
; CHECK-NEXT: mov.b64 %rd6, 0;
; CHECK-NEXT: {
; CHECK-NEXT: .reg .b128 cmp, swap, dst;
@@ -864,7 +864,7 @@ define i128 @test_atomicrmw_xor(ptr %ptr, i128 %val) {
; CHECK-NEXT: mov.b64 %rd13, %rd2;
; CHECK-NEXT: @%p1 bra $L__BB36_1;
; CHECK-NEXT: // %bb.2: // %atomicrmw.end
-; CHECK-NEXT: st.param.v2.b64 [func_retval0], {%rd1, %rd2};
+; CHECK-NEXT: st.param::func.v2.b64 [func_retval0], {%rd1, %rd2};
; CHECK-NEXT: ret;
%ret = atomicrmw xor ptr %ptr, i128 %val monotonic
ret i128 %ret
@@ -877,8 +877,8 @@ define i128 @test_atomicrmw_min(ptr %ptr, i128 %val) {
; CHECK-NEXT: .reg .b64 %rd<14>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.v2.b64 {%rd4, %rd5}, [test_atomicrmw_min_param_1];
-; CHECK-NEXT: ld.param.b64 %rd3, [test_atomicrmw_min_param_0];
+; CHECK-NEXT: ld.param::func.v2.b64 {%rd4, %rd5}, [test_atomicrmw_min_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd3, [test_atomicrmw_min_param_0];
; CHECK-NEXT: mov.b64 %rd6, 0;
; CHECK-NEXT: {
; CHECK-NEXT: .reg .b128 cmp, swap, dst;
@@ -911,7 +911,7 @@ define i128 @test_atomicrmw_min(ptr %ptr, i128 %val) {
; CHECK-NEXT: mov.b64 %rd13, %rd2;
; CHECK-NEXT: @%p6 bra $L__BB37_1;
; CHECK-NEXT: // %bb.2: // %atomicrmw.end
-; CHECK-NEXT: st.param.v2.b64 [func_retval0], {%rd1, %rd2};
+; CHECK-NEXT: st.param::func.v2.b64 [func_retval0], {%rd1, %rd2};
; CHECK-NEXT: ret;
%ret = atomicrmw min ptr %ptr, i128 %val monotonic
ret i128 %ret
@@ -924,8 +924,8 @@ define i128 @test_atomicrmw_max(ptr %ptr, i128 %val) {
; CHECK-NEXT: .reg .b64 %rd<14>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.v2.b64 {%rd4, %rd5}, [test_atomicrmw_max_param_1];
-; CHECK-NEXT: ld.param.b64 %rd3, [test_atomicrmw_max_param_0];
+; CHECK-NEXT: ld.param::func.v2.b64 {%rd4, %rd5}, [test_atomicrmw_max_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd3, [test_atomicrmw_max_param_0];
; CHECK-NEXT: mov.b64 %rd6, 0;
; CHECK-NEXT: {
; CHECK-NEXT: .reg .b128 cmp, swap, dst;
@@ -958,7 +958,7 @@ define i128 @test_atomicrmw_max(ptr %ptr, i128 %val) {
; CHECK-NEXT: mov.b64 %rd13, %rd2;
; CHECK-NEXT: @%p6 bra $L__BB38_1;
; CHECK-NEXT: // %bb.2: // %atomicrmw.end
-; CHECK-NEXT: st.param.v2.b64 [func_retval0], {%rd1, %rd2};
+; CHECK-NEXT: st.param::func.v2.b64 [func_retval0], {%rd1, %rd2};
; CHECK-NEXT: ret;
%ret = atomicrmw max ptr %ptr, i128 %val monotonic
ret i128 %ret
@@ -971,8 +971,8 @@ define i128 @test_atomicrmw_umin(ptr %ptr, i128 %val) {
; CHECK-NEXT: .reg .b64 %rd<14>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.v2.b64 {%rd4, %rd5}, [test_atomicrmw_umin_param_1];
-; CHECK-NEXT: ld.param.b64 %rd3, [test_atomicrmw_umin_param_0];
+; CHECK-NEXT: ld.param::func.v2.b64 {%rd4, %rd5}, [test_atomicrmw_umin_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd3, [test_atomicrmw_umin_param_0];
; CHECK-NEXT: mov.b64 %rd6, 0;
; CHECK-NEXT: {
; CHECK-NEXT: .reg .b128 cmp, swap, dst;
@@ -1005,7 +1005,7 @@ define i128 @test_atomicrmw_umin(ptr %ptr, i128 %val) {
; CHECK-NEXT: mov.b64 %rd13, %rd2;
; CHECK-NEXT: @%p6 bra $L__BB39_1;
; CHECK-NEXT: // %bb.2: // %atomicrmw.end
-; CHECK-NEXT: st.param.v2.b64 [func_retval0], {%rd1, %rd2};
+; CHECK-NEXT: st.param::func.v2.b64 [func_retval0], {%rd1, %rd2};
; CHECK-NEXT: ret;
%ret = atomicrmw umin ptr %ptr, i128 %val monotonic
ret i128 %ret
@@ -1018,8 +1018,8 @@ define i128 @test_atomicrmw_umax(ptr %ptr, i128 %val) {
; CHECK-NEXT: .reg .b64 %rd<14>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.v2.b64 {%rd4, %rd5}, [test_atomicrmw_umax_param_1];
-; CHECK-NEXT: ld.param.b64 %rd3, [test_atomicrmw_umax_param_0];
+; CHECK-NEXT: ld.param::func.v2.b64 {%rd4, %rd5}, [test_atomicrmw_umax_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd3, [test_atomicrmw_umax_param_0];
; CHECK-NEXT: mov.b64 %rd6, 0;
; CHECK-NEXT: {
; CHECK-NEXT: .reg .b128 cmp, swap, dst;
@@ -1052,7 +1052,7 @@ define i128 @test_atomicrmw_umax(ptr %ptr, i128 %val) {
; CHECK-NEXT: mov.b64 %rd13, %rd2;
; CHECK-NEXT: @%p6 bra $L__BB40_1;
; CHECK-NEXT: // %bb.2: // %atomicrmw.end
-; CHECK-NEXT: st.param.v2.b64 [func_retval0], {%rd1, %rd2};
+; CHECK-NEXT: st.param::func.v2.b64 [func_retval0], {%rd1, %rd2};
; CHECK-NEXT: ret;
%ret = atomicrmw umax ptr %ptr, i128 %val monotonic
ret i128 %ret
diff --git a/llvm/test/CodeGen/NVPTX/clusterlaunchcontrol-multicast.ll b/llvm/test/CodeGen/NVPTX/clusterlaunchcontrol-multicast.ll
index 40a73a7b0deee..62020429ac728 100644
--- a/llvm/test/CodeGen/NVPTX/clusterlaunchcontrol-multicast.ll
+++ b/llvm/test/CodeGen/NVPTX/clusterlaunchcontrol-multicast.ll
@@ -35,8 +35,8 @@ define void @nvvm_clusterlaunchcontrol_try_cancel_multicast(
; CHECK-PTX-SHARED64-NEXT: .reg .b64 %rd<3>;
; CHECK-PTX-SHARED64-EMPTY:
; CHECK-PTX-SHARED64-NEXT: // %bb.0:
-; CHECK-PTX-SHARED64-NEXT: ld.param.b64 %rd1, [nvvm_clusterlaunchcontrol_try_cancel_multicast_param_0];
-; CHECK-PTX-SHARED64-NEXT: ld.param.b64 %rd2, [nvvm_clusterlaunchcontrol_try_cancel_multicast_param_1];
+; CHECK-PTX-SHARED64-NEXT: ld.param::func.b64 %rd1, [nvvm_clusterlaunchcontrol_try_cancel_multicast_param_0];
+; CHECK-PTX-SHARED64-NEXT: ld.param::func.b64 %rd2, [nvvm_clusterlaunchcontrol_try_cancel_multicast_param_1];
; CHECK-PTX-SHARED64-NEXT: clusterlaunchcontrol.try_cancel.async.shared::cta.mbarrier::complete_tx::bytes.multicast::cluster::all.b128 [%rd1], [%rd2];
; CHECK-PTX-SHARED64-NEXT: ret;
;
@@ -45,8 +45,8 @@ define void @nvvm_clusterlaunchcontrol_try_cancel_multicast(
; CHECK-PTX-SHARED32-NEXT: .reg .b32 %r<3>;
; CHECK-PTX-SHARED32-EMPTY:
; CHECK-PTX-SHARED32-NEXT: // %bb.0:
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r1, [nvvm_clusterlaunchcontrol_try_cancel_multicast_param_0];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r2, [nvvm_clusterlaunchcontrol_try_cancel_multicast_param_1];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r1, [nvvm_clusterlaunchcontrol_try_cancel_multicast_param_0];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r2, [nvvm_clusterlaunchcontrol_try_cancel_multicast_param_1];
; CHECK-PTX-SHARED32-NEXT: clusterlaunchcontrol.try_cancel.async.shared::cta.mbarrier::complete_tx::bytes.multicast::cluster::all.b128 [%r1], [%r2];
; CHECK-PTX-SHARED32-NEXT: ret;
ptr addrspace(3) %saddr, ptr addrspace(3) %smbar,
diff --git a/llvm/test/CodeGen/NVPTX/clusterlaunchcontrol.ll b/llvm/test/CodeGen/NVPTX/clusterlaunchcontrol.ll
index c35f6c7f72045..a8ffe043e3590 100644
--- a/llvm/test/CodeGen/NVPTX/clusterlaunchcontrol.ll
+++ b/llvm/test/CodeGen/NVPTX/clusterlaunchcontrol.ll
@@ -10,8 +10,8 @@ define void @nvvm_clusterlaunchcontrol_try_cancel(
; CHECK-PTX-SHARED64-NEXT: .reg .b64 %rd<3>;
; CHECK-PTX-SHARED64-EMPTY:
; CHECK-PTX-SHARED64-NEXT: // %bb.0:
-; CHECK-PTX-SHARED64-NEXT: ld.param.b64 %rd1, [nvvm_clusterlaunchcontrol_try_cancel_param_0];
-; CHECK-PTX-SHARED64-NEXT: ld.param.b64 %rd2, [nvvm_clusterlaunchcontrol_try_cancel_param_1];
+; CHECK-PTX-SHARED64-NEXT: ld.param::func.b64 %rd1, [nvvm_clusterlaunchcontrol_try_cancel_param_0];
+; CHECK-PTX-SHARED64-NEXT: ld.param::func.b64 %rd2, [nvvm_clusterlaunchcontrol_try_cancel_param_1];
; CHECK-PTX-SHARED64-NEXT: clusterlaunchcontrol.try_cancel.async.shared::cta.mbarrier::complete_tx::bytes.b128 [%rd1], [%rd2];
; CHECK-PTX-SHARED64-NEXT: ret;
;
@@ -20,8 +20,8 @@ define void @nvvm_clusterlaunchcontrol_try_cancel(
; CHECK-PTX-SHARED32-NEXT: .reg .b32 %r<3>;
; CHECK-PTX-SHARED32-EMPTY:
; CHECK-PTX-SHARED32-NEXT: // %bb.0:
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r1, [nvvm_clusterlaunchcontrol_try_cancel_param_0];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r2, [nvvm_clusterlaunchcontrol_try_cancel_param_1];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r1, [nvvm_clusterlaunchcontrol_try_cancel_param_0];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r2, [nvvm_clusterlaunchcontrol_try_cancel_param_1];
; CHECK-PTX-SHARED32-NEXT: clusterlaunchcontrol.try_cancel.async.shared::cta.mbarrier::complete_tx::bytes.b128 [%r1], [%r2];
; CHECK-PTX-SHARED32-NEXT: ret;
ptr addrspace(3) %saddr, ptr addrspace(3) %smbar,
@@ -39,14 +39,14 @@ define i32 @nvvm_clusterlaunchcontrol_query_cancel_is_canceled(i128 %try_cancel_
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.v2.b64 {%rd1, %rd2}, [nvvm_clusterlaunchcontrol_query_cancel_is_canceled_param_0];
+; CHECK-NEXT: ld.param::func.v2.b64 {%rd1, %rd2}, [nvvm_clusterlaunchcontrol_query_cancel_is_canceled_param_0];
; CHECK-NEXT: {
; CHECK-NEXT: .reg .b128 %clc_handle;
; CHECK-NEXT: mov.b128 %clc_handle, {%rd1, %rd2};
; CHECK-NEXT: clusterlaunchcontrol.query_cancel.is_canceled.pred.b128 %p1, %clc_handle;
; CHECK-NEXT: }
; CHECK-NEXT: selp.b32 %r1, 1, 0, %p1;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
%v0 = call i1 @llvm.nvvm.clusterlaunchcontrol.query_cancel.is_canceled(i128 %try_cancel_response)
%v2 = zext i1 %v0 to i32
@@ -60,13 +60,13 @@ define i32 @nvvm_clusterlaunchcontrol_query_cancel_get_first_ctaid_x(i128 %try_c
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.v2.b64 {%rd1, %rd2}, [nvvm_clusterlaunchcontrol_query_cancel_get_first_ctaid_x_param_0];
+; CHECK-NEXT: ld.param::func.v2.b64 {%rd1, %rd2}, [nvvm_clusterlaunchcontrol_query_cancel_get_first_ctaid_x_param_0];
; CHECK-NEXT: {
; CHECK-NEXT: .reg .b128 %clc_handle;
; CHECK-NEXT: mov.b128 %clc_handle, {%rd1, %rd2};
; CHECK-NEXT: clusterlaunchcontrol.query_cancel.get_first_ctaid::x.b32.b128 %r1, %clc_handle;
; CHECK-NEXT: }
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
%v0 = call i32 @llvm.nvvm.clusterlaunchcontrol.query_cancel.get_first_ctaid.x(i128 %try_cancel_response)
ret i32 %v0;
@@ -79,13 +79,13 @@ define i32 @nvvm_clusterlaunchcontrol_query_cancel_get_first_ctaid_y(i128 %try_c
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.v2.b64 {%rd1, %rd2}, [nvvm_clusterlaunchcontrol_query_cancel_get_first_ctaid_y_param_0];
+; CHECK-NEXT: ld.param::func.v2.b64 {%rd1, %rd2}, [nvvm_clusterlaunchcontrol_query_cancel_get_first_ctaid_y_param_0];
; CHECK-NEXT: {
; CHECK-NEXT: .reg .b128 %clc_handle;
; CHECK-NEXT: mov.b128 %clc_handle, {%rd1, %rd2};
; CHECK-NEXT: clusterlaunchcontrol.query_cancel.get_first_ctaid::y.b32.b128 %r1, %clc_handle;
; CHECK-NEXT: }
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
%v0 = call i32 @llvm.nvvm.clusterlaunchcontrol.query_cancel.get_first_ctaid.y(i128 %try_cancel_response)
ret i32 %v0;
@@ -98,13 +98,13 @@ define i32 @nvvm_clusterlaunchcontrol_query_cancel_get_first_ctaid_z(i128 %try_c
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.v2.b64 {%rd1, %rd2}, [nvvm_clusterlaunchcontrol_query_cancel_get_first_ctaid_z_param_0];
+; CHECK-NEXT: ld.param::func.v2.b64 {%rd1, %rd2}, [nvvm_clusterlaunchcontrol_query_cancel_get_first_ctaid_z_param_0];
; CHECK-NEXT: {
; CHECK-NEXT: .reg .b128 %clc_handle;
; CHECK-NEXT: mov.b128 %clc_handle, {%rd1, %rd2};
; CHECK-NEXT: clusterlaunchcontrol.query_cancel.get_first_ctaid::z.b32.b128 %r1, %clc_handle;
; CHECK-NEXT: }
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
%v0 = call i32 @llvm.nvvm.clusterlaunchcontrol.query_cancel.get_first_ctaid.z(i128 %try_cancel_response)
ret i32 %v0;
diff --git a/llvm/test/CodeGen/NVPTX/cmpxchg-sm90.ll b/llvm/test/CodeGen/NVPTX/cmpxchg-sm90.ll
index 8c34840f3268f..7a28b55af3961 100644
--- a/llvm/test/CodeGen/NVPTX/cmpxchg-sm90.ll
+++ b/llvm/test/CodeGen/NVPTX/cmpxchg-sm90.ll
@@ -12,10 +12,10 @@ define i8 @monotonic_monotonic_i8_global_cta(ptr addrspace(1) %addr, i8 %cmp, i8
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b8 %rs1, [monotonic_monotonic_i8_global_cta_param_2];
-; SM90-NEXT: ld.param.b64 %rd2, [monotonic_monotonic_i8_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b8 %rs1, [monotonic_monotonic_i8_global_cta_param_2];
+; SM90-NEXT: ld.param::func.b64 %rd2, [monotonic_monotonic_i8_global_cta_param_0];
; SM90-NEXT: and.b64 %rd1, %rd2, -4;
-; SM90-NEXT: ld.param.b8 %r7, [monotonic_monotonic_i8_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b8 %r7, [monotonic_monotonic_i8_global_cta_param_1];
; SM90-NEXT: cvt.u32.u64 %r8, %rd2;
; SM90-NEXT: and.b32 %r9, %r8, 3;
; SM90-NEXT: shl.b32 %r1, %r9, 3;
@@ -41,7 +41,7 @@ define i8 @monotonic_monotonic_i8_global_cta(ptr addrspace(1) %addr, i8 %cmp, i8
; SM90-NEXT: mov.b32 %r16, %r6;
; SM90-NEXT: @%p2 bra $L__BB0_1;
; SM90-NEXT: $L__BB0_3: // %partword.cmpxchg.end
-; SM90-NEXT: st.param.b32 [func_retval0], %r12;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r12;
; SM90-NEXT: ret;
%pairold = cmpxchg ptr addrspace(1) %addr, i8 %cmp, i8 %new syncscope("block") monotonic monotonic
ret i8 %new
@@ -56,10 +56,10 @@ define i8 @monotonic_acquire_i8_global_cta(ptr addrspace(1) %addr, i8 %cmp, i8 %
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b8 %rs1, [monotonic_acquire_i8_global_cta_param_2];
-; SM90-NEXT: ld.param.b64 %rd2, [monotonic_acquire_i8_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b8 %rs1, [monotonic_acquire_i8_global_cta_param_2];
+; SM90-NEXT: ld.param::func.b64 %rd2, [monotonic_acquire_i8_global_cta_param_0];
; SM90-NEXT: and.b64 %rd1, %rd2, -4;
-; SM90-NEXT: ld.param.b8 %r7, [monotonic_acquire_i8_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b8 %r7, [monotonic_acquire_i8_global_cta_param_1];
; SM90-NEXT: cvt.u32.u64 %r8, %rd2;
; SM90-NEXT: and.b32 %r9, %r8, 3;
; SM90-NEXT: shl.b32 %r1, %r9, 3;
@@ -86,7 +86,7 @@ define i8 @monotonic_acquire_i8_global_cta(ptr addrspace(1) %addr, i8 %cmp, i8 %
; SM90-NEXT: @%p2 bra $L__BB1_1;
; SM90-NEXT: $L__BB1_3: // %partword.cmpxchg.end
; SM90-NEXT: fence.acquire.cta;
-; SM90-NEXT: st.param.b32 [func_retval0], %r12;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r12;
; SM90-NEXT: ret;
%pairold = cmpxchg ptr addrspace(1) %addr, i8 %cmp, i8 %new syncscope("block") monotonic acquire
ret i8 %new
@@ -101,10 +101,10 @@ define i8 @monotonic_seq_cst_i8_global_cta(ptr addrspace(1) %addr, i8 %cmp, i8 %
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b8 %rs1, [monotonic_seq_cst_i8_global_cta_param_2];
-; SM90-NEXT: ld.param.b64 %rd2, [monotonic_seq_cst_i8_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b8 %rs1, [monotonic_seq_cst_i8_global_cta_param_2];
+; SM90-NEXT: ld.param::func.b64 %rd2, [monotonic_seq_cst_i8_global_cta_param_0];
; SM90-NEXT: fence.sc.cta;
-; SM90-NEXT: ld.param.b8 %r7, [monotonic_seq_cst_i8_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b8 %r7, [monotonic_seq_cst_i8_global_cta_param_1];
; SM90-NEXT: and.b64 %rd1, %rd2, -4;
; SM90-NEXT: cvt.u32.u64 %r8, %rd2;
; SM90-NEXT: and.b32 %r9, %r8, 3;
@@ -132,7 +132,7 @@ define i8 @monotonic_seq_cst_i8_global_cta(ptr addrspace(1) %addr, i8 %cmp, i8 %
; SM90-NEXT: @%p2 bra $L__BB2_1;
; SM90-NEXT: $L__BB2_3: // %partword.cmpxchg.end
; SM90-NEXT: fence.acquire.cta;
-; SM90-NEXT: st.param.b32 [func_retval0], %r12;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r12;
; SM90-NEXT: ret;
%pairold = cmpxchg ptr addrspace(1) %addr, i8 %cmp, i8 %new syncscope("block") monotonic seq_cst
ret i8 %new
@@ -147,10 +147,10 @@ define i8 @acquire_monotonic_i8_global_cta(ptr addrspace(1) %addr, i8 %cmp, i8 %
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b8 %rs1, [acquire_monotonic_i8_global_cta_param_2];
-; SM90-NEXT: ld.param.b64 %rd2, [acquire_monotonic_i8_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b8 %rs1, [acquire_monotonic_i8_global_cta_param_2];
+; SM90-NEXT: ld.param::func.b64 %rd2, [acquire_monotonic_i8_global_cta_param_0];
; SM90-NEXT: and.b64 %rd1, %rd2, -4;
-; SM90-NEXT: ld.param.b8 %r7, [acquire_monotonic_i8_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b8 %r7, [acquire_monotonic_i8_global_cta_param_1];
; SM90-NEXT: cvt.u32.u64 %r8, %rd2;
; SM90-NEXT: and.b32 %r9, %r8, 3;
; SM90-NEXT: shl.b32 %r1, %r9, 3;
@@ -177,7 +177,7 @@ define i8 @acquire_monotonic_i8_global_cta(ptr addrspace(1) %addr, i8 %cmp, i8 %
; SM90-NEXT: @%p2 bra $L__BB3_1;
; SM90-NEXT: $L__BB3_3: // %partword.cmpxchg.end
; SM90-NEXT: fence.acquire.cta;
-; SM90-NEXT: st.param.b32 [func_retval0], %r12;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r12;
; SM90-NEXT: ret;
%pairold = cmpxchg ptr addrspace(1) %addr, i8 %cmp, i8 %new syncscope("block") acquire monotonic
ret i8 %new
@@ -192,10 +192,10 @@ define i8 @acquire_acquire_i8_global_cta(ptr addrspace(1) %addr, i8 %cmp, i8 %ne
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b8 %rs1, [acquire_acquire_i8_global_cta_param_2];
-; SM90-NEXT: ld.param.b64 %rd2, [acquire_acquire_i8_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b8 %rs1, [acquire_acquire_i8_global_cta_param_2];
+; SM90-NEXT: ld.param::func.b64 %rd2, [acquire_acquire_i8_global_cta_param_0];
; SM90-NEXT: and.b64 %rd1, %rd2, -4;
-; SM90-NEXT: ld.param.b8 %r7, [acquire_acquire_i8_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b8 %r7, [acquire_acquire_i8_global_cta_param_1];
; SM90-NEXT: cvt.u32.u64 %r8, %rd2;
; SM90-NEXT: and.b32 %r9, %r8, 3;
; SM90-NEXT: shl.b32 %r1, %r9, 3;
@@ -222,7 +222,7 @@ define i8 @acquire_acquire_i8_global_cta(ptr addrspace(1) %addr, i8 %cmp, i8 %ne
; SM90-NEXT: @%p2 bra $L__BB4_1;
; SM90-NEXT: $L__BB4_3: // %partword.cmpxchg.end
; SM90-NEXT: fence.acquire.cta;
-; SM90-NEXT: st.param.b32 [func_retval0], %r12;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r12;
; SM90-NEXT: ret;
%pairold = cmpxchg ptr addrspace(1) %addr, i8 %cmp, i8 %new syncscope("block") acquire acquire
ret i8 %new
@@ -237,10 +237,10 @@ define i8 @acquire_seq_cst_i8_global_cta(ptr addrspace(1) %addr, i8 %cmp, i8 %ne
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b8 %rs1, [acquire_seq_cst_i8_global_cta_param_2];
-; SM90-NEXT: ld.param.b64 %rd2, [acquire_seq_cst_i8_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b8 %rs1, [acquire_seq_cst_i8_global_cta_param_2];
+; SM90-NEXT: ld.param::func.b64 %rd2, [acquire_seq_cst_i8_global_cta_param_0];
; SM90-NEXT: fence.sc.cta;
-; SM90-NEXT: ld.param.b8 %r7, [acquire_seq_cst_i8_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b8 %r7, [acquire_seq_cst_i8_global_cta_param_1];
; SM90-NEXT: and.b64 %rd1, %rd2, -4;
; SM90-NEXT: cvt.u32.u64 %r8, %rd2;
; SM90-NEXT: and.b32 %r9, %r8, 3;
@@ -268,7 +268,7 @@ define i8 @acquire_seq_cst_i8_global_cta(ptr addrspace(1) %addr, i8 %cmp, i8 %ne
; SM90-NEXT: @%p2 bra $L__BB5_1;
; SM90-NEXT: $L__BB5_3: // %partword.cmpxchg.end
; SM90-NEXT: fence.acquire.cta;
-; SM90-NEXT: st.param.b32 [func_retval0], %r12;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r12;
; SM90-NEXT: ret;
%pairold = cmpxchg ptr addrspace(1) %addr, i8 %cmp, i8 %new syncscope("block") acquire seq_cst
ret i8 %new
@@ -283,10 +283,10 @@ define i8 @release_monotonic_i8_global_cta(ptr addrspace(1) %addr, i8 %cmp, i8 %
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b8 %rs1, [release_monotonic_i8_global_cta_param_2];
-; SM90-NEXT: ld.param.b64 %rd2, [release_monotonic_i8_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b8 %rs1, [release_monotonic_i8_global_cta_param_2];
+; SM90-NEXT: ld.param::func.b64 %rd2, [release_monotonic_i8_global_cta_param_0];
; SM90-NEXT: fence.release.cta;
-; SM90-NEXT: ld.param.b8 %r7, [release_monotonic_i8_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b8 %r7, [release_monotonic_i8_global_cta_param_1];
; SM90-NEXT: and.b64 %rd1, %rd2, -4;
; SM90-NEXT: cvt.u32.u64 %r8, %rd2;
; SM90-NEXT: and.b32 %r9, %r8, 3;
@@ -313,7 +313,7 @@ define i8 @release_monotonic_i8_global_cta(ptr addrspace(1) %addr, i8 %cmp, i8 %
; SM90-NEXT: mov.b32 %r16, %r6;
; SM90-NEXT: @%p2 bra $L__BB6_1;
; SM90-NEXT: $L__BB6_3: // %partword.cmpxchg.end
-; SM90-NEXT: st.param.b32 [func_retval0], %r12;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r12;
; SM90-NEXT: ret;
%pairold = cmpxchg ptr addrspace(1) %addr, i8 %cmp, i8 %new syncscope("block") release monotonic
ret i8 %new
@@ -328,10 +328,10 @@ define i8 @release_acquire_i8_global_cta(ptr addrspace(1) %addr, i8 %cmp, i8 %ne
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b8 %rs1, [release_acquire_i8_global_cta_param_2];
-; SM90-NEXT: ld.param.b64 %rd2, [release_acquire_i8_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b8 %rs1, [release_acquire_i8_global_cta_param_2];
+; SM90-NEXT: ld.param::func.b64 %rd2, [release_acquire_i8_global_cta_param_0];
; SM90-NEXT: fence.release.cta;
-; SM90-NEXT: ld.param.b8 %r7, [release_acquire_i8_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b8 %r7, [release_acquire_i8_global_cta_param_1];
; SM90-NEXT: and.b64 %rd1, %rd2, -4;
; SM90-NEXT: cvt.u32.u64 %r8, %rd2;
; SM90-NEXT: and.b32 %r9, %r8, 3;
@@ -359,7 +359,7 @@ define i8 @release_acquire_i8_global_cta(ptr addrspace(1) %addr, i8 %cmp, i8 %ne
; SM90-NEXT: @%p2 bra $L__BB7_1;
; SM90-NEXT: $L__BB7_3: // %partword.cmpxchg.end
; SM90-NEXT: fence.acquire.cta;
-; SM90-NEXT: st.param.b32 [func_retval0], %r12;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r12;
; SM90-NEXT: ret;
%pairold = cmpxchg ptr addrspace(1) %addr, i8 %cmp, i8 %new syncscope("block") release acquire
ret i8 %new
@@ -374,10 +374,10 @@ define i8 @release_seq_cst_i8_global_cta(ptr addrspace(1) %addr, i8 %cmp, i8 %ne
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b8 %rs1, [release_seq_cst_i8_global_cta_param_2];
-; SM90-NEXT: ld.param.b64 %rd2, [release_seq_cst_i8_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b8 %rs1, [release_seq_cst_i8_global_cta_param_2];
+; SM90-NEXT: ld.param::func.b64 %rd2, [release_seq_cst_i8_global_cta_param_0];
; SM90-NEXT: fence.sc.cta;
-; SM90-NEXT: ld.param.b8 %r7, [release_seq_cst_i8_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b8 %r7, [release_seq_cst_i8_global_cta_param_1];
; SM90-NEXT: and.b64 %rd1, %rd2, -4;
; SM90-NEXT: cvt.u32.u64 %r8, %rd2;
; SM90-NEXT: and.b32 %r9, %r8, 3;
@@ -405,7 +405,7 @@ define i8 @release_seq_cst_i8_global_cta(ptr addrspace(1) %addr, i8 %cmp, i8 %ne
; SM90-NEXT: @%p2 bra $L__BB8_1;
; SM90-NEXT: $L__BB8_3: // %partword.cmpxchg.end
; SM90-NEXT: fence.acquire.cta;
-; SM90-NEXT: st.param.b32 [func_retval0], %r12;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r12;
; SM90-NEXT: ret;
%pairold = cmpxchg ptr addrspace(1) %addr, i8 %cmp, i8 %new syncscope("block") release seq_cst
ret i8 %new
@@ -420,10 +420,10 @@ define i8 @acq_rel_monotonic_i8_global_cta(ptr addrspace(1) %addr, i8 %cmp, i8 %
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b8 %rs1, [acq_rel_monotonic_i8_global_cta_param_2];
-; SM90-NEXT: ld.param.b64 %rd2, [acq_rel_monotonic_i8_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b8 %rs1, [acq_rel_monotonic_i8_global_cta_param_2];
+; SM90-NEXT: ld.param::func.b64 %rd2, [acq_rel_monotonic_i8_global_cta_param_0];
; SM90-NEXT: fence.release.cta;
-; SM90-NEXT: ld.param.b8 %r7, [acq_rel_monotonic_i8_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b8 %r7, [acq_rel_monotonic_i8_global_cta_param_1];
; SM90-NEXT: and.b64 %rd1, %rd2, -4;
; SM90-NEXT: cvt.u32.u64 %r8, %rd2;
; SM90-NEXT: and.b32 %r9, %r8, 3;
@@ -451,7 +451,7 @@ define i8 @acq_rel_monotonic_i8_global_cta(ptr addrspace(1) %addr, i8 %cmp, i8 %
; SM90-NEXT: @%p2 bra $L__BB9_1;
; SM90-NEXT: $L__BB9_3: // %partword.cmpxchg.end
; SM90-NEXT: fence.acquire.cta;
-; SM90-NEXT: st.param.b32 [func_retval0], %r12;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r12;
; SM90-NEXT: ret;
%pairold = cmpxchg ptr addrspace(1) %addr, i8 %cmp, i8 %new syncscope("block") acq_rel monotonic
ret i8 %new
@@ -466,10 +466,10 @@ define i8 @acq_rel_acquire_i8_global_cta(ptr addrspace(1) %addr, i8 %cmp, i8 %ne
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b8 %rs1, [acq_rel_acquire_i8_global_cta_param_2];
-; SM90-NEXT: ld.param.b64 %rd2, [acq_rel_acquire_i8_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b8 %rs1, [acq_rel_acquire_i8_global_cta_param_2];
+; SM90-NEXT: ld.param::func.b64 %rd2, [acq_rel_acquire_i8_global_cta_param_0];
; SM90-NEXT: fence.release.cta;
-; SM90-NEXT: ld.param.b8 %r7, [acq_rel_acquire_i8_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b8 %r7, [acq_rel_acquire_i8_global_cta_param_1];
; SM90-NEXT: and.b64 %rd1, %rd2, -4;
; SM90-NEXT: cvt.u32.u64 %r8, %rd2;
; SM90-NEXT: and.b32 %r9, %r8, 3;
@@ -497,7 +497,7 @@ define i8 @acq_rel_acquire_i8_global_cta(ptr addrspace(1) %addr, i8 %cmp, i8 %ne
; SM90-NEXT: @%p2 bra $L__BB10_1;
; SM90-NEXT: $L__BB10_3: // %partword.cmpxchg.end
; SM90-NEXT: fence.acquire.cta;
-; SM90-NEXT: st.param.b32 [func_retval0], %r12;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r12;
; SM90-NEXT: ret;
%pairold = cmpxchg ptr addrspace(1) %addr, i8 %cmp, i8 %new syncscope("block") acq_rel acquire
ret i8 %new
@@ -512,10 +512,10 @@ define i8 @acq_rel_seq_cst_i8_global_cta(ptr addrspace(1) %addr, i8 %cmp, i8 %ne
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b8 %rs1, [acq_rel_seq_cst_i8_global_cta_param_2];
-; SM90-NEXT: ld.param.b64 %rd2, [acq_rel_seq_cst_i8_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b8 %rs1, [acq_rel_seq_cst_i8_global_cta_param_2];
+; SM90-NEXT: ld.param::func.b64 %rd2, [acq_rel_seq_cst_i8_global_cta_param_0];
; SM90-NEXT: fence.sc.cta;
-; SM90-NEXT: ld.param.b8 %r7, [acq_rel_seq_cst_i8_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b8 %r7, [acq_rel_seq_cst_i8_global_cta_param_1];
; SM90-NEXT: and.b64 %rd1, %rd2, -4;
; SM90-NEXT: cvt.u32.u64 %r8, %rd2;
; SM90-NEXT: and.b32 %r9, %r8, 3;
@@ -543,7 +543,7 @@ define i8 @acq_rel_seq_cst_i8_global_cta(ptr addrspace(1) %addr, i8 %cmp, i8 %ne
; SM90-NEXT: @%p2 bra $L__BB11_1;
; SM90-NEXT: $L__BB11_3: // %partword.cmpxchg.end
; SM90-NEXT: fence.acquire.cta;
-; SM90-NEXT: st.param.b32 [func_retval0], %r12;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r12;
; SM90-NEXT: ret;
%pairold = cmpxchg ptr addrspace(1) %addr, i8 %cmp, i8 %new syncscope("block") acq_rel seq_cst
ret i8 %new
@@ -558,10 +558,10 @@ define i8 @seq_cst_monotonic_i8_global_cta(ptr addrspace(1) %addr, i8 %cmp, i8 %
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b8 %rs1, [seq_cst_monotonic_i8_global_cta_param_2];
-; SM90-NEXT: ld.param.b64 %rd2, [seq_cst_monotonic_i8_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b8 %rs1, [seq_cst_monotonic_i8_global_cta_param_2];
+; SM90-NEXT: ld.param::func.b64 %rd2, [seq_cst_monotonic_i8_global_cta_param_0];
; SM90-NEXT: fence.sc.cta;
-; SM90-NEXT: ld.param.b8 %r7, [seq_cst_monotonic_i8_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b8 %r7, [seq_cst_monotonic_i8_global_cta_param_1];
; SM90-NEXT: and.b64 %rd1, %rd2, -4;
; SM90-NEXT: cvt.u32.u64 %r8, %rd2;
; SM90-NEXT: and.b32 %r9, %r8, 3;
@@ -589,7 +589,7 @@ define i8 @seq_cst_monotonic_i8_global_cta(ptr addrspace(1) %addr, i8 %cmp, i8 %
; SM90-NEXT: @%p2 bra $L__BB12_1;
; SM90-NEXT: $L__BB12_3: // %partword.cmpxchg.end
; SM90-NEXT: fence.acquire.cta;
-; SM90-NEXT: st.param.b32 [func_retval0], %r12;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r12;
; SM90-NEXT: ret;
%pairold = cmpxchg ptr addrspace(1) %addr, i8 %cmp, i8 %new syncscope("block") seq_cst monotonic
ret i8 %new
@@ -604,10 +604,10 @@ define i8 @seq_cst_acquire_i8_global_cta(ptr addrspace(1) %addr, i8 %cmp, i8 %ne
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b8 %rs1, [seq_cst_acquire_i8_global_cta_param_2];
-; SM90-NEXT: ld.param.b64 %rd2, [seq_cst_acquire_i8_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b8 %rs1, [seq_cst_acquire_i8_global_cta_param_2];
+; SM90-NEXT: ld.param::func.b64 %rd2, [seq_cst_acquire_i8_global_cta_param_0];
; SM90-NEXT: fence.sc.cta;
-; SM90-NEXT: ld.param.b8 %r7, [seq_cst_acquire_i8_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b8 %r7, [seq_cst_acquire_i8_global_cta_param_1];
; SM90-NEXT: and.b64 %rd1, %rd2, -4;
; SM90-NEXT: cvt.u32.u64 %r8, %rd2;
; SM90-NEXT: and.b32 %r9, %r8, 3;
@@ -635,7 +635,7 @@ define i8 @seq_cst_acquire_i8_global_cta(ptr addrspace(1) %addr, i8 %cmp, i8 %ne
; SM90-NEXT: @%p2 bra $L__BB13_1;
; SM90-NEXT: $L__BB13_3: // %partword.cmpxchg.end
; SM90-NEXT: fence.acquire.cta;
-; SM90-NEXT: st.param.b32 [func_retval0], %r12;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r12;
; SM90-NEXT: ret;
%pairold = cmpxchg ptr addrspace(1) %addr, i8 %cmp, i8 %new syncscope("block") seq_cst acquire
ret i8 %new
@@ -650,10 +650,10 @@ define i8 @seq_cst_seq_cst_i8_global_cta(ptr addrspace(1) %addr, i8 %cmp, i8 %ne
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b8 %rs1, [seq_cst_seq_cst_i8_global_cta_param_2];
-; SM90-NEXT: ld.param.b64 %rd2, [seq_cst_seq_cst_i8_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b8 %rs1, [seq_cst_seq_cst_i8_global_cta_param_2];
+; SM90-NEXT: ld.param::func.b64 %rd2, [seq_cst_seq_cst_i8_global_cta_param_0];
; SM90-NEXT: fence.sc.cta;
-; SM90-NEXT: ld.param.b8 %r7, [seq_cst_seq_cst_i8_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b8 %r7, [seq_cst_seq_cst_i8_global_cta_param_1];
; SM90-NEXT: and.b64 %rd1, %rd2, -4;
; SM90-NEXT: cvt.u32.u64 %r8, %rd2;
; SM90-NEXT: and.b32 %r9, %r8, 3;
@@ -681,7 +681,7 @@ define i8 @seq_cst_seq_cst_i8_global_cta(ptr addrspace(1) %addr, i8 %cmp, i8 %ne
; SM90-NEXT: @%p2 bra $L__BB14_1;
; SM90-NEXT: $L__BB14_3: // %partword.cmpxchg.end
; SM90-NEXT: fence.acquire.cta;
-; SM90-NEXT: st.param.b32 [func_retval0], %r12;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r12;
; SM90-NEXT: ret;
%pairold = cmpxchg ptr addrspace(1) %addr, i8 %cmp, i8 %new syncscope("block") seq_cst seq_cst
ret i8 %new
@@ -696,10 +696,10 @@ define i16 @monotonic_monotonic_i16_global_cta(ptr addrspace(1) %addr, i16 %cmp,
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b16 %rs1, [monotonic_monotonic_i16_global_cta_param_2];
-; SM90-NEXT: ld.param.b64 %rd2, [monotonic_monotonic_i16_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b16 %rs1, [monotonic_monotonic_i16_global_cta_param_2];
+; SM90-NEXT: ld.param::func.b64 %rd2, [monotonic_monotonic_i16_global_cta_param_0];
; SM90-NEXT: and.b64 %rd1, %rd2, -4;
-; SM90-NEXT: ld.param.b16 %r7, [monotonic_monotonic_i16_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b16 %r7, [monotonic_monotonic_i16_global_cta_param_1];
; SM90-NEXT: cvt.u32.u64 %r8, %rd2;
; SM90-NEXT: and.b32 %r9, %r8, 3;
; SM90-NEXT: shl.b32 %r1, %r9, 3;
@@ -725,7 +725,7 @@ define i16 @monotonic_monotonic_i16_global_cta(ptr addrspace(1) %addr, i16 %cmp,
; SM90-NEXT: mov.b32 %r16, %r6;
; SM90-NEXT: @%p2 bra $L__BB15_1;
; SM90-NEXT: $L__BB15_3: // %partword.cmpxchg.end
-; SM90-NEXT: st.param.b32 [func_retval0], %r12;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r12;
; SM90-NEXT: ret;
%pairold = cmpxchg ptr addrspace(1) %addr, i16 %cmp, i16 %new syncscope("block") monotonic monotonic
ret i16 %new
@@ -740,10 +740,10 @@ define i16 @monotonic_acquire_i16_global_cta(ptr addrspace(1) %addr, i16 %cmp, i
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b16 %rs1, [monotonic_acquire_i16_global_cta_param_2];
-; SM90-NEXT: ld.param.b64 %rd2, [monotonic_acquire_i16_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b16 %rs1, [monotonic_acquire_i16_global_cta_param_2];
+; SM90-NEXT: ld.param::func.b64 %rd2, [monotonic_acquire_i16_global_cta_param_0];
; SM90-NEXT: and.b64 %rd1, %rd2, -4;
-; SM90-NEXT: ld.param.b16 %r7, [monotonic_acquire_i16_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b16 %r7, [monotonic_acquire_i16_global_cta_param_1];
; SM90-NEXT: cvt.u32.u64 %r8, %rd2;
; SM90-NEXT: and.b32 %r9, %r8, 3;
; SM90-NEXT: shl.b32 %r1, %r9, 3;
@@ -770,7 +770,7 @@ define i16 @monotonic_acquire_i16_global_cta(ptr addrspace(1) %addr, i16 %cmp, i
; SM90-NEXT: @%p2 bra $L__BB16_1;
; SM90-NEXT: $L__BB16_3: // %partword.cmpxchg.end
; SM90-NEXT: fence.acquire.cta;
-; SM90-NEXT: st.param.b32 [func_retval0], %r12;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r12;
; SM90-NEXT: ret;
%pairold = cmpxchg ptr addrspace(1) %addr, i16 %cmp, i16 %new syncscope("block") monotonic acquire
ret i16 %new
@@ -785,10 +785,10 @@ define i16 @monotonic_seq_cst_i16_global_cta(ptr addrspace(1) %addr, i16 %cmp, i
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b16 %rs1, [monotonic_seq_cst_i16_global_cta_param_2];
-; SM90-NEXT: ld.param.b64 %rd2, [monotonic_seq_cst_i16_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b16 %rs1, [monotonic_seq_cst_i16_global_cta_param_2];
+; SM90-NEXT: ld.param::func.b64 %rd2, [monotonic_seq_cst_i16_global_cta_param_0];
; SM90-NEXT: fence.sc.cta;
-; SM90-NEXT: ld.param.b16 %r7, [monotonic_seq_cst_i16_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b16 %r7, [monotonic_seq_cst_i16_global_cta_param_1];
; SM90-NEXT: and.b64 %rd1, %rd2, -4;
; SM90-NEXT: cvt.u32.u64 %r8, %rd2;
; SM90-NEXT: and.b32 %r9, %r8, 3;
@@ -816,7 +816,7 @@ define i16 @monotonic_seq_cst_i16_global_cta(ptr addrspace(1) %addr, i16 %cmp, i
; SM90-NEXT: @%p2 bra $L__BB17_1;
; SM90-NEXT: $L__BB17_3: // %partword.cmpxchg.end
; SM90-NEXT: fence.acquire.cta;
-; SM90-NEXT: st.param.b32 [func_retval0], %r12;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r12;
; SM90-NEXT: ret;
%pairold = cmpxchg ptr addrspace(1) %addr, i16 %cmp, i16 %new syncscope("block") monotonic seq_cst
ret i16 %new
@@ -831,10 +831,10 @@ define i16 @acquire_monotonic_i16_global_cta(ptr addrspace(1) %addr, i16 %cmp, i
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b16 %rs1, [acquire_monotonic_i16_global_cta_param_2];
-; SM90-NEXT: ld.param.b64 %rd2, [acquire_monotonic_i16_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b16 %rs1, [acquire_monotonic_i16_global_cta_param_2];
+; SM90-NEXT: ld.param::func.b64 %rd2, [acquire_monotonic_i16_global_cta_param_0];
; SM90-NEXT: and.b64 %rd1, %rd2, -4;
-; SM90-NEXT: ld.param.b16 %r7, [acquire_monotonic_i16_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b16 %r7, [acquire_monotonic_i16_global_cta_param_1];
; SM90-NEXT: cvt.u32.u64 %r8, %rd2;
; SM90-NEXT: and.b32 %r9, %r8, 3;
; SM90-NEXT: shl.b32 %r1, %r9, 3;
@@ -861,7 +861,7 @@ define i16 @acquire_monotonic_i16_global_cta(ptr addrspace(1) %addr, i16 %cmp, i
; SM90-NEXT: @%p2 bra $L__BB18_1;
; SM90-NEXT: $L__BB18_3: // %partword.cmpxchg.end
; SM90-NEXT: fence.acquire.cta;
-; SM90-NEXT: st.param.b32 [func_retval0], %r12;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r12;
; SM90-NEXT: ret;
%pairold = cmpxchg ptr addrspace(1) %addr, i16 %cmp, i16 %new syncscope("block") acquire monotonic
ret i16 %new
@@ -876,10 +876,10 @@ define i16 @acquire_acquire_i16_global_cta(ptr addrspace(1) %addr, i16 %cmp, i16
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b16 %rs1, [acquire_acquire_i16_global_cta_param_2];
-; SM90-NEXT: ld.param.b64 %rd2, [acquire_acquire_i16_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b16 %rs1, [acquire_acquire_i16_global_cta_param_2];
+; SM90-NEXT: ld.param::func.b64 %rd2, [acquire_acquire_i16_global_cta_param_0];
; SM90-NEXT: and.b64 %rd1, %rd2, -4;
-; SM90-NEXT: ld.param.b16 %r7, [acquire_acquire_i16_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b16 %r7, [acquire_acquire_i16_global_cta_param_1];
; SM90-NEXT: cvt.u32.u64 %r8, %rd2;
; SM90-NEXT: and.b32 %r9, %r8, 3;
; SM90-NEXT: shl.b32 %r1, %r9, 3;
@@ -906,7 +906,7 @@ define i16 @acquire_acquire_i16_global_cta(ptr addrspace(1) %addr, i16 %cmp, i16
; SM90-NEXT: @%p2 bra $L__BB19_1;
; SM90-NEXT: $L__BB19_3: // %partword.cmpxchg.end
; SM90-NEXT: fence.acquire.cta;
-; SM90-NEXT: st.param.b32 [func_retval0], %r12;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r12;
; SM90-NEXT: ret;
%pairold = cmpxchg ptr addrspace(1) %addr, i16 %cmp, i16 %new syncscope("block") acquire acquire
ret i16 %new
@@ -921,10 +921,10 @@ define i16 @acquire_seq_cst_i16_global_cta(ptr addrspace(1) %addr, i16 %cmp, i16
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b16 %rs1, [acquire_seq_cst_i16_global_cta_param_2];
-; SM90-NEXT: ld.param.b64 %rd2, [acquire_seq_cst_i16_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b16 %rs1, [acquire_seq_cst_i16_global_cta_param_2];
+; SM90-NEXT: ld.param::func.b64 %rd2, [acquire_seq_cst_i16_global_cta_param_0];
; SM90-NEXT: fence.sc.cta;
-; SM90-NEXT: ld.param.b16 %r7, [acquire_seq_cst_i16_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b16 %r7, [acquire_seq_cst_i16_global_cta_param_1];
; SM90-NEXT: and.b64 %rd1, %rd2, -4;
; SM90-NEXT: cvt.u32.u64 %r8, %rd2;
; SM90-NEXT: and.b32 %r9, %r8, 3;
@@ -952,7 +952,7 @@ define i16 @acquire_seq_cst_i16_global_cta(ptr addrspace(1) %addr, i16 %cmp, i16
; SM90-NEXT: @%p2 bra $L__BB20_1;
; SM90-NEXT: $L__BB20_3: // %partword.cmpxchg.end
; SM90-NEXT: fence.acquire.cta;
-; SM90-NEXT: st.param.b32 [func_retval0], %r12;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r12;
; SM90-NEXT: ret;
%pairold = cmpxchg ptr addrspace(1) %addr, i16 %cmp, i16 %new syncscope("block") acquire seq_cst
ret i16 %new
@@ -967,10 +967,10 @@ define i16 @release_monotonic_i16_global_cta(ptr addrspace(1) %addr, i16 %cmp, i
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b16 %rs1, [release_monotonic_i16_global_cta_param_2];
-; SM90-NEXT: ld.param.b64 %rd2, [release_monotonic_i16_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b16 %rs1, [release_monotonic_i16_global_cta_param_2];
+; SM90-NEXT: ld.param::func.b64 %rd2, [release_monotonic_i16_global_cta_param_0];
; SM90-NEXT: fence.release.cta;
-; SM90-NEXT: ld.param.b16 %r7, [release_monotonic_i16_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b16 %r7, [release_monotonic_i16_global_cta_param_1];
; SM90-NEXT: and.b64 %rd1, %rd2, -4;
; SM90-NEXT: cvt.u32.u64 %r8, %rd2;
; SM90-NEXT: and.b32 %r9, %r8, 3;
@@ -997,7 +997,7 @@ define i16 @release_monotonic_i16_global_cta(ptr addrspace(1) %addr, i16 %cmp, i
; SM90-NEXT: mov.b32 %r16, %r6;
; SM90-NEXT: @%p2 bra $L__BB21_1;
; SM90-NEXT: $L__BB21_3: // %partword.cmpxchg.end
-; SM90-NEXT: st.param.b32 [func_retval0], %r12;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r12;
; SM90-NEXT: ret;
%pairold = cmpxchg ptr addrspace(1) %addr, i16 %cmp, i16 %new syncscope("block") release monotonic
ret i16 %new
@@ -1012,10 +1012,10 @@ define i16 @release_acquire_i16_global_cta(ptr addrspace(1) %addr, i16 %cmp, i16
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b16 %rs1, [release_acquire_i16_global_cta_param_2];
-; SM90-NEXT: ld.param.b64 %rd2, [release_acquire_i16_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b16 %rs1, [release_acquire_i16_global_cta_param_2];
+; SM90-NEXT: ld.param::func.b64 %rd2, [release_acquire_i16_global_cta_param_0];
; SM90-NEXT: fence.release.cta;
-; SM90-NEXT: ld.param.b16 %r7, [release_acquire_i16_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b16 %r7, [release_acquire_i16_global_cta_param_1];
; SM90-NEXT: and.b64 %rd1, %rd2, -4;
; SM90-NEXT: cvt.u32.u64 %r8, %rd2;
; SM90-NEXT: and.b32 %r9, %r8, 3;
@@ -1043,7 +1043,7 @@ define i16 @release_acquire_i16_global_cta(ptr addrspace(1) %addr, i16 %cmp, i16
; SM90-NEXT: @%p2 bra $L__BB22_1;
; SM90-NEXT: $L__BB22_3: // %partword.cmpxchg.end
; SM90-NEXT: fence.acquire.cta;
-; SM90-NEXT: st.param.b32 [func_retval0], %r12;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r12;
; SM90-NEXT: ret;
%pairold = cmpxchg ptr addrspace(1) %addr, i16 %cmp, i16 %new syncscope("block") release acquire
ret i16 %new
@@ -1058,10 +1058,10 @@ define i16 @release_seq_cst_i16_global_cta(ptr addrspace(1) %addr, i16 %cmp, i16
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b16 %rs1, [release_seq_cst_i16_global_cta_param_2];
-; SM90-NEXT: ld.param.b64 %rd2, [release_seq_cst_i16_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b16 %rs1, [release_seq_cst_i16_global_cta_param_2];
+; SM90-NEXT: ld.param::func.b64 %rd2, [release_seq_cst_i16_global_cta_param_0];
; SM90-NEXT: fence.sc.cta;
-; SM90-NEXT: ld.param.b16 %r7, [release_seq_cst_i16_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b16 %r7, [release_seq_cst_i16_global_cta_param_1];
; SM90-NEXT: and.b64 %rd1, %rd2, -4;
; SM90-NEXT: cvt.u32.u64 %r8, %rd2;
; SM90-NEXT: and.b32 %r9, %r8, 3;
@@ -1089,7 +1089,7 @@ define i16 @release_seq_cst_i16_global_cta(ptr addrspace(1) %addr, i16 %cmp, i16
; SM90-NEXT: @%p2 bra $L__BB23_1;
; SM90-NEXT: $L__BB23_3: // %partword.cmpxchg.end
; SM90-NEXT: fence.acquire.cta;
-; SM90-NEXT: st.param.b32 [func_retval0], %r12;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r12;
; SM90-NEXT: ret;
%pairold = cmpxchg ptr addrspace(1) %addr, i16 %cmp, i16 %new syncscope("block") release seq_cst
ret i16 %new
@@ -1104,10 +1104,10 @@ define i16 @acq_rel_monotonic_i16_global_cta(ptr addrspace(1) %addr, i16 %cmp, i
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b16 %rs1, [acq_rel_monotonic_i16_global_cta_param_2];
-; SM90-NEXT: ld.param.b64 %rd2, [acq_rel_monotonic_i16_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b16 %rs1, [acq_rel_monotonic_i16_global_cta_param_2];
+; SM90-NEXT: ld.param::func.b64 %rd2, [acq_rel_monotonic_i16_global_cta_param_0];
; SM90-NEXT: fence.release.cta;
-; SM90-NEXT: ld.param.b16 %r7, [acq_rel_monotonic_i16_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b16 %r7, [acq_rel_monotonic_i16_global_cta_param_1];
; SM90-NEXT: and.b64 %rd1, %rd2, -4;
; SM90-NEXT: cvt.u32.u64 %r8, %rd2;
; SM90-NEXT: and.b32 %r9, %r8, 3;
@@ -1135,7 +1135,7 @@ define i16 @acq_rel_monotonic_i16_global_cta(ptr addrspace(1) %addr, i16 %cmp, i
; SM90-NEXT: @%p2 bra $L__BB24_1;
; SM90-NEXT: $L__BB24_3: // %partword.cmpxchg.end
; SM90-NEXT: fence.acquire.cta;
-; SM90-NEXT: st.param.b32 [func_retval0], %r12;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r12;
; SM90-NEXT: ret;
%pairold = cmpxchg ptr addrspace(1) %addr, i16 %cmp, i16 %new syncscope("block") acq_rel monotonic
ret i16 %new
@@ -1150,10 +1150,10 @@ define i16 @acq_rel_acquire_i16_global_cta(ptr addrspace(1) %addr, i16 %cmp, i16
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b16 %rs1, [acq_rel_acquire_i16_global_cta_param_2];
-; SM90-NEXT: ld.param.b64 %rd2, [acq_rel_acquire_i16_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b16 %rs1, [acq_rel_acquire_i16_global_cta_param_2];
+; SM90-NEXT: ld.param::func.b64 %rd2, [acq_rel_acquire_i16_global_cta_param_0];
; SM90-NEXT: fence.release.cta;
-; SM90-NEXT: ld.param.b16 %r7, [acq_rel_acquire_i16_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b16 %r7, [acq_rel_acquire_i16_global_cta_param_1];
; SM90-NEXT: and.b64 %rd1, %rd2, -4;
; SM90-NEXT: cvt.u32.u64 %r8, %rd2;
; SM90-NEXT: and.b32 %r9, %r8, 3;
@@ -1181,7 +1181,7 @@ define i16 @acq_rel_acquire_i16_global_cta(ptr addrspace(1) %addr, i16 %cmp, i16
; SM90-NEXT: @%p2 bra $L__BB25_1;
; SM90-NEXT: $L__BB25_3: // %partword.cmpxchg.end
; SM90-NEXT: fence.acquire.cta;
-; SM90-NEXT: st.param.b32 [func_retval0], %r12;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r12;
; SM90-NEXT: ret;
%pairold = cmpxchg ptr addrspace(1) %addr, i16 %cmp, i16 %new syncscope("block") acq_rel acquire
ret i16 %new
@@ -1196,10 +1196,10 @@ define i16 @acq_rel_seq_cst_i16_global_cta(ptr addrspace(1) %addr, i16 %cmp, i16
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b16 %rs1, [acq_rel_seq_cst_i16_global_cta_param_2];
-; SM90-NEXT: ld.param.b64 %rd2, [acq_rel_seq_cst_i16_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b16 %rs1, [acq_rel_seq_cst_i16_global_cta_param_2];
+; SM90-NEXT: ld.param::func.b64 %rd2, [acq_rel_seq_cst_i16_global_cta_param_0];
; SM90-NEXT: fence.sc.cta;
-; SM90-NEXT: ld.param.b16 %r7, [acq_rel_seq_cst_i16_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b16 %r7, [acq_rel_seq_cst_i16_global_cta_param_1];
; SM90-NEXT: and.b64 %rd1, %rd2, -4;
; SM90-NEXT: cvt.u32.u64 %r8, %rd2;
; SM90-NEXT: and.b32 %r9, %r8, 3;
@@ -1227,7 +1227,7 @@ define i16 @acq_rel_seq_cst_i16_global_cta(ptr addrspace(1) %addr, i16 %cmp, i16
; SM90-NEXT: @%p2 bra $L__BB26_1;
; SM90-NEXT: $L__BB26_3: // %partword.cmpxchg.end
; SM90-NEXT: fence.acquire.cta;
-; SM90-NEXT: st.param.b32 [func_retval0], %r12;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r12;
; SM90-NEXT: ret;
%pairold = cmpxchg ptr addrspace(1) %addr, i16 %cmp, i16 %new syncscope("block") acq_rel seq_cst
ret i16 %new
@@ -1242,10 +1242,10 @@ define i16 @seq_cst_monotonic_i16_global_cta(ptr addrspace(1) %addr, i16 %cmp, i
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b16 %rs1, [seq_cst_monotonic_i16_global_cta_param_2];
-; SM90-NEXT: ld.param.b64 %rd2, [seq_cst_monotonic_i16_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b16 %rs1, [seq_cst_monotonic_i16_global_cta_param_2];
+; SM90-NEXT: ld.param::func.b64 %rd2, [seq_cst_monotonic_i16_global_cta_param_0];
; SM90-NEXT: fence.sc.cta;
-; SM90-NEXT: ld.param.b16 %r7, [seq_cst_monotonic_i16_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b16 %r7, [seq_cst_monotonic_i16_global_cta_param_1];
; SM90-NEXT: and.b64 %rd1, %rd2, -4;
; SM90-NEXT: cvt.u32.u64 %r8, %rd2;
; SM90-NEXT: and.b32 %r9, %r8, 3;
@@ -1273,7 +1273,7 @@ define i16 @seq_cst_monotonic_i16_global_cta(ptr addrspace(1) %addr, i16 %cmp, i
; SM90-NEXT: @%p2 bra $L__BB27_1;
; SM90-NEXT: $L__BB27_3: // %partword.cmpxchg.end
; SM90-NEXT: fence.acquire.cta;
-; SM90-NEXT: st.param.b32 [func_retval0], %r12;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r12;
; SM90-NEXT: ret;
%pairold = cmpxchg ptr addrspace(1) %addr, i16 %cmp, i16 %new syncscope("block") seq_cst monotonic
ret i16 %new
@@ -1288,10 +1288,10 @@ define i16 @seq_cst_acquire_i16_global_cta(ptr addrspace(1) %addr, i16 %cmp, i16
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b16 %rs1, [seq_cst_acquire_i16_global_cta_param_2];
-; SM90-NEXT: ld.param.b64 %rd2, [seq_cst_acquire_i16_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b16 %rs1, [seq_cst_acquire_i16_global_cta_param_2];
+; SM90-NEXT: ld.param::func.b64 %rd2, [seq_cst_acquire_i16_global_cta_param_0];
; SM90-NEXT: fence.sc.cta;
-; SM90-NEXT: ld.param.b16 %r7, [seq_cst_acquire_i16_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b16 %r7, [seq_cst_acquire_i16_global_cta_param_1];
; SM90-NEXT: and.b64 %rd1, %rd2, -4;
; SM90-NEXT: cvt.u32.u64 %r8, %rd2;
; SM90-NEXT: and.b32 %r9, %r8, 3;
@@ -1319,7 +1319,7 @@ define i16 @seq_cst_acquire_i16_global_cta(ptr addrspace(1) %addr, i16 %cmp, i16
; SM90-NEXT: @%p2 bra $L__BB28_1;
; SM90-NEXT: $L__BB28_3: // %partword.cmpxchg.end
; SM90-NEXT: fence.acquire.cta;
-; SM90-NEXT: st.param.b32 [func_retval0], %r12;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r12;
; SM90-NEXT: ret;
%pairold = cmpxchg ptr addrspace(1) %addr, i16 %cmp, i16 %new syncscope("block") seq_cst acquire
ret i16 %new
@@ -1334,10 +1334,10 @@ define i16 @seq_cst_seq_cst_i16_global_cta(ptr addrspace(1) %addr, i16 %cmp, i16
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b16 %rs1, [seq_cst_seq_cst_i16_global_cta_param_2];
-; SM90-NEXT: ld.param.b64 %rd2, [seq_cst_seq_cst_i16_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b16 %rs1, [seq_cst_seq_cst_i16_global_cta_param_2];
+; SM90-NEXT: ld.param::func.b64 %rd2, [seq_cst_seq_cst_i16_global_cta_param_0];
; SM90-NEXT: fence.sc.cta;
-; SM90-NEXT: ld.param.b16 %r7, [seq_cst_seq_cst_i16_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b16 %r7, [seq_cst_seq_cst_i16_global_cta_param_1];
; SM90-NEXT: and.b64 %rd1, %rd2, -4;
; SM90-NEXT: cvt.u32.u64 %r8, %rd2;
; SM90-NEXT: and.b32 %r9, %r8, 3;
@@ -1365,7 +1365,7 @@ define i16 @seq_cst_seq_cst_i16_global_cta(ptr addrspace(1) %addr, i16 %cmp, i16
; SM90-NEXT: @%p2 bra $L__BB29_1;
; SM90-NEXT: $L__BB29_3: // %partword.cmpxchg.end
; SM90-NEXT: fence.acquire.cta;
-; SM90-NEXT: st.param.b32 [func_retval0], %r12;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r12;
; SM90-NEXT: ret;
%pairold = cmpxchg ptr addrspace(1) %addr, i16 %cmp, i16 %new syncscope("block") seq_cst seq_cst
ret i16 %new
@@ -1378,11 +1378,11 @@ define i32 @monotonic_monotonic_i32_global_cta(ptr addrspace(1) %addr, i32 %cmp,
; SM90-NEXT: .reg .b64 %rd<2>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [monotonic_monotonic_i32_global_cta_param_0];
-; SM90-NEXT: ld.param.b32 %r1, [monotonic_monotonic_i32_global_cta_param_1];
-; SM90-NEXT: ld.param.b32 %r2, [monotonic_monotonic_i32_global_cta_param_2];
+; SM90-NEXT: ld.param::func.b64 %rd1, [monotonic_monotonic_i32_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b32 %r1, [monotonic_monotonic_i32_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b32 %r2, [monotonic_monotonic_i32_global_cta_param_2];
; SM90-NEXT: atom.relaxed.cta.global.cas.b32 %r3, [%rd1], %r1, %r2;
-; SM90-NEXT: st.param.b32 [func_retval0], %r2;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r2;
; SM90-NEXT: ret;
%pairold = cmpxchg ptr addrspace(1) %addr, i32 %cmp, i32 %new syncscope("block") monotonic monotonic
ret i32 %new
@@ -1395,11 +1395,11 @@ define i32 @monotonic_acquire_i32_global_cta(ptr addrspace(1) %addr, i32 %cmp, i
; SM90-NEXT: .reg .b64 %rd<2>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [monotonic_acquire_i32_global_cta_param_0];
-; SM90-NEXT: ld.param.b32 %r1, [monotonic_acquire_i32_global_cta_param_1];
-; SM90-NEXT: ld.param.b32 %r2, [monotonic_acquire_i32_global_cta_param_2];
+; SM90-NEXT: ld.param::func.b64 %rd1, [monotonic_acquire_i32_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b32 %r1, [monotonic_acquire_i32_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b32 %r2, [monotonic_acquire_i32_global_cta_param_2];
; SM90-NEXT: atom.acquire.cta.global.cas.b32 %r3, [%rd1], %r1, %r2;
-; SM90-NEXT: st.param.b32 [func_retval0], %r2;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r2;
; SM90-NEXT: ret;
%pairold = cmpxchg ptr addrspace(1) %addr, i32 %cmp, i32 %new syncscope("block") monotonic acquire
ret i32 %new
@@ -1412,12 +1412,12 @@ define i32 @monotonic_seq_cst_i32_global_cta(ptr addrspace(1) %addr, i32 %cmp, i
; SM90-NEXT: .reg .b64 %rd<2>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [monotonic_seq_cst_i32_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd1, [monotonic_seq_cst_i32_global_cta_param_0];
; SM90-NEXT: fence.sc.cta;
-; SM90-NEXT: ld.param.b32 %r1, [monotonic_seq_cst_i32_global_cta_param_1];
-; SM90-NEXT: ld.param.b32 %r2, [monotonic_seq_cst_i32_global_cta_param_2];
+; SM90-NEXT: ld.param::func.b32 %r1, [monotonic_seq_cst_i32_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b32 %r2, [monotonic_seq_cst_i32_global_cta_param_2];
; SM90-NEXT: atom.acquire.cta.global.cas.b32 %r3, [%rd1], %r1, %r2;
-; SM90-NEXT: st.param.b32 [func_retval0], %r2;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r2;
; SM90-NEXT: ret;
%pairold = cmpxchg ptr addrspace(1) %addr, i32 %cmp, i32 %new syncscope("block") monotonic seq_cst
ret i32 %new
@@ -1430,11 +1430,11 @@ define i32 @acquire_monotonic_i32_global_cta(ptr addrspace(1) %addr, i32 %cmp, i
; SM90-NEXT: .reg .b64 %rd<2>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [acquire_monotonic_i32_global_cta_param_0];
-; SM90-NEXT: ld.param.b32 %r1, [acquire_monotonic_i32_global_cta_param_1];
-; SM90-NEXT: ld.param.b32 %r2, [acquire_monotonic_i32_global_cta_param_2];
+; SM90-NEXT: ld.param::func.b64 %rd1, [acquire_monotonic_i32_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b32 %r1, [acquire_monotonic_i32_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b32 %r2, [acquire_monotonic_i32_global_cta_param_2];
; SM90-NEXT: atom.acquire.cta.global.cas.b32 %r3, [%rd1], %r1, %r2;
-; SM90-NEXT: st.param.b32 [func_retval0], %r2;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r2;
; SM90-NEXT: ret;
%pairold = cmpxchg ptr addrspace(1) %addr, i32 %cmp, i32 %new syncscope("block") acquire monotonic
ret i32 %new
@@ -1447,11 +1447,11 @@ define i32 @acquire_acquire_i32_global_cta(ptr addrspace(1) %addr, i32 %cmp, i32
; SM90-NEXT: .reg .b64 %rd<2>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [acquire_acquire_i32_global_cta_param_0];
-; SM90-NEXT: ld.param.b32 %r1, [acquire_acquire_i32_global_cta_param_1];
-; SM90-NEXT: ld.param.b32 %r2, [acquire_acquire_i32_global_cta_param_2];
+; SM90-NEXT: ld.param::func.b64 %rd1, [acquire_acquire_i32_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b32 %r1, [acquire_acquire_i32_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b32 %r2, [acquire_acquire_i32_global_cta_param_2];
; SM90-NEXT: atom.acquire.cta.global.cas.b32 %r3, [%rd1], %r1, %r2;
-; SM90-NEXT: st.param.b32 [func_retval0], %r2;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r2;
; SM90-NEXT: ret;
%pairold = cmpxchg ptr addrspace(1) %addr, i32 %cmp, i32 %new syncscope("block") acquire acquire
ret i32 %new
@@ -1464,12 +1464,12 @@ define i32 @acquire_seq_cst_i32_global_cta(ptr addrspace(1) %addr, i32 %cmp, i32
; SM90-NEXT: .reg .b64 %rd<2>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [acquire_seq_cst_i32_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd1, [acquire_seq_cst_i32_global_cta_param_0];
; SM90-NEXT: fence.sc.cta;
-; SM90-NEXT: ld.param.b32 %r1, [acquire_seq_cst_i32_global_cta_param_1];
-; SM90-NEXT: ld.param.b32 %r2, [acquire_seq_cst_i32_global_cta_param_2];
+; SM90-NEXT: ld.param::func.b32 %r1, [acquire_seq_cst_i32_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b32 %r2, [acquire_seq_cst_i32_global_cta_param_2];
; SM90-NEXT: atom.acquire.cta.global.cas.b32 %r3, [%rd1], %r1, %r2;
-; SM90-NEXT: st.param.b32 [func_retval0], %r2;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r2;
; SM90-NEXT: ret;
%pairold = cmpxchg ptr addrspace(1) %addr, i32 %cmp, i32 %new syncscope("block") acquire seq_cst
ret i32 %new
@@ -1482,11 +1482,11 @@ define i32 @release_monotonic_i32_global_cta(ptr addrspace(1) %addr, i32 %cmp, i
; SM90-NEXT: .reg .b64 %rd<2>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [release_monotonic_i32_global_cta_param_0];
-; SM90-NEXT: ld.param.b32 %r1, [release_monotonic_i32_global_cta_param_1];
-; SM90-NEXT: ld.param.b32 %r2, [release_monotonic_i32_global_cta_param_2];
+; SM90-NEXT: ld.param::func.b64 %rd1, [release_monotonic_i32_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b32 %r1, [release_monotonic_i32_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b32 %r2, [release_monotonic_i32_global_cta_param_2];
; SM90-NEXT: atom.release.cta.global.cas.b32 %r3, [%rd1], %r1, %r2;
-; SM90-NEXT: st.param.b32 [func_retval0], %r2;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r2;
; SM90-NEXT: ret;
%pairold = cmpxchg ptr addrspace(1) %addr, i32 %cmp, i32 %new syncscope("block") release monotonic
ret i32 %new
@@ -1499,11 +1499,11 @@ define i32 @release_acquire_i32_global_cta(ptr addrspace(1) %addr, i32 %cmp, i32
; SM90-NEXT: .reg .b64 %rd<2>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [release_acquire_i32_global_cta_param_0];
-; SM90-NEXT: ld.param.b32 %r1, [release_acquire_i32_global_cta_param_1];
-; SM90-NEXT: ld.param.b32 %r2, [release_acquire_i32_global_cta_param_2];
+; SM90-NEXT: ld.param::func.b64 %rd1, [release_acquire_i32_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b32 %r1, [release_acquire_i32_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b32 %r2, [release_acquire_i32_global_cta_param_2];
; SM90-NEXT: atom.acq_rel.cta.global.cas.b32 %r3, [%rd1], %r1, %r2;
-; SM90-NEXT: st.param.b32 [func_retval0], %r2;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r2;
; SM90-NEXT: ret;
%pairold = cmpxchg ptr addrspace(1) %addr, i32 %cmp, i32 %new syncscope("block") release acquire
ret i32 %new
@@ -1516,12 +1516,12 @@ define i32 @release_seq_cst_i32_global_cta(ptr addrspace(1) %addr, i32 %cmp, i32
; SM90-NEXT: .reg .b64 %rd<2>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [release_seq_cst_i32_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd1, [release_seq_cst_i32_global_cta_param_0];
; SM90-NEXT: fence.sc.cta;
-; SM90-NEXT: ld.param.b32 %r1, [release_seq_cst_i32_global_cta_param_1];
-; SM90-NEXT: ld.param.b32 %r2, [release_seq_cst_i32_global_cta_param_2];
+; SM90-NEXT: ld.param::func.b32 %r1, [release_seq_cst_i32_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b32 %r2, [release_seq_cst_i32_global_cta_param_2];
; SM90-NEXT: atom.acquire.cta.global.cas.b32 %r3, [%rd1], %r1, %r2;
-; SM90-NEXT: st.param.b32 [func_retval0], %r2;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r2;
; SM90-NEXT: ret;
%pairold = cmpxchg ptr addrspace(1) %addr, i32 %cmp, i32 %new syncscope("block") release seq_cst
ret i32 %new
@@ -1534,11 +1534,11 @@ define i32 @acq_rel_monotonic_i32_global_cta(ptr addrspace(1) %addr, i32 %cmp, i
; SM90-NEXT: .reg .b64 %rd<2>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [acq_rel_monotonic_i32_global_cta_param_0];
-; SM90-NEXT: ld.param.b32 %r1, [acq_rel_monotonic_i32_global_cta_param_1];
-; SM90-NEXT: ld.param.b32 %r2, [acq_rel_monotonic_i32_global_cta_param_2];
+; SM90-NEXT: ld.param::func.b64 %rd1, [acq_rel_monotonic_i32_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b32 %r1, [acq_rel_monotonic_i32_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b32 %r2, [acq_rel_monotonic_i32_global_cta_param_2];
; SM90-NEXT: atom.acq_rel.cta.global.cas.b32 %r3, [%rd1], %r1, %r2;
-; SM90-NEXT: st.param.b32 [func_retval0], %r2;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r2;
; SM90-NEXT: ret;
%pairold = cmpxchg ptr addrspace(1) %addr, i32 %cmp, i32 %new syncscope("block") acq_rel monotonic
ret i32 %new
@@ -1551,11 +1551,11 @@ define i32 @acq_rel_acquire_i32_global_cta(ptr addrspace(1) %addr, i32 %cmp, i32
; SM90-NEXT: .reg .b64 %rd<2>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [acq_rel_acquire_i32_global_cta_param_0];
-; SM90-NEXT: ld.param.b32 %r1, [acq_rel_acquire_i32_global_cta_param_1];
-; SM90-NEXT: ld.param.b32 %r2, [acq_rel_acquire_i32_global_cta_param_2];
+; SM90-NEXT: ld.param::func.b64 %rd1, [acq_rel_acquire_i32_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b32 %r1, [acq_rel_acquire_i32_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b32 %r2, [acq_rel_acquire_i32_global_cta_param_2];
; SM90-NEXT: atom.acq_rel.cta.global.cas.b32 %r3, [%rd1], %r1, %r2;
-; SM90-NEXT: st.param.b32 [func_retval0], %r2;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r2;
; SM90-NEXT: ret;
%pairold = cmpxchg ptr addrspace(1) %addr, i32 %cmp, i32 %new syncscope("block") acq_rel acquire
ret i32 %new
@@ -1568,12 +1568,12 @@ define i32 @acq_rel_seq_cst_i32_global_cta(ptr addrspace(1) %addr, i32 %cmp, i32
; SM90-NEXT: .reg .b64 %rd<2>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [acq_rel_seq_cst_i32_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd1, [acq_rel_seq_cst_i32_global_cta_param_0];
; SM90-NEXT: fence.sc.cta;
-; SM90-NEXT: ld.param.b32 %r1, [acq_rel_seq_cst_i32_global_cta_param_1];
-; SM90-NEXT: ld.param.b32 %r2, [acq_rel_seq_cst_i32_global_cta_param_2];
+; SM90-NEXT: ld.param::func.b32 %r1, [acq_rel_seq_cst_i32_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b32 %r2, [acq_rel_seq_cst_i32_global_cta_param_2];
; SM90-NEXT: atom.acquire.cta.global.cas.b32 %r3, [%rd1], %r1, %r2;
-; SM90-NEXT: st.param.b32 [func_retval0], %r2;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r2;
; SM90-NEXT: ret;
%pairold = cmpxchg ptr addrspace(1) %addr, i32 %cmp, i32 %new syncscope("block") acq_rel seq_cst
ret i32 %new
@@ -1586,12 +1586,12 @@ define i32 @seq_cst_monotonic_i32_global_cta(ptr addrspace(1) %addr, i32 %cmp, i
; SM90-NEXT: .reg .b64 %rd<2>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [seq_cst_monotonic_i32_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd1, [seq_cst_monotonic_i32_global_cta_param_0];
; SM90-NEXT: fence.sc.cta;
-; SM90-NEXT: ld.param.b32 %r1, [seq_cst_monotonic_i32_global_cta_param_1];
-; SM90-NEXT: ld.param.b32 %r2, [seq_cst_monotonic_i32_global_cta_param_2];
+; SM90-NEXT: ld.param::func.b32 %r1, [seq_cst_monotonic_i32_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b32 %r2, [seq_cst_monotonic_i32_global_cta_param_2];
; SM90-NEXT: atom.acquire.cta.global.cas.b32 %r3, [%rd1], %r1, %r2;
-; SM90-NEXT: st.param.b32 [func_retval0], %r2;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r2;
; SM90-NEXT: ret;
%pairold = cmpxchg ptr addrspace(1) %addr, i32 %cmp, i32 %new syncscope("block") seq_cst monotonic
ret i32 %new
@@ -1604,12 +1604,12 @@ define i32 @seq_cst_acquire_i32_global_cta(ptr addrspace(1) %addr, i32 %cmp, i32
; SM90-NEXT: .reg .b64 %rd<2>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [seq_cst_acquire_i32_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd1, [seq_cst_acquire_i32_global_cta_param_0];
; SM90-NEXT: fence.sc.cta;
-; SM90-NEXT: ld.param.b32 %r1, [seq_cst_acquire_i32_global_cta_param_1];
-; SM90-NEXT: ld.param.b32 %r2, [seq_cst_acquire_i32_global_cta_param_2];
+; SM90-NEXT: ld.param::func.b32 %r1, [seq_cst_acquire_i32_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b32 %r2, [seq_cst_acquire_i32_global_cta_param_2];
; SM90-NEXT: atom.acquire.cta.global.cas.b32 %r3, [%rd1], %r1, %r2;
-; SM90-NEXT: st.param.b32 [func_retval0], %r2;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r2;
; SM90-NEXT: ret;
%pairold = cmpxchg ptr addrspace(1) %addr, i32 %cmp, i32 %new syncscope("block") seq_cst acquire
ret i32 %new
@@ -1622,12 +1622,12 @@ define i32 @seq_cst_seq_cst_i32_global_cta(ptr addrspace(1) %addr, i32 %cmp, i32
; SM90-NEXT: .reg .b64 %rd<2>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [seq_cst_seq_cst_i32_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd1, [seq_cst_seq_cst_i32_global_cta_param_0];
; SM90-NEXT: fence.sc.cta;
-; SM90-NEXT: ld.param.b32 %r1, [seq_cst_seq_cst_i32_global_cta_param_1];
-; SM90-NEXT: ld.param.b32 %r2, [seq_cst_seq_cst_i32_global_cta_param_2];
+; SM90-NEXT: ld.param::func.b32 %r1, [seq_cst_seq_cst_i32_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b32 %r2, [seq_cst_seq_cst_i32_global_cta_param_2];
; SM90-NEXT: atom.acquire.cta.global.cas.b32 %r3, [%rd1], %r1, %r2;
-; SM90-NEXT: st.param.b32 [func_retval0], %r2;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r2;
; SM90-NEXT: ret;
%pairold = cmpxchg ptr addrspace(1) %addr, i32 %cmp, i32 %new syncscope("block") seq_cst seq_cst
ret i32 %new
@@ -1639,11 +1639,11 @@ define i64 @monotonic_monotonic_i64_global_cta(ptr addrspace(1) %addr, i64 %cmp,
; SM90-NEXT: .reg .b64 %rd<5>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [monotonic_monotonic_i64_global_cta_param_0];
-; SM90-NEXT: ld.param.b64 %rd2, [monotonic_monotonic_i64_global_cta_param_1];
-; SM90-NEXT: ld.param.b64 %rd3, [monotonic_monotonic_i64_global_cta_param_2];
+; SM90-NEXT: ld.param::func.b64 %rd1, [monotonic_monotonic_i64_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd2, [monotonic_monotonic_i64_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd3, [monotonic_monotonic_i64_global_cta_param_2];
; SM90-NEXT: atom.relaxed.cta.global.cas.b64 %rd4, [%rd1], %rd2, %rd3;
-; SM90-NEXT: st.param.b64 [func_retval0], %rd3;
+; SM90-NEXT: st.param::func.b64 [func_retval0], %rd3;
; SM90-NEXT: ret;
%pairold = cmpxchg ptr addrspace(1) %addr, i64 %cmp, i64 %new syncscope("block") monotonic monotonic
ret i64 %new
@@ -1655,11 +1655,11 @@ define i64 @monotonic_acquire_i64_global_cta(ptr addrspace(1) %addr, i64 %cmp, i
; SM90-NEXT: .reg .b64 %rd<5>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [monotonic_acquire_i64_global_cta_param_0];
-; SM90-NEXT: ld.param.b64 %rd2, [monotonic_acquire_i64_global_cta_param_1];
-; SM90-NEXT: ld.param.b64 %rd3, [monotonic_acquire_i64_global_cta_param_2];
+; SM90-NEXT: ld.param::func.b64 %rd1, [monotonic_acquire_i64_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd2, [monotonic_acquire_i64_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd3, [monotonic_acquire_i64_global_cta_param_2];
; SM90-NEXT: atom.acquire.cta.global.cas.b64 %rd4, [%rd1], %rd2, %rd3;
-; SM90-NEXT: st.param.b64 [func_retval0], %rd3;
+; SM90-NEXT: st.param::func.b64 [func_retval0], %rd3;
; SM90-NEXT: ret;
%pairold = cmpxchg ptr addrspace(1) %addr, i64 %cmp, i64 %new syncscope("block") monotonic acquire
ret i64 %new
@@ -1671,12 +1671,12 @@ define i64 @monotonic_seq_cst_i64_global_cta(ptr addrspace(1) %addr, i64 %cmp, i
; SM90-NEXT: .reg .b64 %rd<5>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [monotonic_seq_cst_i64_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd1, [monotonic_seq_cst_i64_global_cta_param_0];
; SM90-NEXT: fence.sc.cta;
-; SM90-NEXT: ld.param.b64 %rd2, [monotonic_seq_cst_i64_global_cta_param_1];
-; SM90-NEXT: ld.param.b64 %rd3, [monotonic_seq_cst_i64_global_cta_param_2];
+; SM90-NEXT: ld.param::func.b64 %rd2, [monotonic_seq_cst_i64_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd3, [monotonic_seq_cst_i64_global_cta_param_2];
; SM90-NEXT: atom.acquire.cta.global.cas.b64 %rd4, [%rd1], %rd2, %rd3;
-; SM90-NEXT: st.param.b64 [func_retval0], %rd3;
+; SM90-NEXT: st.param::func.b64 [func_retval0], %rd3;
; SM90-NEXT: ret;
%pairold = cmpxchg ptr addrspace(1) %addr, i64 %cmp, i64 %new syncscope("block") monotonic seq_cst
ret i64 %new
@@ -1688,11 +1688,11 @@ define i64 @acquire_monotonic_i64_global_cta(ptr addrspace(1) %addr, i64 %cmp, i
; SM90-NEXT: .reg .b64 %rd<5>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [acquire_monotonic_i64_global_cta_param_0];
-; SM90-NEXT: ld.param.b64 %rd2, [acquire_monotonic_i64_global_cta_param_1];
-; SM90-NEXT: ld.param.b64 %rd3, [acquire_monotonic_i64_global_cta_param_2];
+; SM90-NEXT: ld.param::func.b64 %rd1, [acquire_monotonic_i64_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd2, [acquire_monotonic_i64_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd3, [acquire_monotonic_i64_global_cta_param_2];
; SM90-NEXT: atom.acquire.cta.global.cas.b64 %rd4, [%rd1], %rd2, %rd3;
-; SM90-NEXT: st.param.b64 [func_retval0], %rd3;
+; SM90-NEXT: st.param::func.b64 [func_retval0], %rd3;
; SM90-NEXT: ret;
%pairold = cmpxchg ptr addrspace(1) %addr, i64 %cmp, i64 %new syncscope("block") acquire monotonic
ret i64 %new
@@ -1704,11 +1704,11 @@ define i64 @acquire_acquire_i64_global_cta(ptr addrspace(1) %addr, i64 %cmp, i64
; SM90-NEXT: .reg .b64 %rd<5>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [acquire_acquire_i64_global_cta_param_0];
-; SM90-NEXT: ld.param.b64 %rd2, [acquire_acquire_i64_global_cta_param_1];
-; SM90-NEXT: ld.param.b64 %rd3, [acquire_acquire_i64_global_cta_param_2];
+; SM90-NEXT: ld.param::func.b64 %rd1, [acquire_acquire_i64_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd2, [acquire_acquire_i64_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd3, [acquire_acquire_i64_global_cta_param_2];
; SM90-NEXT: atom.acquire.cta.global.cas.b64 %rd4, [%rd1], %rd2, %rd3;
-; SM90-NEXT: st.param.b64 [func_retval0], %rd3;
+; SM90-NEXT: st.param::func.b64 [func_retval0], %rd3;
; SM90-NEXT: ret;
%pairold = cmpxchg ptr addrspace(1) %addr, i64 %cmp, i64 %new syncscope("block") acquire acquire
ret i64 %new
@@ -1720,12 +1720,12 @@ define i64 @acquire_seq_cst_i64_global_cta(ptr addrspace(1) %addr, i64 %cmp, i64
; SM90-NEXT: .reg .b64 %rd<5>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [acquire_seq_cst_i64_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd1, [acquire_seq_cst_i64_global_cta_param_0];
; SM90-NEXT: fence.sc.cta;
-; SM90-NEXT: ld.param.b64 %rd2, [acquire_seq_cst_i64_global_cta_param_1];
-; SM90-NEXT: ld.param.b64 %rd3, [acquire_seq_cst_i64_global_cta_param_2];
+; SM90-NEXT: ld.param::func.b64 %rd2, [acquire_seq_cst_i64_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd3, [acquire_seq_cst_i64_global_cta_param_2];
; SM90-NEXT: atom.acquire.cta.global.cas.b64 %rd4, [%rd1], %rd2, %rd3;
-; SM90-NEXT: st.param.b64 [func_retval0], %rd3;
+; SM90-NEXT: st.param::func.b64 [func_retval0], %rd3;
; SM90-NEXT: ret;
%pairold = cmpxchg ptr addrspace(1) %addr, i64 %cmp, i64 %new syncscope("block") acquire seq_cst
ret i64 %new
@@ -1737,11 +1737,11 @@ define i64 @release_monotonic_i64_global_cta(ptr addrspace(1) %addr, i64 %cmp, i
; SM90-NEXT: .reg .b64 %rd<5>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [release_monotonic_i64_global_cta_param_0];
-; SM90-NEXT: ld.param.b64 %rd2, [release_monotonic_i64_global_cta_param_1];
-; SM90-NEXT: ld.param.b64 %rd3, [release_monotonic_i64_global_cta_param_2];
+; SM90-NEXT: ld.param::func.b64 %rd1, [release_monotonic_i64_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd2, [release_monotonic_i64_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd3, [release_monotonic_i64_global_cta_param_2];
; SM90-NEXT: atom.release.cta.global.cas.b64 %rd4, [%rd1], %rd2, %rd3;
-; SM90-NEXT: st.param.b64 [func_retval0], %rd3;
+; SM90-NEXT: st.param::func.b64 [func_retval0], %rd3;
; SM90-NEXT: ret;
%pairold = cmpxchg ptr addrspace(1) %addr, i64 %cmp, i64 %new syncscope("block") release monotonic
ret i64 %new
@@ -1753,11 +1753,11 @@ define i64 @release_acquire_i64_global_cta(ptr addrspace(1) %addr, i64 %cmp, i64
; SM90-NEXT: .reg .b64 %rd<5>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [release_acquire_i64_global_cta_param_0];
-; SM90-NEXT: ld.param.b64 %rd2, [release_acquire_i64_global_cta_param_1];
-; SM90-NEXT: ld.param.b64 %rd3, [release_acquire_i64_global_cta_param_2];
+; SM90-NEXT: ld.param::func.b64 %rd1, [release_acquire_i64_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd2, [release_acquire_i64_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd3, [release_acquire_i64_global_cta_param_2];
; SM90-NEXT: atom.acq_rel.cta.global.cas.b64 %rd4, [%rd1], %rd2, %rd3;
-; SM90-NEXT: st.param.b64 [func_retval0], %rd3;
+; SM90-NEXT: st.param::func.b64 [func_retval0], %rd3;
; SM90-NEXT: ret;
%pairold = cmpxchg ptr addrspace(1) %addr, i64 %cmp, i64 %new syncscope("block") release acquire
ret i64 %new
@@ -1769,12 +1769,12 @@ define i64 @release_seq_cst_i64_global_cta(ptr addrspace(1) %addr, i64 %cmp, i64
; SM90-NEXT: .reg .b64 %rd<5>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [release_seq_cst_i64_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd1, [release_seq_cst_i64_global_cta_param_0];
; SM90-NEXT: fence.sc.cta;
-; SM90-NEXT: ld.param.b64 %rd2, [release_seq_cst_i64_global_cta_param_1];
-; SM90-NEXT: ld.param.b64 %rd3, [release_seq_cst_i64_global_cta_param_2];
+; SM90-NEXT: ld.param::func.b64 %rd2, [release_seq_cst_i64_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd3, [release_seq_cst_i64_global_cta_param_2];
; SM90-NEXT: atom.acquire.cta.global.cas.b64 %rd4, [%rd1], %rd2, %rd3;
-; SM90-NEXT: st.param.b64 [func_retval0], %rd3;
+; SM90-NEXT: st.param::func.b64 [func_retval0], %rd3;
; SM90-NEXT: ret;
%pairold = cmpxchg ptr addrspace(1) %addr, i64 %cmp, i64 %new syncscope("block") release seq_cst
ret i64 %new
@@ -1786,11 +1786,11 @@ define i64 @acq_rel_monotonic_i64_global_cta(ptr addrspace(1) %addr, i64 %cmp, i
; SM90-NEXT: .reg .b64 %rd<5>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [acq_rel_monotonic_i64_global_cta_param_0];
-; SM90-NEXT: ld.param.b64 %rd2, [acq_rel_monotonic_i64_global_cta_param_1];
-; SM90-NEXT: ld.param.b64 %rd3, [acq_rel_monotonic_i64_global_cta_param_2];
+; SM90-NEXT: ld.param::func.b64 %rd1, [acq_rel_monotonic_i64_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd2, [acq_rel_monotonic_i64_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd3, [acq_rel_monotonic_i64_global_cta_param_2];
; SM90-NEXT: atom.acq_rel.cta.global.cas.b64 %rd4, [%rd1], %rd2, %rd3;
-; SM90-NEXT: st.param.b64 [func_retval0], %rd3;
+; SM90-NEXT: st.param::func.b64 [func_retval0], %rd3;
; SM90-NEXT: ret;
%pairold = cmpxchg ptr addrspace(1) %addr, i64 %cmp, i64 %new syncscope("block") acq_rel monotonic
ret i64 %new
@@ -1802,11 +1802,11 @@ define i64 @acq_rel_acquire_i64_global_cta(ptr addrspace(1) %addr, i64 %cmp, i64
; SM90-NEXT: .reg .b64 %rd<5>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [acq_rel_acquire_i64_global_cta_param_0];
-; SM90-NEXT: ld.param.b64 %rd2, [acq_rel_acquire_i64_global_cta_param_1];
-; SM90-NEXT: ld.param.b64 %rd3, [acq_rel_acquire_i64_global_cta_param_2];
+; SM90-NEXT: ld.param::func.b64 %rd1, [acq_rel_acquire_i64_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd2, [acq_rel_acquire_i64_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd3, [acq_rel_acquire_i64_global_cta_param_2];
; SM90-NEXT: atom.acq_rel.cta.global.cas.b64 %rd4, [%rd1], %rd2, %rd3;
-; SM90-NEXT: st.param.b64 [func_retval0], %rd3;
+; SM90-NEXT: st.param::func.b64 [func_retval0], %rd3;
; SM90-NEXT: ret;
%pairold = cmpxchg ptr addrspace(1) %addr, i64 %cmp, i64 %new syncscope("block") acq_rel acquire
ret i64 %new
@@ -1818,12 +1818,12 @@ define i64 @acq_rel_seq_cst_i64_global_cta(ptr addrspace(1) %addr, i64 %cmp, i64
; SM90-NEXT: .reg .b64 %rd<5>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [acq_rel_seq_cst_i64_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd1, [acq_rel_seq_cst_i64_global_cta_param_0];
; SM90-NEXT: fence.sc.cta;
-; SM90-NEXT: ld.param.b64 %rd2, [acq_rel_seq_cst_i64_global_cta_param_1];
-; SM90-NEXT: ld.param.b64 %rd3, [acq_rel_seq_cst_i64_global_cta_param_2];
+; SM90-NEXT: ld.param::func.b64 %rd2, [acq_rel_seq_cst_i64_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd3, [acq_rel_seq_cst_i64_global_cta_param_2];
; SM90-NEXT: atom.acquire.cta.global.cas.b64 %rd4, [%rd1], %rd2, %rd3;
-; SM90-NEXT: st.param.b64 [func_retval0], %rd3;
+; SM90-NEXT: st.param::func.b64 [func_retval0], %rd3;
; SM90-NEXT: ret;
%pairold = cmpxchg ptr addrspace(1) %addr, i64 %cmp, i64 %new syncscope("block") acq_rel seq_cst
ret i64 %new
@@ -1835,12 +1835,12 @@ define i64 @seq_cst_monotonic_i64_global_cta(ptr addrspace(1) %addr, i64 %cmp, i
; SM90-NEXT: .reg .b64 %rd<5>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [seq_cst_monotonic_i64_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd1, [seq_cst_monotonic_i64_global_cta_param_0];
; SM90-NEXT: fence.sc.cta;
-; SM90-NEXT: ld.param.b64 %rd2, [seq_cst_monotonic_i64_global_cta_param_1];
-; SM90-NEXT: ld.param.b64 %rd3, [seq_cst_monotonic_i64_global_cta_param_2];
+; SM90-NEXT: ld.param::func.b64 %rd2, [seq_cst_monotonic_i64_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd3, [seq_cst_monotonic_i64_global_cta_param_2];
; SM90-NEXT: atom.acquire.cta.global.cas.b64 %rd4, [%rd1], %rd2, %rd3;
-; SM90-NEXT: st.param.b64 [func_retval0], %rd3;
+; SM90-NEXT: st.param::func.b64 [func_retval0], %rd3;
; SM90-NEXT: ret;
%pairold = cmpxchg ptr addrspace(1) %addr, i64 %cmp, i64 %new syncscope("block") seq_cst monotonic
ret i64 %new
@@ -1852,12 +1852,12 @@ define i64 @seq_cst_acquire_i64_global_cta(ptr addrspace(1) %addr, i64 %cmp, i64
; SM90-NEXT: .reg .b64 %rd<5>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [seq_cst_acquire_i64_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd1, [seq_cst_acquire_i64_global_cta_param_0];
; SM90-NEXT: fence.sc.cta;
-; SM90-NEXT: ld.param.b64 %rd2, [seq_cst_acquire_i64_global_cta_param_1];
-; SM90-NEXT: ld.param.b64 %rd3, [seq_cst_acquire_i64_global_cta_param_2];
+; SM90-NEXT: ld.param::func.b64 %rd2, [seq_cst_acquire_i64_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd3, [seq_cst_acquire_i64_global_cta_param_2];
; SM90-NEXT: atom.acquire.cta.global.cas.b64 %rd4, [%rd1], %rd2, %rd3;
-; SM90-NEXT: st.param.b64 [func_retval0], %rd3;
+; SM90-NEXT: st.param::func.b64 [func_retval0], %rd3;
; SM90-NEXT: ret;
%pairold = cmpxchg ptr addrspace(1) %addr, i64 %cmp, i64 %new syncscope("block") seq_cst acquire
ret i64 %new
@@ -1869,12 +1869,12 @@ define i64 @seq_cst_seq_cst_i64_global_cta(ptr addrspace(1) %addr, i64 %cmp, i64
; SM90-NEXT: .reg .b64 %rd<5>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [seq_cst_seq_cst_i64_global_cta_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd1, [seq_cst_seq_cst_i64_global_cta_param_0];
; SM90-NEXT: fence.sc.cta;
-; SM90-NEXT: ld.param.b64 %rd2, [seq_cst_seq_cst_i64_global_cta_param_1];
-; SM90-NEXT: ld.param.b64 %rd3, [seq_cst_seq_cst_i64_global_cta_param_2];
+; SM90-NEXT: ld.param::func.b64 %rd2, [seq_cst_seq_cst_i64_global_cta_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd3, [seq_cst_seq_cst_i64_global_cta_param_2];
; SM90-NEXT: atom.acquire.cta.global.cas.b64 %rd4, [%rd1], %rd2, %rd3;
-; SM90-NEXT: st.param.b64 [func_retval0], %rd3;
+; SM90-NEXT: st.param::func.b64 [func_retval0], %rd3;
; SM90-NEXT: ret;
%pairold = cmpxchg ptr addrspace(1) %addr, i64 %cmp, i64 %new syncscope("block") seq_cst seq_cst
ret i64 %new
@@ -1889,10 +1889,10 @@ define i8 @acq_rel_acquire_i8_global(ptr addrspace(1) %addr, i8 %cmp, i8 %new) {
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b8 %rs1, [acq_rel_acquire_i8_global_param_2];
-; SM90-NEXT: ld.param.b64 %rd2, [acq_rel_acquire_i8_global_param_0];
+; SM90-NEXT: ld.param::func.b8 %rs1, [acq_rel_acquire_i8_global_param_2];
+; SM90-NEXT: ld.param::func.b64 %rd2, [acq_rel_acquire_i8_global_param_0];
; SM90-NEXT: fence.release.sys;
-; SM90-NEXT: ld.param.b8 %r7, [acq_rel_acquire_i8_global_param_1];
+; SM90-NEXT: ld.param::func.b8 %r7, [acq_rel_acquire_i8_global_param_1];
; SM90-NEXT: and.b64 %rd1, %rd2, -4;
; SM90-NEXT: cvt.u32.u64 %r8, %rd2;
; SM90-NEXT: and.b32 %r9, %r8, 3;
@@ -1920,7 +1920,7 @@ define i8 @acq_rel_acquire_i8_global(ptr addrspace(1) %addr, i8 %cmp, i8 %new) {
; SM90-NEXT: @%p2 bra $L__BB60_1;
; SM90-NEXT: $L__BB60_3: // %partword.cmpxchg.end
; SM90-NEXT: fence.acquire.sys;
-; SM90-NEXT: st.param.b32 [func_retval0], %r12;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r12;
; SM90-NEXT: ret;
%pairold = cmpxchg ptr addrspace(1) %addr, i8 %cmp, i8 %new acq_rel acquire
ret i8 %new
@@ -1933,11 +1933,11 @@ define i32 @acq_rel_acquire_i32_global(ptr addrspace(1) %addr, i32 %cmp, i32 %ne
; SM90-NEXT: .reg .b64 %rd<2>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [acq_rel_acquire_i32_global_param_0];
-; SM90-NEXT: ld.param.b32 %r1, [acq_rel_acquire_i32_global_param_1];
-; SM90-NEXT: ld.param.b32 %r2, [acq_rel_acquire_i32_global_param_2];
+; SM90-NEXT: ld.param::func.b64 %rd1, [acq_rel_acquire_i32_global_param_0];
+; SM90-NEXT: ld.param::func.b32 %r1, [acq_rel_acquire_i32_global_param_1];
+; SM90-NEXT: ld.param::func.b32 %r2, [acq_rel_acquire_i32_global_param_2];
; SM90-NEXT: atom.acq_rel.sys.global.cas.b32 %r3, [%rd1], %r1, %r2;
-; SM90-NEXT: st.param.b32 [func_retval0], %r2;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r2;
; SM90-NEXT: ret;
%pairold = cmpxchg ptr addrspace(1) %addr, i32 %cmp, i32 %new acq_rel acquire
ret i32 %new
@@ -1950,11 +1950,11 @@ define i32 @acq_rel_acquire_i32_global_sys(ptr addrspace(1) %addr, i32 %cmp, i32
; SM90-NEXT: .reg .b64 %rd<2>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [acq_rel_acquire_i32_global_sys_param_0];
-; SM90-NEXT: ld.param.b32 %r1, [acq_rel_acquire_i32_global_sys_param_1];
-; SM90-NEXT: ld.param.b32 %r2, [acq_rel_acquire_i32_global_sys_param_2];
+; SM90-NEXT: ld.param::func.b64 %rd1, [acq_rel_acquire_i32_global_sys_param_0];
+; SM90-NEXT: ld.param::func.b32 %r1, [acq_rel_acquire_i32_global_sys_param_1];
+; SM90-NEXT: ld.param::func.b32 %r2, [acq_rel_acquire_i32_global_sys_param_2];
; SM90-NEXT: atom.acq_rel.sys.global.cas.b32 %r3, [%rd1], %r1, %r2;
-; SM90-NEXT: st.param.b32 [func_retval0], %r2;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r2;
; SM90-NEXT: ret;
%pairold = cmpxchg ptr addrspace(1) %addr, i32 %cmp, i32 %new syncscope("") acq_rel acquire
ret i32 %new
@@ -1967,11 +1967,11 @@ define i32 @acq_rel_acquire_i32_global_cluster(ptr addrspace(1) %addr, i32 %cmp,
; SM90-NEXT: .reg .b64 %rd<2>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [acq_rel_acquire_i32_global_cluster_param_0];
-; SM90-NEXT: ld.param.b32 %r1, [acq_rel_acquire_i32_global_cluster_param_1];
-; SM90-NEXT: ld.param.b32 %r2, [acq_rel_acquire_i32_global_cluster_param_2];
+; SM90-NEXT: ld.param::func.b64 %rd1, [acq_rel_acquire_i32_global_cluster_param_0];
+; SM90-NEXT: ld.param::func.b32 %r1, [acq_rel_acquire_i32_global_cluster_param_1];
+; SM90-NEXT: ld.param::func.b32 %r2, [acq_rel_acquire_i32_global_cluster_param_2];
; SM90-NEXT: atom.acq_rel.cluster.global.cas.b32 %r3, [%rd1], %r1, %r2;
-; SM90-NEXT: st.param.b32 [func_retval0], %r2;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r2;
; SM90-NEXT: ret;
%pairold = cmpxchg ptr addrspace(1) %addr, i32 %cmp, i32 %new syncscope("cluster") acq_rel acquire
ret i32 %new
@@ -1984,11 +1984,11 @@ define i32 @acq_rel_acquire_i32_global_gpu(ptr addrspace(1) %addr, i32 %cmp, i32
; SM90-NEXT: .reg .b64 %rd<2>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [acq_rel_acquire_i32_global_gpu_param_0];
-; SM90-NEXT: ld.param.b32 %r1, [acq_rel_acquire_i32_global_gpu_param_1];
-; SM90-NEXT: ld.param.b32 %r2, [acq_rel_acquire_i32_global_gpu_param_2];
+; SM90-NEXT: ld.param::func.b64 %rd1, [acq_rel_acquire_i32_global_gpu_param_0];
+; SM90-NEXT: ld.param::func.b32 %r1, [acq_rel_acquire_i32_global_gpu_param_1];
+; SM90-NEXT: ld.param::func.b32 %r2, [acq_rel_acquire_i32_global_gpu_param_2];
; SM90-NEXT: atom.acq_rel.gpu.global.cas.b32 %r3, [%rd1], %r1, %r2;
-; SM90-NEXT: st.param.b32 [func_retval0], %r2;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r2;
; SM90-NEXT: ret;
%pairold = cmpxchg ptr addrspace(1) %addr, i32 %cmp, i32 %new syncscope("device") acq_rel acquire
ret i32 %new
@@ -2003,10 +2003,10 @@ define i8 @acq_rel_acquire_i8_generic_cta(ptr %addr, i8 %cmp, i8 %new) {
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b8 %rs1, [acq_rel_acquire_i8_generic_cta_param_2];
-; SM90-NEXT: ld.param.b64 %rd2, [acq_rel_acquire_i8_generic_cta_param_0];
+; SM90-NEXT: ld.param::func.b8 %rs1, [acq_rel_acquire_i8_generic_cta_param_2];
+; SM90-NEXT: ld.param::func.b64 %rd2, [acq_rel_acquire_i8_generic_cta_param_0];
; SM90-NEXT: fence.release.cta;
-; SM90-NEXT: ld.param.b8 %r7, [acq_rel_acquire_i8_generic_cta_param_1];
+; SM90-NEXT: ld.param::func.b8 %r7, [acq_rel_acquire_i8_generic_cta_param_1];
; SM90-NEXT: and.b64 %rd1, %rd2, -4;
; SM90-NEXT: cvt.u32.u64 %r8, %rd2;
; SM90-NEXT: and.b32 %r9, %r8, 3;
@@ -2034,7 +2034,7 @@ define i8 @acq_rel_acquire_i8_generic_cta(ptr %addr, i8 %cmp, i8 %new) {
; SM90-NEXT: @%p2 bra $L__BB65_1;
; SM90-NEXT: $L__BB65_3: // %partword.cmpxchg.end
; SM90-NEXT: fence.acquire.cta;
-; SM90-NEXT: st.param.b32 [func_retval0], %r12;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r12;
; SM90-NEXT: ret;
%pairold = cmpxchg ptr %addr, i8 %cmp, i8 %new syncscope("block") acq_rel acquire
ret i8 %new
@@ -2049,10 +2049,10 @@ define i8 @acq_rel_acquire_i8_shared_cta(ptr addrspace(3) %addr, i8 %cmp, i8 %ne
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b8 %rs1, [acq_rel_acquire_i8_shared_cta_param_2];
-; SM90-NEXT: ld.param.b64 %rd2, [acq_rel_acquire_i8_shared_cta_param_0];
+; SM90-NEXT: ld.param::func.b8 %rs1, [acq_rel_acquire_i8_shared_cta_param_2];
+; SM90-NEXT: ld.param::func.b64 %rd2, [acq_rel_acquire_i8_shared_cta_param_0];
; SM90-NEXT: fence.release.cta;
-; SM90-NEXT: ld.param.b8 %r7, [acq_rel_acquire_i8_shared_cta_param_1];
+; SM90-NEXT: ld.param::func.b8 %r7, [acq_rel_acquire_i8_shared_cta_param_1];
; SM90-NEXT: and.b64 %rd1, %rd2, -4;
; SM90-NEXT: cvt.u32.u64 %r8, %rd2;
; SM90-NEXT: and.b32 %r9, %r8, 3;
@@ -2080,7 +2080,7 @@ define i8 @acq_rel_acquire_i8_shared_cta(ptr addrspace(3) %addr, i8 %cmp, i8 %ne
; SM90-NEXT: @%p2 bra $L__BB66_1;
; SM90-NEXT: $L__BB66_3: // %partword.cmpxchg.end
; SM90-NEXT: fence.acquire.cta;
-; SM90-NEXT: st.param.b32 [func_retval0], %r12;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r12;
; SM90-NEXT: ret;
%pairold = cmpxchg ptr addrspace(3) %addr, i8 %cmp, i8 %new syncscope("block") acq_rel acquire
ret i8 %new
@@ -2093,11 +2093,11 @@ define i32 @acq_rel_acquire_i32_generic_cta(ptr %addr, i32 %cmp, i32 %new) {
; SM90-NEXT: .reg .b64 %rd<2>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [acq_rel_acquire_i32_generic_cta_param_0];
-; SM90-NEXT: ld.param.b32 %r1, [acq_rel_acquire_i32_generic_cta_param_1];
-; SM90-NEXT: ld.param.b32 %r2, [acq_rel_acquire_i32_generic_cta_param_2];
+; SM90-NEXT: ld.param::func.b64 %rd1, [acq_rel_acquire_i32_generic_cta_param_0];
+; SM90-NEXT: ld.param::func.b32 %r1, [acq_rel_acquire_i32_generic_cta_param_1];
+; SM90-NEXT: ld.param::func.b32 %r2, [acq_rel_acquire_i32_generic_cta_param_2];
; SM90-NEXT: atom.acq_rel.cta.cas.b32 %r3, [%rd1], %r1, %r2;
-; SM90-NEXT: st.param.b32 [func_retval0], %r2;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r2;
; SM90-NEXT: ret;
%pairold = cmpxchg ptr %addr, i32 %cmp, i32 %new syncscope("block") acq_rel acquire
ret i32 %new
@@ -2110,11 +2110,11 @@ define i32 @acq_rel_acquire_i32_shared_cta(ptr addrspace(3) %addr, i32 %cmp, i32
; SM90-NEXT: .reg .b64 %rd<2>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [acq_rel_acquire_i32_shared_cta_param_0];
-; SM90-NEXT: ld.param.b32 %r1, [acq_rel_acquire_i32_shared_cta_param_1];
-; SM90-NEXT: ld.param.b32 %r2, [acq_rel_acquire_i32_shared_cta_param_2];
+; SM90-NEXT: ld.param::func.b64 %rd1, [acq_rel_acquire_i32_shared_cta_param_0];
+; SM90-NEXT: ld.param::func.b32 %r1, [acq_rel_acquire_i32_shared_cta_param_1];
+; SM90-NEXT: ld.param::func.b32 %r2, [acq_rel_acquire_i32_shared_cta_param_2];
; SM90-NEXT: atom.acq_rel.cta.shared.cas.b32 %r3, [%rd1], %r1, %r2;
-; SM90-NEXT: st.param.b32 [func_retval0], %r2;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r2;
; SM90-NEXT: ret;
%pairold = cmpxchg ptr addrspace(3) %addr, i32 %cmp, i32 %new syncscope("block") acq_rel acquire
ret i32 %new
diff --git a/llvm/test/CodeGen/NVPTX/convert-sm100.ll b/llvm/test/CodeGen/NVPTX/convert-sm100.ll
index a89b35cad3582..7c820869ebe81 100644
--- a/llvm/test/CodeGen/NVPTX/convert-sm100.ll
+++ b/llvm/test/CodeGen/NVPTX/convert-sm100.ll
@@ -13,9 +13,9 @@ define i32 @cvt_rn_satf_tf32_f32(float %f1) {
; CHECK-NEXT: .reg .b32 %r<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [cvt_rn_satf_tf32_f32_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r1, [cvt_rn_satf_tf32_f32_param_0];
; CHECK-NEXT: cvt.rn.satfinite.tf32.f32 %r2, %r1;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r2;
; CHECK-NEXT: ret;
%val = call i32 @llvm.nvvm.f2tf32.rn.satfinite(float %f1)
ret i32 %val
@@ -27,9 +27,9 @@ define i32 @cvt_rn_relu_satf_tf32_f32(float %f1) {
; CHECK-NEXT: .reg .b32 %r<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [cvt_rn_relu_satf_tf32_f32_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r1, [cvt_rn_relu_satf_tf32_f32_param_0];
; CHECK-NEXT: cvt.rn.relu.satfinite.tf32.f32 %r2, %r1;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r2;
; CHECK-NEXT: ret;
%val = call i32 @llvm.nvvm.f2tf32.rn.relu.satfinite(float %f1)
ret i32 %val
@@ -41,9 +41,9 @@ define i32 @cvt_rz_satf_tf32_f32(float %f1) {
; CHECK-NEXT: .reg .b32 %r<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [cvt_rz_satf_tf32_f32_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r1, [cvt_rz_satf_tf32_f32_param_0];
; CHECK-NEXT: cvt.rz.satfinite.tf32.f32 %r2, %r1;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r2;
; CHECK-NEXT: ret;
%val = call i32 @llvm.nvvm.f2tf32.rz.satfinite(float %f1)
ret i32 %val
@@ -55,9 +55,9 @@ define i32 @cvt_rz_relu_satf_tf32_f32(float %f1) {
; CHECK-NEXT: .reg .b32 %r<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [cvt_rz_relu_satf_tf32_f32_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r1, [cvt_rz_relu_satf_tf32_f32_param_0];
; CHECK-NEXT: cvt.rz.relu.satfinite.tf32.f32 %r2, %r1;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r2;
; CHECK-NEXT: ret;
%val = call i32 @llvm.nvvm.f2tf32.rz.relu.satfinite(float %f1)
ret i32 %val
diff --git a/llvm/test/CodeGen/NVPTX/convert-sm100a.ll b/llvm/test/CodeGen/NVPTX/convert-sm100a.ll
index cbf7c114b06ca..b3368a603a0ff 100644
--- a/llvm/test/CodeGen/NVPTX/convert-sm100a.ll
+++ b/llvm/test/CodeGen/NVPTX/convert-sm100a.ll
@@ -13,11 +13,11 @@ define i16 @cvt_rn_sf_e2m3x2_f32(float %f1, float %f2) {
; CHECK-NEXT: .reg .b32 %r<4>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [cvt_rn_sf_e2m3x2_f32_param_0];
-; CHECK-NEXT: ld.param.b32 %r2, [cvt_rn_sf_e2m3x2_f32_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r1, [cvt_rn_sf_e2m3x2_f32_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r2, [cvt_rn_sf_e2m3x2_f32_param_1];
; CHECK-NEXT: cvt.rn.satfinite.e2m3x2.f32 %rs1, %r1, %r2;
; CHECK-NEXT: cvt.u32.u16 %r3, %rs1;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r3;
; CHECK-NEXT: ret;
%val = call i16 @llvm.nvvm.ff.to.e2m3x2.rn.satfinite(float %f1, float %f2)
ret i16 %val
@@ -30,11 +30,11 @@ define i16 @cvt_rn_relu_sf_e2m3x2_f32(float %f1, float %f2) {
; CHECK-NEXT: .reg .b32 %r<4>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [cvt_rn_relu_sf_e2m3x2_f32_param_0];
-; CHECK-NEXT: ld.param.b32 %r2, [cvt_rn_relu_sf_e2m3x2_f32_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r1, [cvt_rn_relu_sf_e2m3x2_f32_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r2, [cvt_rn_relu_sf_e2m3x2_f32_param_1];
; CHECK-NEXT: cvt.rn.satfinite.relu.e2m3x2.f32 %rs1, %r1, %r2;
; CHECK-NEXT: cvt.u32.u16 %r3, %rs1;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r3;
; CHECK-NEXT: ret;
%val = call i16 @llvm.nvvm.ff.to.e2m3x2.rn.relu.satfinite(float %f1, float %f2)
ret i16 %val
@@ -47,11 +47,11 @@ define i16 @cvt_rn_sf_e3m2x2_f32(float %f1, float %f2) {
; CHECK-NEXT: .reg .b32 %r<4>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [cvt_rn_sf_e3m2x2_f32_param_0];
-; CHECK-NEXT: ld.param.b32 %r2, [cvt_rn_sf_e3m2x2_f32_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r1, [cvt_rn_sf_e3m2x2_f32_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r2, [cvt_rn_sf_e3m2x2_f32_param_1];
; CHECK-NEXT: cvt.rn.satfinite.e3m2x2.f32 %rs1, %r1, %r2;
; CHECK-NEXT: cvt.u32.u16 %r3, %rs1;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r3;
; CHECK-NEXT: ret;
%val = call i16 @llvm.nvvm.ff.to.e3m2x2.rn.satfinite(float %f1, float %f2)
ret i16 %val
@@ -64,11 +64,11 @@ define i16 @cvt_rn_relu_sf_e3m2x2_f32(float %f1, float %f2) {
; CHECK-NEXT: .reg .b32 %r<4>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [cvt_rn_relu_sf_e3m2x2_f32_param_0];
-; CHECK-NEXT: ld.param.b32 %r2, [cvt_rn_relu_sf_e3m2x2_f32_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r1, [cvt_rn_relu_sf_e3m2x2_f32_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r2, [cvt_rn_relu_sf_e3m2x2_f32_param_1];
; CHECK-NEXT: cvt.rn.satfinite.relu.e3m2x2.f32 %rs1, %r1, %r2;
; CHECK-NEXT: cvt.u32.u16 %r3, %rs1;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r3;
; CHECK-NEXT: ret;
%val = call i16 @llvm.nvvm.ff.to.e3m2x2.rn.relu.satfinite(float %f1, float %f2)
ret i16 %val
@@ -81,9 +81,9 @@ define <2 x half> @cvt_rn_f16x2_e2m3x2(i16 %in) {
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b16 %rs1, [cvt_rn_f16x2_e2m3x2_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [cvt_rn_f16x2_e2m3x2_param_0];
; CHECK-NEXT: cvt.rn.f16x2.e2m3x2 %r1, %rs1;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
%val = call <2 x half> @llvm.nvvm.e2m3x2.to.f16x2.rn(i16 %in)
ret <2 x half> %val
@@ -96,9 +96,9 @@ define <2 x half> @cvt_rn_relu_f16x2_e2m3x2_relu(i16 %in) {
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b16 %rs1, [cvt_rn_relu_f16x2_e2m3x2_relu_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [cvt_rn_relu_f16x2_e2m3x2_relu_param_0];
; CHECK-NEXT: cvt.rn.relu.f16x2.e2m3x2 %r1, %rs1;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
%val = call <2 x half> @llvm.nvvm.e2m3x2.to.f16x2.rn.relu(i16 %in)
ret <2 x half> %val
@@ -111,9 +111,9 @@ define <2 x half> @cvt_rn_f16x2_e3m2x2(i16 %in) {
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b16 %rs1, [cvt_rn_f16x2_e3m2x2_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [cvt_rn_f16x2_e3m2x2_param_0];
; CHECK-NEXT: cvt.rn.f16x2.e3m2x2 %r1, %rs1;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
%val = call <2 x half> @llvm.nvvm.e3m2x2.to.f16x2.rn(i16 %in)
ret <2 x half> %val
@@ -126,9 +126,9 @@ define <2 x half> @cvt_rn_relu_f16x2_e3m2x2(i16 %in) {
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b16 %rs1, [cvt_rn_relu_f16x2_e3m2x2_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [cvt_rn_relu_f16x2_e3m2x2_param_0];
; CHECK-NEXT: cvt.rn.relu.f16x2.e3m2x2 %r1, %rs1;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
%val = call <2 x half> @llvm.nvvm.e3m2x2.to.f16x2.rn.relu(i16 %in)
ret <2 x half> %val
@@ -141,11 +141,11 @@ define i16 @cvt_rz_ue8m0x2_f32(float %f1, float %f2) {
; CHECK-NEXT: .reg .b32 %r<4>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [cvt_rz_ue8m0x2_f32_param_0];
-; CHECK-NEXT: ld.param.b32 %r2, [cvt_rz_ue8m0x2_f32_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r1, [cvt_rz_ue8m0x2_f32_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r2, [cvt_rz_ue8m0x2_f32_param_1];
; CHECK-NEXT: cvt.rz.ue8m0x2.f32 %rs1, %r1, %r2;
; CHECK-NEXT: cvt.u32.u16 %r3, %rs1;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r3;
; CHECK-NEXT: ret;
%val = call i16 @llvm.nvvm.ff.to.ue8m0x2.rz(float %f1, float %f2)
ret i16 %val
@@ -158,11 +158,11 @@ define i16 @cvt_rz_sf_ue8m0x2_f32(float %f1, float %f2) {
; CHECK-NEXT: .reg .b32 %r<4>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [cvt_rz_sf_ue8m0x2_f32_param_0];
-; CHECK-NEXT: ld.param.b32 %r2, [cvt_rz_sf_ue8m0x2_f32_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r1, [cvt_rz_sf_ue8m0x2_f32_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r2, [cvt_rz_sf_ue8m0x2_f32_param_1];
; CHECK-NEXT: cvt.rz.satfinite.ue8m0x2.f32 %rs1, %r1, %r2;
; CHECK-NEXT: cvt.u32.u16 %r3, %rs1;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r3;
; CHECK-NEXT: ret;
%val = call i16 @llvm.nvvm.ff.to.ue8m0x2.rz.satfinite(float %f1, float %f2)
ret i16 %val
@@ -175,11 +175,11 @@ define i16 @cvt_rp_ue8m0x2_f32(float %f1, float %f2) {
; CHECK-NEXT: .reg .b32 %r<4>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [cvt_rp_ue8m0x2_f32_param_0];
-; CHECK-NEXT: ld.param.b32 %r2, [cvt_rp_ue8m0x2_f32_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r1, [cvt_rp_ue8m0x2_f32_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r2, [cvt_rp_ue8m0x2_f32_param_1];
; CHECK-NEXT: cvt.rp.ue8m0x2.f32 %rs1, %r1, %r2;
; CHECK-NEXT: cvt.u32.u16 %r3, %rs1;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r3;
; CHECK-NEXT: ret;
%val = call i16 @llvm.nvvm.ff.to.ue8m0x2.rp(float %f1, float %f2)
ret i16 %val
@@ -192,11 +192,11 @@ define i16 @cvt_rp_sf_ue8m0x2_f32(float %f1, float %f2) {
; CHECK-NEXT: .reg .b32 %r<4>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [cvt_rp_sf_ue8m0x2_f32_param_0];
-; CHECK-NEXT: ld.param.b32 %r2, [cvt_rp_sf_ue8m0x2_f32_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r1, [cvt_rp_sf_ue8m0x2_f32_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r2, [cvt_rp_sf_ue8m0x2_f32_param_1];
; CHECK-NEXT: cvt.rp.satfinite.ue8m0x2.f32 %rs1, %r1, %r2;
; CHECK-NEXT: cvt.u32.u16 %r3, %rs1;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r3;
; CHECK-NEXT: ret;
%val = call i16 @llvm.nvvm.ff.to.ue8m0x2.rp.satfinite(float %f1, float %f2)
ret i16 %val
@@ -209,10 +209,10 @@ define i16 @cvt_rz_ue8m0x2_bf16x2(<2 x bfloat> %in) {
; CHECK-NEXT: .reg .b32 %r<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [cvt_rz_ue8m0x2_bf16x2_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r1, [cvt_rz_ue8m0x2_bf16x2_param_0];
; CHECK-NEXT: cvt.rz.ue8m0x2.bf16x2 %rs1, %r1;
; CHECK-NEXT: cvt.u32.u16 %r2, %rs1;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r2;
; CHECK-NEXT: ret;
%val = call i16 @llvm.nvvm.bf16x2.to.ue8m0x2.rz(<2 x bfloat> %in)
ret i16 %val
@@ -225,10 +225,10 @@ define i16 @cvt_rz_sf_ue8m0x2_bf16x2(<2 x bfloat> %in) {
; CHECK-NEXT: .reg .b32 %r<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [cvt_rz_sf_ue8m0x2_bf16x2_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r1, [cvt_rz_sf_ue8m0x2_bf16x2_param_0];
; CHECK-NEXT: cvt.rz.satfinite.ue8m0x2.bf16x2 %rs1, %r1;
; CHECK-NEXT: cvt.u32.u16 %r2, %rs1;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r2;
; CHECK-NEXT: ret;
%val = call i16 @llvm.nvvm.bf16x2.to.ue8m0x2.rz.satfinite(<2 x bfloat> %in)
ret i16 %val
@@ -241,10 +241,10 @@ define i16 @cvt_rp_ue8m0x2_bf16x2(<2 x bfloat> %in) {
; CHECK-NEXT: .reg .b32 %r<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [cvt_rp_ue8m0x2_bf16x2_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r1, [cvt_rp_ue8m0x2_bf16x2_param_0];
; CHECK-NEXT: cvt.rp.ue8m0x2.bf16x2 %rs1, %r1;
; CHECK-NEXT: cvt.u32.u16 %r2, %rs1;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r2;
; CHECK-NEXT: ret;
%val = call i16 @llvm.nvvm.bf16x2.to.ue8m0x2.rp(<2 x bfloat> %in)
ret i16 %val
@@ -257,10 +257,10 @@ define i16 @cvt_rp_sf_ue8m0x2_bf16x2(<2 x bfloat> %in) {
; CHECK-NEXT: .reg .b32 %r<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [cvt_rp_sf_ue8m0x2_bf16x2_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r1, [cvt_rp_sf_ue8m0x2_bf16x2_param_0];
; CHECK-NEXT: cvt.rp.satfinite.ue8m0x2.bf16x2 %rs1, %r1;
; CHECK-NEXT: cvt.u32.u16 %r2, %rs1;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r2;
; CHECK-NEXT: ret;
%val = call i16 @llvm.nvvm.bf16x2.to.ue8m0x2.rp.satfinite(<2 x bfloat> %in)
ret i16 %val
@@ -273,9 +273,9 @@ define <2 x bfloat> @cvt_bf16x2_ue8m0x2(i16 %in) {
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b16 %rs1, [cvt_bf16x2_ue8m0x2_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [cvt_bf16x2_ue8m0x2_param_0];
; CHECK-NEXT: cvt.rn.bf16x2.ue8m0x2 %r1, %rs1;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
%val = call <2 x bfloat> @llvm.nvvm.ue8m0x2.to.bf16x2(i16 %in)
ret <2 x bfloat> %val
@@ -288,15 +288,15 @@ define i16 @cvt_rn_sf_e2m1x2_f32(float %f1, float %f2) {
; CHECK-NEXT: .reg .b32 %r<4>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [cvt_rn_sf_e2m1x2_f32_param_0];
-; CHECK-NEXT: ld.param.b32 %r2, [cvt_rn_sf_e2m1x2_f32_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r1, [cvt_rn_sf_e2m1x2_f32_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r2, [cvt_rn_sf_e2m1x2_f32_param_1];
; CHECK-NEXT: {
; CHECK-NEXT: .reg .b8 %e2m1x2_out;
; CHECK-NEXT: cvt.rn.satfinite.e2m1x2.f32 %e2m1x2_out, %r1, %r2;
; CHECK-NEXT: cvt.u16.u8 %rs1, %e2m1x2_out;
; CHECK-NEXT: }
; CHECK-NEXT: cvt.u32.u16 %r3, %rs1;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r3;
; CHECK-NEXT: ret;
%val = call i16 @llvm.nvvm.ff.to.e2m1x2.rn.satfinite(float %f1, float %f2)
ret i16 %val
@@ -309,15 +309,15 @@ define i16 @cvt_rn_relu_sf_e2m1x2_f32(float %f1, float %f2) {
; CHECK-NEXT: .reg .b32 %r<4>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [cvt_rn_relu_sf_e2m1x2_f32_param_0];
-; CHECK-NEXT: ld.param.b32 %r2, [cvt_rn_relu_sf_e2m1x2_f32_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r1, [cvt_rn_relu_sf_e2m1x2_f32_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r2, [cvt_rn_relu_sf_e2m1x2_f32_param_1];
; CHECK-NEXT: {
; CHECK-NEXT: .reg .b8 %e2m1x2_out;
; CHECK-NEXT: cvt.rn.satfinite.relu.e2m1x2.f32 %e2m1x2_out, %r1, %r2;
; CHECK-NEXT: cvt.u16.u8 %rs1, %e2m1x2_out;
; CHECK-NEXT: }
; CHECK-NEXT: cvt.u32.u16 %r3, %rs1;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r3;
; CHECK-NEXT: ret;
%val = call i16 @llvm.nvvm.ff.to.e2m1x2.rn.relu.satfinite(float %f1, float %f2)
ret i16 %val
@@ -330,13 +330,13 @@ define <2 x half> @cvt_rn_f16x2_e2m1x2(i16 %in) {
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b16 %rs1, [cvt_rn_f16x2_e2m1x2_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [cvt_rn_f16x2_e2m1x2_param_0];
; CHECK-NEXT: {
; CHECK-NEXT: .reg .b8 %e2m1x2_in;
; CHECK-NEXT: cvt.u8.u16 %e2m1x2_in, %rs1;
; CHECK-NEXT: cvt.rn.f16x2.e2m1x2 %r1, %e2m1x2_in;
; CHECK-NEXT: }
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
%val = call <2 x half> @llvm.nvvm.e2m1x2.to.f16x2.rn(i16 %in)
ret <2 x half> %val
@@ -349,13 +349,13 @@ define <2 x half> @cvt_rn_relu_f16x2_e2m1x2(i16 %in) {
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b16 %rs1, [cvt_rn_relu_f16x2_e2m1x2_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [cvt_rn_relu_f16x2_e2m1x2_param_0];
; CHECK-NEXT: {
; CHECK-NEXT: .reg .b8 %e2m1x2_in;
; CHECK-NEXT: cvt.u8.u16 %e2m1x2_in, %rs1;
; CHECK-NEXT: cvt.rn.relu.f16x2.e2m1x2 %r1, %e2m1x2_in;
; CHECK-NEXT: }
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
%val = call <2 x half> @llvm.nvvm.e2m1x2.to.f16x2.rn.relu(i16 %in)
ret <2 x half> %val
diff --git a/llvm/test/CodeGen/NVPTX/convert-sm103a.ll b/llvm/test/CodeGen/NVPTX/convert-sm103a.ll
index b58c8b3e7abc5..75a394e4764ed 100644
--- a/llvm/test/CodeGen/NVPTX/convert-sm103a.ll
+++ b/llvm/test/CodeGen/NVPTX/convert-sm103a.ll
@@ -12,11 +12,11 @@ define <2 x half> @cvt_rs_f16x2_f32(float %f1, float %f2, i32 %rbits) {
; CHECK-NEXT: .reg .b32 %r<5>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [cvt_rs_f16x2_f32_param_0];
-; CHECK-NEXT: ld.param.b32 %r2, [cvt_rs_f16x2_f32_param_1];
-; CHECK-NEXT: ld.param.b32 %r3, [cvt_rs_f16x2_f32_param_2];
+; CHECK-NEXT: ld.param::func.b32 %r1, [cvt_rs_f16x2_f32_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r2, [cvt_rs_f16x2_f32_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r3, [cvt_rs_f16x2_f32_param_2];
; CHECK-NEXT: cvt.rs.f16x2.f32 %r4, %r1, %r2, %r3;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r4;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r4;
; CHECK-NEXT: ret;
%val = call <2 x half> @llvm.nvvm.ff2f16x2.rs(float %f1, float %f2, i32 %rbits)
ret <2 x half> %val
@@ -28,11 +28,11 @@ define <2 x half> @cvt_rs_relu_f16x2_f32(float %f1, float %f2, i32 %rbits) {
; CHECK-NEXT: .reg .b32 %r<5>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [cvt_rs_relu_f16x2_f32_param_0];
-; CHECK-NEXT: ld.param.b32 %r2, [cvt_rs_relu_f16x2_f32_param_1];
-; CHECK-NEXT: ld.param.b32 %r3, [cvt_rs_relu_f16x2_f32_param_2];
+; CHECK-NEXT: ld.param::func.b32 %r1, [cvt_rs_relu_f16x2_f32_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r2, [cvt_rs_relu_f16x2_f32_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r3, [cvt_rs_relu_f16x2_f32_param_2];
; CHECK-NEXT: cvt.rs.relu.f16x2.f32 %r4, %r1, %r2, %r3;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r4;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r4;
; CHECK-NEXT: ret;
%val = call <2 x half> @llvm.nvvm.ff2f16x2.rs.relu(float %f1, float %f2, i32 %rbits)
ret <2 x half> %val
@@ -44,11 +44,11 @@ define <2 x half> @cvt_rs_sf_f16x2_f32(float %f1, float %f2, i32 %rbits) {
; CHECK-NEXT: .reg .b32 %r<5>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [cvt_rs_sf_f16x2_f32_param_0];
-; CHECK-NEXT: ld.param.b32 %r2, [cvt_rs_sf_f16x2_f32_param_1];
-; CHECK-NEXT: ld.param.b32 %r3, [cvt_rs_sf_f16x2_f32_param_2];
+; CHECK-NEXT: ld.param::func.b32 %r1, [cvt_rs_sf_f16x2_f32_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r2, [cvt_rs_sf_f16x2_f32_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r3, [cvt_rs_sf_f16x2_f32_param_2];
; CHECK-NEXT: cvt.rs.satfinite.f16x2.f32 %r4, %r1, %r2, %r3;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r4;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r4;
; CHECK-NEXT: ret;
%val = call <2 x half> @llvm.nvvm.ff2f16x2.rs.satfinite(float %f1, float %f2, i32 %rbits)
ret <2 x half> %val
@@ -60,11 +60,11 @@ define <2 x half> @cvt_rs_relu_sf_f16x2_f32(float %f1, float %f2, i32 %rbits) {
; CHECK-NEXT: .reg .b32 %r<5>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [cvt_rs_relu_sf_f16x2_f32_param_0];
-; CHECK-NEXT: ld.param.b32 %r2, [cvt_rs_relu_sf_f16x2_f32_param_1];
-; CHECK-NEXT: ld.param.b32 %r3, [cvt_rs_relu_sf_f16x2_f32_param_2];
+; CHECK-NEXT: ld.param::func.b32 %r1, [cvt_rs_relu_sf_f16x2_f32_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r2, [cvt_rs_relu_sf_f16x2_f32_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r3, [cvt_rs_relu_sf_f16x2_f32_param_2];
; CHECK-NEXT: cvt.rs.relu.satfinite.f16x2.f32 %r4, %r1, %r2, %r3;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r4;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r4;
; CHECK-NEXT: ret;
%val = call <2 x half> @llvm.nvvm.ff2f16x2.rs.relu.satfinite(float %f1, float %f2, i32 %rbits)
ret <2 x half> %val
@@ -78,11 +78,11 @@ define <2 x bfloat> @cvt_rs_bf16x2_f32(float %f1, float %f2, i32 %rbits) {
; CHECK-NEXT: .reg .b32 %r<5>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [cvt_rs_bf16x2_f32_param_0];
-; CHECK-NEXT: ld.param.b32 %r2, [cvt_rs_bf16x2_f32_param_1];
-; CHECK-NEXT: ld.param.b32 %r3, [cvt_rs_bf16x2_f32_param_2];
+; CHECK-NEXT: ld.param::func.b32 %r1, [cvt_rs_bf16x2_f32_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r2, [cvt_rs_bf16x2_f32_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r3, [cvt_rs_bf16x2_f32_param_2];
; CHECK-NEXT: cvt.rs.bf16x2.f32 %r4, %r1, %r2, %r3;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r4;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r4;
; CHECK-NEXT: ret;
%val = call <2 x bfloat> @llvm.nvvm.ff2bf16x2.rs(float %f1, float %f2, i32 %rbits)
ret <2 x bfloat> %val
@@ -94,11 +94,11 @@ define <2 x bfloat> @cvt_rs_relu_bf16x2_f32(float %f1, float %f2, i32 %rbits) {
; CHECK-NEXT: .reg .b32 %r<5>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [cvt_rs_relu_bf16x2_f32_param_0];
-; CHECK-NEXT: ld.param.b32 %r2, [cvt_rs_relu_bf16x2_f32_param_1];
-; CHECK-NEXT: ld.param.b32 %r3, [cvt_rs_relu_bf16x2_f32_param_2];
+; CHECK-NEXT: ld.param::func.b32 %r1, [cvt_rs_relu_bf16x2_f32_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r2, [cvt_rs_relu_bf16x2_f32_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r3, [cvt_rs_relu_bf16x2_f32_param_2];
; CHECK-NEXT: cvt.rs.relu.bf16x2.f32 %r4, %r1, %r2, %r3;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r4;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r4;
; CHECK-NEXT: ret;
%val = call <2 x bfloat> @llvm.nvvm.ff2bf16x2.rs.relu(float %f1, float %f2, i32 %rbits)
ret <2 x bfloat> %val
@@ -110,11 +110,11 @@ define <2 x bfloat> @cvt_rs_sf_bf16x2_f32(float %f1, float %f2, i32 %rbits) {
; CHECK-NEXT: .reg .b32 %r<5>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [cvt_rs_sf_bf16x2_f32_param_0];
-; CHECK-NEXT: ld.param.b32 %r2, [cvt_rs_sf_bf16x2_f32_param_1];
-; CHECK-NEXT: ld.param.b32 %r3, [cvt_rs_sf_bf16x2_f32_param_2];
+; CHECK-NEXT: ld.param::func.b32 %r1, [cvt_rs_sf_bf16x2_f32_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r2, [cvt_rs_sf_bf16x2_f32_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r3, [cvt_rs_sf_bf16x2_f32_param_2];
; CHECK-NEXT: cvt.rs.satfinite.bf16x2.f32 %r4, %r1, %r2, %r3;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r4;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r4;
; CHECK-NEXT: ret;
%val = call <2 x bfloat> @llvm.nvvm.ff2bf16x2.rs.satfinite(float %f1, float %f2, i32 %rbits)
ret <2 x bfloat> %val
@@ -126,11 +126,11 @@ define <2 x bfloat> @cvt_rs_relu_sf_bf16x2_f32(float %f1, float %f2, i32 %rbits)
; CHECK-NEXT: .reg .b32 %r<5>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [cvt_rs_relu_sf_bf16x2_f32_param_0];
-; CHECK-NEXT: ld.param.b32 %r2, [cvt_rs_relu_sf_bf16x2_f32_param_1];
-; CHECK-NEXT: ld.param.b32 %r3, [cvt_rs_relu_sf_bf16x2_f32_param_2];
+; CHECK-NEXT: ld.param::func.b32 %r1, [cvt_rs_relu_sf_bf16x2_f32_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r2, [cvt_rs_relu_sf_bf16x2_f32_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r3, [cvt_rs_relu_sf_bf16x2_f32_param_2];
; CHECK-NEXT: cvt.rs.relu.satfinite.bf16x2.f32 %r4, %r1, %r2, %r3;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r4;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r4;
; CHECK-NEXT: ret;
%val = call <2 x bfloat> @llvm.nvvm.ff2bf16x2.rs.relu.satfinite(float %f1, float %f2, i32 %rbits)
ret <2 x bfloat> %val
@@ -144,10 +144,10 @@ define <4 x i8> @cvt_rs_sf_e4m3x4_f32(<4 x float> %fvec, i32 %rbits) {
; CHECK-NEXT: .reg .b32 %r<7>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [cvt_rs_sf_e4m3x4_f32_param_0];
-; CHECK-NEXT: ld.param.b32 %r5, [cvt_rs_sf_e4m3x4_f32_param_1];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r1, %r2, %r3, %r4}, [cvt_rs_sf_e4m3x4_f32_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r5, [cvt_rs_sf_e4m3x4_f32_param_1];
; CHECK-NEXT: cvt.rs.satfinite.e4m3x4.f32 %r6, {%r1, %r2, %r3, %r4}, %r5;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r6;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r6;
; CHECK-NEXT: ret;
%val = call <4 x i8> @llvm.nvvm.f32x4.to.e4m3x4.rs.satfinite(<4 x float> %fvec, i32 %rbits)
ret <4 x i8> %val
@@ -159,10 +159,10 @@ define <4 x i8> @cvt_rs_relu_sf_e4m3x4_f32(<4 x float> %fvec, i32 %rbits) {
; CHECK-NEXT: .reg .b32 %r<7>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [cvt_rs_relu_sf_e4m3x4_f32_param_0];
-; CHECK-NEXT: ld.param.b32 %r5, [cvt_rs_relu_sf_e4m3x4_f32_param_1];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r1, %r2, %r3, %r4}, [cvt_rs_relu_sf_e4m3x4_f32_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r5, [cvt_rs_relu_sf_e4m3x4_f32_param_1];
; CHECK-NEXT: cvt.rs.relu.satfinite.e4m3x4.f32 %r6, {%r1, %r2, %r3, %r4}, %r5;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r6;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r6;
; CHECK-NEXT: ret;
%val = call <4 x i8> @llvm.nvvm.f32x4.to.e4m3x4.rs.relu.satfinite(<4 x float> %fvec, i32 %rbits)
ret <4 x i8> %val
@@ -174,10 +174,10 @@ define <4 x i8> @cvt_rs_sf_e5m2x4_f32(<4 x float> %fvec, i32 %rbits) {
; CHECK-NEXT: .reg .b32 %r<7>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [cvt_rs_sf_e5m2x4_f32_param_0];
-; CHECK-NEXT: ld.param.b32 %r5, [cvt_rs_sf_e5m2x4_f32_param_1];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r1, %r2, %r3, %r4}, [cvt_rs_sf_e5m2x4_f32_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r5, [cvt_rs_sf_e5m2x4_f32_param_1];
; CHECK-NEXT: cvt.rs.satfinite.e5m2x4.f32 %r6, {%r1, %r2, %r3, %r4}, %r5;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r6;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r6;
; CHECK-NEXT: ret;
%val = call <4 x i8> @llvm.nvvm.f32x4.to.e5m2x4.rs.satfinite(<4 x float> %fvec, i32 %rbits)
ret <4 x i8> %val
@@ -189,10 +189,10 @@ define <4 x i8> @cvt_rs_relu_sf_e5m2x4_f32(<4 x float> %fvec, i32 %rbits) {
; CHECK-NEXT: .reg .b32 %r<7>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [cvt_rs_relu_sf_e5m2x4_f32_param_0];
-; CHECK-NEXT: ld.param.b32 %r5, [cvt_rs_relu_sf_e5m2x4_f32_param_1];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r1, %r2, %r3, %r4}, [cvt_rs_relu_sf_e5m2x4_f32_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r5, [cvt_rs_relu_sf_e5m2x4_f32_param_1];
; CHECK-NEXT: cvt.rs.relu.satfinite.e5m2x4.f32 %r6, {%r1, %r2, %r3, %r4}, %r5;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r6;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r6;
; CHECK-NEXT: ret;
%val = call <4 x i8> @llvm.nvvm.f32x4.to.e5m2x4.rs.relu.satfinite(<4 x float> %fvec, i32 %rbits)
ret <4 x i8> %val
@@ -206,10 +206,10 @@ define <4 x i8> @cvt_rs_sf_e2m3x4_f32(<4 x float> %fvec, i32 %rbits) {
; CHECK-NEXT: .reg .b32 %r<7>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [cvt_rs_sf_e2m3x4_f32_param_0];
-; CHECK-NEXT: ld.param.b32 %r5, [cvt_rs_sf_e2m3x4_f32_param_1];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r1, %r2, %r3, %r4}, [cvt_rs_sf_e2m3x4_f32_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r5, [cvt_rs_sf_e2m3x4_f32_param_1];
; CHECK-NEXT: cvt.rs.satfinite.e2m3x4.f32 %r6, {%r1, %r2, %r3, %r4}, %r5;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r6;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r6;
; CHECK-NEXT: ret;
%val = call <4 x i8> @llvm.nvvm.f32x4.to.e2m3x4.rs.satfinite(<4 x float> %fvec, i32 %rbits)
ret <4 x i8> %val
@@ -221,10 +221,10 @@ define <4 x i8> @cvt_rs_relu_sf_e2m3x4_f32(<4 x float> %fvec, i32 %rbits) {
; CHECK-NEXT: .reg .b32 %r<7>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [cvt_rs_relu_sf_e2m3x4_f32_param_0];
-; CHECK-NEXT: ld.param.b32 %r5, [cvt_rs_relu_sf_e2m3x4_f32_param_1];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r1, %r2, %r3, %r4}, [cvt_rs_relu_sf_e2m3x4_f32_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r5, [cvt_rs_relu_sf_e2m3x4_f32_param_1];
; CHECK-NEXT: cvt.rs.relu.satfinite.e2m3x4.f32 %r6, {%r1, %r2, %r3, %r4}, %r5;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r6;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r6;
; CHECK-NEXT: ret;
%val = call <4 x i8> @llvm.nvvm.f32x4.to.e2m3x4.rs.relu.satfinite(<4 x float> %fvec, i32 %rbits)
ret <4 x i8> %val
@@ -236,10 +236,10 @@ define <4 x i8> @cvt_rs_sf_e3m2x4_f32(<4 x float> %fvec, i32 %rbits) {
; CHECK-NEXT: .reg .b32 %r<7>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [cvt_rs_sf_e3m2x4_f32_param_0];
-; CHECK-NEXT: ld.param.b32 %r5, [cvt_rs_sf_e3m2x4_f32_param_1];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r1, %r2, %r3, %r4}, [cvt_rs_sf_e3m2x4_f32_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r5, [cvt_rs_sf_e3m2x4_f32_param_1];
; CHECK-NEXT: cvt.rs.satfinite.e3m2x4.f32 %r6, {%r1, %r2, %r3, %r4}, %r5;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r6;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r6;
; CHECK-NEXT: ret;
%val = call <4 x i8> @llvm.nvvm.f32x4.to.e3m2x4.rs.satfinite(<4 x float> %fvec, i32 %rbits)
ret <4 x i8> %val
@@ -251,10 +251,10 @@ define <4 x i8> @cvt_rs_relu_sf_e3m2x4_f32(<4 x float> %fvec, i32 %rbits) {
; CHECK-NEXT: .reg .b32 %r<7>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [cvt_rs_relu_sf_e3m2x4_f32_param_0];
-; CHECK-NEXT: ld.param.b32 %r5, [cvt_rs_relu_sf_e3m2x4_f32_param_1];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r1, %r2, %r3, %r4}, [cvt_rs_relu_sf_e3m2x4_f32_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r5, [cvt_rs_relu_sf_e3m2x4_f32_param_1];
; CHECK-NEXT: cvt.rs.relu.satfinite.e3m2x4.f32 %r6, {%r1, %r2, %r3, %r4}, %r5;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r6;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r6;
; CHECK-NEXT: ret;
%val = call <4 x i8> @llvm.nvvm.f32x4.to.e3m2x4.rs.relu.satfinite(<4 x float> %fvec, i32 %rbits)
ret <4 x i8> %val
@@ -269,11 +269,11 @@ define i16 @cvt_rs_sf_e2m1x4_f32(<4 x float> %fvec, i32 %rbits) {
; CHECK-NEXT: .reg .b32 %r<7>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [cvt_rs_sf_e2m1x4_f32_param_0];
-; CHECK-NEXT: ld.param.b32 %r5, [cvt_rs_sf_e2m1x4_f32_param_1];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r1, %r2, %r3, %r4}, [cvt_rs_sf_e2m1x4_f32_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r5, [cvt_rs_sf_e2m1x4_f32_param_1];
; CHECK-NEXT: cvt.rs.satfinite.e2m1x4.f32 %rs1, {%r1, %r2, %r3, %r4}, %r5;
; CHECK-NEXT: cvt.u32.u16 %r6, %rs1;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r6;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r6;
; CHECK-NEXT: ret;
%val = call i16 @llvm.nvvm.f32x4.to.e2m1x4.rs.satfinite(<4 x float> %fvec, i32 %rbits)
ret i16 %val
@@ -286,11 +286,11 @@ define i16 @cvt_rs_relu_sf_e2m1x4_f32(<4 x float> %fvec, i32 %rbits) {
; CHECK-NEXT: .reg .b32 %r<7>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [cvt_rs_relu_sf_e2m1x4_f32_param_0];
-; CHECK-NEXT: ld.param.b32 %r5, [cvt_rs_relu_sf_e2m1x4_f32_param_1];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r1, %r2, %r3, %r4}, [cvt_rs_relu_sf_e2m1x4_f32_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r5, [cvt_rs_relu_sf_e2m1x4_f32_param_1];
; CHECK-NEXT: cvt.rs.relu.satfinite.e2m1x4.f32 %rs1, {%r1, %r2, %r3, %r4}, %r5;
; CHECK-NEXT: cvt.u32.u16 %r6, %rs1;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r6;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r6;
; CHECK-NEXT: ret;
%val = call i16 @llvm.nvvm.f32x4.to.e2m1x4.rs.relu.satfinite(<4 x float> %fvec, i32 %rbits)
ret i16 %val
diff --git a/llvm/test/CodeGen/NVPTX/convert-ue5m3x2.ll b/llvm/test/CodeGen/NVPTX/convert-ue5m3x2.ll
index fe544aee19afc..f24b80e52f0bf 100644
--- a/llvm/test/CodeGen/NVPTX/convert-ue5m3x2.ll
+++ b/llvm/test/CodeGen/NVPTX/convert-ue5m3x2.ll
@@ -9,9 +9,9 @@ define <2 x half> @test_ue5m3x2_to_f16x2_rn(i16 %a) {
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b16 %rs1, [test_ue5m3x2_to_f16x2_rn_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_ue5m3x2_to_f16x2_rn_param_0];
; CHECK-NEXT: cvt.rn.f16x2.ue5m3x2 %r1, %rs1;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
%val = call <2 x half> @llvm.nvvm.ue5m3x2.to.f16x2.rn(i16 %a)
ret <2 x half> %val
@@ -24,9 +24,9 @@ define <2 x bfloat> @test_ue5m3x2_to_bf16x2_rn(i16 %a) {
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b16 %rs1, [test_ue5m3x2_to_bf16x2_rn_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_ue5m3x2_to_bf16x2_rn_param_0];
; CHECK-NEXT: cvt.rn.bf16x2.ue5m3x2 %r1, %rs1;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
%val = call <2 x bfloat> @llvm.nvvm.ue5m3x2.to.bf16x2.rn(i16 %a)
ret <2 x bfloat> %val
@@ -39,9 +39,9 @@ define <2 x bfloat> @test_ue5m3x2_to_bf16x2_rn_satfinite(i16 %a) {
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b16 %rs1, [test_ue5m3x2_to_bf16x2_rn_satfinite_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_ue5m3x2_to_bf16x2_rn_satfinite_param_0];
; CHECK-NEXT: cvt.rn.satfinite.bf16x2.ue5m3x2 %r1, %rs1;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
%val = call <2 x bfloat> @llvm.nvvm.ue5m3x2.to.bf16x2.rn.satfinite(i16 %a)
ret <2 x bfloat> %val
@@ -54,10 +54,10 @@ define <2 x bfloat> @test_ue5m3x2_to_bf16x2_rn_scale_ue8m0(i16 %a, i16 %b) {
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b16 %rs1, [test_ue5m3x2_to_bf16x2_rn_scale_ue8m0_param_0];
-; CHECK-NEXT: ld.param.b16 %rs2, [test_ue5m3x2_to_bf16x2_rn_scale_ue8m0_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_ue5m3x2_to_bf16x2_rn_scale_ue8m0_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs2, [test_ue5m3x2_to_bf16x2_rn_scale_ue8m0_param_1];
; CHECK-NEXT: cvt.rn.scaled::n2::ue8m0.bf16x2.ue5m3x2 %r1, %rs1, %rs2;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
%val = call <2 x bfloat> @llvm.nvvm.ue5m3x2.to.bf16x2.rn.scale.n2.ue8m0(i16 %a, i16 %b)
ret <2 x bfloat> %val
@@ -70,10 +70,10 @@ define <2 x bfloat> @test_ue5m3x2_to_bf16x2_rn_satfinite_scale_ue8m0(i16 %a, i16
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b16 %rs1, [test_ue5m3x2_to_bf16x2_rn_satfinite_scale_ue8m0_param_0];
-; CHECK-NEXT: ld.param.b16 %rs2, [test_ue5m3x2_to_bf16x2_rn_satfinite_scale_ue8m0_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_ue5m3x2_to_bf16x2_rn_satfinite_scale_ue8m0_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs2, [test_ue5m3x2_to_bf16x2_rn_satfinite_scale_ue8m0_param_1];
; CHECK-NEXT: cvt.rn.satfinite.scaled::n2::ue8m0.bf16x2.ue5m3x2 %r1, %rs1, %rs2;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
%val = call <2 x bfloat> @llvm.nvvm.ue5m3x2.to.bf16x2.rn.satfinite.scale.n2.ue8m0(i16 %a, i16 %b)
ret <2 x bfloat> %val
diff --git a/llvm/test/CodeGen/NVPTX/convert_fp4x2_sm_100f.ll b/llvm/test/CodeGen/NVPTX/convert_fp4x2_sm_100f.ll
index c35ccf5dc318b..bff97137be9ca 100644
--- a/llvm/test/CodeGen/NVPTX/convert_fp4x2_sm_100f.ll
+++ b/llvm/test/CodeGen/NVPTX/convert_fp4x2_sm_100f.ll
@@ -14,14 +14,14 @@ define i16 @cvt_rn_f16x2_e2m1x2(<2 x half> %in) {
; CHECK-NEXT: .reg .b32 %r<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [cvt_rn_f16x2_e2m1x2_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r1, [cvt_rn_f16x2_e2m1x2_param_0];
; CHECK-NEXT: {
; CHECK-NEXT: .reg .b8 %e2m1x2_out;
; CHECK-NEXT: cvt.rn.satfinite.e2m1x2.f16x2 %e2m1x2_out, %r1;
; CHECK-NEXT: cvt.u16.u8 %rs1, %e2m1x2_out;
; CHECK-NEXT: }
; CHECK-NEXT: cvt.u32.u16 %r2, %rs1;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r2;
; CHECK-NEXT: ret;
%val = call i16 @llvm.nvvm.f16x2.to.e2m1x2.rn.satfinite(<2 x half> %in)
ret i16 %val
@@ -34,14 +34,14 @@ define i16 @cvt_rn_relu_f16x2_e2m1x2(<2 x half> %in) {
; CHECK-NEXT: .reg .b32 %r<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [cvt_rn_relu_f16x2_e2m1x2_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r1, [cvt_rn_relu_f16x2_e2m1x2_param_0];
; CHECK-NEXT: {
; CHECK-NEXT: .reg .b8 %e2m1x2_out;
; CHECK-NEXT: cvt.rn.satfinite.relu.e2m1x2.f16x2 %e2m1x2_out, %r1;
; CHECK-NEXT: cvt.u16.u8 %rs1, %e2m1x2_out;
; CHECK-NEXT: }
; CHECK-NEXT: cvt.u32.u16 %r2, %rs1;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r2;
; CHECK-NEXT: ret;
%val = call i16 @llvm.nvvm.f16x2.to.e2m1x2.rn.relu.satfinite(<2 x half> %in)
ret i16 %val
@@ -55,14 +55,14 @@ define i16 @cvt_rn_sf_e2m1x2_bf16x2(<2 x bfloat> %in) {
; CHECK-NEXT: .reg .b32 %r<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [cvt_rn_sf_e2m1x2_bf16x2_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r1, [cvt_rn_sf_e2m1x2_bf16x2_param_0];
; CHECK-NEXT: {
; CHECK-NEXT: .reg .b8 %e2m1x2_out;
; CHECK-NEXT: cvt.rn.satfinite.e2m1x2.bf16x2 %e2m1x2_out, %r1;
; CHECK-NEXT: cvt.u16.u8 %rs1, %e2m1x2_out;
; CHECK-NEXT: }
; CHECK-NEXT: cvt.u32.u16 %r2, %rs1;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r2;
; CHECK-NEXT: ret;
%val = call i16 @llvm.nvvm.bf16x2.to.e2m1x2.rn.satfinite(<2 x bfloat> %in)
ret i16 %val
@@ -75,14 +75,14 @@ define i16 @cvt_rn_relu_sf_e2m1x2_bf16x2(<2 x bfloat> %in) {
; CHECK-NEXT: .reg .b32 %r<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [cvt_rn_relu_sf_e2m1x2_bf16x2_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r1, [cvt_rn_relu_sf_e2m1x2_bf16x2_param_0];
; CHECK-NEXT: {
; CHECK-NEXT: .reg .b8 %e2m1x2_out;
; CHECK-NEXT: cvt.rn.satfinite.relu.e2m1x2.bf16x2 %e2m1x2_out, %r1;
; CHECK-NEXT: cvt.u16.u8 %rs1, %e2m1x2_out;
; CHECK-NEXT: }
; CHECK-NEXT: cvt.u32.u16 %r2, %rs1;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r2;
; CHECK-NEXT: ret;
%val = call i16 @llvm.nvvm.bf16x2.to.e2m1x2.rn.relu.satfinite(<2 x bfloat> %in)
ret i16 %val
diff --git a/llvm/test/CodeGen/NVPTX/convert_fp4x2_to_bf16x2.ll b/llvm/test/CodeGen/NVPTX/convert_fp4x2_to_bf16x2.ll
index 3560ef5b57936..a6a24d7c036f7 100644
--- a/llvm/test/CodeGen/NVPTX/convert_fp4x2_to_bf16x2.ll
+++ b/llvm/test/CodeGen/NVPTX/convert_fp4x2_to_bf16x2.ll
@@ -13,14 +13,14 @@ define <2 x bfloat> @test_e2m1x2_to_bf16x2_rn_scale_ue8m0(i16 %a, i16 %b) {
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b16 %rs1, [test_e2m1x2_to_bf16x2_rn_scale_ue8m0_param_0];
-; CHECK-NEXT: ld.param.b16 %rs2, [test_e2m1x2_to_bf16x2_rn_scale_ue8m0_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_e2m1x2_to_bf16x2_rn_scale_ue8m0_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs2, [test_e2m1x2_to_bf16x2_rn_scale_ue8m0_param_1];
; CHECK-NEXT: {
; CHECK-NEXT: .reg .b8 %e2m1x2_in;
; CHECK-NEXT: cvt.u8.u16 %e2m1x2_in, %rs1;
; CHECK-NEXT: cvt.rn.scaled::n2::ue8m0.bf16x2.e2m1x2 %r1, %e2m1x2_in, %rs2;
; CHECK-NEXT: }
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
%val = call <2 x bfloat> @llvm.nvvm.e2m1x2.to.bf16x2.rn.scale.n2.ue8m0(i16 %a, i16 %b)
ret <2 x bfloat> %val
@@ -33,14 +33,14 @@ define <2 x bfloat> @test_e2m1x2_to_bf16x2_rn_relu_scale_ue8m0(i16 %a, i16 %b) {
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b16 %rs1, [test_e2m1x2_to_bf16x2_rn_relu_scale_ue8m0_param_0];
-; CHECK-NEXT: ld.param.b16 %rs2, [test_e2m1x2_to_bf16x2_rn_relu_scale_ue8m0_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_e2m1x2_to_bf16x2_rn_relu_scale_ue8m0_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs2, [test_e2m1x2_to_bf16x2_rn_relu_scale_ue8m0_param_1];
; CHECK-NEXT: {
; CHECK-NEXT: .reg .b8 %e2m1x2_in;
; CHECK-NEXT: cvt.u8.u16 %e2m1x2_in, %rs1;
; CHECK-NEXT: cvt.rn.relu.scaled::n2::ue8m0.bf16x2.e2m1x2 %r1, %e2m1x2_in, %rs2;
; CHECK-NEXT: }
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
%val = call <2 x bfloat> @llvm.nvvm.e2m1x2.to.bf16x2.rn.relu.scale.n2.ue8m0(i16 %a, i16 %b)
ret <2 x bfloat> %val
@@ -53,14 +53,14 @@ define <2 x bfloat> @test_e2m1x2_to_bf16x2_rn_satfinite_scale_ue8m0(i16 %a, i16
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b16 %rs1, [test_e2m1x2_to_bf16x2_rn_satfinite_scale_ue8m0_param_0];
-; CHECK-NEXT: ld.param.b16 %rs2, [test_e2m1x2_to_bf16x2_rn_satfinite_scale_ue8m0_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_e2m1x2_to_bf16x2_rn_satfinite_scale_ue8m0_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs2, [test_e2m1x2_to_bf16x2_rn_satfinite_scale_ue8m0_param_1];
; CHECK-NEXT: {
; CHECK-NEXT: .reg .b8 %e2m1x2_in;
; CHECK-NEXT: cvt.u8.u16 %e2m1x2_in, %rs1;
; CHECK-NEXT: cvt.rn.satfinite.scaled::n2::ue8m0.bf16x2.e2m1x2 %r1, %e2m1x2_in, %rs2;
; CHECK-NEXT: }
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
%val = call <2 x bfloat> @llvm.nvvm.e2m1x2.to.bf16x2.rn.satfinite.scale.n2.ue8m0(i16 %a, i16 %b)
ret <2 x bfloat> %val
@@ -73,14 +73,14 @@ define <2 x bfloat> @test_e2m1x2_to_bf16x2_rn_relu_satfinite_scale_ue8m0(i16 %a,
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b16 %rs1, [test_e2m1x2_to_bf16x2_rn_relu_satfinite_scale_ue8m0_param_0];
-; CHECK-NEXT: ld.param.b16 %rs2, [test_e2m1x2_to_bf16x2_rn_relu_satfinite_scale_ue8m0_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_e2m1x2_to_bf16x2_rn_relu_satfinite_scale_ue8m0_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs2, [test_e2m1x2_to_bf16x2_rn_relu_satfinite_scale_ue8m0_param_1];
; CHECK-NEXT: {
; CHECK-NEXT: .reg .b8 %e2m1x2_in;
; CHECK-NEXT: cvt.u8.u16 %e2m1x2_in, %rs1;
; CHECK-NEXT: cvt.rn.relu.satfinite.scaled::n2::ue8m0.bf16x2.e2m1x2 %r1, %e2m1x2_in, %rs2;
; CHECK-NEXT: }
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
%val = call <2 x bfloat> @llvm.nvvm.e2m1x2.to.bf16x2.rn.relu.satfinite.scale.n2.ue8m0(i16 %a, i16 %b)
ret <2 x bfloat> %val
diff --git a/llvm/test/CodeGen/NVPTX/convert_fp6x2_sm_100f.ll b/llvm/test/CodeGen/NVPTX/convert_fp6x2_sm_100f.ll
index 624e0ff14a13b..5b55fc3a9c1d4 100644
--- a/llvm/test/CodeGen/NVPTX/convert_fp6x2_sm_100f.ll
+++ b/llvm/test/CodeGen/NVPTX/convert_fp6x2_sm_100f.ll
@@ -14,10 +14,10 @@ define i16 @cvt_rn_f16x2_e2m3x2(<2 x half> %in) {
; CHECK-NEXT: .reg .b32 %r<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [cvt_rn_f16x2_e2m3x2_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r1, [cvt_rn_f16x2_e2m3x2_param_0];
; CHECK-NEXT: cvt.rn.satfinite.e2m3x2.f16x2 %rs1, %r1;
; CHECK-NEXT: cvt.u32.u16 %r2, %rs1;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r2;
; CHECK-NEXT: ret;
%val = call i16 @llvm.nvvm.f16x2.to.e2m3x2.rn.satfinite(<2 x half> %in)
ret i16 %val
@@ -30,10 +30,10 @@ define i16 @cvt_rn_relu_f16x2_e2m3x2(<2 x half> %in) {
; CHECK-NEXT: .reg .b32 %r<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [cvt_rn_relu_f16x2_e2m3x2_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r1, [cvt_rn_relu_f16x2_e2m3x2_param_0];
; CHECK-NEXT: cvt.rn.satfinite.relu.e2m3x2.f16x2 %rs1, %r1;
; CHECK-NEXT: cvt.u32.u16 %r2, %rs1;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r2;
; CHECK-NEXT: ret;
%val = call i16 @llvm.nvvm.f16x2.to.e2m3x2.rn.relu.satfinite(<2 x half> %in)
ret i16 %val
@@ -46,10 +46,10 @@ define i16 @cvt_rn_f16x2_e3m2x2(<2 x half> %in) {
; CHECK-NEXT: .reg .b32 %r<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [cvt_rn_f16x2_e3m2x2_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r1, [cvt_rn_f16x2_e3m2x2_param_0];
; CHECK-NEXT: cvt.rn.satfinite.e3m2x2.f16x2 %rs1, %r1;
; CHECK-NEXT: cvt.u32.u16 %r2, %rs1;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r2;
; CHECK-NEXT: ret;
%val = call i16 @llvm.nvvm.f16x2.to.e3m2x2.rn.satfinite(<2 x half> %in)
ret i16 %val
@@ -62,10 +62,10 @@ define i16 @cvt_rn_relu_f16x2_e3m2x2(<2 x half> %in) {
; CHECK-NEXT: .reg .b32 %r<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [cvt_rn_relu_f16x2_e3m2x2_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r1, [cvt_rn_relu_f16x2_e3m2x2_param_0];
; CHECK-NEXT: cvt.rn.satfinite.relu.e3m2x2.f16x2 %rs1, %r1;
; CHECK-NEXT: cvt.u32.u16 %r2, %rs1;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r2;
; CHECK-NEXT: ret;
%val = call i16 @llvm.nvvm.f16x2.to.e3m2x2.rn.relu.satfinite(<2 x half> %in)
ret i16 %val
@@ -79,10 +79,10 @@ define i16 @cvt_rn_sf_e2m3x2_bf16x2(<2 x bfloat> %in) {
; CHECK-NEXT: .reg .b32 %r<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [cvt_rn_sf_e2m3x2_bf16x2_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r1, [cvt_rn_sf_e2m3x2_bf16x2_param_0];
; CHECK-NEXT: cvt.rn.satfinite.e2m3x2.bf16x2 %rs1, %r1;
; CHECK-NEXT: cvt.u32.u16 %r2, %rs1;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r2;
; CHECK-NEXT: ret;
%val = call i16 @llvm.nvvm.bf16x2.to.e2m3x2.rn.satfinite(<2 x bfloat> %in)
ret i16 %val
@@ -95,10 +95,10 @@ define i16 @cvt_rn_relu_sf_e2m3x2_bf16x2(<2 x bfloat> %in) {
; CHECK-NEXT: .reg .b32 %r<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [cvt_rn_relu_sf_e2m3x2_bf16x2_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r1, [cvt_rn_relu_sf_e2m3x2_bf16x2_param_0];
; CHECK-NEXT: cvt.rn.satfinite.relu.e2m3x2.bf16x2 %rs1, %r1;
; CHECK-NEXT: cvt.u32.u16 %r2, %rs1;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r2;
; CHECK-NEXT: ret;
%val = call i16 @llvm.nvvm.bf16x2.to.e2m3x2.rn.relu.satfinite(<2 x bfloat> %in)
ret i16 %val
@@ -111,10 +111,10 @@ define i16 @cvt_rn_sf_e3m2x2_bf16x2(<2 x bfloat> %in) {
; CHECK-NEXT: .reg .b32 %r<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [cvt_rn_sf_e3m2x2_bf16x2_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r1, [cvt_rn_sf_e3m2x2_bf16x2_param_0];
; CHECK-NEXT: cvt.rn.satfinite.e3m2x2.bf16x2 %rs1, %r1;
; CHECK-NEXT: cvt.u32.u16 %r2, %rs1;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r2;
; CHECK-NEXT: ret;
%val = call i16 @llvm.nvvm.bf16x2.to.e3m2x2.rn.satfinite(<2 x bfloat> %in)
ret i16 %val
@@ -127,10 +127,10 @@ define i16 @cvt_rn_relu_sf_e3m2x2_bf16x2(<2 x bfloat> %in) {
; CHECK-NEXT: .reg .b32 %r<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [cvt_rn_relu_sf_e3m2x2_bf16x2_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r1, [cvt_rn_relu_sf_e3m2x2_bf16x2_param_0];
; CHECK-NEXT: cvt.rn.satfinite.relu.e3m2x2.bf16x2 %rs1, %r1;
; CHECK-NEXT: cvt.u32.u16 %r2, %rs1;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r2;
; CHECK-NEXT: ret;
%val = call i16 @llvm.nvvm.bf16x2.to.e3m2x2.rn.relu.satfinite(<2 x bfloat> %in)
ret i16 %val
diff --git a/llvm/test/CodeGen/NVPTX/convert_fp6x2_to_bf16x2.ll b/llvm/test/CodeGen/NVPTX/convert_fp6x2_to_bf16x2.ll
index 56476252641df..da874190f8ead 100644
--- a/llvm/test/CodeGen/NVPTX/convert_fp6x2_to_bf16x2.ll
+++ b/llvm/test/CodeGen/NVPTX/convert_fp6x2_to_bf16x2.ll
@@ -13,10 +13,10 @@ define <2 x bfloat> @test_e2m3x2_to_bf16x2_rn_scale_ue8m0(i16 %a, i16 %b) {
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b16 %rs1, [test_e2m3x2_to_bf16x2_rn_scale_ue8m0_param_0];
-; CHECK-NEXT: ld.param.b16 %rs2, [test_e2m3x2_to_bf16x2_rn_scale_ue8m0_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_e2m3x2_to_bf16x2_rn_scale_ue8m0_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs2, [test_e2m3x2_to_bf16x2_rn_scale_ue8m0_param_1];
; CHECK-NEXT: cvt.rn.scaled::n2::ue8m0.bf16x2.e2m3x2 %r1, %rs1, %rs2;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
%val = call <2 x bfloat> @llvm.nvvm.e2m3x2.to.bf16x2.rn.scale.n2.ue8m0(i16 %a, i16 %b)
ret <2 x bfloat> %val
@@ -29,10 +29,10 @@ define <2 x bfloat> @test_e2m3x2_to_bf16x2_rn_relu_scale_ue8m0(i16 %a, i16 %b) {
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b16 %rs1, [test_e2m3x2_to_bf16x2_rn_relu_scale_ue8m0_param_0];
-; CHECK-NEXT: ld.param.b16 %rs2, [test_e2m3x2_to_bf16x2_rn_relu_scale_ue8m0_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_e2m3x2_to_bf16x2_rn_relu_scale_ue8m0_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs2, [test_e2m3x2_to_bf16x2_rn_relu_scale_ue8m0_param_1];
; CHECK-NEXT: cvt.rn.relu.scaled::n2::ue8m0.bf16x2.e2m3x2 %r1, %rs1, %rs2;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
%val = call <2 x bfloat> @llvm.nvvm.e2m3x2.to.bf16x2.rn.relu.scale.n2.ue8m0(i16 %a, i16 %b)
ret <2 x bfloat> %val
@@ -45,10 +45,10 @@ define <2 x bfloat> @test_e2m3x2_to_bf16x2_rn_satfinite_scale_ue8m0(i16 %a, i16
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b16 %rs1, [test_e2m3x2_to_bf16x2_rn_satfinite_scale_ue8m0_param_0];
-; CHECK-NEXT: ld.param.b16 %rs2, [test_e2m3x2_to_bf16x2_rn_satfinite_scale_ue8m0_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_e2m3x2_to_bf16x2_rn_satfinite_scale_ue8m0_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs2, [test_e2m3x2_to_bf16x2_rn_satfinite_scale_ue8m0_param_1];
; CHECK-NEXT: cvt.rn.satfinite.scaled::n2::ue8m0.bf16x2.e2m3x2 %r1, %rs1, %rs2;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
%val = call <2 x bfloat> @llvm.nvvm.e2m3x2.to.bf16x2.rn.satfinite.scale.n2.ue8m0(i16 %a, i16 %b)
ret <2 x bfloat> %val
@@ -61,10 +61,10 @@ define <2 x bfloat> @test_e2m3x2_to_bf16x2_rn_relu_satfinite_scale_ue8m0(i16 %a,
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b16 %rs1, [test_e2m3x2_to_bf16x2_rn_relu_satfinite_scale_ue8m0_param_0];
-; CHECK-NEXT: ld.param.b16 %rs2, [test_e2m3x2_to_bf16x2_rn_relu_satfinite_scale_ue8m0_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_e2m3x2_to_bf16x2_rn_relu_satfinite_scale_ue8m0_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs2, [test_e2m3x2_to_bf16x2_rn_relu_satfinite_scale_ue8m0_param_1];
; CHECK-NEXT: cvt.rn.relu.satfinite.scaled::n2::ue8m0.bf16x2.e2m3x2 %r1, %rs1, %rs2;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
%val = call <2 x bfloat> @llvm.nvvm.e2m3x2.to.bf16x2.rn.relu.satfinite.scale.n2.ue8m0(i16 %a, i16 %b)
ret <2 x bfloat> %val
@@ -77,10 +77,10 @@ define <2 x bfloat> @test_e3m2x2_to_bf16x2_rn_scale_ue8m0(i16 %a, i16 %b) {
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b16 %rs1, [test_e3m2x2_to_bf16x2_rn_scale_ue8m0_param_0];
-; CHECK-NEXT: ld.param.b16 %rs2, [test_e3m2x2_to_bf16x2_rn_scale_ue8m0_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_e3m2x2_to_bf16x2_rn_scale_ue8m0_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs2, [test_e3m2x2_to_bf16x2_rn_scale_ue8m0_param_1];
; CHECK-NEXT: cvt.rn.scaled::n2::ue8m0.bf16x2.e3m2x2 %r1, %rs1, %rs2;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
%val = call <2 x bfloat> @llvm.nvvm.e3m2x2.to.bf16x2.rn.scale.n2.ue8m0(i16 %a, i16 %b)
ret <2 x bfloat> %val
@@ -93,10 +93,10 @@ define <2 x bfloat> @test_e3m2x2_to_bf16x2_rn_relu_scale_ue8m0(i16 %a, i16 %b) {
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b16 %rs1, [test_e3m2x2_to_bf16x2_rn_relu_scale_ue8m0_param_0];
-; CHECK-NEXT: ld.param.b16 %rs2, [test_e3m2x2_to_bf16x2_rn_relu_scale_ue8m0_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_e3m2x2_to_bf16x2_rn_relu_scale_ue8m0_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs2, [test_e3m2x2_to_bf16x2_rn_relu_scale_ue8m0_param_1];
; CHECK-NEXT: cvt.rn.relu.scaled::n2::ue8m0.bf16x2.e3m2x2 %r1, %rs1, %rs2;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
%val = call <2 x bfloat> @llvm.nvvm.e3m2x2.to.bf16x2.rn.relu.scale.n2.ue8m0(i16 %a, i16 %b)
ret <2 x bfloat> %val
@@ -109,10 +109,10 @@ define <2 x bfloat> @test_e3m2x2_to_bf16x2_rn_satfinite_scale_ue8m0(i16 %a, i16
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b16 %rs1, [test_e3m2x2_to_bf16x2_rn_satfinite_scale_ue8m0_param_0];
-; CHECK-NEXT: ld.param.b16 %rs2, [test_e3m2x2_to_bf16x2_rn_satfinite_scale_ue8m0_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_e3m2x2_to_bf16x2_rn_satfinite_scale_ue8m0_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs2, [test_e3m2x2_to_bf16x2_rn_satfinite_scale_ue8m0_param_1];
; CHECK-NEXT: cvt.rn.satfinite.scaled::n2::ue8m0.bf16x2.e3m2x2 %r1, %rs1, %rs2;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
%val = call <2 x bfloat> @llvm.nvvm.e3m2x2.to.bf16x2.rn.satfinite.scale.n2.ue8m0(i16 %a, i16 %b)
ret <2 x bfloat> %val
@@ -125,10 +125,10 @@ define <2 x bfloat> @test_e3m2x2_to_bf16x2_rn_relu_satfinite_scale_ue8m0(i16 %a,
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b16 %rs1, [test_e3m2x2_to_bf16x2_rn_relu_satfinite_scale_ue8m0_param_0];
-; CHECK-NEXT: ld.param.b16 %rs2, [test_e3m2x2_to_bf16x2_rn_relu_satfinite_scale_ue8m0_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_e3m2x2_to_bf16x2_rn_relu_satfinite_scale_ue8m0_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs2, [test_e3m2x2_to_bf16x2_rn_relu_satfinite_scale_ue8m0_param_1];
; CHECK-NEXT: cvt.rn.relu.satfinite.scaled::n2::ue8m0.bf16x2.e3m2x2 %r1, %rs1, %rs2;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
%val = call <2 x bfloat> @llvm.nvvm.e3m2x2.to.bf16x2.rn.relu.satfinite.scale.n2.ue8m0(i16 %a, i16 %b)
ret <2 x bfloat> %val
diff --git a/llvm/test/CodeGen/NVPTX/convert_fp8x2_sm_100f.ll b/llvm/test/CodeGen/NVPTX/convert_fp8x2_sm_100f.ll
index d889517e6f25d..2b60e910a777a 100644
--- a/llvm/test/CodeGen/NVPTX/convert_fp8x2_sm_100f.ll
+++ b/llvm/test/CodeGen/NVPTX/convert_fp8x2_sm_100f.ll
@@ -14,10 +14,10 @@ define i16 @cvt_rn_e4m3x2_bf16x2(<2 x bfloat> %in) {
; CHECK-NEXT: .reg .b32 %r<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [cvt_rn_e4m3x2_bf16x2_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r1, [cvt_rn_e4m3x2_bf16x2_param_0];
; CHECK-NEXT: cvt.rn.satfinite.e4m3x2.bf16x2 %rs1, %r1;
; CHECK-NEXT: cvt.u32.u16 %r2, %rs1;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r2;
; CHECK-NEXT: ret;
%val = call i16 @llvm.nvvm.bf16x2.to.e4m3x2.rn.satfinite(<2 x bfloat> %in)
ret i16 %val
@@ -30,10 +30,10 @@ define i16 @cvt_rn_relu_e4m3x2_bf16x2(<2 x bfloat> %in) {
; CHECK-NEXT: .reg .b32 %r<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [cvt_rn_relu_e4m3x2_bf16x2_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r1, [cvt_rn_relu_e4m3x2_bf16x2_param_0];
; CHECK-NEXT: cvt.rn.satfinite.relu.e4m3x2.bf16x2 %rs1, %r1;
; CHECK-NEXT: cvt.u32.u16 %r2, %rs1;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r2;
; CHECK-NEXT: ret;
%val = call i16 @llvm.nvvm.bf16x2.to.e4m3x2.rn.relu.satfinite(<2 x bfloat> %in)
ret i16 %val
@@ -46,10 +46,10 @@ define i16 @cvt_rn_e5m2x2_bf16x2(<2 x bfloat> %in) {
; CHECK-NEXT: .reg .b32 %r<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [cvt_rn_e5m2x2_bf16x2_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r1, [cvt_rn_e5m2x2_bf16x2_param_0];
; CHECK-NEXT: cvt.rn.satfinite.e5m2x2.bf16x2 %rs1, %r1;
; CHECK-NEXT: cvt.u32.u16 %r2, %rs1;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r2;
; CHECK-NEXT: ret;
%val = call i16 @llvm.nvvm.bf16x2.to.e5m2x2.rn.satfinite(<2 x bfloat> %in)
ret i16 %val
@@ -62,10 +62,10 @@ define i16 @cvt_rn_relu_e5m2x2_bf16x2(<2 x bfloat> %in) {
; CHECK-NEXT: .reg .b32 %r<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [cvt_rn_relu_e5m2x2_bf16x2_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r1, [cvt_rn_relu_e5m2x2_bf16x2_param_0];
; CHECK-NEXT: cvt.rn.satfinite.relu.e5m2x2.bf16x2 %rs1, %r1;
; CHECK-NEXT: cvt.u32.u16 %r2, %rs1;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r2;
; CHECK-NEXT: ret;
%val = call i16 @llvm.nvvm.bf16x2.to.e5m2x2.rn.relu.satfinite(<2 x bfloat> %in)
ret i16 %val
diff --git a/llvm/test/CodeGen/NVPTX/convert_fp8x2_to_bf16x2.ll b/llvm/test/CodeGen/NVPTX/convert_fp8x2_to_bf16x2.ll
index 1199df2fb5697..8d1685e7d7782 100644
--- a/llvm/test/CodeGen/NVPTX/convert_fp8x2_to_bf16x2.ll
+++ b/llvm/test/CodeGen/NVPTX/convert_fp8x2_to_bf16x2.ll
@@ -13,10 +13,10 @@ define <2 x bfloat> @test_e4m3x2_to_bf16x2_rn_scale_ue8m0(i16 %a, i16 %b) {
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b16 %rs1, [test_e4m3x2_to_bf16x2_rn_scale_ue8m0_param_0];
-; CHECK-NEXT: ld.param.b16 %rs2, [test_e4m3x2_to_bf16x2_rn_scale_ue8m0_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_e4m3x2_to_bf16x2_rn_scale_ue8m0_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs2, [test_e4m3x2_to_bf16x2_rn_scale_ue8m0_param_1];
; CHECK-NEXT: cvt.rn.scaled::n2::ue8m0.bf16x2.e4m3x2 %r1, %rs1, %rs2;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
%val = call <2 x bfloat> @llvm.nvvm.e4m3x2.to.bf16x2.rn.scale.n2.ue8m0(i16 %a, i16 %b)
ret <2 x bfloat> %val
@@ -29,10 +29,10 @@ define <2 x bfloat> @test_e4m3x2_to_bf16x2_rn_relu_scale_ue8m0(i16 %a, i16 %b) {
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b16 %rs1, [test_e4m3x2_to_bf16x2_rn_relu_scale_ue8m0_param_0];
-; CHECK-NEXT: ld.param.b16 %rs2, [test_e4m3x2_to_bf16x2_rn_relu_scale_ue8m0_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_e4m3x2_to_bf16x2_rn_relu_scale_ue8m0_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs2, [test_e4m3x2_to_bf16x2_rn_relu_scale_ue8m0_param_1];
; CHECK-NEXT: cvt.rn.relu.scaled::n2::ue8m0.bf16x2.e4m3x2 %r1, %rs1, %rs2;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
%val = call <2 x bfloat> @llvm.nvvm.e4m3x2.to.bf16x2.rn.relu.scale.n2.ue8m0(i16 %a, i16 %b)
ret <2 x bfloat> %val
@@ -45,10 +45,10 @@ define <2 x bfloat> @test_e4m3x2_to_bf16x2_rn_satfinite_scale_ue8m0(i16 %a, i16
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b16 %rs1, [test_e4m3x2_to_bf16x2_rn_satfinite_scale_ue8m0_param_0];
-; CHECK-NEXT: ld.param.b16 %rs2, [test_e4m3x2_to_bf16x2_rn_satfinite_scale_ue8m0_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_e4m3x2_to_bf16x2_rn_satfinite_scale_ue8m0_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs2, [test_e4m3x2_to_bf16x2_rn_satfinite_scale_ue8m0_param_1];
; CHECK-NEXT: cvt.rn.satfinite.scaled::n2::ue8m0.bf16x2.e4m3x2 %r1, %rs1, %rs2;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
%val = call <2 x bfloat> @llvm.nvvm.e4m3x2.to.bf16x2.rn.satfinite.scale.n2.ue8m0(i16 %a, i16 %b)
ret <2 x bfloat> %val
@@ -61,10 +61,10 @@ define <2 x bfloat> @test_e4m3x2_to_bf16x2_rn_relu_satfinite_scale_ue8m0(i16 %a,
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b16 %rs1, [test_e4m3x2_to_bf16x2_rn_relu_satfinite_scale_ue8m0_param_0];
-; CHECK-NEXT: ld.param.b16 %rs2, [test_e4m3x2_to_bf16x2_rn_relu_satfinite_scale_ue8m0_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_e4m3x2_to_bf16x2_rn_relu_satfinite_scale_ue8m0_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs2, [test_e4m3x2_to_bf16x2_rn_relu_satfinite_scale_ue8m0_param_1];
; CHECK-NEXT: cvt.rn.relu.satfinite.scaled::n2::ue8m0.bf16x2.e4m3x2 %r1, %rs1, %rs2;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
%val = call <2 x bfloat> @llvm.nvvm.e4m3x2.to.bf16x2.rn.relu.satfinite.scale.n2.ue8m0(i16 %a, i16 %b)
ret <2 x bfloat> %val
@@ -77,10 +77,10 @@ define <2 x bfloat> @test_e5m2x2_to_bf16x2_rn_scale_ue8m0(i16 %a, i16 %b) {
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b16 %rs1, [test_e5m2x2_to_bf16x2_rn_scale_ue8m0_param_0];
-; CHECK-NEXT: ld.param.b16 %rs2, [test_e5m2x2_to_bf16x2_rn_scale_ue8m0_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_e5m2x2_to_bf16x2_rn_scale_ue8m0_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs2, [test_e5m2x2_to_bf16x2_rn_scale_ue8m0_param_1];
; CHECK-NEXT: cvt.rn.scaled::n2::ue8m0.bf16x2.e5m2x2 %r1, %rs1, %rs2;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
%val = call <2 x bfloat> @llvm.nvvm.e5m2x2.to.bf16x2.rn.scale.n2.ue8m0(i16 %a, i16 %b)
ret <2 x bfloat> %val
@@ -93,10 +93,10 @@ define <2 x bfloat> @test_e5m2x2_to_bf16x2_rn_relu_scale_ue8m0(i16 %a, i16 %b) {
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b16 %rs1, [test_e5m2x2_to_bf16x2_rn_relu_scale_ue8m0_param_0];
-; CHECK-NEXT: ld.param.b16 %rs2, [test_e5m2x2_to_bf16x2_rn_relu_scale_ue8m0_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_e5m2x2_to_bf16x2_rn_relu_scale_ue8m0_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs2, [test_e5m2x2_to_bf16x2_rn_relu_scale_ue8m0_param_1];
; CHECK-NEXT: cvt.rn.relu.scaled::n2::ue8m0.bf16x2.e5m2x2 %r1, %rs1, %rs2;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
%val = call <2 x bfloat> @llvm.nvvm.e5m2x2.to.bf16x2.rn.relu.scale.n2.ue8m0(i16 %a, i16 %b)
ret <2 x bfloat> %val
@@ -109,10 +109,10 @@ define <2 x bfloat> @test_e5m2x2_to_bf16x2_rn_satfinite_scale_ue8m0(i16 %a, i16
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b16 %rs1, [test_e5m2x2_to_bf16x2_rn_satfinite_scale_ue8m0_param_0];
-; CHECK-NEXT: ld.param.b16 %rs2, [test_e5m2x2_to_bf16x2_rn_satfinite_scale_ue8m0_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_e5m2x2_to_bf16x2_rn_satfinite_scale_ue8m0_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs2, [test_e5m2x2_to_bf16x2_rn_satfinite_scale_ue8m0_param_1];
; CHECK-NEXT: cvt.rn.satfinite.scaled::n2::ue8m0.bf16x2.e5m2x2 %r1, %rs1, %rs2;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
%val = call <2 x bfloat> @llvm.nvvm.e5m2x2.to.bf16x2.rn.satfinite.scale.n2.ue8m0(i16 %a, i16 %b)
ret <2 x bfloat> %val
@@ -125,10 +125,10 @@ define <2 x bfloat> @test_e5m2x2_to_bf16x2_rn_relu_satfinite_scale_ue8m0(i16 %a,
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b16 %rs1, [test_e5m2x2_to_bf16x2_rn_relu_satfinite_scale_ue8m0_param_0];
-; CHECK-NEXT: ld.param.b16 %rs2, [test_e5m2x2_to_bf16x2_rn_relu_satfinite_scale_ue8m0_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_e5m2x2_to_bf16x2_rn_relu_satfinite_scale_ue8m0_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs2, [test_e5m2x2_to_bf16x2_rn_relu_satfinite_scale_ue8m0_param_1];
; CHECK-NEXT: cvt.rn.relu.satfinite.scaled::n2::ue8m0.bf16x2.e5m2x2 %r1, %rs1, %rs2;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
%val = call <2 x bfloat> @llvm.nvvm.e5m2x2.to.bf16x2.rn.relu.satfinite.scale.n2.ue8m0(i16 %a, i16 %b)
ret <2 x bfloat> %val
diff --git a/llvm/test/CodeGen/NVPTX/convert_s2f6x2_sm_100a.ll b/llvm/test/CodeGen/NVPTX/convert_s2f6x2_sm_100a.ll
index 0e9c48df99a5d..1bf2943ba749d 100644
--- a/llvm/test/CodeGen/NVPTX/convert_s2f6x2_sm_100a.ll
+++ b/llvm/test/CodeGen/NVPTX/convert_s2f6x2_sm_100a.ll
@@ -19,12 +19,12 @@ define i16 @cvt_s2f6x2_f32_f32_rn_scale(float %f1, float %f2, i16 %scale) {
; CHECK-NEXT: .reg .b32 %r<4>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [cvt_s2f6x2_f32_f32_rn_scale_param_0];
-; CHECK-NEXT: ld.param.b32 %r2, [cvt_s2f6x2_f32_f32_rn_scale_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [cvt_s2f6x2_f32_f32_rn_scale_param_2];
+; CHECK-NEXT: ld.param::func.b32 %r1, [cvt_s2f6x2_f32_f32_rn_scale_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r2, [cvt_s2f6x2_f32_f32_rn_scale_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [cvt_s2f6x2_f32_f32_rn_scale_param_2];
; CHECK-NEXT: cvt.rn.satfinite.scaled::n2::ue8m0.s2f6x2.f32 %rs2, %r1, %r2, %rs1;
; CHECK-NEXT: cvt.u32.u16 %r3, %rs2;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r3;
; CHECK-NEXT: ret;
%val = call i16 @llvm.nvvm.ff.to.s2f6x2.rn.satfinite.scale.n2.ue8m0(float %f1, float %f2, i16 %scale)
ret i16 %val
@@ -37,12 +37,12 @@ define i16 @cvt_s2f6x2_f32_f32_rn_relu_scale(float %f1, float %f2, i16 %scale) {
; CHECK-NEXT: .reg .b32 %r<4>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [cvt_s2f6x2_f32_f32_rn_relu_scale_param_0];
-; CHECK-NEXT: ld.param.b32 %r2, [cvt_s2f6x2_f32_f32_rn_relu_scale_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [cvt_s2f6x2_f32_f32_rn_relu_scale_param_2];
+; CHECK-NEXT: ld.param::func.b32 %r1, [cvt_s2f6x2_f32_f32_rn_relu_scale_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r2, [cvt_s2f6x2_f32_f32_rn_relu_scale_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [cvt_s2f6x2_f32_f32_rn_relu_scale_param_2];
; CHECK-NEXT: cvt.rn.satfinite.relu.scaled::n2::ue8m0.s2f6x2.f32 %rs2, %r1, %r2, %rs1;
; CHECK-NEXT: cvt.u32.u16 %r3, %rs2;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r3;
; CHECK-NEXT: ret;
%val = call i16 @llvm.nvvm.ff.to.s2f6x2.rn.relu.satfinite.scale.n2.ue8m0(float %f1, float %f2, i16 %scale)
ret i16 %val
@@ -57,11 +57,11 @@ define i16 @cvt_s2f6x2_bf16x2_rn_scale(<2 x bfloat> %f, i16 %scale) {
; CHECK-NEXT: .reg .b32 %r<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [cvt_s2f6x2_bf16x2_rn_scale_param_0];
-; CHECK-NEXT: ld.param.b16 %rs1, [cvt_s2f6x2_bf16x2_rn_scale_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r1, [cvt_s2f6x2_bf16x2_rn_scale_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [cvt_s2f6x2_bf16x2_rn_scale_param_1];
; CHECK-NEXT: cvt.rn.satfinite.scaled::n2::ue8m0.s2f6x2.bf16x2 %rs2, %r1, %rs1;
; CHECK-NEXT: cvt.u32.u16 %r2, %rs2;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r2;
; CHECK-NEXT: ret;
%val = call i16 @llvm.nvvm.bf16x2.to.s2f6x2.rn.satfinite.scale.n2.ue8m0(<2 x bfloat> %f, i16 %scale)
ret i16 %val
@@ -74,11 +74,11 @@ define i16 @cvt_s2f6x2_bf16x2_rn_relu_scale(<2 x bfloat> %f, i16 %scale) {
; CHECK-NEXT: .reg .b32 %r<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [cvt_s2f6x2_bf16x2_rn_relu_scale_param_0];
-; CHECK-NEXT: ld.param.b16 %rs1, [cvt_s2f6x2_bf16x2_rn_relu_scale_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r1, [cvt_s2f6x2_bf16x2_rn_relu_scale_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [cvt_s2f6x2_bf16x2_rn_relu_scale_param_1];
; CHECK-NEXT: cvt.rn.satfinite.relu.scaled::n2::ue8m0.s2f6x2.bf16x2 %rs2, %r1, %rs1;
; CHECK-NEXT: cvt.u32.u16 %r2, %rs2;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r2;
; CHECK-NEXT: ret;
%val = call i16 @llvm.nvvm.bf16x2.to.s2f6x2.rn.relu.satfinite.scale.n2.ue8m0(<2 x bfloat> %f, i16 %scale)
ret i16 %val
@@ -93,10 +93,10 @@ define <2 x bfloat> @cvt_bf16x2_s2f6x2_rn_scale(i16 %a, i16 %scale) {
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b16 %rs1, [cvt_bf16x2_s2f6x2_rn_scale_param_0];
-; CHECK-NEXT: ld.param.b16 %rs2, [cvt_bf16x2_s2f6x2_rn_scale_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [cvt_bf16x2_s2f6x2_rn_scale_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs2, [cvt_bf16x2_s2f6x2_rn_scale_param_1];
; CHECK-NEXT: cvt.rn.scaled::n2::ue8m0.bf16x2.s2f6x2 %r1, %rs1, %rs2;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
%val = call <2 x bfloat> @llvm.nvvm.s2f6x2.to.bf16x2.rn.scale.n2.ue8m0(i16 %a, i16 %scale)
ret <2 x bfloat> %val
@@ -109,10 +109,10 @@ define <2 x bfloat> @cvt_bf16x2_s2f6x2_rn_relu_scale(i16 %a, i16 %scale) {
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b16 %rs1, [cvt_bf16x2_s2f6x2_rn_relu_scale_param_0];
-; CHECK-NEXT: ld.param.b16 %rs2, [cvt_bf16x2_s2f6x2_rn_relu_scale_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [cvt_bf16x2_s2f6x2_rn_relu_scale_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs2, [cvt_bf16x2_s2f6x2_rn_relu_scale_param_1];
; CHECK-NEXT: cvt.rn.relu.scaled::n2::ue8m0.bf16x2.s2f6x2 %r1, %rs1, %rs2;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
%val = call <2 x bfloat> @llvm.nvvm.s2f6x2.to.bf16x2.rn.relu.scale.n2.ue8m0(i16 %a, i16 %scale)
ret <2 x bfloat> %val
@@ -125,10 +125,10 @@ define <2 x bfloat> @cvt_bf16x2_s2f6x2_rn_sf_scale(i16 %a, i16 %scale) {
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b16 %rs1, [cvt_bf16x2_s2f6x2_rn_sf_scale_param_0];
-; CHECK-NEXT: ld.param.b16 %rs2, [cvt_bf16x2_s2f6x2_rn_sf_scale_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [cvt_bf16x2_s2f6x2_rn_sf_scale_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs2, [cvt_bf16x2_s2f6x2_rn_sf_scale_param_1];
; CHECK-NEXT: cvt.rn.satfinite.scaled::n2::ue8m0.bf16x2.s2f6x2 %r1, %rs1, %rs2;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
%val = call <2 x bfloat> @llvm.nvvm.s2f6x2.to.bf16x2.rn.satfinite.scale.n2.ue8m0(i16 %a, i16 %scale)
ret <2 x bfloat> %val
@@ -141,10 +141,10 @@ define <2 x bfloat> @cvt_bf16x2_s2f6x2_rn_relu_sf_scale(i16 %a, i16 %scale) {
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b16 %rs1, [cvt_bf16x2_s2f6x2_rn_relu_sf_scale_param_0];
-; CHECK-NEXT: ld.param.b16 %rs2, [cvt_bf16x2_s2f6x2_rn_relu_sf_scale_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [cvt_bf16x2_s2f6x2_rn_relu_sf_scale_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs2, [cvt_bf16x2_s2f6x2_rn_relu_sf_scale_param_1];
; CHECK-NEXT: cvt.rn.satfinite.relu.scaled::n2::ue8m0.bf16x2.s2f6x2 %r1, %rs1, %rs2;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
%val = call <2 x bfloat> @llvm.nvvm.s2f6x2.to.bf16x2.rn.relu.satfinite.scale.n2.ue8m0(i16 %a, i16 %scale)
ret <2 x bfloat> %val
diff --git a/llvm/test/CodeGen/NVPTX/cp-async-bulk-ptx86.ll b/llvm/test/CodeGen/NVPTX/cp-async-bulk-ptx86.ll
index c179749c0e536..eb951a5641b7a 100644
--- a/llvm/test/CodeGen/NVPTX/cp-async-bulk-ptx86.ll
+++ b/llvm/test/CodeGen/NVPTX/cp-async-bulk-ptx86.ll
@@ -15,11 +15,11 @@ define void @cp_async_bulk_g2s(ptr addrspace(1) %src, ptr addrspace(3) %bar, ptr
; CHECK-PTX64-NEXT: .reg .b64 %rd<5>;
; CHECK-PTX64-EMPTY:
; CHECK-PTX64-NEXT: // %bb.0:
-; CHECK-PTX64-NEXT: ld.param.b64 %rd1, [cp_async_bulk_g2s_param_0];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd2, [cp_async_bulk_g2s_param_1];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd3, [cp_async_bulk_g2s_param_2];
-; CHECK-PTX64-NEXT: ld.param.b32 %r1, [cp_async_bulk_g2s_param_3];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd4, [cp_async_bulk_g2s_param_4];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd1, [cp_async_bulk_g2s_param_0];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd2, [cp_async_bulk_g2s_param_1];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd3, [cp_async_bulk_g2s_param_2];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r1, [cp_async_bulk_g2s_param_3];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd4, [cp_async_bulk_g2s_param_4];
; CHECK-PTX64-NEXT: cp.async.bulk.shared::cta.global.mbarrier::complete_tx::bytes [%rd3], [%rd1], %r1, [%rd2];
; CHECK-PTX64-NEXT: cp.async.bulk.shared::cta.global.mbarrier::complete_tx::bytes.L2::cache_hint [%rd3], [%rd1], %r1, [%rd2], %rd4;
; CHECK-PTX64-NEXT: ret;
@@ -30,11 +30,11 @@ define void @cp_async_bulk_g2s(ptr addrspace(1) %src, ptr addrspace(3) %bar, ptr
; CHECK-PTX-SHARED32-NEXT: .reg .b64 %rd<3>;
; CHECK-PTX-SHARED32-EMPTY:
; CHECK-PTX-SHARED32-NEXT: // %bb.0:
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd1, [cp_async_bulk_g2s_param_0];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r1, [cp_async_bulk_g2s_param_1];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r2, [cp_async_bulk_g2s_param_2];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r3, [cp_async_bulk_g2s_param_3];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd2, [cp_async_bulk_g2s_param_4];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd1, [cp_async_bulk_g2s_param_0];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r1, [cp_async_bulk_g2s_param_1];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r2, [cp_async_bulk_g2s_param_2];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r3, [cp_async_bulk_g2s_param_3];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd2, [cp_async_bulk_g2s_param_4];
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.shared::cta.global.mbarrier::complete_tx::bytes [%r2], [%rd1], %r3, [%r1];
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.shared::cta.global.mbarrier::complete_tx::bytes.L2::cache_hint [%r2], [%rd1], %r3, [%r1], %rd2;
; CHECK-PTX-SHARED32-NEXT: ret;
diff --git a/llvm/test/CodeGen/NVPTX/cp-async-bulk-s2g-sm100.ll b/llvm/test/CodeGen/NVPTX/cp-async-bulk-s2g-sm100.ll
index 5ae0202bf7484..4d72eab8963ce 100644
--- a/llvm/test/CodeGen/NVPTX/cp-async-bulk-s2g-sm100.ll
+++ b/llvm/test/CodeGen/NVPTX/cp-async-bulk-s2g-sm100.ll
@@ -16,11 +16,11 @@ define void @cp_async_bulk_s2g_bytemask(ptr addrspace(1) %dst, ptr addrspace(3)
; CHECK-PTX64-NEXT: .reg .b64 %rd<4>;
; CHECK-PTX64-EMPTY:
; CHECK-PTX64-NEXT: // %bb.0:
-; CHECK-PTX64-NEXT: ld.param.b64 %rd1, [cp_async_bulk_s2g_bytemask_param_0];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd2, [cp_async_bulk_s2g_bytemask_param_1];
-; CHECK-PTX64-NEXT: ld.param.b32 %r1, [cp_async_bulk_s2g_bytemask_param_2];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd3, [cp_async_bulk_s2g_bytemask_param_3];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs1, [cp_async_bulk_s2g_bytemask_param_4];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd1, [cp_async_bulk_s2g_bytemask_param_0];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd2, [cp_async_bulk_s2g_bytemask_param_1];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r1, [cp_async_bulk_s2g_bytemask_param_2];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd3, [cp_async_bulk_s2g_bytemask_param_3];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs1, [cp_async_bulk_s2g_bytemask_param_4];
; CHECK-PTX64-NEXT: cp.async.bulk.global.shared::cta.bulk_group.L2::cache_hint.cp_mask [%rd1], [%rd2], %r1, %rd3, %rs1;
; CHECK-PTX64-NEXT: cp.async.bulk.global.shared::cta.bulk_group.cp_mask [%rd1], [%rd2], %r1, %rs1;
; CHECK-PTX64-NEXT: ret;
@@ -32,11 +32,11 @@ define void @cp_async_bulk_s2g_bytemask(ptr addrspace(1) %dst, ptr addrspace(3)
; CHECK-PTX-SHARED32-NEXT: .reg .b64 %rd<3>;
; CHECK-PTX-SHARED32-EMPTY:
; CHECK-PTX-SHARED32-NEXT: // %bb.0:
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd1, [cp_async_bulk_s2g_bytemask_param_0];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r1, [cp_async_bulk_s2g_bytemask_param_1];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r2, [cp_async_bulk_s2g_bytemask_param_2];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd2, [cp_async_bulk_s2g_bytemask_param_3];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs1, [cp_async_bulk_s2g_bytemask_param_4];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd1, [cp_async_bulk_s2g_bytemask_param_0];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r1, [cp_async_bulk_s2g_bytemask_param_1];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r2, [cp_async_bulk_s2g_bytemask_param_2];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd2, [cp_async_bulk_s2g_bytemask_param_3];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs1, [cp_async_bulk_s2g_bytemask_param_4];
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.global.shared::cta.bulk_group.L2::cache_hint.cp_mask [%rd1], [%r1], %r2, %rd2, %rs1;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.global.shared::cta.bulk_group.cp_mask [%rd1], [%r1], %r2, %rs1;
; CHECK-PTX-SHARED32-NEXT: ret;
diff --git a/llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-1cta.ll b/llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-1cta.ll
index fefa00189a2af..c5521b00fa237 100644
--- a/llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-1cta.ll
+++ b/llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-1cta.ll
@@ -29,12 +29,12 @@ define void @test_cp_async_bulk_tensor_g2s_tile_1d(ptr addrspace(7) %d, ptr addr
; CHECK-PTX64-NEXT: .reg .b64 %rd<5>;
; CHECK-PTX64-EMPTY:
; CHECK-PTX64-NEXT: // %bb.0:
-; CHECK-PTX64-NEXT: ld.param.b64 %rd1, [test_cp_async_bulk_tensor_g2s_tile_1d_param_0];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd2, [test_cp_async_bulk_tensor_g2s_tile_1d_param_1];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd3, [test_cp_async_bulk_tensor_g2s_tile_1d_param_2];
-; CHECK-PTX64-NEXT: ld.param.b32 %r1, [test_cp_async_bulk_tensor_g2s_tile_1d_param_3];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs1, [test_cp_async_bulk_tensor_g2s_tile_1d_param_4];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd4, [test_cp_async_bulk_tensor_g2s_tile_1d_param_5];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd1, [test_cp_async_bulk_tensor_g2s_tile_1d_param_0];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd2, [test_cp_async_bulk_tensor_g2s_tile_1d_param_1];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd3, [test_cp_async_bulk_tensor_g2s_tile_1d_param_2];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r1, [test_cp_async_bulk_tensor_g2s_tile_1d_param_3];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs1, [test_cp_async_bulk_tensor_g2s_tile_1d_param_4];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd4, [test_cp_async_bulk_tensor_g2s_tile_1d_param_5];
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.1d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint.cta_group::1 [%rd1], [%rd3, {%r1}], [%rd2], %rs1, %rd4;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.1d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::1 [%rd1], [%rd3, {%r1}], [%rd2], %rs1;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.1d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.L2::cache_hint.cta_group::1 [%rd1], [%rd3, {%r1}], [%rd2], %rd4;
@@ -48,12 +48,12 @@ define void @test_cp_async_bulk_tensor_g2s_tile_1d(ptr addrspace(7) %d, ptr addr
; CHECK-PTX-SHARED32-NEXT: .reg .b64 %rd<3>;
; CHECK-PTX-SHARED32-EMPTY:
; CHECK-PTX-SHARED32-NEXT: // %bb.0:
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r1, [test_cp_async_bulk_tensor_g2s_tile_1d_param_0];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r2, [test_cp_async_bulk_tensor_g2s_tile_1d_param_1];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd1, [test_cp_async_bulk_tensor_g2s_tile_1d_param_2];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r3, [test_cp_async_bulk_tensor_g2s_tile_1d_param_3];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs1, [test_cp_async_bulk_tensor_g2s_tile_1d_param_4];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd2, [test_cp_async_bulk_tensor_g2s_tile_1d_param_5];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r1, [test_cp_async_bulk_tensor_g2s_tile_1d_param_0];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r2, [test_cp_async_bulk_tensor_g2s_tile_1d_param_1];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd1, [test_cp_async_bulk_tensor_g2s_tile_1d_param_2];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r3, [test_cp_async_bulk_tensor_g2s_tile_1d_param_3];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs1, [test_cp_async_bulk_tensor_g2s_tile_1d_param_4];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd2, [test_cp_async_bulk_tensor_g2s_tile_1d_param_5];
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.1d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint.cta_group::1 [%r1], [%rd1, {%r3}], [%r2], %rs1, %rd2;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.1d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::1 [%r1], [%rd1, {%r3}], [%r2], %rs1;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.1d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.L2::cache_hint.cta_group::1 [%r1], [%rd1, {%r3}], [%r2], %rd2;
@@ -75,13 +75,13 @@ define void @test_cp_async_bulk_tensor_g2s_tile_2d(ptr addrspace(7) %d, ptr addr
; CHECK-PTX64-NEXT: .reg .b64 %rd<5>;
; CHECK-PTX64-EMPTY:
; CHECK-PTX64-NEXT: // %bb.0:
-; CHECK-PTX64-NEXT: ld.param.b64 %rd1, [test_cp_async_bulk_tensor_g2s_tile_2d_param_0];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd2, [test_cp_async_bulk_tensor_g2s_tile_2d_param_1];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd3, [test_cp_async_bulk_tensor_g2s_tile_2d_param_2];
-; CHECK-PTX64-NEXT: ld.param.b32 %r1, [test_cp_async_bulk_tensor_g2s_tile_2d_param_3];
-; CHECK-PTX64-NEXT: ld.param.b32 %r2, [test_cp_async_bulk_tensor_g2s_tile_2d_param_4];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs1, [test_cp_async_bulk_tensor_g2s_tile_2d_param_5];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd4, [test_cp_async_bulk_tensor_g2s_tile_2d_param_6];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd1, [test_cp_async_bulk_tensor_g2s_tile_2d_param_0];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd2, [test_cp_async_bulk_tensor_g2s_tile_2d_param_1];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd3, [test_cp_async_bulk_tensor_g2s_tile_2d_param_2];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r1, [test_cp_async_bulk_tensor_g2s_tile_2d_param_3];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r2, [test_cp_async_bulk_tensor_g2s_tile_2d_param_4];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs1, [test_cp_async_bulk_tensor_g2s_tile_2d_param_5];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd4, [test_cp_async_bulk_tensor_g2s_tile_2d_param_6];
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.2d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint.cta_group::1 [%rd1], [%rd3, {%r1, %r2}], [%rd2], %rs1, %rd4;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.2d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::1 [%rd1], [%rd3, {%r1, %r2}], [%rd2], %rs1;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.2d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.L2::cache_hint.cta_group::1 [%rd1], [%rd3, {%r1, %r2}], [%rd2], %rd4;
@@ -95,13 +95,13 @@ define void @test_cp_async_bulk_tensor_g2s_tile_2d(ptr addrspace(7) %d, ptr addr
; CHECK-PTX-SHARED32-NEXT: .reg .b64 %rd<3>;
; CHECK-PTX-SHARED32-EMPTY:
; CHECK-PTX-SHARED32-NEXT: // %bb.0:
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r1, [test_cp_async_bulk_tensor_g2s_tile_2d_param_0];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r2, [test_cp_async_bulk_tensor_g2s_tile_2d_param_1];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd1, [test_cp_async_bulk_tensor_g2s_tile_2d_param_2];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r3, [test_cp_async_bulk_tensor_g2s_tile_2d_param_3];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r4, [test_cp_async_bulk_tensor_g2s_tile_2d_param_4];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs1, [test_cp_async_bulk_tensor_g2s_tile_2d_param_5];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd2, [test_cp_async_bulk_tensor_g2s_tile_2d_param_6];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r1, [test_cp_async_bulk_tensor_g2s_tile_2d_param_0];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r2, [test_cp_async_bulk_tensor_g2s_tile_2d_param_1];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd1, [test_cp_async_bulk_tensor_g2s_tile_2d_param_2];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r3, [test_cp_async_bulk_tensor_g2s_tile_2d_param_3];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r4, [test_cp_async_bulk_tensor_g2s_tile_2d_param_4];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs1, [test_cp_async_bulk_tensor_g2s_tile_2d_param_5];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd2, [test_cp_async_bulk_tensor_g2s_tile_2d_param_6];
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.2d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint.cta_group::1 [%r1], [%rd1, {%r3, %r4}], [%r2], %rs1, %rd2;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.2d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::1 [%r1], [%rd1, {%r3, %r4}], [%r2], %rs1;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.2d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.L2::cache_hint.cta_group::1 [%r1], [%rd1, {%r3, %r4}], [%r2], %rd2;
@@ -123,14 +123,14 @@ define void @test_cp_async_bulk_tensor_g2s_tile_3d(ptr addrspace(7) %d, ptr addr
; CHECK-PTX64-NEXT: .reg .b64 %rd<5>;
; CHECK-PTX64-EMPTY:
; CHECK-PTX64-NEXT: // %bb.0:
-; CHECK-PTX64-NEXT: ld.param.b64 %rd1, [test_cp_async_bulk_tensor_g2s_tile_3d_param_0];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd2, [test_cp_async_bulk_tensor_g2s_tile_3d_param_1];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd3, [test_cp_async_bulk_tensor_g2s_tile_3d_param_2];
-; CHECK-PTX64-NEXT: ld.param.b32 %r1, [test_cp_async_bulk_tensor_g2s_tile_3d_param_3];
-; CHECK-PTX64-NEXT: ld.param.b32 %r2, [test_cp_async_bulk_tensor_g2s_tile_3d_param_4];
-; CHECK-PTX64-NEXT: ld.param.b32 %r3, [test_cp_async_bulk_tensor_g2s_tile_3d_param_5];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs1, [test_cp_async_bulk_tensor_g2s_tile_3d_param_6];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd4, [test_cp_async_bulk_tensor_g2s_tile_3d_param_7];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd1, [test_cp_async_bulk_tensor_g2s_tile_3d_param_0];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd2, [test_cp_async_bulk_tensor_g2s_tile_3d_param_1];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd3, [test_cp_async_bulk_tensor_g2s_tile_3d_param_2];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r1, [test_cp_async_bulk_tensor_g2s_tile_3d_param_3];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r2, [test_cp_async_bulk_tensor_g2s_tile_3d_param_4];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r3, [test_cp_async_bulk_tensor_g2s_tile_3d_param_5];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs1, [test_cp_async_bulk_tensor_g2s_tile_3d_param_6];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd4, [test_cp_async_bulk_tensor_g2s_tile_3d_param_7];
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.3d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint.cta_group::1 [%rd1], [%rd3, {%r1, %r2, %r3}], [%rd2], %rs1, %rd4;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.3d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::1 [%rd1], [%rd3, {%r1, %r2, %r3}], [%rd2], %rs1;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.3d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.L2::cache_hint.cta_group::1 [%rd1], [%rd3, {%r1, %r2, %r3}], [%rd2], %rd4;
@@ -144,14 +144,14 @@ define void @test_cp_async_bulk_tensor_g2s_tile_3d(ptr addrspace(7) %d, ptr addr
; CHECK-PTX-SHARED32-NEXT: .reg .b64 %rd<3>;
; CHECK-PTX-SHARED32-EMPTY:
; CHECK-PTX-SHARED32-NEXT: // %bb.0:
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r1, [test_cp_async_bulk_tensor_g2s_tile_3d_param_0];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r2, [test_cp_async_bulk_tensor_g2s_tile_3d_param_1];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd1, [test_cp_async_bulk_tensor_g2s_tile_3d_param_2];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r3, [test_cp_async_bulk_tensor_g2s_tile_3d_param_3];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r4, [test_cp_async_bulk_tensor_g2s_tile_3d_param_4];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r5, [test_cp_async_bulk_tensor_g2s_tile_3d_param_5];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs1, [test_cp_async_bulk_tensor_g2s_tile_3d_param_6];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd2, [test_cp_async_bulk_tensor_g2s_tile_3d_param_7];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r1, [test_cp_async_bulk_tensor_g2s_tile_3d_param_0];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r2, [test_cp_async_bulk_tensor_g2s_tile_3d_param_1];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd1, [test_cp_async_bulk_tensor_g2s_tile_3d_param_2];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r3, [test_cp_async_bulk_tensor_g2s_tile_3d_param_3];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r4, [test_cp_async_bulk_tensor_g2s_tile_3d_param_4];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r5, [test_cp_async_bulk_tensor_g2s_tile_3d_param_5];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs1, [test_cp_async_bulk_tensor_g2s_tile_3d_param_6];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd2, [test_cp_async_bulk_tensor_g2s_tile_3d_param_7];
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.3d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint.cta_group::1 [%r1], [%rd1, {%r3, %r4, %r5}], [%r2], %rs1, %rd2;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.3d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::1 [%r1], [%rd1, {%r3, %r4, %r5}], [%r2], %rs1;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.3d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.L2::cache_hint.cta_group::1 [%r1], [%rd1, {%r3, %r4, %r5}], [%r2], %rd2;
@@ -173,15 +173,15 @@ define void @test_cp_async_bulk_tensor_g2s_tile_4d(ptr addrspace(7) %d, ptr addr
; CHECK-PTX64-NEXT: .reg .b64 %rd<5>;
; CHECK-PTX64-EMPTY:
; CHECK-PTX64-NEXT: // %bb.0:
-; CHECK-PTX64-NEXT: ld.param.b64 %rd1, [test_cp_async_bulk_tensor_g2s_tile_4d_param_0];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd2, [test_cp_async_bulk_tensor_g2s_tile_4d_param_1];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd3, [test_cp_async_bulk_tensor_g2s_tile_4d_param_2];
-; CHECK-PTX64-NEXT: ld.param.b32 %r1, [test_cp_async_bulk_tensor_g2s_tile_4d_param_3];
-; CHECK-PTX64-NEXT: ld.param.b32 %r2, [test_cp_async_bulk_tensor_g2s_tile_4d_param_4];
-; CHECK-PTX64-NEXT: ld.param.b32 %r3, [test_cp_async_bulk_tensor_g2s_tile_4d_param_5];
-; CHECK-PTX64-NEXT: ld.param.b32 %r4, [test_cp_async_bulk_tensor_g2s_tile_4d_param_6];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs1, [test_cp_async_bulk_tensor_g2s_tile_4d_param_7];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd4, [test_cp_async_bulk_tensor_g2s_tile_4d_param_8];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd1, [test_cp_async_bulk_tensor_g2s_tile_4d_param_0];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd2, [test_cp_async_bulk_tensor_g2s_tile_4d_param_1];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd3, [test_cp_async_bulk_tensor_g2s_tile_4d_param_2];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r1, [test_cp_async_bulk_tensor_g2s_tile_4d_param_3];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r2, [test_cp_async_bulk_tensor_g2s_tile_4d_param_4];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r3, [test_cp_async_bulk_tensor_g2s_tile_4d_param_5];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r4, [test_cp_async_bulk_tensor_g2s_tile_4d_param_6];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs1, [test_cp_async_bulk_tensor_g2s_tile_4d_param_7];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd4, [test_cp_async_bulk_tensor_g2s_tile_4d_param_8];
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.4d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint.cta_group::1 [%rd1], [%rd3, {%r1, %r2, %r3, %r4}], [%rd2], %rs1, %rd4;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.4d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::1 [%rd1], [%rd3, {%r1, %r2, %r3, %r4}], [%rd2], %rs1;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.4d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.L2::cache_hint.cta_group::1 [%rd1], [%rd3, {%r1, %r2, %r3, %r4}], [%rd2], %rd4;
@@ -195,15 +195,15 @@ define void @test_cp_async_bulk_tensor_g2s_tile_4d(ptr addrspace(7) %d, ptr addr
; CHECK-PTX-SHARED32-NEXT: .reg .b64 %rd<3>;
; CHECK-PTX-SHARED32-EMPTY:
; CHECK-PTX-SHARED32-NEXT: // %bb.0:
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r1, [test_cp_async_bulk_tensor_g2s_tile_4d_param_0];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r2, [test_cp_async_bulk_tensor_g2s_tile_4d_param_1];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd1, [test_cp_async_bulk_tensor_g2s_tile_4d_param_2];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r3, [test_cp_async_bulk_tensor_g2s_tile_4d_param_3];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r4, [test_cp_async_bulk_tensor_g2s_tile_4d_param_4];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r5, [test_cp_async_bulk_tensor_g2s_tile_4d_param_5];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r6, [test_cp_async_bulk_tensor_g2s_tile_4d_param_6];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs1, [test_cp_async_bulk_tensor_g2s_tile_4d_param_7];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd2, [test_cp_async_bulk_tensor_g2s_tile_4d_param_8];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r1, [test_cp_async_bulk_tensor_g2s_tile_4d_param_0];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r2, [test_cp_async_bulk_tensor_g2s_tile_4d_param_1];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd1, [test_cp_async_bulk_tensor_g2s_tile_4d_param_2];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r3, [test_cp_async_bulk_tensor_g2s_tile_4d_param_3];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r4, [test_cp_async_bulk_tensor_g2s_tile_4d_param_4];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r5, [test_cp_async_bulk_tensor_g2s_tile_4d_param_5];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r6, [test_cp_async_bulk_tensor_g2s_tile_4d_param_6];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs1, [test_cp_async_bulk_tensor_g2s_tile_4d_param_7];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd2, [test_cp_async_bulk_tensor_g2s_tile_4d_param_8];
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.4d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint.cta_group::1 [%r1], [%rd1, {%r3, %r4, %r5, %r6}], [%r2], %rs1, %rd2;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.4d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::1 [%r1], [%rd1, {%r3, %r4, %r5, %r6}], [%r2], %rs1;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.4d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.L2::cache_hint.cta_group::1 [%r1], [%rd1, {%r3, %r4, %r5, %r6}], [%r2], %rd2;
@@ -225,16 +225,16 @@ define void @test_cp_async_bulk_tensor_g2s_tile_5d(ptr addrspace(7) %d, ptr addr
; CHECK-PTX64-NEXT: .reg .b64 %rd<5>;
; CHECK-PTX64-EMPTY:
; CHECK-PTX64-NEXT: // %bb.0:
-; CHECK-PTX64-NEXT: ld.param.b64 %rd1, [test_cp_async_bulk_tensor_g2s_tile_5d_param_0];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd2, [test_cp_async_bulk_tensor_g2s_tile_5d_param_1];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd3, [test_cp_async_bulk_tensor_g2s_tile_5d_param_2];
-; CHECK-PTX64-NEXT: ld.param.b32 %r1, [test_cp_async_bulk_tensor_g2s_tile_5d_param_3];
-; CHECK-PTX64-NEXT: ld.param.b32 %r2, [test_cp_async_bulk_tensor_g2s_tile_5d_param_4];
-; CHECK-PTX64-NEXT: ld.param.b32 %r3, [test_cp_async_bulk_tensor_g2s_tile_5d_param_5];
-; CHECK-PTX64-NEXT: ld.param.b32 %r4, [test_cp_async_bulk_tensor_g2s_tile_5d_param_6];
-; CHECK-PTX64-NEXT: ld.param.b32 %r5, [test_cp_async_bulk_tensor_g2s_tile_5d_param_7];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs1, [test_cp_async_bulk_tensor_g2s_tile_5d_param_8];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd4, [test_cp_async_bulk_tensor_g2s_tile_5d_param_9];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd1, [test_cp_async_bulk_tensor_g2s_tile_5d_param_0];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd2, [test_cp_async_bulk_tensor_g2s_tile_5d_param_1];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd3, [test_cp_async_bulk_tensor_g2s_tile_5d_param_2];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r1, [test_cp_async_bulk_tensor_g2s_tile_5d_param_3];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r2, [test_cp_async_bulk_tensor_g2s_tile_5d_param_4];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r3, [test_cp_async_bulk_tensor_g2s_tile_5d_param_5];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r4, [test_cp_async_bulk_tensor_g2s_tile_5d_param_6];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r5, [test_cp_async_bulk_tensor_g2s_tile_5d_param_7];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs1, [test_cp_async_bulk_tensor_g2s_tile_5d_param_8];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd4, [test_cp_async_bulk_tensor_g2s_tile_5d_param_9];
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.5d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint.cta_group::1 [%rd1], [%rd3, {%r1, %r2, %r3, %r4, %r5}], [%rd2], %rs1, %rd4;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.5d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::1 [%rd1], [%rd3, {%r1, %r2, %r3, %r4, %r5}], [%rd2], %rs1;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.5d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.L2::cache_hint.cta_group::1 [%rd1], [%rd3, {%r1, %r2, %r3, %r4, %r5}], [%rd2], %rd4;
@@ -248,16 +248,16 @@ define void @test_cp_async_bulk_tensor_g2s_tile_5d(ptr addrspace(7) %d, ptr addr
; CHECK-PTX-SHARED32-NEXT: .reg .b64 %rd<3>;
; CHECK-PTX-SHARED32-EMPTY:
; CHECK-PTX-SHARED32-NEXT: // %bb.0:
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r1, [test_cp_async_bulk_tensor_g2s_tile_5d_param_0];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r2, [test_cp_async_bulk_tensor_g2s_tile_5d_param_1];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd1, [test_cp_async_bulk_tensor_g2s_tile_5d_param_2];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r3, [test_cp_async_bulk_tensor_g2s_tile_5d_param_3];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r4, [test_cp_async_bulk_tensor_g2s_tile_5d_param_4];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r5, [test_cp_async_bulk_tensor_g2s_tile_5d_param_5];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r6, [test_cp_async_bulk_tensor_g2s_tile_5d_param_6];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r7, [test_cp_async_bulk_tensor_g2s_tile_5d_param_7];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs1, [test_cp_async_bulk_tensor_g2s_tile_5d_param_8];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd2, [test_cp_async_bulk_tensor_g2s_tile_5d_param_9];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r1, [test_cp_async_bulk_tensor_g2s_tile_5d_param_0];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r2, [test_cp_async_bulk_tensor_g2s_tile_5d_param_1];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd1, [test_cp_async_bulk_tensor_g2s_tile_5d_param_2];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r3, [test_cp_async_bulk_tensor_g2s_tile_5d_param_3];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r4, [test_cp_async_bulk_tensor_g2s_tile_5d_param_4];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r5, [test_cp_async_bulk_tensor_g2s_tile_5d_param_5];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r6, [test_cp_async_bulk_tensor_g2s_tile_5d_param_6];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r7, [test_cp_async_bulk_tensor_g2s_tile_5d_param_7];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs1, [test_cp_async_bulk_tensor_g2s_tile_5d_param_8];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd2, [test_cp_async_bulk_tensor_g2s_tile_5d_param_9];
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.5d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint.cta_group::1 [%r1], [%rd1, {%r3, %r4, %r5, %r6, %r7}], [%r2], %rs1, %rd2;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.5d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::1 [%r1], [%rd1, {%r3, %r4, %r5, %r6, %r7}], [%r2], %rs1;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.5d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.L2::cache_hint.cta_group::1 [%r1], [%rd1, {%r3, %r4, %r5, %r6, %r7}], [%r2], %rd2;
@@ -279,15 +279,15 @@ define void @test_cp_async_bulk_tensor_g2s_im2col_3d(ptr addrspace(7) %d, ptr ad
; CHECK-PTX64-NEXT: .reg .b64 %rd<5>;
; CHECK-PTX64-EMPTY:
; CHECK-PTX64-NEXT: // %bb.0:
-; CHECK-PTX64-NEXT: ld.param.b64 %rd1, [test_cp_async_bulk_tensor_g2s_im2col_3d_param_0];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd2, [test_cp_async_bulk_tensor_g2s_im2col_3d_param_1];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd3, [test_cp_async_bulk_tensor_g2s_im2col_3d_param_2];
-; CHECK-PTX64-NEXT: ld.param.b32 %r1, [test_cp_async_bulk_tensor_g2s_im2col_3d_param_3];
-; CHECK-PTX64-NEXT: ld.param.b32 %r2, [test_cp_async_bulk_tensor_g2s_im2col_3d_param_4];
-; CHECK-PTX64-NEXT: ld.param.b32 %r3, [test_cp_async_bulk_tensor_g2s_im2col_3d_param_5];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs1, [test_cp_async_bulk_tensor_g2s_im2col_3d_param_6];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs2, [test_cp_async_bulk_tensor_g2s_im2col_3d_param_7];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd4, [test_cp_async_bulk_tensor_g2s_im2col_3d_param_8];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd1, [test_cp_async_bulk_tensor_g2s_im2col_3d_param_0];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd2, [test_cp_async_bulk_tensor_g2s_im2col_3d_param_1];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd3, [test_cp_async_bulk_tensor_g2s_im2col_3d_param_2];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r1, [test_cp_async_bulk_tensor_g2s_im2col_3d_param_3];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r2, [test_cp_async_bulk_tensor_g2s_im2col_3d_param_4];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r3, [test_cp_async_bulk_tensor_g2s_im2col_3d_param_5];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs1, [test_cp_async_bulk_tensor_g2s_im2col_3d_param_6];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs2, [test_cp_async_bulk_tensor_g2s_im2col_3d_param_7];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd4, [test_cp_async_bulk_tensor_g2s_im2col_3d_param_8];
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.3d.shared::cluster.global.im2col.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint.cta_group::1 [%rd1], [%rd3, {%r1, %r2, %r3}], [%rd2], {%rs1}, %rs2, %rd4;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.3d.shared::cluster.global.im2col.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::1 [%rd1], [%rd3, {%r1, %r2, %r3}], [%rd2], {%rs1}, %rs2;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.3d.shared::cluster.global.im2col.mbarrier::complete_tx::bytes.L2::cache_hint.cta_group::1 [%rd1], [%rd3, {%r1, %r2, %r3}], [%rd2], {%rs1}, %rd4;
@@ -301,15 +301,15 @@ define void @test_cp_async_bulk_tensor_g2s_im2col_3d(ptr addrspace(7) %d, ptr ad
; CHECK-PTX-SHARED32-NEXT: .reg .b64 %rd<3>;
; CHECK-PTX-SHARED32-EMPTY:
; CHECK-PTX-SHARED32-NEXT: // %bb.0:
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r1, [test_cp_async_bulk_tensor_g2s_im2col_3d_param_0];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r2, [test_cp_async_bulk_tensor_g2s_im2col_3d_param_1];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd1, [test_cp_async_bulk_tensor_g2s_im2col_3d_param_2];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r3, [test_cp_async_bulk_tensor_g2s_im2col_3d_param_3];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r4, [test_cp_async_bulk_tensor_g2s_im2col_3d_param_4];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r5, [test_cp_async_bulk_tensor_g2s_im2col_3d_param_5];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs1, [test_cp_async_bulk_tensor_g2s_im2col_3d_param_6];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs2, [test_cp_async_bulk_tensor_g2s_im2col_3d_param_7];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd2, [test_cp_async_bulk_tensor_g2s_im2col_3d_param_8];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r1, [test_cp_async_bulk_tensor_g2s_im2col_3d_param_0];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r2, [test_cp_async_bulk_tensor_g2s_im2col_3d_param_1];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd1, [test_cp_async_bulk_tensor_g2s_im2col_3d_param_2];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r3, [test_cp_async_bulk_tensor_g2s_im2col_3d_param_3];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r4, [test_cp_async_bulk_tensor_g2s_im2col_3d_param_4];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r5, [test_cp_async_bulk_tensor_g2s_im2col_3d_param_5];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs1, [test_cp_async_bulk_tensor_g2s_im2col_3d_param_6];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs2, [test_cp_async_bulk_tensor_g2s_im2col_3d_param_7];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd2, [test_cp_async_bulk_tensor_g2s_im2col_3d_param_8];
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.3d.shared::cluster.global.im2col.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint.cta_group::1 [%r1], [%rd1, {%r3, %r4, %r5}], [%r2], {%rs1}, %rs2, %rd2;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.3d.shared::cluster.global.im2col.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::1 [%r1], [%rd1, {%r3, %r4, %r5}], [%r2], {%rs1}, %rs2;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.3d.shared::cluster.global.im2col.mbarrier::complete_tx::bytes.L2::cache_hint.cta_group::1 [%r1], [%rd1, {%r3, %r4, %r5}], [%r2], {%rs1}, %rd2;
@@ -331,17 +331,17 @@ define void @test_cp_async_bulk_tensor_g2s_im2col_4d(ptr addrspace(7) %d, ptr ad
; CHECK-PTX64-NEXT: .reg .b64 %rd<5>;
; CHECK-PTX64-EMPTY:
; CHECK-PTX64-NEXT: // %bb.0:
-; CHECK-PTX64-NEXT: ld.param.b64 %rd1, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_0];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd2, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_1];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd3, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_2];
-; CHECK-PTX64-NEXT: ld.param.b32 %r1, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_3];
-; CHECK-PTX64-NEXT: ld.param.b32 %r2, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_4];
-; CHECK-PTX64-NEXT: ld.param.b32 %r3, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_5];
-; CHECK-PTX64-NEXT: ld.param.b32 %r4, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_6];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs1, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_7];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs2, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_8];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs3, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_9];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd4, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_10];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd1, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_0];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd2, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_1];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd3, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_2];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r1, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_3];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r2, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_4];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r3, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_5];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r4, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_6];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs1, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_7];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs2, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_8];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs3, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_9];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd4, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_10];
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.4d.shared::cluster.global.im2col.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint.cta_group::1 [%rd1], [%rd3, {%r1, %r2, %r3, %r4}], [%rd2], {%rs1, %rs2}, %rs3, %rd4;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.4d.shared::cluster.global.im2col.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::1 [%rd1], [%rd3, {%r1, %r2, %r3, %r4}], [%rd2], {%rs1, %rs2}, %rs3;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.4d.shared::cluster.global.im2col.mbarrier::complete_tx::bytes.L2::cache_hint.cta_group::1 [%rd1], [%rd3, {%r1, %r2, %r3, %r4}], [%rd2], {%rs1, %rs2}, %rd4;
@@ -355,17 +355,17 @@ define void @test_cp_async_bulk_tensor_g2s_im2col_4d(ptr addrspace(7) %d, ptr ad
; CHECK-PTX-SHARED32-NEXT: .reg .b64 %rd<3>;
; CHECK-PTX-SHARED32-EMPTY:
; CHECK-PTX-SHARED32-NEXT: // %bb.0:
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r1, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_0];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r2, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_1];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd1, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_2];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r3, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_3];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r4, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_4];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r5, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_5];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r6, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_6];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs1, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_7];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs2, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_8];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs3, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_9];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd2, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_10];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r1, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_0];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r2, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_1];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd1, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_2];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r3, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_3];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r4, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_4];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r5, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_5];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r6, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_6];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs1, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_7];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs2, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_8];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs3, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_9];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd2, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_10];
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.4d.shared::cluster.global.im2col.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint.cta_group::1 [%r1], [%rd1, {%r3, %r4, %r5, %r6}], [%r2], {%rs1, %rs2}, %rs3, %rd2;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.4d.shared::cluster.global.im2col.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::1 [%r1], [%rd1, {%r3, %r4, %r5, %r6}], [%r2], {%rs1, %rs2}, %rs3;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.4d.shared::cluster.global.im2col.mbarrier::complete_tx::bytes.L2::cache_hint.cta_group::1 [%r1], [%rd1, {%r3, %r4, %r5, %r6}], [%r2], {%rs1, %rs2}, %rd2;
@@ -387,19 +387,19 @@ define void @test_cp_async_bulk_tensor_g2s_im2col_5d(ptr addrspace(7) %d, ptr ad
; CHECK-PTX64-NEXT: .reg .b64 %rd<5>;
; CHECK-PTX64-EMPTY:
; CHECK-PTX64-NEXT: // %bb.0:
-; CHECK-PTX64-NEXT: ld.param.b64 %rd1, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_0];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd2, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_1];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd3, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_2];
-; CHECK-PTX64-NEXT: ld.param.b32 %r1, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_3];
-; CHECK-PTX64-NEXT: ld.param.b32 %r2, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_4];
-; CHECK-PTX64-NEXT: ld.param.b32 %r3, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_5];
-; CHECK-PTX64-NEXT: ld.param.b32 %r4, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_6];
-; CHECK-PTX64-NEXT: ld.param.b32 %r5, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_7];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs1, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_8];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs2, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_9];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs3, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_10];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs4, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_11];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd4, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_12];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd1, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_0];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd2, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_1];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd3, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_2];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r1, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_3];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r2, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_4];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r3, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_5];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r4, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_6];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r5, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_7];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs1, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_8];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs2, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_9];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs3, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_10];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs4, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_11];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd4, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_12];
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.5d.shared::cluster.global.im2col.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint.cta_group::1 [%rd1], [%rd3, {%r1, %r2, %r3, %r4, %r5}], [%rd2], {%rs1, %rs2, %rs3}, %rs4, %rd4;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.5d.shared::cluster.global.im2col.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::1 [%rd1], [%rd3, {%r1, %r2, %r3, %r4, %r5}], [%rd2], {%rs1, %rs2, %rs3}, %rs4;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.5d.shared::cluster.global.im2col.mbarrier::complete_tx::bytes.L2::cache_hint.cta_group::1 [%rd1], [%rd3, {%r1, %r2, %r3, %r4, %r5}], [%rd2], {%rs1, %rs2, %rs3}, %rd4;
@@ -413,19 +413,19 @@ define void @test_cp_async_bulk_tensor_g2s_im2col_5d(ptr addrspace(7) %d, ptr ad
; CHECK-PTX-SHARED32-NEXT: .reg .b64 %rd<3>;
; CHECK-PTX-SHARED32-EMPTY:
; CHECK-PTX-SHARED32-NEXT: // %bb.0:
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r1, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_0];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r2, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_1];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd1, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_2];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r3, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_3];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r4, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_4];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r5, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_5];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r6, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_6];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r7, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_7];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs1, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_8];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs2, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_9];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs3, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_10];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs4, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_11];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd2, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_12];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r1, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_0];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r2, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_1];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd1, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_2];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r3, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_3];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r4, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_4];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r5, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_5];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r6, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_6];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r7, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_7];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs1, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_8];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs2, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_9];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs3, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_10];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs4, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_11];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd2, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_12];
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.5d.shared::cluster.global.im2col.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint.cta_group::1 [%r1], [%rd1, {%r3, %r4, %r5, %r6, %r7}], [%r2], {%rs1, %rs2, %rs3}, %rs4, %rd2;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.5d.shared::cluster.global.im2col.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::1 [%r1], [%rd1, {%r3, %r4, %r5, %r6, %r7}], [%r2], {%rs1, %rs2, %rs3}, %rs4;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.5d.shared::cluster.global.im2col.mbarrier::complete_tx::bytes.L2::cache_hint.cta_group::1 [%r1], [%rd1, {%r3, %r4, %r5, %r6, %r7}], [%r2], {%rs1, %rs2, %rs3}, %rd2;
diff --git a/llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-2cta.ll b/llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-2cta.ll
index c070eb23c0544..c8a0fa6e96ce2 100644
--- a/llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-2cta.ll
+++ b/llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-2cta.ll
@@ -29,12 +29,12 @@ define void @test_cp_async_bulk_tensor_g2s_tile_1d(ptr addrspace(7) %d, ptr addr
; CHECK-PTX64-NEXT: .reg .b64 %rd<5>;
; CHECK-PTX64-EMPTY:
; CHECK-PTX64-NEXT: // %bb.0:
-; CHECK-PTX64-NEXT: ld.param.b64 %rd1, [test_cp_async_bulk_tensor_g2s_tile_1d_param_0];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd2, [test_cp_async_bulk_tensor_g2s_tile_1d_param_1];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd3, [test_cp_async_bulk_tensor_g2s_tile_1d_param_2];
-; CHECK-PTX64-NEXT: ld.param.b32 %r1, [test_cp_async_bulk_tensor_g2s_tile_1d_param_3];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs1, [test_cp_async_bulk_tensor_g2s_tile_1d_param_4];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd4, [test_cp_async_bulk_tensor_g2s_tile_1d_param_5];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd1, [test_cp_async_bulk_tensor_g2s_tile_1d_param_0];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd2, [test_cp_async_bulk_tensor_g2s_tile_1d_param_1];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd3, [test_cp_async_bulk_tensor_g2s_tile_1d_param_2];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r1, [test_cp_async_bulk_tensor_g2s_tile_1d_param_3];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs1, [test_cp_async_bulk_tensor_g2s_tile_1d_param_4];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd4, [test_cp_async_bulk_tensor_g2s_tile_1d_param_5];
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.1d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint.cta_group::2 [%rd1], [%rd3, {%r1}], [%rd2], %rs1, %rd4;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.1d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::2 [%rd1], [%rd3, {%r1}], [%rd2], %rs1;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.1d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.L2::cache_hint.cta_group::2 [%rd1], [%rd3, {%r1}], [%rd2], %rd4;
@@ -48,12 +48,12 @@ define void @test_cp_async_bulk_tensor_g2s_tile_1d(ptr addrspace(7) %d, ptr addr
; CHECK-PTX-SHARED32-NEXT: .reg .b64 %rd<3>;
; CHECK-PTX-SHARED32-EMPTY:
; CHECK-PTX-SHARED32-NEXT: // %bb.0:
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r1, [test_cp_async_bulk_tensor_g2s_tile_1d_param_0];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r2, [test_cp_async_bulk_tensor_g2s_tile_1d_param_1];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd1, [test_cp_async_bulk_tensor_g2s_tile_1d_param_2];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r3, [test_cp_async_bulk_tensor_g2s_tile_1d_param_3];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs1, [test_cp_async_bulk_tensor_g2s_tile_1d_param_4];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd2, [test_cp_async_bulk_tensor_g2s_tile_1d_param_5];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r1, [test_cp_async_bulk_tensor_g2s_tile_1d_param_0];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r2, [test_cp_async_bulk_tensor_g2s_tile_1d_param_1];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd1, [test_cp_async_bulk_tensor_g2s_tile_1d_param_2];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r3, [test_cp_async_bulk_tensor_g2s_tile_1d_param_3];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs1, [test_cp_async_bulk_tensor_g2s_tile_1d_param_4];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd2, [test_cp_async_bulk_tensor_g2s_tile_1d_param_5];
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.1d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint.cta_group::2 [%r1], [%rd1, {%r3}], [%r2], %rs1, %rd2;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.1d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::2 [%r1], [%rd1, {%r3}], [%r2], %rs1;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.1d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.L2::cache_hint.cta_group::2 [%r1], [%rd1, {%r3}], [%r2], %rd2;
@@ -75,13 +75,13 @@ define void @test_cp_async_bulk_tensor_g2s_tile_2d(ptr addrspace(7) %d, ptr addr
; CHECK-PTX64-NEXT: .reg .b64 %rd<5>;
; CHECK-PTX64-EMPTY:
; CHECK-PTX64-NEXT: // %bb.0:
-; CHECK-PTX64-NEXT: ld.param.b64 %rd1, [test_cp_async_bulk_tensor_g2s_tile_2d_param_0];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd2, [test_cp_async_bulk_tensor_g2s_tile_2d_param_1];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd3, [test_cp_async_bulk_tensor_g2s_tile_2d_param_2];
-; CHECK-PTX64-NEXT: ld.param.b32 %r1, [test_cp_async_bulk_tensor_g2s_tile_2d_param_3];
-; CHECK-PTX64-NEXT: ld.param.b32 %r2, [test_cp_async_bulk_tensor_g2s_tile_2d_param_4];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs1, [test_cp_async_bulk_tensor_g2s_tile_2d_param_5];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd4, [test_cp_async_bulk_tensor_g2s_tile_2d_param_6];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd1, [test_cp_async_bulk_tensor_g2s_tile_2d_param_0];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd2, [test_cp_async_bulk_tensor_g2s_tile_2d_param_1];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd3, [test_cp_async_bulk_tensor_g2s_tile_2d_param_2];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r1, [test_cp_async_bulk_tensor_g2s_tile_2d_param_3];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r2, [test_cp_async_bulk_tensor_g2s_tile_2d_param_4];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs1, [test_cp_async_bulk_tensor_g2s_tile_2d_param_5];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd4, [test_cp_async_bulk_tensor_g2s_tile_2d_param_6];
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.2d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint.cta_group::2 [%rd1], [%rd3, {%r1, %r2}], [%rd2], %rs1, %rd4;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.2d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::2 [%rd1], [%rd3, {%r1, %r2}], [%rd2], %rs1;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.2d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.L2::cache_hint.cta_group::2 [%rd1], [%rd3, {%r1, %r2}], [%rd2], %rd4;
@@ -95,13 +95,13 @@ define void @test_cp_async_bulk_tensor_g2s_tile_2d(ptr addrspace(7) %d, ptr addr
; CHECK-PTX-SHARED32-NEXT: .reg .b64 %rd<3>;
; CHECK-PTX-SHARED32-EMPTY:
; CHECK-PTX-SHARED32-NEXT: // %bb.0:
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r1, [test_cp_async_bulk_tensor_g2s_tile_2d_param_0];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r2, [test_cp_async_bulk_tensor_g2s_tile_2d_param_1];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd1, [test_cp_async_bulk_tensor_g2s_tile_2d_param_2];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r3, [test_cp_async_bulk_tensor_g2s_tile_2d_param_3];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r4, [test_cp_async_bulk_tensor_g2s_tile_2d_param_4];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs1, [test_cp_async_bulk_tensor_g2s_tile_2d_param_5];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd2, [test_cp_async_bulk_tensor_g2s_tile_2d_param_6];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r1, [test_cp_async_bulk_tensor_g2s_tile_2d_param_0];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r2, [test_cp_async_bulk_tensor_g2s_tile_2d_param_1];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd1, [test_cp_async_bulk_tensor_g2s_tile_2d_param_2];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r3, [test_cp_async_bulk_tensor_g2s_tile_2d_param_3];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r4, [test_cp_async_bulk_tensor_g2s_tile_2d_param_4];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs1, [test_cp_async_bulk_tensor_g2s_tile_2d_param_5];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd2, [test_cp_async_bulk_tensor_g2s_tile_2d_param_6];
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.2d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint.cta_group::2 [%r1], [%rd1, {%r3, %r4}], [%r2], %rs1, %rd2;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.2d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::2 [%r1], [%rd1, {%r3, %r4}], [%r2], %rs1;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.2d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.L2::cache_hint.cta_group::2 [%r1], [%rd1, {%r3, %r4}], [%r2], %rd2;
@@ -123,14 +123,14 @@ define void @test_cp_async_bulk_tensor_g2s_tile_3d(ptr addrspace(7) %d, ptr addr
; CHECK-PTX64-NEXT: .reg .b64 %rd<5>;
; CHECK-PTX64-EMPTY:
; CHECK-PTX64-NEXT: // %bb.0:
-; CHECK-PTX64-NEXT: ld.param.b64 %rd1, [test_cp_async_bulk_tensor_g2s_tile_3d_param_0];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd2, [test_cp_async_bulk_tensor_g2s_tile_3d_param_1];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd3, [test_cp_async_bulk_tensor_g2s_tile_3d_param_2];
-; CHECK-PTX64-NEXT: ld.param.b32 %r1, [test_cp_async_bulk_tensor_g2s_tile_3d_param_3];
-; CHECK-PTX64-NEXT: ld.param.b32 %r2, [test_cp_async_bulk_tensor_g2s_tile_3d_param_4];
-; CHECK-PTX64-NEXT: ld.param.b32 %r3, [test_cp_async_bulk_tensor_g2s_tile_3d_param_5];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs1, [test_cp_async_bulk_tensor_g2s_tile_3d_param_6];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd4, [test_cp_async_bulk_tensor_g2s_tile_3d_param_7];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd1, [test_cp_async_bulk_tensor_g2s_tile_3d_param_0];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd2, [test_cp_async_bulk_tensor_g2s_tile_3d_param_1];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd3, [test_cp_async_bulk_tensor_g2s_tile_3d_param_2];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r1, [test_cp_async_bulk_tensor_g2s_tile_3d_param_3];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r2, [test_cp_async_bulk_tensor_g2s_tile_3d_param_4];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r3, [test_cp_async_bulk_tensor_g2s_tile_3d_param_5];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs1, [test_cp_async_bulk_tensor_g2s_tile_3d_param_6];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd4, [test_cp_async_bulk_tensor_g2s_tile_3d_param_7];
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.3d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint.cta_group::2 [%rd1], [%rd3, {%r1, %r2, %r3}], [%rd2], %rs1, %rd4;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.3d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::2 [%rd1], [%rd3, {%r1, %r2, %r3}], [%rd2], %rs1;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.3d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.L2::cache_hint.cta_group::2 [%rd1], [%rd3, {%r1, %r2, %r3}], [%rd2], %rd4;
@@ -144,14 +144,14 @@ define void @test_cp_async_bulk_tensor_g2s_tile_3d(ptr addrspace(7) %d, ptr addr
; CHECK-PTX-SHARED32-NEXT: .reg .b64 %rd<3>;
; CHECK-PTX-SHARED32-EMPTY:
; CHECK-PTX-SHARED32-NEXT: // %bb.0:
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r1, [test_cp_async_bulk_tensor_g2s_tile_3d_param_0];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r2, [test_cp_async_bulk_tensor_g2s_tile_3d_param_1];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd1, [test_cp_async_bulk_tensor_g2s_tile_3d_param_2];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r3, [test_cp_async_bulk_tensor_g2s_tile_3d_param_3];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r4, [test_cp_async_bulk_tensor_g2s_tile_3d_param_4];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r5, [test_cp_async_bulk_tensor_g2s_tile_3d_param_5];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs1, [test_cp_async_bulk_tensor_g2s_tile_3d_param_6];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd2, [test_cp_async_bulk_tensor_g2s_tile_3d_param_7];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r1, [test_cp_async_bulk_tensor_g2s_tile_3d_param_0];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r2, [test_cp_async_bulk_tensor_g2s_tile_3d_param_1];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd1, [test_cp_async_bulk_tensor_g2s_tile_3d_param_2];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r3, [test_cp_async_bulk_tensor_g2s_tile_3d_param_3];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r4, [test_cp_async_bulk_tensor_g2s_tile_3d_param_4];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r5, [test_cp_async_bulk_tensor_g2s_tile_3d_param_5];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs1, [test_cp_async_bulk_tensor_g2s_tile_3d_param_6];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd2, [test_cp_async_bulk_tensor_g2s_tile_3d_param_7];
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.3d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint.cta_group::2 [%r1], [%rd1, {%r3, %r4, %r5}], [%r2], %rs1, %rd2;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.3d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::2 [%r1], [%rd1, {%r3, %r4, %r5}], [%r2], %rs1;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.3d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.L2::cache_hint.cta_group::2 [%r1], [%rd1, {%r3, %r4, %r5}], [%r2], %rd2;
@@ -173,15 +173,15 @@ define void @test_cp_async_bulk_tensor_g2s_tile_4d(ptr addrspace(7) %d, ptr addr
; CHECK-PTX64-NEXT: .reg .b64 %rd<5>;
; CHECK-PTX64-EMPTY:
; CHECK-PTX64-NEXT: // %bb.0:
-; CHECK-PTX64-NEXT: ld.param.b64 %rd1, [test_cp_async_bulk_tensor_g2s_tile_4d_param_0];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd2, [test_cp_async_bulk_tensor_g2s_tile_4d_param_1];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd3, [test_cp_async_bulk_tensor_g2s_tile_4d_param_2];
-; CHECK-PTX64-NEXT: ld.param.b32 %r1, [test_cp_async_bulk_tensor_g2s_tile_4d_param_3];
-; CHECK-PTX64-NEXT: ld.param.b32 %r2, [test_cp_async_bulk_tensor_g2s_tile_4d_param_4];
-; CHECK-PTX64-NEXT: ld.param.b32 %r3, [test_cp_async_bulk_tensor_g2s_tile_4d_param_5];
-; CHECK-PTX64-NEXT: ld.param.b32 %r4, [test_cp_async_bulk_tensor_g2s_tile_4d_param_6];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs1, [test_cp_async_bulk_tensor_g2s_tile_4d_param_7];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd4, [test_cp_async_bulk_tensor_g2s_tile_4d_param_8];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd1, [test_cp_async_bulk_tensor_g2s_tile_4d_param_0];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd2, [test_cp_async_bulk_tensor_g2s_tile_4d_param_1];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd3, [test_cp_async_bulk_tensor_g2s_tile_4d_param_2];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r1, [test_cp_async_bulk_tensor_g2s_tile_4d_param_3];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r2, [test_cp_async_bulk_tensor_g2s_tile_4d_param_4];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r3, [test_cp_async_bulk_tensor_g2s_tile_4d_param_5];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r4, [test_cp_async_bulk_tensor_g2s_tile_4d_param_6];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs1, [test_cp_async_bulk_tensor_g2s_tile_4d_param_7];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd4, [test_cp_async_bulk_tensor_g2s_tile_4d_param_8];
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.4d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint.cta_group::2 [%rd1], [%rd3, {%r1, %r2, %r3, %r4}], [%rd2], %rs1, %rd4;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.4d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::2 [%rd1], [%rd3, {%r1, %r2, %r3, %r4}], [%rd2], %rs1;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.4d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.L2::cache_hint.cta_group::2 [%rd1], [%rd3, {%r1, %r2, %r3, %r4}], [%rd2], %rd4;
@@ -195,15 +195,15 @@ define void @test_cp_async_bulk_tensor_g2s_tile_4d(ptr addrspace(7) %d, ptr addr
; CHECK-PTX-SHARED32-NEXT: .reg .b64 %rd<3>;
; CHECK-PTX-SHARED32-EMPTY:
; CHECK-PTX-SHARED32-NEXT: // %bb.0:
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r1, [test_cp_async_bulk_tensor_g2s_tile_4d_param_0];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r2, [test_cp_async_bulk_tensor_g2s_tile_4d_param_1];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd1, [test_cp_async_bulk_tensor_g2s_tile_4d_param_2];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r3, [test_cp_async_bulk_tensor_g2s_tile_4d_param_3];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r4, [test_cp_async_bulk_tensor_g2s_tile_4d_param_4];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r5, [test_cp_async_bulk_tensor_g2s_tile_4d_param_5];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r6, [test_cp_async_bulk_tensor_g2s_tile_4d_param_6];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs1, [test_cp_async_bulk_tensor_g2s_tile_4d_param_7];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd2, [test_cp_async_bulk_tensor_g2s_tile_4d_param_8];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r1, [test_cp_async_bulk_tensor_g2s_tile_4d_param_0];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r2, [test_cp_async_bulk_tensor_g2s_tile_4d_param_1];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd1, [test_cp_async_bulk_tensor_g2s_tile_4d_param_2];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r3, [test_cp_async_bulk_tensor_g2s_tile_4d_param_3];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r4, [test_cp_async_bulk_tensor_g2s_tile_4d_param_4];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r5, [test_cp_async_bulk_tensor_g2s_tile_4d_param_5];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r6, [test_cp_async_bulk_tensor_g2s_tile_4d_param_6];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs1, [test_cp_async_bulk_tensor_g2s_tile_4d_param_7];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd2, [test_cp_async_bulk_tensor_g2s_tile_4d_param_8];
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.4d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint.cta_group::2 [%r1], [%rd1, {%r3, %r4, %r5, %r6}], [%r2], %rs1, %rd2;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.4d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::2 [%r1], [%rd1, {%r3, %r4, %r5, %r6}], [%r2], %rs1;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.4d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.L2::cache_hint.cta_group::2 [%r1], [%rd1, {%r3, %r4, %r5, %r6}], [%r2], %rd2;
@@ -225,16 +225,16 @@ define void @test_cp_async_bulk_tensor_g2s_tile_5d(ptr addrspace(7) %d, ptr addr
; CHECK-PTX64-NEXT: .reg .b64 %rd<5>;
; CHECK-PTX64-EMPTY:
; CHECK-PTX64-NEXT: // %bb.0:
-; CHECK-PTX64-NEXT: ld.param.b64 %rd1, [test_cp_async_bulk_tensor_g2s_tile_5d_param_0];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd2, [test_cp_async_bulk_tensor_g2s_tile_5d_param_1];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd3, [test_cp_async_bulk_tensor_g2s_tile_5d_param_2];
-; CHECK-PTX64-NEXT: ld.param.b32 %r1, [test_cp_async_bulk_tensor_g2s_tile_5d_param_3];
-; CHECK-PTX64-NEXT: ld.param.b32 %r2, [test_cp_async_bulk_tensor_g2s_tile_5d_param_4];
-; CHECK-PTX64-NEXT: ld.param.b32 %r3, [test_cp_async_bulk_tensor_g2s_tile_5d_param_5];
-; CHECK-PTX64-NEXT: ld.param.b32 %r4, [test_cp_async_bulk_tensor_g2s_tile_5d_param_6];
-; CHECK-PTX64-NEXT: ld.param.b32 %r5, [test_cp_async_bulk_tensor_g2s_tile_5d_param_7];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs1, [test_cp_async_bulk_tensor_g2s_tile_5d_param_8];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd4, [test_cp_async_bulk_tensor_g2s_tile_5d_param_9];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd1, [test_cp_async_bulk_tensor_g2s_tile_5d_param_0];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd2, [test_cp_async_bulk_tensor_g2s_tile_5d_param_1];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd3, [test_cp_async_bulk_tensor_g2s_tile_5d_param_2];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r1, [test_cp_async_bulk_tensor_g2s_tile_5d_param_3];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r2, [test_cp_async_bulk_tensor_g2s_tile_5d_param_4];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r3, [test_cp_async_bulk_tensor_g2s_tile_5d_param_5];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r4, [test_cp_async_bulk_tensor_g2s_tile_5d_param_6];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r5, [test_cp_async_bulk_tensor_g2s_tile_5d_param_7];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs1, [test_cp_async_bulk_tensor_g2s_tile_5d_param_8];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd4, [test_cp_async_bulk_tensor_g2s_tile_5d_param_9];
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.5d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint.cta_group::2 [%rd1], [%rd3, {%r1, %r2, %r3, %r4, %r5}], [%rd2], %rs1, %rd4;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.5d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::2 [%rd1], [%rd3, {%r1, %r2, %r3, %r4, %r5}], [%rd2], %rs1;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.5d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.L2::cache_hint.cta_group::2 [%rd1], [%rd3, {%r1, %r2, %r3, %r4, %r5}], [%rd2], %rd4;
@@ -248,16 +248,16 @@ define void @test_cp_async_bulk_tensor_g2s_tile_5d(ptr addrspace(7) %d, ptr addr
; CHECK-PTX-SHARED32-NEXT: .reg .b64 %rd<3>;
; CHECK-PTX-SHARED32-EMPTY:
; CHECK-PTX-SHARED32-NEXT: // %bb.0:
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r1, [test_cp_async_bulk_tensor_g2s_tile_5d_param_0];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r2, [test_cp_async_bulk_tensor_g2s_tile_5d_param_1];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd1, [test_cp_async_bulk_tensor_g2s_tile_5d_param_2];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r3, [test_cp_async_bulk_tensor_g2s_tile_5d_param_3];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r4, [test_cp_async_bulk_tensor_g2s_tile_5d_param_4];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r5, [test_cp_async_bulk_tensor_g2s_tile_5d_param_5];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r6, [test_cp_async_bulk_tensor_g2s_tile_5d_param_6];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r7, [test_cp_async_bulk_tensor_g2s_tile_5d_param_7];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs1, [test_cp_async_bulk_tensor_g2s_tile_5d_param_8];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd2, [test_cp_async_bulk_tensor_g2s_tile_5d_param_9];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r1, [test_cp_async_bulk_tensor_g2s_tile_5d_param_0];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r2, [test_cp_async_bulk_tensor_g2s_tile_5d_param_1];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd1, [test_cp_async_bulk_tensor_g2s_tile_5d_param_2];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r3, [test_cp_async_bulk_tensor_g2s_tile_5d_param_3];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r4, [test_cp_async_bulk_tensor_g2s_tile_5d_param_4];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r5, [test_cp_async_bulk_tensor_g2s_tile_5d_param_5];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r6, [test_cp_async_bulk_tensor_g2s_tile_5d_param_6];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r7, [test_cp_async_bulk_tensor_g2s_tile_5d_param_7];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs1, [test_cp_async_bulk_tensor_g2s_tile_5d_param_8];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd2, [test_cp_async_bulk_tensor_g2s_tile_5d_param_9];
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.5d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint.cta_group::2 [%r1], [%rd1, {%r3, %r4, %r5, %r6, %r7}], [%r2], %rs1, %rd2;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.5d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::2 [%r1], [%rd1, {%r3, %r4, %r5, %r6, %r7}], [%r2], %rs1;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.5d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.L2::cache_hint.cta_group::2 [%r1], [%rd1, {%r3, %r4, %r5, %r6, %r7}], [%r2], %rd2;
@@ -279,15 +279,15 @@ define void @test_cp_async_bulk_tensor_g2s_im2col_3d(ptr addrspace(7) %d, ptr ad
; CHECK-PTX64-NEXT: .reg .b64 %rd<5>;
; CHECK-PTX64-EMPTY:
; CHECK-PTX64-NEXT: // %bb.0:
-; CHECK-PTX64-NEXT: ld.param.b64 %rd1, [test_cp_async_bulk_tensor_g2s_im2col_3d_param_0];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd2, [test_cp_async_bulk_tensor_g2s_im2col_3d_param_1];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd3, [test_cp_async_bulk_tensor_g2s_im2col_3d_param_2];
-; CHECK-PTX64-NEXT: ld.param.b32 %r1, [test_cp_async_bulk_tensor_g2s_im2col_3d_param_3];
-; CHECK-PTX64-NEXT: ld.param.b32 %r2, [test_cp_async_bulk_tensor_g2s_im2col_3d_param_4];
-; CHECK-PTX64-NEXT: ld.param.b32 %r3, [test_cp_async_bulk_tensor_g2s_im2col_3d_param_5];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs1, [test_cp_async_bulk_tensor_g2s_im2col_3d_param_6];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs2, [test_cp_async_bulk_tensor_g2s_im2col_3d_param_7];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd4, [test_cp_async_bulk_tensor_g2s_im2col_3d_param_8];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd1, [test_cp_async_bulk_tensor_g2s_im2col_3d_param_0];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd2, [test_cp_async_bulk_tensor_g2s_im2col_3d_param_1];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd3, [test_cp_async_bulk_tensor_g2s_im2col_3d_param_2];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r1, [test_cp_async_bulk_tensor_g2s_im2col_3d_param_3];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r2, [test_cp_async_bulk_tensor_g2s_im2col_3d_param_4];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r3, [test_cp_async_bulk_tensor_g2s_im2col_3d_param_5];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs1, [test_cp_async_bulk_tensor_g2s_im2col_3d_param_6];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs2, [test_cp_async_bulk_tensor_g2s_im2col_3d_param_7];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd4, [test_cp_async_bulk_tensor_g2s_im2col_3d_param_8];
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.3d.shared::cluster.global.im2col.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint.cta_group::2 [%rd1], [%rd3, {%r1, %r2, %r3}], [%rd2], {%rs1}, %rs2, %rd4;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.3d.shared::cluster.global.im2col.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::2 [%rd1], [%rd3, {%r1, %r2, %r3}], [%rd2], {%rs1}, %rs2;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.3d.shared::cluster.global.im2col.mbarrier::complete_tx::bytes.L2::cache_hint.cta_group::2 [%rd1], [%rd3, {%r1, %r2, %r3}], [%rd2], {%rs1}, %rd4;
@@ -301,15 +301,15 @@ define void @test_cp_async_bulk_tensor_g2s_im2col_3d(ptr addrspace(7) %d, ptr ad
; CHECK-PTX-SHARED32-NEXT: .reg .b64 %rd<3>;
; CHECK-PTX-SHARED32-EMPTY:
; CHECK-PTX-SHARED32-NEXT: // %bb.0:
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r1, [test_cp_async_bulk_tensor_g2s_im2col_3d_param_0];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r2, [test_cp_async_bulk_tensor_g2s_im2col_3d_param_1];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd1, [test_cp_async_bulk_tensor_g2s_im2col_3d_param_2];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r3, [test_cp_async_bulk_tensor_g2s_im2col_3d_param_3];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r4, [test_cp_async_bulk_tensor_g2s_im2col_3d_param_4];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r5, [test_cp_async_bulk_tensor_g2s_im2col_3d_param_5];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs1, [test_cp_async_bulk_tensor_g2s_im2col_3d_param_6];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs2, [test_cp_async_bulk_tensor_g2s_im2col_3d_param_7];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd2, [test_cp_async_bulk_tensor_g2s_im2col_3d_param_8];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r1, [test_cp_async_bulk_tensor_g2s_im2col_3d_param_0];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r2, [test_cp_async_bulk_tensor_g2s_im2col_3d_param_1];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd1, [test_cp_async_bulk_tensor_g2s_im2col_3d_param_2];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r3, [test_cp_async_bulk_tensor_g2s_im2col_3d_param_3];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r4, [test_cp_async_bulk_tensor_g2s_im2col_3d_param_4];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r5, [test_cp_async_bulk_tensor_g2s_im2col_3d_param_5];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs1, [test_cp_async_bulk_tensor_g2s_im2col_3d_param_6];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs2, [test_cp_async_bulk_tensor_g2s_im2col_3d_param_7];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd2, [test_cp_async_bulk_tensor_g2s_im2col_3d_param_8];
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.3d.shared::cluster.global.im2col.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint.cta_group::2 [%r1], [%rd1, {%r3, %r4, %r5}], [%r2], {%rs1}, %rs2, %rd2;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.3d.shared::cluster.global.im2col.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::2 [%r1], [%rd1, {%r3, %r4, %r5}], [%r2], {%rs1}, %rs2;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.3d.shared::cluster.global.im2col.mbarrier::complete_tx::bytes.L2::cache_hint.cta_group::2 [%r1], [%rd1, {%r3, %r4, %r5}], [%r2], {%rs1}, %rd2;
@@ -331,17 +331,17 @@ define void @test_cp_async_bulk_tensor_g2s_im2col_4d(ptr addrspace(7) %d, ptr ad
; CHECK-PTX64-NEXT: .reg .b64 %rd<5>;
; CHECK-PTX64-EMPTY:
; CHECK-PTX64-NEXT: // %bb.0:
-; CHECK-PTX64-NEXT: ld.param.b64 %rd1, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_0];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd2, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_1];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd3, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_2];
-; CHECK-PTX64-NEXT: ld.param.b32 %r1, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_3];
-; CHECK-PTX64-NEXT: ld.param.b32 %r2, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_4];
-; CHECK-PTX64-NEXT: ld.param.b32 %r3, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_5];
-; CHECK-PTX64-NEXT: ld.param.b32 %r4, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_6];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs1, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_7];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs2, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_8];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs3, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_9];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd4, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_10];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd1, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_0];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd2, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_1];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd3, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_2];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r1, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_3];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r2, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_4];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r3, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_5];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r4, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_6];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs1, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_7];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs2, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_8];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs3, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_9];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd4, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_10];
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.4d.shared::cluster.global.im2col.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint.cta_group::2 [%rd1], [%rd3, {%r1, %r2, %r3, %r4}], [%rd2], {%rs1, %rs2}, %rs3, %rd4;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.4d.shared::cluster.global.im2col.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::2 [%rd1], [%rd3, {%r1, %r2, %r3, %r4}], [%rd2], {%rs1, %rs2}, %rs3;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.4d.shared::cluster.global.im2col.mbarrier::complete_tx::bytes.L2::cache_hint.cta_group::2 [%rd1], [%rd3, {%r1, %r2, %r3, %r4}], [%rd2], {%rs1, %rs2}, %rd4;
@@ -355,17 +355,17 @@ define void @test_cp_async_bulk_tensor_g2s_im2col_4d(ptr addrspace(7) %d, ptr ad
; CHECK-PTX-SHARED32-NEXT: .reg .b64 %rd<3>;
; CHECK-PTX-SHARED32-EMPTY:
; CHECK-PTX-SHARED32-NEXT: // %bb.0:
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r1, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_0];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r2, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_1];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd1, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_2];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r3, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_3];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r4, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_4];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r5, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_5];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r6, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_6];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs1, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_7];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs2, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_8];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs3, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_9];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd2, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_10];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r1, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_0];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r2, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_1];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd1, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_2];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r3, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_3];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r4, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_4];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r5, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_5];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r6, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_6];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs1, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_7];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs2, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_8];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs3, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_9];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd2, [test_cp_async_bulk_tensor_g2s_im2col_4d_param_10];
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.4d.shared::cluster.global.im2col.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint.cta_group::2 [%r1], [%rd1, {%r3, %r4, %r5, %r6}], [%r2], {%rs1, %rs2}, %rs3, %rd2;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.4d.shared::cluster.global.im2col.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::2 [%r1], [%rd1, {%r3, %r4, %r5, %r6}], [%r2], {%rs1, %rs2}, %rs3;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.4d.shared::cluster.global.im2col.mbarrier::complete_tx::bytes.L2::cache_hint.cta_group::2 [%r1], [%rd1, {%r3, %r4, %r5, %r6}], [%r2], {%rs1, %rs2}, %rd2;
@@ -387,19 +387,19 @@ define void @test_cp_async_bulk_tensor_g2s_im2col_5d(ptr addrspace(7) %d, ptr ad
; CHECK-PTX64-NEXT: .reg .b64 %rd<5>;
; CHECK-PTX64-EMPTY:
; CHECK-PTX64-NEXT: // %bb.0:
-; CHECK-PTX64-NEXT: ld.param.b64 %rd1, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_0];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd2, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_1];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd3, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_2];
-; CHECK-PTX64-NEXT: ld.param.b32 %r1, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_3];
-; CHECK-PTX64-NEXT: ld.param.b32 %r2, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_4];
-; CHECK-PTX64-NEXT: ld.param.b32 %r3, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_5];
-; CHECK-PTX64-NEXT: ld.param.b32 %r4, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_6];
-; CHECK-PTX64-NEXT: ld.param.b32 %r5, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_7];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs1, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_8];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs2, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_9];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs3, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_10];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs4, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_11];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd4, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_12];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd1, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_0];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd2, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_1];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd3, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_2];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r1, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_3];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r2, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_4];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r3, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_5];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r4, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_6];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r5, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_7];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs1, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_8];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs2, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_9];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs3, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_10];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs4, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_11];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd4, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_12];
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.5d.shared::cluster.global.im2col.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint.cta_group::2 [%rd1], [%rd3, {%r1, %r2, %r3, %r4, %r5}], [%rd2], {%rs1, %rs2, %rs3}, %rs4, %rd4;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.5d.shared::cluster.global.im2col.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::2 [%rd1], [%rd3, {%r1, %r2, %r3, %r4, %r5}], [%rd2], {%rs1, %rs2, %rs3}, %rs4;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.5d.shared::cluster.global.im2col.mbarrier::complete_tx::bytes.L2::cache_hint.cta_group::2 [%rd1], [%rd3, {%r1, %r2, %r3, %r4, %r5}], [%rd2], {%rs1, %rs2, %rs3}, %rd4;
@@ -413,19 +413,19 @@ define void @test_cp_async_bulk_tensor_g2s_im2col_5d(ptr addrspace(7) %d, ptr ad
; CHECK-PTX-SHARED32-NEXT: .reg .b64 %rd<3>;
; CHECK-PTX-SHARED32-EMPTY:
; CHECK-PTX-SHARED32-NEXT: // %bb.0:
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r1, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_0];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r2, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_1];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd1, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_2];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r3, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_3];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r4, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_4];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r5, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_5];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r6, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_6];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r7, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_7];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs1, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_8];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs2, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_9];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs3, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_10];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs4, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_11];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd2, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_12];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r1, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_0];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r2, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_1];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd1, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_2];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r3, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_3];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r4, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_4];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r5, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_5];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r6, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_6];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r7, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_7];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs1, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_8];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs2, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_9];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs3, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_10];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs4, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_11];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd2, [test_cp_async_bulk_tensor_g2s_im2col_5d_param_12];
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.5d.shared::cluster.global.im2col.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint.cta_group::2 [%r1], [%rd1, {%r3, %r4, %r5, %r6, %r7}], [%r2], {%rs1, %rs2, %rs3}, %rs4, %rd2;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.5d.shared::cluster.global.im2col.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::2 [%r1], [%rd1, {%r3, %r4, %r5, %r6, %r7}], [%r2], {%rs1, %rs2, %rs3}, %rs4;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.5d.shared::cluster.global.im2col.mbarrier::complete_tx::bytes.L2::cache_hint.cta_group::2 [%r1], [%rd1, {%r3, %r4, %r5, %r6, %r7}], [%r2], {%rs1, %rs2, %rs3}, %rd2;
diff --git a/llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-cta-sm100.ll b/llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-cta-sm100.ll
index 6928c1f1bdfea..65221a6c6e2ef 100644
--- a/llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-cta-sm100.ll
+++ b/llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-cta-sm100.ll
@@ -18,15 +18,15 @@ define void @test_cp_async_bulk_tensor_g2s_cta_im2col_w_3d(ptr addrspace(3) %d,
; CHECK-PTX64-NEXT: .reg .b64 %rd<5>;
; CHECK-PTX64-EMPTY:
; CHECK-PTX64-NEXT: // %bb.0:
-; CHECK-PTX64-NEXT: ld.param.b64 %rd1, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_3d_param_0];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd2, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_3d_param_1];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd3, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_3d_param_2];
-; CHECK-PTX64-NEXT: ld.param.b32 %r1, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_3d_param_3];
-; CHECK-PTX64-NEXT: ld.param.b32 %r2, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_3d_param_4];
-; CHECK-PTX64-NEXT: ld.param.b32 %r3, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_3d_param_5];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs1, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_3d_param_6];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs2, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_3d_param_7];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd4, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_3d_param_8];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd1, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_3d_param_0];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd2, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_3d_param_1];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd3, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_3d_param_2];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r1, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_3d_param_3];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r2, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_3d_param_4];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r3, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_3d_param_5];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs1, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_3d_param_6];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs2, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_3d_param_7];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd4, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_3d_param_8];
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.3d.shared::cta.global.im2col::w.mbarrier::complete_tx::bytes.L2::cache_hint [%rd1], [%rd3, {%r1, %r2, %r3}], [%rd2], {%rs1, %rs2}, %rd4;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.3d.shared::cta.global.im2col::w.mbarrier::complete_tx::bytes [%rd1], [%rd3, {%r1, %r2, %r3}], [%rd2], {%rs1, %rs2};
; CHECK-PTX64-NEXT: ret;
@@ -38,15 +38,15 @@ define void @test_cp_async_bulk_tensor_g2s_cta_im2col_w_3d(ptr addrspace(3) %d,
; CHECK-PTX-SHARED32-NEXT: .reg .b64 %rd<3>;
; CHECK-PTX-SHARED32-EMPTY:
; CHECK-PTX-SHARED32-NEXT: // %bb.0:
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r1, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_3d_param_0];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r2, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_3d_param_1];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd1, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_3d_param_2];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r3, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_3d_param_3];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r4, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_3d_param_4];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r5, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_3d_param_5];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs1, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_3d_param_6];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs2, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_3d_param_7];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd2, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_3d_param_8];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r1, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_3d_param_0];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r2, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_3d_param_1];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd1, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_3d_param_2];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r3, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_3d_param_3];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r4, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_3d_param_4];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r5, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_3d_param_5];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs1, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_3d_param_6];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs2, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_3d_param_7];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd2, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_3d_param_8];
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.3d.shared::cta.global.im2col::w.mbarrier::complete_tx::bytes.L2::cache_hint [%r1], [%rd1, {%r3, %r4, %r5}], [%r2], {%rs1, %rs2}, %rd2;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.3d.shared::cta.global.im2col::w.mbarrier::complete_tx::bytes [%r1], [%rd1, {%r3, %r4, %r5}], [%r2], {%rs1, %rs2};
; CHECK-PTX-SHARED32-NEXT: ret;
@@ -63,16 +63,16 @@ define void @test_cp_async_bulk_tensor_g2s_cta_im2col_w_4d(ptr addrspace(3) %d,
; CHECK-PTX64-NEXT: .reg .b64 %rd<5>;
; CHECK-PTX64-EMPTY:
; CHECK-PTX64-NEXT: // %bb.0:
-; CHECK-PTX64-NEXT: ld.param.b64 %rd1, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_4d_param_0];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd2, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_4d_param_1];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd3, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_4d_param_2];
-; CHECK-PTX64-NEXT: ld.param.b32 %r1, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_4d_param_3];
-; CHECK-PTX64-NEXT: ld.param.b32 %r2, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_4d_param_4];
-; CHECK-PTX64-NEXT: ld.param.b32 %r3, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_4d_param_5];
-; CHECK-PTX64-NEXT: ld.param.b32 %r4, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_4d_param_6];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs1, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_4d_param_7];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs2, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_4d_param_8];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd4, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_4d_param_9];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd1, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_4d_param_0];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd2, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_4d_param_1];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd3, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_4d_param_2];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r1, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_4d_param_3];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r2, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_4d_param_4];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r3, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_4d_param_5];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r4, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_4d_param_6];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs1, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_4d_param_7];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs2, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_4d_param_8];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd4, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_4d_param_9];
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.4d.shared::cta.global.im2col::w.mbarrier::complete_tx::bytes.L2::cache_hint [%rd1], [%rd3, {%r1, %r2, %r3, %r4}], [%rd2], {%rs1, %rs2}, %rd4;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.4d.shared::cta.global.im2col::w.mbarrier::complete_tx::bytes [%rd1], [%rd3, {%r1, %r2, %r3, %r4}], [%rd2], {%rs1, %rs2};
; CHECK-PTX64-NEXT: ret;
@@ -84,16 +84,16 @@ define void @test_cp_async_bulk_tensor_g2s_cta_im2col_w_4d(ptr addrspace(3) %d,
; CHECK-PTX-SHARED32-NEXT: .reg .b64 %rd<3>;
; CHECK-PTX-SHARED32-EMPTY:
; CHECK-PTX-SHARED32-NEXT: // %bb.0:
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r1, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_4d_param_0];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r2, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_4d_param_1];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd1, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_4d_param_2];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r3, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_4d_param_3];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r4, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_4d_param_4];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r5, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_4d_param_5];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r6, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_4d_param_6];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs1, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_4d_param_7];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs2, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_4d_param_8];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd2, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_4d_param_9];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r1, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_4d_param_0];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r2, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_4d_param_1];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd1, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_4d_param_2];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r3, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_4d_param_3];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r4, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_4d_param_4];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r5, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_4d_param_5];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r6, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_4d_param_6];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs1, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_4d_param_7];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs2, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_4d_param_8];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd2, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_4d_param_9];
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.4d.shared::cta.global.im2col::w.mbarrier::complete_tx::bytes.L2::cache_hint [%r1], [%rd1, {%r3, %r4, %r5, %r6}], [%r2], {%rs1, %rs2}, %rd2;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.4d.shared::cta.global.im2col::w.mbarrier::complete_tx::bytes [%r1], [%rd1, {%r3, %r4, %r5, %r6}], [%r2], {%rs1, %rs2};
; CHECK-PTX-SHARED32-NEXT: ret;
@@ -110,17 +110,17 @@ define void @test_cp_async_bulk_tensor_g2s_cta_im2col_w_5d(ptr addrspace(3) %d,
; CHECK-PTX64-NEXT: .reg .b64 %rd<5>;
; CHECK-PTX64-EMPTY:
; CHECK-PTX64-NEXT: // %bb.0:
-; CHECK-PTX64-NEXT: ld.param.b64 %rd1, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_5d_param_0];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd2, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_5d_param_1];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd3, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_5d_param_2];
-; CHECK-PTX64-NEXT: ld.param.b32 %r1, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_5d_param_3];
-; CHECK-PTX64-NEXT: ld.param.b32 %r2, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_5d_param_4];
-; CHECK-PTX64-NEXT: ld.param.b32 %r3, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_5d_param_5];
-; CHECK-PTX64-NEXT: ld.param.b32 %r4, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_5d_param_6];
-; CHECK-PTX64-NEXT: ld.param.b32 %r5, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_5d_param_7];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs1, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_5d_param_8];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs2, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_5d_param_9];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd4, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_5d_param_10];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd1, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_5d_param_0];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd2, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_5d_param_1];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd3, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_5d_param_2];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r1, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_5d_param_3];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r2, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_5d_param_4];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r3, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_5d_param_5];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r4, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_5d_param_6];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r5, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_5d_param_7];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs1, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_5d_param_8];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs2, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_5d_param_9];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd4, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_5d_param_10];
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.5d.shared::cta.global.im2col::w.mbarrier::complete_tx::bytes.L2::cache_hint [%rd1], [%rd3, {%r1, %r2, %r3, %r4, %r5}], [%rd2], {%rs1, %rs2}, %rd4;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.5d.shared::cta.global.im2col::w.mbarrier::complete_tx::bytes [%rd1], [%rd3, {%r1, %r2, %r3, %r4, %r5}], [%rd2], {%rs1, %rs2};
; CHECK-PTX64-NEXT: ret;
@@ -132,17 +132,17 @@ define void @test_cp_async_bulk_tensor_g2s_cta_im2col_w_5d(ptr addrspace(3) %d,
; CHECK-PTX-SHARED32-NEXT: .reg .b64 %rd<3>;
; CHECK-PTX-SHARED32-EMPTY:
; CHECK-PTX-SHARED32-NEXT: // %bb.0:
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r1, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_5d_param_0];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r2, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_5d_param_1];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd1, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_5d_param_2];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r3, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_5d_param_3];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r4, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_5d_param_4];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r5, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_5d_param_5];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r6, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_5d_param_6];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r7, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_5d_param_7];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs1, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_5d_param_8];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs2, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_5d_param_9];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd2, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_5d_param_10];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r1, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_5d_param_0];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r2, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_5d_param_1];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd1, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_5d_param_2];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r3, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_5d_param_3];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r4, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_5d_param_4];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r5, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_5d_param_5];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r6, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_5d_param_6];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r7, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_5d_param_7];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs1, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_5d_param_8];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs2, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_5d_param_9];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd2, [test_cp_async_bulk_tensor_g2s_cta_im2col_w_5d_param_10];
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.5d.shared::cta.global.im2col::w.mbarrier::complete_tx::bytes.L2::cache_hint [%r1], [%rd1, {%r3, %r4, %r5, %r6, %r7}], [%r2], {%rs1, %rs2}, %rd2;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.5d.shared::cta.global.im2col::w.mbarrier::complete_tx::bytes [%r1], [%rd1, {%r3, %r4, %r5, %r6, %r7}], [%r2], {%rs1, %rs2};
; CHECK-PTX-SHARED32-NEXT: ret;
@@ -158,15 +158,15 @@ define void @test_cp_async_bulk_tensor_g2s_cta_tile_gather4_2d(ptr addrspace(3)
; CHECK-PTX64-NEXT: .reg .b64 %rd<5>;
; CHECK-PTX64-EMPTY:
; CHECK-PTX64-NEXT: // %bb.0:
-; CHECK-PTX64-NEXT: ld.param.b64 %rd1, [test_cp_async_bulk_tensor_g2s_cta_tile_gather4_2d_param_0];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd2, [test_cp_async_bulk_tensor_g2s_cta_tile_gather4_2d_param_1];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd3, [test_cp_async_bulk_tensor_g2s_cta_tile_gather4_2d_param_2];
-; CHECK-PTX64-NEXT: ld.param.b32 %r1, [test_cp_async_bulk_tensor_g2s_cta_tile_gather4_2d_param_3];
-; CHECK-PTX64-NEXT: ld.param.b32 %r2, [test_cp_async_bulk_tensor_g2s_cta_tile_gather4_2d_param_4];
-; CHECK-PTX64-NEXT: ld.param.b32 %r3, [test_cp_async_bulk_tensor_g2s_cta_tile_gather4_2d_param_5];
-; CHECK-PTX64-NEXT: ld.param.b32 %r4, [test_cp_async_bulk_tensor_g2s_cta_tile_gather4_2d_param_6];
-; CHECK-PTX64-NEXT: ld.param.b32 %r5, [test_cp_async_bulk_tensor_g2s_cta_tile_gather4_2d_param_7];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd4, [test_cp_async_bulk_tensor_g2s_cta_tile_gather4_2d_param_8];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd1, [test_cp_async_bulk_tensor_g2s_cta_tile_gather4_2d_param_0];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd2, [test_cp_async_bulk_tensor_g2s_cta_tile_gather4_2d_param_1];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd3, [test_cp_async_bulk_tensor_g2s_cta_tile_gather4_2d_param_2];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r1, [test_cp_async_bulk_tensor_g2s_cta_tile_gather4_2d_param_3];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r2, [test_cp_async_bulk_tensor_g2s_cta_tile_gather4_2d_param_4];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r3, [test_cp_async_bulk_tensor_g2s_cta_tile_gather4_2d_param_5];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r4, [test_cp_async_bulk_tensor_g2s_cta_tile_gather4_2d_param_6];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r5, [test_cp_async_bulk_tensor_g2s_cta_tile_gather4_2d_param_7];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd4, [test_cp_async_bulk_tensor_g2s_cta_tile_gather4_2d_param_8];
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.2d.shared::cta.global.tile::gather4.mbarrier::complete_tx::bytes.L2::cache_hint [%rd1], [%rd3, {%r1, %r2, %r3, %r4, %r5}], [%rd2], %rd4;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.2d.shared::cta.global.tile::gather4.mbarrier::complete_tx::bytes [%rd1], [%rd3, {%r1, %r2, %r3, %r4, %r5}], [%rd2];
; CHECK-PTX64-NEXT: ret;
@@ -177,15 +177,15 @@ define void @test_cp_async_bulk_tensor_g2s_cta_tile_gather4_2d(ptr addrspace(3)
; CHECK-PTX-SHARED32-NEXT: .reg .b64 %rd<3>;
; CHECK-PTX-SHARED32-EMPTY:
; CHECK-PTX-SHARED32-NEXT: // %bb.0:
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r1, [test_cp_async_bulk_tensor_g2s_cta_tile_gather4_2d_param_0];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r2, [test_cp_async_bulk_tensor_g2s_cta_tile_gather4_2d_param_1];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd1, [test_cp_async_bulk_tensor_g2s_cta_tile_gather4_2d_param_2];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r3, [test_cp_async_bulk_tensor_g2s_cta_tile_gather4_2d_param_3];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r4, [test_cp_async_bulk_tensor_g2s_cta_tile_gather4_2d_param_4];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r5, [test_cp_async_bulk_tensor_g2s_cta_tile_gather4_2d_param_5];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r6, [test_cp_async_bulk_tensor_g2s_cta_tile_gather4_2d_param_6];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r7, [test_cp_async_bulk_tensor_g2s_cta_tile_gather4_2d_param_7];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd2, [test_cp_async_bulk_tensor_g2s_cta_tile_gather4_2d_param_8];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r1, [test_cp_async_bulk_tensor_g2s_cta_tile_gather4_2d_param_0];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r2, [test_cp_async_bulk_tensor_g2s_cta_tile_gather4_2d_param_1];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd1, [test_cp_async_bulk_tensor_g2s_cta_tile_gather4_2d_param_2];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r3, [test_cp_async_bulk_tensor_g2s_cta_tile_gather4_2d_param_3];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r4, [test_cp_async_bulk_tensor_g2s_cta_tile_gather4_2d_param_4];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r5, [test_cp_async_bulk_tensor_g2s_cta_tile_gather4_2d_param_5];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r6, [test_cp_async_bulk_tensor_g2s_cta_tile_gather4_2d_param_6];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r7, [test_cp_async_bulk_tensor_g2s_cta_tile_gather4_2d_param_7];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd2, [test_cp_async_bulk_tensor_g2s_cta_tile_gather4_2d_param_8];
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.2d.shared::cta.global.tile::gather4.mbarrier::complete_tx::bytes.L2::cache_hint [%r1], [%rd1, {%r3, %r4, %r5, %r6, %r7}], [%r2], %rd2;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.2d.shared::cta.global.tile::gather4.mbarrier::complete_tx::bytes [%r1], [%rd1, {%r3, %r4, %r5, %r6, %r7}], [%r2];
; CHECK-PTX-SHARED32-NEXT: ret;
diff --git a/llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-cta-sm100a.ll b/llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-cta-sm100a.ll
index d769e783bc460..fe4c0af579b72 100644
--- a/llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-cta-sm100a.ll
+++ b/llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-cta-sm100a.ll
@@ -18,15 +18,15 @@ define void @test_cp_async_bulk_tensor_g2s_cta_im2col_w128_3d(ptr addrspace(3) %
; CHECK-PTX64-NEXT: .reg .b64 %rd<5>;
; CHECK-PTX64-EMPTY:
; CHECK-PTX64-NEXT: // %bb.0:
-; CHECK-PTX64-NEXT: ld.param.b64 %rd1, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_3d_param_0];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd2, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_3d_param_1];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd3, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_3d_param_2];
-; CHECK-PTX64-NEXT: ld.param.b32 %r1, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_3d_param_3];
-; CHECK-PTX64-NEXT: ld.param.b32 %r2, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_3d_param_4];
-; CHECK-PTX64-NEXT: ld.param.b32 %r3, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_3d_param_5];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs1, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_3d_param_6];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs2, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_3d_param_7];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd4, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_3d_param_8];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd1, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_3d_param_0];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd2, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_3d_param_1];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd3, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_3d_param_2];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r1, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_3d_param_3];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r2, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_3d_param_4];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r3, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_3d_param_5];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs1, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_3d_param_6];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs2, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_3d_param_7];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd4, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_3d_param_8];
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.3d.shared::cta.global.im2col::w::128.mbarrier::complete_tx::bytes.L2::cache_hint [%rd1], [%rd3, {%r1, %r2, %r3}], [%rd2], {%rs1, %rs2}, %rd4;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.3d.shared::cta.global.im2col::w::128.mbarrier::complete_tx::bytes [%rd1], [%rd3, {%r1, %r2, %r3}], [%rd2], {%rs1, %rs2};
; CHECK-PTX64-NEXT: ret;
@@ -38,15 +38,15 @@ define void @test_cp_async_bulk_tensor_g2s_cta_im2col_w128_3d(ptr addrspace(3) %
; CHECK-PTX-SHARED32-NEXT: .reg .b64 %rd<3>;
; CHECK-PTX-SHARED32-EMPTY:
; CHECK-PTX-SHARED32-NEXT: // %bb.0:
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r1, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_3d_param_0];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r2, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_3d_param_1];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd1, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_3d_param_2];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r3, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_3d_param_3];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r4, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_3d_param_4];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r5, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_3d_param_5];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs1, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_3d_param_6];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs2, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_3d_param_7];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd2, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_3d_param_8];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r1, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_3d_param_0];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r2, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_3d_param_1];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd1, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_3d_param_2];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r3, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_3d_param_3];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r4, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_3d_param_4];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r5, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_3d_param_5];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs1, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_3d_param_6];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs2, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_3d_param_7];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd2, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_3d_param_8];
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.3d.shared::cta.global.im2col::w::128.mbarrier::complete_tx::bytes.L2::cache_hint [%r1], [%rd1, {%r3, %r4, %r5}], [%r2], {%rs1, %rs2}, %rd2;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.3d.shared::cta.global.im2col::w::128.mbarrier::complete_tx::bytes [%r1], [%rd1, {%r3, %r4, %r5}], [%r2], {%rs1, %rs2};
; CHECK-PTX-SHARED32-NEXT: ret;
@@ -63,16 +63,16 @@ define void @test_cp_async_bulk_tensor_g2s_cta_im2col_w128_4d(ptr addrspace(3) %
; CHECK-PTX64-NEXT: .reg .b64 %rd<5>;
; CHECK-PTX64-EMPTY:
; CHECK-PTX64-NEXT: // %bb.0:
-; CHECK-PTX64-NEXT: ld.param.b64 %rd1, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_4d_param_0];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd2, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_4d_param_1];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd3, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_4d_param_2];
-; CHECK-PTX64-NEXT: ld.param.b32 %r1, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_4d_param_3];
-; CHECK-PTX64-NEXT: ld.param.b32 %r2, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_4d_param_4];
-; CHECK-PTX64-NEXT: ld.param.b32 %r3, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_4d_param_5];
-; CHECK-PTX64-NEXT: ld.param.b32 %r4, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_4d_param_6];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs1, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_4d_param_7];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs2, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_4d_param_8];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd4, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_4d_param_9];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd1, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_4d_param_0];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd2, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_4d_param_1];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd3, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_4d_param_2];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r1, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_4d_param_3];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r2, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_4d_param_4];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r3, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_4d_param_5];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r4, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_4d_param_6];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs1, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_4d_param_7];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs2, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_4d_param_8];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd4, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_4d_param_9];
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.4d.shared::cta.global.im2col::w::128.mbarrier::complete_tx::bytes.L2::cache_hint [%rd1], [%rd3, {%r1, %r2, %r3, %r4}], [%rd2], {%rs1, %rs2}, %rd4;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.4d.shared::cta.global.im2col::w::128.mbarrier::complete_tx::bytes [%rd1], [%rd3, {%r1, %r2, %r3, %r4}], [%rd2], {%rs1, %rs2};
; CHECK-PTX64-NEXT: ret;
@@ -84,16 +84,16 @@ define void @test_cp_async_bulk_tensor_g2s_cta_im2col_w128_4d(ptr addrspace(3) %
; CHECK-PTX-SHARED32-NEXT: .reg .b64 %rd<3>;
; CHECK-PTX-SHARED32-EMPTY:
; CHECK-PTX-SHARED32-NEXT: // %bb.0:
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r1, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_4d_param_0];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r2, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_4d_param_1];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd1, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_4d_param_2];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r3, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_4d_param_3];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r4, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_4d_param_4];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r5, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_4d_param_5];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r6, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_4d_param_6];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs1, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_4d_param_7];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs2, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_4d_param_8];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd2, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_4d_param_9];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r1, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_4d_param_0];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r2, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_4d_param_1];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd1, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_4d_param_2];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r3, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_4d_param_3];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r4, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_4d_param_4];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r5, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_4d_param_5];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r6, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_4d_param_6];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs1, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_4d_param_7];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs2, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_4d_param_8];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd2, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_4d_param_9];
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.4d.shared::cta.global.im2col::w::128.mbarrier::complete_tx::bytes.L2::cache_hint [%r1], [%rd1, {%r3, %r4, %r5, %r6}], [%r2], {%rs1, %rs2}, %rd2;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.4d.shared::cta.global.im2col::w::128.mbarrier::complete_tx::bytes [%r1], [%rd1, {%r3, %r4, %r5, %r6}], [%r2], {%rs1, %rs2};
; CHECK-PTX-SHARED32-NEXT: ret;
@@ -110,17 +110,17 @@ define void @test_cp_async_bulk_tensor_g2s_cta_im2col_w128_5d(ptr addrspace(3) %
; CHECK-PTX64-NEXT: .reg .b64 %rd<5>;
; CHECK-PTX64-EMPTY:
; CHECK-PTX64-NEXT: // %bb.0:
-; CHECK-PTX64-NEXT: ld.param.b64 %rd1, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_5d_param_0];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd2, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_5d_param_1];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd3, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_5d_param_2];
-; CHECK-PTX64-NEXT: ld.param.b32 %r1, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_5d_param_3];
-; CHECK-PTX64-NEXT: ld.param.b32 %r2, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_5d_param_4];
-; CHECK-PTX64-NEXT: ld.param.b32 %r3, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_5d_param_5];
-; CHECK-PTX64-NEXT: ld.param.b32 %r4, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_5d_param_6];
-; CHECK-PTX64-NEXT: ld.param.b32 %r5, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_5d_param_7];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs1, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_5d_param_8];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs2, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_5d_param_9];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd4, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_5d_param_10];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd1, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_5d_param_0];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd2, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_5d_param_1];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd3, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_5d_param_2];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r1, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_5d_param_3];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r2, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_5d_param_4];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r3, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_5d_param_5];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r4, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_5d_param_6];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r5, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_5d_param_7];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs1, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_5d_param_8];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs2, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_5d_param_9];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd4, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_5d_param_10];
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.5d.shared::cta.global.im2col::w::128.mbarrier::complete_tx::bytes.L2::cache_hint [%rd1], [%rd3, {%r1, %r2, %r3, %r4, %r5}], [%rd2], {%rs1, %rs2}, %rd4;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.5d.shared::cta.global.im2col::w::128.mbarrier::complete_tx::bytes [%rd1], [%rd3, {%r1, %r2, %r3, %r4, %r5}], [%rd2], {%rs1, %rs2};
; CHECK-PTX64-NEXT: ret;
@@ -132,17 +132,17 @@ define void @test_cp_async_bulk_tensor_g2s_cta_im2col_w128_5d(ptr addrspace(3) %
; CHECK-PTX-SHARED32-NEXT: .reg .b64 %rd<3>;
; CHECK-PTX-SHARED32-EMPTY:
; CHECK-PTX-SHARED32-NEXT: // %bb.0:
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r1, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_5d_param_0];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r2, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_5d_param_1];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd1, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_5d_param_2];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r3, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_5d_param_3];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r4, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_5d_param_4];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r5, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_5d_param_5];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r6, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_5d_param_6];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r7, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_5d_param_7];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs1, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_5d_param_8];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs2, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_5d_param_9];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd2, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_5d_param_10];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r1, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_5d_param_0];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r2, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_5d_param_1];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd1, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_5d_param_2];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r3, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_5d_param_3];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r4, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_5d_param_4];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r5, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_5d_param_5];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r6, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_5d_param_6];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r7, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_5d_param_7];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs1, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_5d_param_8];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs2, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_5d_param_9];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd2, [test_cp_async_bulk_tensor_g2s_cta_im2col_w128_5d_param_10];
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.5d.shared::cta.global.im2col::w::128.mbarrier::complete_tx::bytes.L2::cache_hint [%r1], [%rd1, {%r3, %r4, %r5, %r6, %r7}], [%r2], {%rs1, %rs2}, %rd2;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.5d.shared::cta.global.im2col::w::128.mbarrier::complete_tx::bytes [%r1], [%rd1, {%r3, %r4, %r5, %r6, %r7}], [%r2], {%rs1, %rs2};
; CHECK-PTX-SHARED32-NEXT: ret;
diff --git a/llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-cta-sm90.ll b/llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-cta-sm90.ll
index 7b7a0ecdd461c..6cd82e5d0db5d 100644
--- a/llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-cta-sm90.ll
+++ b/llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-cta-sm90.ll
@@ -19,11 +19,11 @@ define void @cp_async_bulk_tensor_g2s_cta_tile_1d(ptr addrspace(3) %d, ptr addrs
; CHECK-PTX64-NEXT: .reg .b64 %rd<5>;
; CHECK-PTX64-EMPTY:
; CHECK-PTX64-NEXT: // %bb.0:
-; CHECK-PTX64-NEXT: ld.param.b64 %rd1, [cp_async_bulk_tensor_g2s_cta_tile_1d_param_0];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd2, [cp_async_bulk_tensor_g2s_cta_tile_1d_param_1];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd3, [cp_async_bulk_tensor_g2s_cta_tile_1d_param_2];
-; CHECK-PTX64-NEXT: ld.param.b32 %r1, [cp_async_bulk_tensor_g2s_cta_tile_1d_param_3];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd4, [cp_async_bulk_tensor_g2s_cta_tile_1d_param_4];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd1, [cp_async_bulk_tensor_g2s_cta_tile_1d_param_0];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd2, [cp_async_bulk_tensor_g2s_cta_tile_1d_param_1];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd3, [cp_async_bulk_tensor_g2s_cta_tile_1d_param_2];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r1, [cp_async_bulk_tensor_g2s_cta_tile_1d_param_3];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd4, [cp_async_bulk_tensor_g2s_cta_tile_1d_param_4];
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.1d.shared::cta.global.tile.mbarrier::complete_tx::bytes.L2::cache_hint [%rd1], [%rd3, {%r1}], [%rd2], %rd4;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.1d.shared::cta.global.tile.mbarrier::complete_tx::bytes [%rd1], [%rd3, {%r1}], [%rd2];
; CHECK-PTX64-NEXT: ret;
@@ -34,11 +34,11 @@ define void @cp_async_bulk_tensor_g2s_cta_tile_1d(ptr addrspace(3) %d, ptr addrs
; CHECK-PTX-SHARED32-NEXT: .reg .b64 %rd<3>;
; CHECK-PTX-SHARED32-EMPTY:
; CHECK-PTX-SHARED32-NEXT: // %bb.0:
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r1, [cp_async_bulk_tensor_g2s_cta_tile_1d_param_0];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r2, [cp_async_bulk_tensor_g2s_cta_tile_1d_param_1];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd1, [cp_async_bulk_tensor_g2s_cta_tile_1d_param_2];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r3, [cp_async_bulk_tensor_g2s_cta_tile_1d_param_3];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd2, [cp_async_bulk_tensor_g2s_cta_tile_1d_param_4];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r1, [cp_async_bulk_tensor_g2s_cta_tile_1d_param_0];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r2, [cp_async_bulk_tensor_g2s_cta_tile_1d_param_1];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd1, [cp_async_bulk_tensor_g2s_cta_tile_1d_param_2];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r3, [cp_async_bulk_tensor_g2s_cta_tile_1d_param_3];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd2, [cp_async_bulk_tensor_g2s_cta_tile_1d_param_4];
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.1d.shared::cta.global.tile.mbarrier::complete_tx::bytes.L2::cache_hint [%r1], [%rd1, {%r3}], [%r2], %rd2;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.1d.shared::cta.global.tile.mbarrier::complete_tx::bytes [%r1], [%rd1, {%r3}], [%r2];
; CHECK-PTX-SHARED32-NEXT: ret;
@@ -54,12 +54,12 @@ define void @cp_async_bulk_tensor_g2s_cta_tile_2d(ptr addrspace(3) %d, ptr addrs
; CHECK-PTX64-NEXT: .reg .b64 %rd<5>;
; CHECK-PTX64-EMPTY:
; CHECK-PTX64-NEXT: // %bb.0:
-; CHECK-PTX64-NEXT: ld.param.b64 %rd1, [cp_async_bulk_tensor_g2s_cta_tile_2d_param_0];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd2, [cp_async_bulk_tensor_g2s_cta_tile_2d_param_1];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd3, [cp_async_bulk_tensor_g2s_cta_tile_2d_param_2];
-; CHECK-PTX64-NEXT: ld.param.b32 %r1, [cp_async_bulk_tensor_g2s_cta_tile_2d_param_3];
-; CHECK-PTX64-NEXT: ld.param.b32 %r2, [cp_async_bulk_tensor_g2s_cta_tile_2d_param_4];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd4, [cp_async_bulk_tensor_g2s_cta_tile_2d_param_5];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd1, [cp_async_bulk_tensor_g2s_cta_tile_2d_param_0];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd2, [cp_async_bulk_tensor_g2s_cta_tile_2d_param_1];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd3, [cp_async_bulk_tensor_g2s_cta_tile_2d_param_2];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r1, [cp_async_bulk_tensor_g2s_cta_tile_2d_param_3];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r2, [cp_async_bulk_tensor_g2s_cta_tile_2d_param_4];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd4, [cp_async_bulk_tensor_g2s_cta_tile_2d_param_5];
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.2d.shared::cta.global.tile.mbarrier::complete_tx::bytes.L2::cache_hint [%rd1], [%rd3, {%r1, %r2}], [%rd2], %rd4;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.2d.shared::cta.global.tile.mbarrier::complete_tx::bytes [%rd1], [%rd3, {%r1, %r2}], [%rd2];
; CHECK-PTX64-NEXT: ret;
@@ -70,12 +70,12 @@ define void @cp_async_bulk_tensor_g2s_cta_tile_2d(ptr addrspace(3) %d, ptr addrs
; CHECK-PTX-SHARED32-NEXT: .reg .b64 %rd<3>;
; CHECK-PTX-SHARED32-EMPTY:
; CHECK-PTX-SHARED32-NEXT: // %bb.0:
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r1, [cp_async_bulk_tensor_g2s_cta_tile_2d_param_0];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r2, [cp_async_bulk_tensor_g2s_cta_tile_2d_param_1];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd1, [cp_async_bulk_tensor_g2s_cta_tile_2d_param_2];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r3, [cp_async_bulk_tensor_g2s_cta_tile_2d_param_3];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r4, [cp_async_bulk_tensor_g2s_cta_tile_2d_param_4];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd2, [cp_async_bulk_tensor_g2s_cta_tile_2d_param_5];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r1, [cp_async_bulk_tensor_g2s_cta_tile_2d_param_0];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r2, [cp_async_bulk_tensor_g2s_cta_tile_2d_param_1];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd1, [cp_async_bulk_tensor_g2s_cta_tile_2d_param_2];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r3, [cp_async_bulk_tensor_g2s_cta_tile_2d_param_3];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r4, [cp_async_bulk_tensor_g2s_cta_tile_2d_param_4];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd2, [cp_async_bulk_tensor_g2s_cta_tile_2d_param_5];
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.2d.shared::cta.global.tile.mbarrier::complete_tx::bytes.L2::cache_hint [%r1], [%rd1, {%r3, %r4}], [%r2], %rd2;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.2d.shared::cta.global.tile.mbarrier::complete_tx::bytes [%r1], [%rd1, {%r3, %r4}], [%r2];
; CHECK-PTX-SHARED32-NEXT: ret;
@@ -91,13 +91,13 @@ define void @cp_async_bulk_tensor_g2s_cta_tile_3d(ptr addrspace(3) %d, ptr addrs
; CHECK-PTX64-NEXT: .reg .b64 %rd<5>;
; CHECK-PTX64-EMPTY:
; CHECK-PTX64-NEXT: // %bb.0:
-; CHECK-PTX64-NEXT: ld.param.b64 %rd1, [cp_async_bulk_tensor_g2s_cta_tile_3d_param_0];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd2, [cp_async_bulk_tensor_g2s_cta_tile_3d_param_1];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd3, [cp_async_bulk_tensor_g2s_cta_tile_3d_param_2];
-; CHECK-PTX64-NEXT: ld.param.b32 %r1, [cp_async_bulk_tensor_g2s_cta_tile_3d_param_3];
-; CHECK-PTX64-NEXT: ld.param.b32 %r2, [cp_async_bulk_tensor_g2s_cta_tile_3d_param_4];
-; CHECK-PTX64-NEXT: ld.param.b32 %r3, [cp_async_bulk_tensor_g2s_cta_tile_3d_param_5];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd4, [cp_async_bulk_tensor_g2s_cta_tile_3d_param_6];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd1, [cp_async_bulk_tensor_g2s_cta_tile_3d_param_0];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd2, [cp_async_bulk_tensor_g2s_cta_tile_3d_param_1];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd3, [cp_async_bulk_tensor_g2s_cta_tile_3d_param_2];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r1, [cp_async_bulk_tensor_g2s_cta_tile_3d_param_3];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r2, [cp_async_bulk_tensor_g2s_cta_tile_3d_param_4];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r3, [cp_async_bulk_tensor_g2s_cta_tile_3d_param_5];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd4, [cp_async_bulk_tensor_g2s_cta_tile_3d_param_6];
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.3d.shared::cta.global.tile.mbarrier::complete_tx::bytes.L2::cache_hint [%rd1], [%rd3, {%r1, %r2, %r3}], [%rd2], %rd4;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.3d.shared::cta.global.tile.mbarrier::complete_tx::bytes [%rd1], [%rd3, {%r1, %r2, %r3}], [%rd2];
; CHECK-PTX64-NEXT: ret;
@@ -108,13 +108,13 @@ define void @cp_async_bulk_tensor_g2s_cta_tile_3d(ptr addrspace(3) %d, ptr addrs
; CHECK-PTX-SHARED32-NEXT: .reg .b64 %rd<3>;
; CHECK-PTX-SHARED32-EMPTY:
; CHECK-PTX-SHARED32-NEXT: // %bb.0:
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r1, [cp_async_bulk_tensor_g2s_cta_tile_3d_param_0];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r2, [cp_async_bulk_tensor_g2s_cta_tile_3d_param_1];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd1, [cp_async_bulk_tensor_g2s_cta_tile_3d_param_2];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r3, [cp_async_bulk_tensor_g2s_cta_tile_3d_param_3];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r4, [cp_async_bulk_tensor_g2s_cta_tile_3d_param_4];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r5, [cp_async_bulk_tensor_g2s_cta_tile_3d_param_5];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd2, [cp_async_bulk_tensor_g2s_cta_tile_3d_param_6];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r1, [cp_async_bulk_tensor_g2s_cta_tile_3d_param_0];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r2, [cp_async_bulk_tensor_g2s_cta_tile_3d_param_1];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd1, [cp_async_bulk_tensor_g2s_cta_tile_3d_param_2];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r3, [cp_async_bulk_tensor_g2s_cta_tile_3d_param_3];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r4, [cp_async_bulk_tensor_g2s_cta_tile_3d_param_4];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r5, [cp_async_bulk_tensor_g2s_cta_tile_3d_param_5];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd2, [cp_async_bulk_tensor_g2s_cta_tile_3d_param_6];
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.3d.shared::cta.global.tile.mbarrier::complete_tx::bytes.L2::cache_hint [%r1], [%rd1, {%r3, %r4, %r5}], [%r2], %rd2;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.3d.shared::cta.global.tile.mbarrier::complete_tx::bytes [%r1], [%rd1, {%r3, %r4, %r5}], [%r2];
; CHECK-PTX-SHARED32-NEXT: ret;
@@ -130,14 +130,14 @@ define void @cp_async_bulk_tensor_g2s_cta_tile_4d(ptr addrspace(3) %d, ptr addrs
; CHECK-PTX64-NEXT: .reg .b64 %rd<5>;
; CHECK-PTX64-EMPTY:
; CHECK-PTX64-NEXT: // %bb.0:
-; CHECK-PTX64-NEXT: ld.param.b64 %rd1, [cp_async_bulk_tensor_g2s_cta_tile_4d_param_0];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd2, [cp_async_bulk_tensor_g2s_cta_tile_4d_param_1];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd3, [cp_async_bulk_tensor_g2s_cta_tile_4d_param_2];
-; CHECK-PTX64-NEXT: ld.param.b32 %r1, [cp_async_bulk_tensor_g2s_cta_tile_4d_param_3];
-; CHECK-PTX64-NEXT: ld.param.b32 %r2, [cp_async_bulk_tensor_g2s_cta_tile_4d_param_4];
-; CHECK-PTX64-NEXT: ld.param.b32 %r3, [cp_async_bulk_tensor_g2s_cta_tile_4d_param_5];
-; CHECK-PTX64-NEXT: ld.param.b32 %r4, [cp_async_bulk_tensor_g2s_cta_tile_4d_param_6];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd4, [cp_async_bulk_tensor_g2s_cta_tile_4d_param_7];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd1, [cp_async_bulk_tensor_g2s_cta_tile_4d_param_0];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd2, [cp_async_bulk_tensor_g2s_cta_tile_4d_param_1];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd3, [cp_async_bulk_tensor_g2s_cta_tile_4d_param_2];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r1, [cp_async_bulk_tensor_g2s_cta_tile_4d_param_3];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r2, [cp_async_bulk_tensor_g2s_cta_tile_4d_param_4];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r3, [cp_async_bulk_tensor_g2s_cta_tile_4d_param_5];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r4, [cp_async_bulk_tensor_g2s_cta_tile_4d_param_6];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd4, [cp_async_bulk_tensor_g2s_cta_tile_4d_param_7];
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.4d.shared::cta.global.tile.mbarrier::complete_tx::bytes.L2::cache_hint [%rd1], [%rd3, {%r1, %r2, %r3, %r4}], [%rd2], %rd4;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.4d.shared::cta.global.tile.mbarrier::complete_tx::bytes [%rd1], [%rd3, {%r1, %r2, %r3, %r4}], [%rd2];
; CHECK-PTX64-NEXT: ret;
@@ -148,14 +148,14 @@ define void @cp_async_bulk_tensor_g2s_cta_tile_4d(ptr addrspace(3) %d, ptr addrs
; CHECK-PTX-SHARED32-NEXT: .reg .b64 %rd<3>;
; CHECK-PTX-SHARED32-EMPTY:
; CHECK-PTX-SHARED32-NEXT: // %bb.0:
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r1, [cp_async_bulk_tensor_g2s_cta_tile_4d_param_0];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r2, [cp_async_bulk_tensor_g2s_cta_tile_4d_param_1];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd1, [cp_async_bulk_tensor_g2s_cta_tile_4d_param_2];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r3, [cp_async_bulk_tensor_g2s_cta_tile_4d_param_3];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r4, [cp_async_bulk_tensor_g2s_cta_tile_4d_param_4];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r5, [cp_async_bulk_tensor_g2s_cta_tile_4d_param_5];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r6, [cp_async_bulk_tensor_g2s_cta_tile_4d_param_6];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd2, [cp_async_bulk_tensor_g2s_cta_tile_4d_param_7];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r1, [cp_async_bulk_tensor_g2s_cta_tile_4d_param_0];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r2, [cp_async_bulk_tensor_g2s_cta_tile_4d_param_1];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd1, [cp_async_bulk_tensor_g2s_cta_tile_4d_param_2];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r3, [cp_async_bulk_tensor_g2s_cta_tile_4d_param_3];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r4, [cp_async_bulk_tensor_g2s_cta_tile_4d_param_4];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r5, [cp_async_bulk_tensor_g2s_cta_tile_4d_param_5];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r6, [cp_async_bulk_tensor_g2s_cta_tile_4d_param_6];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd2, [cp_async_bulk_tensor_g2s_cta_tile_4d_param_7];
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.4d.shared::cta.global.tile.mbarrier::complete_tx::bytes.L2::cache_hint [%r1], [%rd1, {%r3, %r4, %r5, %r6}], [%r2], %rd2;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.4d.shared::cta.global.tile.mbarrier::complete_tx::bytes [%r1], [%rd1, {%r3, %r4, %r5, %r6}], [%r2];
; CHECK-PTX-SHARED32-NEXT: ret;
@@ -171,15 +171,15 @@ define void @cp_async_bulk_tensor_g2s_cta_tile_5d(ptr addrspace(3) %d, ptr addrs
; CHECK-PTX64-NEXT: .reg .b64 %rd<5>;
; CHECK-PTX64-EMPTY:
; CHECK-PTX64-NEXT: // %bb.0:
-; CHECK-PTX64-NEXT: ld.param.b64 %rd1, [cp_async_bulk_tensor_g2s_cta_tile_5d_param_0];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd2, [cp_async_bulk_tensor_g2s_cta_tile_5d_param_1];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd3, [cp_async_bulk_tensor_g2s_cta_tile_5d_param_2];
-; CHECK-PTX64-NEXT: ld.param.b32 %r1, [cp_async_bulk_tensor_g2s_cta_tile_5d_param_3];
-; CHECK-PTX64-NEXT: ld.param.b32 %r2, [cp_async_bulk_tensor_g2s_cta_tile_5d_param_4];
-; CHECK-PTX64-NEXT: ld.param.b32 %r3, [cp_async_bulk_tensor_g2s_cta_tile_5d_param_5];
-; CHECK-PTX64-NEXT: ld.param.b32 %r4, [cp_async_bulk_tensor_g2s_cta_tile_5d_param_6];
-; CHECK-PTX64-NEXT: ld.param.b32 %r5, [cp_async_bulk_tensor_g2s_cta_tile_5d_param_7];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd4, [cp_async_bulk_tensor_g2s_cta_tile_5d_param_8];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd1, [cp_async_bulk_tensor_g2s_cta_tile_5d_param_0];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd2, [cp_async_bulk_tensor_g2s_cta_tile_5d_param_1];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd3, [cp_async_bulk_tensor_g2s_cta_tile_5d_param_2];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r1, [cp_async_bulk_tensor_g2s_cta_tile_5d_param_3];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r2, [cp_async_bulk_tensor_g2s_cta_tile_5d_param_4];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r3, [cp_async_bulk_tensor_g2s_cta_tile_5d_param_5];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r4, [cp_async_bulk_tensor_g2s_cta_tile_5d_param_6];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r5, [cp_async_bulk_tensor_g2s_cta_tile_5d_param_7];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd4, [cp_async_bulk_tensor_g2s_cta_tile_5d_param_8];
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.5d.shared::cta.global.tile.mbarrier::complete_tx::bytes.L2::cache_hint [%rd1], [%rd3, {%r1, %r2, %r3, %r4, %r5}], [%rd2], %rd4;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.5d.shared::cta.global.tile.mbarrier::complete_tx::bytes [%rd1], [%rd3, {%r1, %r2, %r3, %r4, %r5}], [%rd2];
; CHECK-PTX64-NEXT: ret;
@@ -190,15 +190,15 @@ define void @cp_async_bulk_tensor_g2s_cta_tile_5d(ptr addrspace(3) %d, ptr addrs
; CHECK-PTX-SHARED32-NEXT: .reg .b64 %rd<3>;
; CHECK-PTX-SHARED32-EMPTY:
; CHECK-PTX-SHARED32-NEXT: // %bb.0:
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r1, [cp_async_bulk_tensor_g2s_cta_tile_5d_param_0];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r2, [cp_async_bulk_tensor_g2s_cta_tile_5d_param_1];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd1, [cp_async_bulk_tensor_g2s_cta_tile_5d_param_2];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r3, [cp_async_bulk_tensor_g2s_cta_tile_5d_param_3];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r4, [cp_async_bulk_tensor_g2s_cta_tile_5d_param_4];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r5, [cp_async_bulk_tensor_g2s_cta_tile_5d_param_5];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r6, [cp_async_bulk_tensor_g2s_cta_tile_5d_param_6];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r7, [cp_async_bulk_tensor_g2s_cta_tile_5d_param_7];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd2, [cp_async_bulk_tensor_g2s_cta_tile_5d_param_8];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r1, [cp_async_bulk_tensor_g2s_cta_tile_5d_param_0];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r2, [cp_async_bulk_tensor_g2s_cta_tile_5d_param_1];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd1, [cp_async_bulk_tensor_g2s_cta_tile_5d_param_2];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r3, [cp_async_bulk_tensor_g2s_cta_tile_5d_param_3];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r4, [cp_async_bulk_tensor_g2s_cta_tile_5d_param_4];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r5, [cp_async_bulk_tensor_g2s_cta_tile_5d_param_5];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r6, [cp_async_bulk_tensor_g2s_cta_tile_5d_param_6];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r7, [cp_async_bulk_tensor_g2s_cta_tile_5d_param_7];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd2, [cp_async_bulk_tensor_g2s_cta_tile_5d_param_8];
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.5d.shared::cta.global.tile.mbarrier::complete_tx::bytes.L2::cache_hint [%r1], [%rd1, {%r3, %r4, %r5, %r6, %r7}], [%r2], %rd2;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.5d.shared::cta.global.tile.mbarrier::complete_tx::bytes [%r1], [%rd1, {%r3, %r4, %r5, %r6, %r7}], [%r2];
; CHECK-PTX-SHARED32-NEXT: ret;
@@ -219,14 +219,14 @@ define void @test_cp_async_bulk_tensor_g2s_cta_im2col_3d(ptr addrspace(3) %d, pt
; CHECK-PTX64-NEXT: .reg .b64 %rd<5>;
; CHECK-PTX64-EMPTY:
; CHECK-PTX64-NEXT: // %bb.0:
-; CHECK-PTX64-NEXT: ld.param.b64 %rd1, [test_cp_async_bulk_tensor_g2s_cta_im2col_3d_param_0];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd2, [test_cp_async_bulk_tensor_g2s_cta_im2col_3d_param_1];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd3, [test_cp_async_bulk_tensor_g2s_cta_im2col_3d_param_2];
-; CHECK-PTX64-NEXT: ld.param.b32 %r1, [test_cp_async_bulk_tensor_g2s_cta_im2col_3d_param_3];
-; CHECK-PTX64-NEXT: ld.param.b32 %r2, [test_cp_async_bulk_tensor_g2s_cta_im2col_3d_param_4];
-; CHECK-PTX64-NEXT: ld.param.b32 %r3, [test_cp_async_bulk_tensor_g2s_cta_im2col_3d_param_5];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs1, [test_cp_async_bulk_tensor_g2s_cta_im2col_3d_param_6];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd4, [test_cp_async_bulk_tensor_g2s_cta_im2col_3d_param_7];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd1, [test_cp_async_bulk_tensor_g2s_cta_im2col_3d_param_0];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd2, [test_cp_async_bulk_tensor_g2s_cta_im2col_3d_param_1];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd3, [test_cp_async_bulk_tensor_g2s_cta_im2col_3d_param_2];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r1, [test_cp_async_bulk_tensor_g2s_cta_im2col_3d_param_3];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r2, [test_cp_async_bulk_tensor_g2s_cta_im2col_3d_param_4];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r3, [test_cp_async_bulk_tensor_g2s_cta_im2col_3d_param_5];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs1, [test_cp_async_bulk_tensor_g2s_cta_im2col_3d_param_6];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd4, [test_cp_async_bulk_tensor_g2s_cta_im2col_3d_param_7];
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.3d.shared::cta.global.im2col.mbarrier::complete_tx::bytes.L2::cache_hint [%rd1], [%rd3, {%r1, %r2, %r3}], [%rd2], {%rs1}, %rd4;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.3d.shared::cta.global.im2col.mbarrier::complete_tx::bytes [%rd1], [%rd3, {%r1, %r2, %r3}], [%rd2], {%rs1};
; CHECK-PTX64-NEXT: ret;
@@ -238,14 +238,14 @@ define void @test_cp_async_bulk_tensor_g2s_cta_im2col_3d(ptr addrspace(3) %d, pt
; CHECK-PTX-SHARED32-NEXT: .reg .b64 %rd<3>;
; CHECK-PTX-SHARED32-EMPTY:
; CHECK-PTX-SHARED32-NEXT: // %bb.0:
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r1, [test_cp_async_bulk_tensor_g2s_cta_im2col_3d_param_0];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r2, [test_cp_async_bulk_tensor_g2s_cta_im2col_3d_param_1];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd1, [test_cp_async_bulk_tensor_g2s_cta_im2col_3d_param_2];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r3, [test_cp_async_bulk_tensor_g2s_cta_im2col_3d_param_3];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r4, [test_cp_async_bulk_tensor_g2s_cta_im2col_3d_param_4];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r5, [test_cp_async_bulk_tensor_g2s_cta_im2col_3d_param_5];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs1, [test_cp_async_bulk_tensor_g2s_cta_im2col_3d_param_6];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd2, [test_cp_async_bulk_tensor_g2s_cta_im2col_3d_param_7];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r1, [test_cp_async_bulk_tensor_g2s_cta_im2col_3d_param_0];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r2, [test_cp_async_bulk_tensor_g2s_cta_im2col_3d_param_1];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd1, [test_cp_async_bulk_tensor_g2s_cta_im2col_3d_param_2];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r3, [test_cp_async_bulk_tensor_g2s_cta_im2col_3d_param_3];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r4, [test_cp_async_bulk_tensor_g2s_cta_im2col_3d_param_4];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r5, [test_cp_async_bulk_tensor_g2s_cta_im2col_3d_param_5];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs1, [test_cp_async_bulk_tensor_g2s_cta_im2col_3d_param_6];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd2, [test_cp_async_bulk_tensor_g2s_cta_im2col_3d_param_7];
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.3d.shared::cta.global.im2col.mbarrier::complete_tx::bytes.L2::cache_hint [%r1], [%rd1, {%r3, %r4, %r5}], [%r2], {%rs1}, %rd2;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.3d.shared::cta.global.im2col.mbarrier::complete_tx::bytes [%r1], [%rd1, {%r3, %r4, %r5}], [%r2], {%rs1};
; CHECK-PTX-SHARED32-NEXT: ret;
@@ -262,16 +262,16 @@ define void @test_cp_async_bulk_tensor_g2s_cta_im2col_4d(ptr addrspace(3) %d, pt
; CHECK-PTX64-NEXT: .reg .b64 %rd<5>;
; CHECK-PTX64-EMPTY:
; CHECK-PTX64-NEXT: // %bb.0:
-; CHECK-PTX64-NEXT: ld.param.b64 %rd1, [test_cp_async_bulk_tensor_g2s_cta_im2col_4d_param_0];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd2, [test_cp_async_bulk_tensor_g2s_cta_im2col_4d_param_1];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd3, [test_cp_async_bulk_tensor_g2s_cta_im2col_4d_param_2];
-; CHECK-PTX64-NEXT: ld.param.b32 %r1, [test_cp_async_bulk_tensor_g2s_cta_im2col_4d_param_3];
-; CHECK-PTX64-NEXT: ld.param.b32 %r2, [test_cp_async_bulk_tensor_g2s_cta_im2col_4d_param_4];
-; CHECK-PTX64-NEXT: ld.param.b32 %r3, [test_cp_async_bulk_tensor_g2s_cta_im2col_4d_param_5];
-; CHECK-PTX64-NEXT: ld.param.b32 %r4, [test_cp_async_bulk_tensor_g2s_cta_im2col_4d_param_6];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs1, [test_cp_async_bulk_tensor_g2s_cta_im2col_4d_param_7];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs2, [test_cp_async_bulk_tensor_g2s_cta_im2col_4d_param_8];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd4, [test_cp_async_bulk_tensor_g2s_cta_im2col_4d_param_9];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd1, [test_cp_async_bulk_tensor_g2s_cta_im2col_4d_param_0];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd2, [test_cp_async_bulk_tensor_g2s_cta_im2col_4d_param_1];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd3, [test_cp_async_bulk_tensor_g2s_cta_im2col_4d_param_2];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r1, [test_cp_async_bulk_tensor_g2s_cta_im2col_4d_param_3];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r2, [test_cp_async_bulk_tensor_g2s_cta_im2col_4d_param_4];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r3, [test_cp_async_bulk_tensor_g2s_cta_im2col_4d_param_5];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r4, [test_cp_async_bulk_tensor_g2s_cta_im2col_4d_param_6];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs1, [test_cp_async_bulk_tensor_g2s_cta_im2col_4d_param_7];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs2, [test_cp_async_bulk_tensor_g2s_cta_im2col_4d_param_8];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd4, [test_cp_async_bulk_tensor_g2s_cta_im2col_4d_param_9];
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.4d.shared::cta.global.im2col.mbarrier::complete_tx::bytes.L2::cache_hint [%rd1], [%rd3, {%r1, %r2, %r3, %r4}], [%rd2], {%rs1, %rs2}, %rd4;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.4d.shared::cta.global.im2col.mbarrier::complete_tx::bytes [%rd1], [%rd3, {%r1, %r2, %r3, %r4}], [%rd2], {%rs1, %rs2};
; CHECK-PTX64-NEXT: ret;
@@ -283,16 +283,16 @@ define void @test_cp_async_bulk_tensor_g2s_cta_im2col_4d(ptr addrspace(3) %d, pt
; CHECK-PTX-SHARED32-NEXT: .reg .b64 %rd<3>;
; CHECK-PTX-SHARED32-EMPTY:
; CHECK-PTX-SHARED32-NEXT: // %bb.0:
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r1, [test_cp_async_bulk_tensor_g2s_cta_im2col_4d_param_0];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r2, [test_cp_async_bulk_tensor_g2s_cta_im2col_4d_param_1];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd1, [test_cp_async_bulk_tensor_g2s_cta_im2col_4d_param_2];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r3, [test_cp_async_bulk_tensor_g2s_cta_im2col_4d_param_3];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r4, [test_cp_async_bulk_tensor_g2s_cta_im2col_4d_param_4];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r5, [test_cp_async_bulk_tensor_g2s_cta_im2col_4d_param_5];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r6, [test_cp_async_bulk_tensor_g2s_cta_im2col_4d_param_6];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs1, [test_cp_async_bulk_tensor_g2s_cta_im2col_4d_param_7];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs2, [test_cp_async_bulk_tensor_g2s_cta_im2col_4d_param_8];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd2, [test_cp_async_bulk_tensor_g2s_cta_im2col_4d_param_9];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r1, [test_cp_async_bulk_tensor_g2s_cta_im2col_4d_param_0];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r2, [test_cp_async_bulk_tensor_g2s_cta_im2col_4d_param_1];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd1, [test_cp_async_bulk_tensor_g2s_cta_im2col_4d_param_2];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r3, [test_cp_async_bulk_tensor_g2s_cta_im2col_4d_param_3];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r4, [test_cp_async_bulk_tensor_g2s_cta_im2col_4d_param_4];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r5, [test_cp_async_bulk_tensor_g2s_cta_im2col_4d_param_5];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r6, [test_cp_async_bulk_tensor_g2s_cta_im2col_4d_param_6];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs1, [test_cp_async_bulk_tensor_g2s_cta_im2col_4d_param_7];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs2, [test_cp_async_bulk_tensor_g2s_cta_im2col_4d_param_8];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd2, [test_cp_async_bulk_tensor_g2s_cta_im2col_4d_param_9];
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.4d.shared::cta.global.im2col.mbarrier::complete_tx::bytes.L2::cache_hint [%r1], [%rd1, {%r3, %r4, %r5, %r6}], [%r2], {%rs1, %rs2}, %rd2;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.4d.shared::cta.global.im2col.mbarrier::complete_tx::bytes [%r1], [%rd1, {%r3, %r4, %r5, %r6}], [%r2], {%rs1, %rs2};
; CHECK-PTX-SHARED32-NEXT: ret;
@@ -309,18 +309,18 @@ define void @test_cp_async_bulk_tensor_g2s_cta_im2col_5d(ptr addrspace(3) %d, pt
; CHECK-PTX64-NEXT: .reg .b64 %rd<5>;
; CHECK-PTX64-EMPTY:
; CHECK-PTX64-NEXT: // %bb.0:
-; CHECK-PTX64-NEXT: ld.param.b64 %rd1, [test_cp_async_bulk_tensor_g2s_cta_im2col_5d_param_0];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd2, [test_cp_async_bulk_tensor_g2s_cta_im2col_5d_param_1];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd3, [test_cp_async_bulk_tensor_g2s_cta_im2col_5d_param_2];
-; CHECK-PTX64-NEXT: ld.param.b32 %r1, [test_cp_async_bulk_tensor_g2s_cta_im2col_5d_param_3];
-; CHECK-PTX64-NEXT: ld.param.b32 %r2, [test_cp_async_bulk_tensor_g2s_cta_im2col_5d_param_4];
-; CHECK-PTX64-NEXT: ld.param.b32 %r3, [test_cp_async_bulk_tensor_g2s_cta_im2col_5d_param_5];
-; CHECK-PTX64-NEXT: ld.param.b32 %r4, [test_cp_async_bulk_tensor_g2s_cta_im2col_5d_param_6];
-; CHECK-PTX64-NEXT: ld.param.b32 %r5, [test_cp_async_bulk_tensor_g2s_cta_im2col_5d_param_7];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs1, [test_cp_async_bulk_tensor_g2s_cta_im2col_5d_param_8];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs2, [test_cp_async_bulk_tensor_g2s_cta_im2col_5d_param_9];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs3, [test_cp_async_bulk_tensor_g2s_cta_im2col_5d_param_10];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd4, [test_cp_async_bulk_tensor_g2s_cta_im2col_5d_param_11];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd1, [test_cp_async_bulk_tensor_g2s_cta_im2col_5d_param_0];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd2, [test_cp_async_bulk_tensor_g2s_cta_im2col_5d_param_1];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd3, [test_cp_async_bulk_tensor_g2s_cta_im2col_5d_param_2];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r1, [test_cp_async_bulk_tensor_g2s_cta_im2col_5d_param_3];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r2, [test_cp_async_bulk_tensor_g2s_cta_im2col_5d_param_4];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r3, [test_cp_async_bulk_tensor_g2s_cta_im2col_5d_param_5];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r4, [test_cp_async_bulk_tensor_g2s_cta_im2col_5d_param_6];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r5, [test_cp_async_bulk_tensor_g2s_cta_im2col_5d_param_7];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs1, [test_cp_async_bulk_tensor_g2s_cta_im2col_5d_param_8];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs2, [test_cp_async_bulk_tensor_g2s_cta_im2col_5d_param_9];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs3, [test_cp_async_bulk_tensor_g2s_cta_im2col_5d_param_10];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd4, [test_cp_async_bulk_tensor_g2s_cta_im2col_5d_param_11];
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.5d.shared::cta.global.im2col.mbarrier::complete_tx::bytes.L2::cache_hint [%rd1], [%rd3, {%r1, %r2, %r3, %r4, %r5}], [%rd2], {%rs1, %rs2, %rs3}, %rd4;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.5d.shared::cta.global.im2col.mbarrier::complete_tx::bytes [%rd1], [%rd3, {%r1, %r2, %r3, %r4, %r5}], [%rd2], {%rs1, %rs2, %rs3};
; CHECK-PTX64-NEXT: ret;
@@ -332,18 +332,18 @@ define void @test_cp_async_bulk_tensor_g2s_cta_im2col_5d(ptr addrspace(3) %d, pt
; CHECK-PTX-SHARED32-NEXT: .reg .b64 %rd<3>;
; CHECK-PTX-SHARED32-EMPTY:
; CHECK-PTX-SHARED32-NEXT: // %bb.0:
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r1, [test_cp_async_bulk_tensor_g2s_cta_im2col_5d_param_0];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r2, [test_cp_async_bulk_tensor_g2s_cta_im2col_5d_param_1];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd1, [test_cp_async_bulk_tensor_g2s_cta_im2col_5d_param_2];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r3, [test_cp_async_bulk_tensor_g2s_cta_im2col_5d_param_3];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r4, [test_cp_async_bulk_tensor_g2s_cta_im2col_5d_param_4];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r5, [test_cp_async_bulk_tensor_g2s_cta_im2col_5d_param_5];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r6, [test_cp_async_bulk_tensor_g2s_cta_im2col_5d_param_6];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r7, [test_cp_async_bulk_tensor_g2s_cta_im2col_5d_param_7];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs1, [test_cp_async_bulk_tensor_g2s_cta_im2col_5d_param_8];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs2, [test_cp_async_bulk_tensor_g2s_cta_im2col_5d_param_9];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs3, [test_cp_async_bulk_tensor_g2s_cta_im2col_5d_param_10];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd2, [test_cp_async_bulk_tensor_g2s_cta_im2col_5d_param_11];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r1, [test_cp_async_bulk_tensor_g2s_cta_im2col_5d_param_0];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r2, [test_cp_async_bulk_tensor_g2s_cta_im2col_5d_param_1];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd1, [test_cp_async_bulk_tensor_g2s_cta_im2col_5d_param_2];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r3, [test_cp_async_bulk_tensor_g2s_cta_im2col_5d_param_3];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r4, [test_cp_async_bulk_tensor_g2s_cta_im2col_5d_param_4];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r5, [test_cp_async_bulk_tensor_g2s_cta_im2col_5d_param_5];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r6, [test_cp_async_bulk_tensor_g2s_cta_im2col_5d_param_6];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r7, [test_cp_async_bulk_tensor_g2s_cta_im2col_5d_param_7];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs1, [test_cp_async_bulk_tensor_g2s_cta_im2col_5d_param_8];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs2, [test_cp_async_bulk_tensor_g2s_cta_im2col_5d_param_9];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs3, [test_cp_async_bulk_tensor_g2s_cta_im2col_5d_param_10];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd2, [test_cp_async_bulk_tensor_g2s_cta_im2col_5d_param_11];
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.5d.shared::cta.global.im2col.mbarrier::complete_tx::bytes.L2::cache_hint [%r1], [%rd1, {%r3, %r4, %r5, %r6, %r7}], [%r2], {%rs1, %rs2, %rs3}, %rd2;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.5d.shared::cta.global.im2col.mbarrier::complete_tx::bytes [%r1], [%rd1, {%r3, %r4, %r5, %r6, %r7}], [%r2], {%rs1, %rs2, %rs3};
; CHECK-PTX-SHARED32-NEXT: ret;
diff --git a/llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-gather4.ll b/llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-gather4.ll
index e06bc58aa3700..5e67e9f66d05d 100644
--- a/llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-gather4.ll
+++ b/llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-gather4.ll
@@ -21,16 +21,16 @@ define void @test_cp_async_bulk_tensor_g2s_tile_gather4_2d(ptr addrspace(7) %d,
; CHECK-PTX64-NEXT: .reg .b64 %rd<5>;
; CHECK-PTX64-EMPTY:
; CHECK-PTX64-NEXT: // %bb.0:
-; CHECK-PTX64-NEXT: ld.param.b64 %rd1, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_param_0];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd2, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_param_1];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd3, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_param_2];
-; CHECK-PTX64-NEXT: ld.param.b32 %r1, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_param_3];
-; CHECK-PTX64-NEXT: ld.param.b32 %r2, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_param_4];
-; CHECK-PTX64-NEXT: ld.param.b32 %r3, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_param_5];
-; CHECK-PTX64-NEXT: ld.param.b32 %r4, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_param_6];
-; CHECK-PTX64-NEXT: ld.param.b32 %r5, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_param_7];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs1, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_param_8];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd4, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_param_9];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd1, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_param_0];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd2, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_param_1];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd3, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_param_2];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r1, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_param_3];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r2, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_param_4];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r3, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_param_5];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r4, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_param_6];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r5, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_param_7];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs1, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_param_8];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd4, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_param_9];
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.2d.shared::cluster.global.tile::gather4.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint [%rd1], [%rd3, {%r1, %r2, %r3, %r4, %r5}], [%rd2], %rs1, %rd4;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.2d.shared::cluster.global.tile::gather4.mbarrier::complete_tx::bytes.multicast::cluster [%rd1], [%rd3, {%r1, %r2, %r3, %r4, %r5}], [%rd2], %rs1;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.2d.shared::cluster.global.tile::gather4.mbarrier::complete_tx::bytes.L2::cache_hint [%rd1], [%rd3, {%r1, %r2, %r3, %r4, %r5}], [%rd2], %rd4;
@@ -44,16 +44,16 @@ define void @test_cp_async_bulk_tensor_g2s_tile_gather4_2d(ptr addrspace(7) %d,
; CHECK-PTX-SHARED32-NEXT: .reg .b64 %rd<3>;
; CHECK-PTX-SHARED32-EMPTY:
; CHECK-PTX-SHARED32-NEXT: // %bb.0:
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r1, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_param_0];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r2, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_param_1];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd1, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_param_2];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r3, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_param_3];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r4, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_param_4];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r5, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_param_5];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r6, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_param_6];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r7, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_param_7];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs1, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_param_8];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd2, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_param_9];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r1, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_param_0];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r2, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_param_1];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd1, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_param_2];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r3, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_param_3];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r4, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_param_4];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r5, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_param_5];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r6, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_param_6];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r7, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_param_7];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs1, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_param_8];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd2, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_param_9];
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.2d.shared::cluster.global.tile::gather4.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint [%r1], [%rd1, {%r3, %r4, %r5, %r6, %r7}], [%r2], %rs1, %rd2;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.2d.shared::cluster.global.tile::gather4.mbarrier::complete_tx::bytes.multicast::cluster [%r1], [%rd1, {%r3, %r4, %r5, %r6, %r7}], [%r2], %rs1;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.2d.shared::cluster.global.tile::gather4.mbarrier::complete_tx::bytes.L2::cache_hint [%r1], [%rd1, {%r3, %r4, %r5, %r6, %r7}], [%r2], %rd2;
@@ -76,16 +76,16 @@ define void @test_cp_async_bulk_tensor_g2s_tile_gather4_2d_cg1(ptr addrspace(7)
; CHECK-PTX64-NEXT: .reg .b64 %rd<5>;
; CHECK-PTX64-EMPTY:
; CHECK-PTX64-NEXT: // %bb.0:
-; CHECK-PTX64-NEXT: ld.param.b64 %rd1, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_cg1_param_0];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd2, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_cg1_param_1];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd3, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_cg1_param_2];
-; CHECK-PTX64-NEXT: ld.param.b32 %r1, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_cg1_param_3];
-; CHECK-PTX64-NEXT: ld.param.b32 %r2, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_cg1_param_4];
-; CHECK-PTX64-NEXT: ld.param.b32 %r3, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_cg1_param_5];
-; CHECK-PTX64-NEXT: ld.param.b32 %r4, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_cg1_param_6];
-; CHECK-PTX64-NEXT: ld.param.b32 %r5, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_cg1_param_7];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs1, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_cg1_param_8];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd4, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_cg1_param_9];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd1, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_cg1_param_0];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd2, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_cg1_param_1];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd3, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_cg1_param_2];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r1, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_cg1_param_3];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r2, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_cg1_param_4];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r3, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_cg1_param_5];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r4, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_cg1_param_6];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r5, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_cg1_param_7];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs1, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_cg1_param_8];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd4, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_cg1_param_9];
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.2d.shared::cluster.global.tile::gather4.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint.cta_group::1 [%rd1], [%rd3, {%r1, %r2, %r3, %r4, %r5}], [%rd2], %rs1, %rd4;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.2d.shared::cluster.global.tile::gather4.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::1 [%rd1], [%rd3, {%r1, %r2, %r3, %r4, %r5}], [%rd2], %rs1;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.2d.shared::cluster.global.tile::gather4.mbarrier::complete_tx::bytes.L2::cache_hint.cta_group::1 [%rd1], [%rd3, {%r1, %r2, %r3, %r4, %r5}], [%rd2], %rd4;
@@ -99,16 +99,16 @@ define void @test_cp_async_bulk_tensor_g2s_tile_gather4_2d_cg1(ptr addrspace(7)
; CHECK-PTX-SHARED32-NEXT: .reg .b64 %rd<3>;
; CHECK-PTX-SHARED32-EMPTY:
; CHECK-PTX-SHARED32-NEXT: // %bb.0:
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r1, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_cg1_param_0];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r2, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_cg1_param_1];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd1, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_cg1_param_2];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r3, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_cg1_param_3];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r4, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_cg1_param_4];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r5, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_cg1_param_5];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r6, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_cg1_param_6];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r7, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_cg1_param_7];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs1, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_cg1_param_8];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd2, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_cg1_param_9];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r1, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_cg1_param_0];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r2, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_cg1_param_1];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd1, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_cg1_param_2];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r3, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_cg1_param_3];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r4, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_cg1_param_4];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r5, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_cg1_param_5];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r6, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_cg1_param_6];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r7, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_cg1_param_7];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs1, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_cg1_param_8];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd2, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_cg1_param_9];
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.2d.shared::cluster.global.tile::gather4.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint.cta_group::1 [%r1], [%rd1, {%r3, %r4, %r5, %r6, %r7}], [%r2], %rs1, %rd2;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.2d.shared::cluster.global.tile::gather4.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::1 [%r1], [%rd1, {%r3, %r4, %r5, %r6, %r7}], [%r2], %rs1;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.2d.shared::cluster.global.tile::gather4.mbarrier::complete_tx::bytes.L2::cache_hint.cta_group::1 [%r1], [%rd1, {%r3, %r4, %r5, %r6, %r7}], [%r2], %rd2;
@@ -131,16 +131,16 @@ define void @test_cp_async_bulk_tensor_g2s_tile_gather4_2d_cg2(ptr addrspace(7)
; CHECK-PTX64-NEXT: .reg .b64 %rd<5>;
; CHECK-PTX64-EMPTY:
; CHECK-PTX64-NEXT: // %bb.0:
-; CHECK-PTX64-NEXT: ld.param.b64 %rd1, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_cg2_param_0];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd2, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_cg2_param_1];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd3, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_cg2_param_2];
-; CHECK-PTX64-NEXT: ld.param.b32 %r1, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_cg2_param_3];
-; CHECK-PTX64-NEXT: ld.param.b32 %r2, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_cg2_param_4];
-; CHECK-PTX64-NEXT: ld.param.b32 %r3, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_cg2_param_5];
-; CHECK-PTX64-NEXT: ld.param.b32 %r4, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_cg2_param_6];
-; CHECK-PTX64-NEXT: ld.param.b32 %r5, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_cg2_param_7];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs1, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_cg2_param_8];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd4, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_cg2_param_9];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd1, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_cg2_param_0];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd2, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_cg2_param_1];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd3, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_cg2_param_2];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r1, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_cg2_param_3];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r2, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_cg2_param_4];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r3, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_cg2_param_5];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r4, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_cg2_param_6];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r5, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_cg2_param_7];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs1, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_cg2_param_8];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd4, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_cg2_param_9];
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.2d.shared::cluster.global.tile::gather4.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint.cta_group::2 [%rd1], [%rd3, {%r1, %r2, %r3, %r4, %r5}], [%rd2], %rs1, %rd4;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.2d.shared::cluster.global.tile::gather4.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::2 [%rd1], [%rd3, {%r1, %r2, %r3, %r4, %r5}], [%rd2], %rs1;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.2d.shared::cluster.global.tile::gather4.mbarrier::complete_tx::bytes.L2::cache_hint.cta_group::2 [%rd1], [%rd3, {%r1, %r2, %r3, %r4, %r5}], [%rd2], %rd4;
@@ -154,16 +154,16 @@ define void @test_cp_async_bulk_tensor_g2s_tile_gather4_2d_cg2(ptr addrspace(7)
; CHECK-PTX-SHARED32-NEXT: .reg .b64 %rd<3>;
; CHECK-PTX-SHARED32-EMPTY:
; CHECK-PTX-SHARED32-NEXT: // %bb.0:
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r1, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_cg2_param_0];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r2, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_cg2_param_1];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd1, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_cg2_param_2];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r3, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_cg2_param_3];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r4, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_cg2_param_4];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r5, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_cg2_param_5];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r6, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_cg2_param_6];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r7, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_cg2_param_7];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs1, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_cg2_param_8];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd2, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_cg2_param_9];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r1, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_cg2_param_0];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r2, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_cg2_param_1];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd1, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_cg2_param_2];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r3, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_cg2_param_3];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r4, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_cg2_param_4];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r5, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_cg2_param_5];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r6, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_cg2_param_6];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r7, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_cg2_param_7];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs1, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_cg2_param_8];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd2, [test_cp_async_bulk_tensor_g2s_tile_gather4_2d_cg2_param_9];
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.2d.shared::cluster.global.tile::gather4.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint.cta_group::2 [%r1], [%rd1, {%r3, %r4, %r5, %r6, %r7}], [%r2], %rs1, %rd2;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.2d.shared::cluster.global.tile::gather4.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::2 [%r1], [%rd1, {%r3, %r4, %r5, %r6, %r7}], [%r2], %rs1;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.2d.shared::cluster.global.tile::gather4.mbarrier::complete_tx::bytes.L2::cache_hint.cta_group::2 [%r1], [%rd1, {%r3, %r4, %r5, %r6, %r7}], [%r2], %rd2;
diff --git a/llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-im2colw.ll b/llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-im2colw.ll
index d267028560b5a..7018f7f6fd399 100644
--- a/llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-im2colw.ll
+++ b/llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-im2colw.ll
@@ -23,16 +23,16 @@ define void @cp_async_bulk_tensor_g2s_im2colw_3d(ptr addrspace(7) %d, ptr addrsp
; CHECK-PTX64-NEXT: .reg .b64 %rd<5>;
; CHECK-PTX64-EMPTY:
; CHECK-PTX64-NEXT: // %bb.0:
-; CHECK-PTX64-NEXT: ld.param.b64 %rd1, [cp_async_bulk_tensor_g2s_im2colw_3d_param_0];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd2, [cp_async_bulk_tensor_g2s_im2colw_3d_param_1];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd3, [cp_async_bulk_tensor_g2s_im2colw_3d_param_2];
-; CHECK-PTX64-NEXT: ld.param.b32 %r1, [cp_async_bulk_tensor_g2s_im2colw_3d_param_3];
-; CHECK-PTX64-NEXT: ld.param.b32 %r2, [cp_async_bulk_tensor_g2s_im2colw_3d_param_4];
-; CHECK-PTX64-NEXT: ld.param.b32 %r3, [cp_async_bulk_tensor_g2s_im2colw_3d_param_5];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs1, [cp_async_bulk_tensor_g2s_im2colw_3d_param_6];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs2, [cp_async_bulk_tensor_g2s_im2colw_3d_param_7];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs3, [cp_async_bulk_tensor_g2s_im2colw_3d_param_8];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd4, [cp_async_bulk_tensor_g2s_im2colw_3d_param_9];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd1, [cp_async_bulk_tensor_g2s_im2colw_3d_param_0];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd2, [cp_async_bulk_tensor_g2s_im2colw_3d_param_1];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd3, [cp_async_bulk_tensor_g2s_im2colw_3d_param_2];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r1, [cp_async_bulk_tensor_g2s_im2colw_3d_param_3];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r2, [cp_async_bulk_tensor_g2s_im2colw_3d_param_4];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r3, [cp_async_bulk_tensor_g2s_im2colw_3d_param_5];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs1, [cp_async_bulk_tensor_g2s_im2colw_3d_param_6];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs2, [cp_async_bulk_tensor_g2s_im2colw_3d_param_7];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs3, [cp_async_bulk_tensor_g2s_im2colw_3d_param_8];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd4, [cp_async_bulk_tensor_g2s_im2colw_3d_param_9];
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.3d.shared::cluster.global.im2col::w.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint [%rd1], [%rd3, {%r1, %r2, %r3}], [%rd2], {%rs1, %rs2}, %rs3, %rd4;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.3d.shared::cluster.global.im2col::w.mbarrier::complete_tx::bytes.multicast::cluster [%rd1], [%rd3, {%r1, %r2, %r3}], [%rd2], {%rs1, %rs2}, %rs3;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.3d.shared::cluster.global.im2col::w.mbarrier::complete_tx::bytes.L2::cache_hint [%rd1], [%rd3, {%r1, %r2, %r3}], [%rd2], {%rs1, %rs2}, %rd4;
@@ -46,16 +46,16 @@ define void @cp_async_bulk_tensor_g2s_im2colw_3d(ptr addrspace(7) %d, ptr addrsp
; CHECK-PTX-SHARED32-NEXT: .reg .b64 %rd<3>;
; CHECK-PTX-SHARED32-EMPTY:
; CHECK-PTX-SHARED32-NEXT: // %bb.0:
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r1, [cp_async_bulk_tensor_g2s_im2colw_3d_param_0];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r2, [cp_async_bulk_tensor_g2s_im2colw_3d_param_1];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd1, [cp_async_bulk_tensor_g2s_im2colw_3d_param_2];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r3, [cp_async_bulk_tensor_g2s_im2colw_3d_param_3];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r4, [cp_async_bulk_tensor_g2s_im2colw_3d_param_4];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r5, [cp_async_bulk_tensor_g2s_im2colw_3d_param_5];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs1, [cp_async_bulk_tensor_g2s_im2colw_3d_param_6];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs2, [cp_async_bulk_tensor_g2s_im2colw_3d_param_7];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs3, [cp_async_bulk_tensor_g2s_im2colw_3d_param_8];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd2, [cp_async_bulk_tensor_g2s_im2colw_3d_param_9];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r1, [cp_async_bulk_tensor_g2s_im2colw_3d_param_0];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r2, [cp_async_bulk_tensor_g2s_im2colw_3d_param_1];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd1, [cp_async_bulk_tensor_g2s_im2colw_3d_param_2];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r3, [cp_async_bulk_tensor_g2s_im2colw_3d_param_3];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r4, [cp_async_bulk_tensor_g2s_im2colw_3d_param_4];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r5, [cp_async_bulk_tensor_g2s_im2colw_3d_param_5];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs1, [cp_async_bulk_tensor_g2s_im2colw_3d_param_6];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs2, [cp_async_bulk_tensor_g2s_im2colw_3d_param_7];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs3, [cp_async_bulk_tensor_g2s_im2colw_3d_param_8];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd2, [cp_async_bulk_tensor_g2s_im2colw_3d_param_9];
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.3d.shared::cluster.global.im2col::w.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint [%r1], [%rd1, {%r3, %r4, %r5}], [%r2], {%rs1, %rs2}, %rs3, %rd2;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.3d.shared::cluster.global.im2col::w.mbarrier::complete_tx::bytes.multicast::cluster [%r1], [%rd1, {%r3, %r4, %r5}], [%r2], {%rs1, %rs2}, %rs3;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.3d.shared::cluster.global.im2col::w.mbarrier::complete_tx::bytes.L2::cache_hint [%r1], [%rd1, {%r3, %r4, %r5}], [%r2], {%rs1, %rs2}, %rd2;
@@ -78,16 +78,16 @@ define void @cp_async_bulk_tensor_g2s_im2colw_3d_cg1(ptr addrspace(7) %d, ptr ad
; CHECK-PTX64-NEXT: .reg .b64 %rd<5>;
; CHECK-PTX64-EMPTY:
; CHECK-PTX64-NEXT: // %bb.0:
-; CHECK-PTX64-NEXT: ld.param.b64 %rd1, [cp_async_bulk_tensor_g2s_im2colw_3d_cg1_param_0];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd2, [cp_async_bulk_tensor_g2s_im2colw_3d_cg1_param_1];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd3, [cp_async_bulk_tensor_g2s_im2colw_3d_cg1_param_2];
-; CHECK-PTX64-NEXT: ld.param.b32 %r1, [cp_async_bulk_tensor_g2s_im2colw_3d_cg1_param_3];
-; CHECK-PTX64-NEXT: ld.param.b32 %r2, [cp_async_bulk_tensor_g2s_im2colw_3d_cg1_param_4];
-; CHECK-PTX64-NEXT: ld.param.b32 %r3, [cp_async_bulk_tensor_g2s_im2colw_3d_cg1_param_5];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs1, [cp_async_bulk_tensor_g2s_im2colw_3d_cg1_param_6];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs2, [cp_async_bulk_tensor_g2s_im2colw_3d_cg1_param_7];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs3, [cp_async_bulk_tensor_g2s_im2colw_3d_cg1_param_8];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd4, [cp_async_bulk_tensor_g2s_im2colw_3d_cg1_param_9];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd1, [cp_async_bulk_tensor_g2s_im2colw_3d_cg1_param_0];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd2, [cp_async_bulk_tensor_g2s_im2colw_3d_cg1_param_1];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd3, [cp_async_bulk_tensor_g2s_im2colw_3d_cg1_param_2];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r1, [cp_async_bulk_tensor_g2s_im2colw_3d_cg1_param_3];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r2, [cp_async_bulk_tensor_g2s_im2colw_3d_cg1_param_4];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r3, [cp_async_bulk_tensor_g2s_im2colw_3d_cg1_param_5];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs1, [cp_async_bulk_tensor_g2s_im2colw_3d_cg1_param_6];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs2, [cp_async_bulk_tensor_g2s_im2colw_3d_cg1_param_7];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs3, [cp_async_bulk_tensor_g2s_im2colw_3d_cg1_param_8];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd4, [cp_async_bulk_tensor_g2s_im2colw_3d_cg1_param_9];
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.3d.shared::cluster.global.im2col::w.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint.cta_group::1 [%rd1], [%rd3, {%r1, %r2, %r3}], [%rd2], {%rs1, %rs2}, %rs3, %rd4;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.3d.shared::cluster.global.im2col::w.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::1 [%rd1], [%rd3, {%r1, %r2, %r3}], [%rd2], {%rs1, %rs2}, %rs3;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.3d.shared::cluster.global.im2col::w.mbarrier::complete_tx::bytes.L2::cache_hint.cta_group::1 [%rd1], [%rd3, {%r1, %r2, %r3}], [%rd2], {%rs1, %rs2}, %rd4;
@@ -101,16 +101,16 @@ define void @cp_async_bulk_tensor_g2s_im2colw_3d_cg1(ptr addrspace(7) %d, ptr ad
; CHECK-PTX-SHARED32-NEXT: .reg .b64 %rd<3>;
; CHECK-PTX-SHARED32-EMPTY:
; CHECK-PTX-SHARED32-NEXT: // %bb.0:
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r1, [cp_async_bulk_tensor_g2s_im2colw_3d_cg1_param_0];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r2, [cp_async_bulk_tensor_g2s_im2colw_3d_cg1_param_1];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd1, [cp_async_bulk_tensor_g2s_im2colw_3d_cg1_param_2];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r3, [cp_async_bulk_tensor_g2s_im2colw_3d_cg1_param_3];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r4, [cp_async_bulk_tensor_g2s_im2colw_3d_cg1_param_4];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r5, [cp_async_bulk_tensor_g2s_im2colw_3d_cg1_param_5];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs1, [cp_async_bulk_tensor_g2s_im2colw_3d_cg1_param_6];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs2, [cp_async_bulk_tensor_g2s_im2colw_3d_cg1_param_7];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs3, [cp_async_bulk_tensor_g2s_im2colw_3d_cg1_param_8];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd2, [cp_async_bulk_tensor_g2s_im2colw_3d_cg1_param_9];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r1, [cp_async_bulk_tensor_g2s_im2colw_3d_cg1_param_0];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r2, [cp_async_bulk_tensor_g2s_im2colw_3d_cg1_param_1];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd1, [cp_async_bulk_tensor_g2s_im2colw_3d_cg1_param_2];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r3, [cp_async_bulk_tensor_g2s_im2colw_3d_cg1_param_3];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r4, [cp_async_bulk_tensor_g2s_im2colw_3d_cg1_param_4];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r5, [cp_async_bulk_tensor_g2s_im2colw_3d_cg1_param_5];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs1, [cp_async_bulk_tensor_g2s_im2colw_3d_cg1_param_6];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs2, [cp_async_bulk_tensor_g2s_im2colw_3d_cg1_param_7];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs3, [cp_async_bulk_tensor_g2s_im2colw_3d_cg1_param_8];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd2, [cp_async_bulk_tensor_g2s_im2colw_3d_cg1_param_9];
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.3d.shared::cluster.global.im2col::w.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint.cta_group::1 [%r1], [%rd1, {%r3, %r4, %r5}], [%r2], {%rs1, %rs2}, %rs3, %rd2;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.3d.shared::cluster.global.im2col::w.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::1 [%r1], [%rd1, {%r3, %r4, %r5}], [%r2], {%rs1, %rs2}, %rs3;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.3d.shared::cluster.global.im2col::w.mbarrier::complete_tx::bytes.L2::cache_hint.cta_group::1 [%r1], [%rd1, {%r3, %r4, %r5}], [%r2], {%rs1, %rs2}, %rd2;
@@ -133,16 +133,16 @@ define void @cp_async_bulk_tensor_g2s_im2colw_3d_cg2(ptr addrspace(7) %d, ptr ad
; CHECK-PTX64-NEXT: .reg .b64 %rd<5>;
; CHECK-PTX64-EMPTY:
; CHECK-PTX64-NEXT: // %bb.0:
-; CHECK-PTX64-NEXT: ld.param.b64 %rd1, [cp_async_bulk_tensor_g2s_im2colw_3d_cg2_param_0];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd2, [cp_async_bulk_tensor_g2s_im2colw_3d_cg2_param_1];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd3, [cp_async_bulk_tensor_g2s_im2colw_3d_cg2_param_2];
-; CHECK-PTX64-NEXT: ld.param.b32 %r1, [cp_async_bulk_tensor_g2s_im2colw_3d_cg2_param_3];
-; CHECK-PTX64-NEXT: ld.param.b32 %r2, [cp_async_bulk_tensor_g2s_im2colw_3d_cg2_param_4];
-; CHECK-PTX64-NEXT: ld.param.b32 %r3, [cp_async_bulk_tensor_g2s_im2colw_3d_cg2_param_5];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs1, [cp_async_bulk_tensor_g2s_im2colw_3d_cg2_param_6];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs2, [cp_async_bulk_tensor_g2s_im2colw_3d_cg2_param_7];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs3, [cp_async_bulk_tensor_g2s_im2colw_3d_cg2_param_8];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd4, [cp_async_bulk_tensor_g2s_im2colw_3d_cg2_param_9];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd1, [cp_async_bulk_tensor_g2s_im2colw_3d_cg2_param_0];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd2, [cp_async_bulk_tensor_g2s_im2colw_3d_cg2_param_1];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd3, [cp_async_bulk_tensor_g2s_im2colw_3d_cg2_param_2];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r1, [cp_async_bulk_tensor_g2s_im2colw_3d_cg2_param_3];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r2, [cp_async_bulk_tensor_g2s_im2colw_3d_cg2_param_4];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r3, [cp_async_bulk_tensor_g2s_im2colw_3d_cg2_param_5];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs1, [cp_async_bulk_tensor_g2s_im2colw_3d_cg2_param_6];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs2, [cp_async_bulk_tensor_g2s_im2colw_3d_cg2_param_7];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs3, [cp_async_bulk_tensor_g2s_im2colw_3d_cg2_param_8];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd4, [cp_async_bulk_tensor_g2s_im2colw_3d_cg2_param_9];
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.3d.shared::cluster.global.im2col::w.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint.cta_group::2 [%rd1], [%rd3, {%r1, %r2, %r3}], [%rd2], {%rs1, %rs2}, %rs3, %rd4;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.3d.shared::cluster.global.im2col::w.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::2 [%rd1], [%rd3, {%r1, %r2, %r3}], [%rd2], {%rs1, %rs2}, %rs3;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.3d.shared::cluster.global.im2col::w.mbarrier::complete_tx::bytes.L2::cache_hint.cta_group::2 [%rd1], [%rd3, {%r1, %r2, %r3}], [%rd2], {%rs1, %rs2}, %rd4;
@@ -156,16 +156,16 @@ define void @cp_async_bulk_tensor_g2s_im2colw_3d_cg2(ptr addrspace(7) %d, ptr ad
; CHECK-PTX-SHARED32-NEXT: .reg .b64 %rd<3>;
; CHECK-PTX-SHARED32-EMPTY:
; CHECK-PTX-SHARED32-NEXT: // %bb.0:
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r1, [cp_async_bulk_tensor_g2s_im2colw_3d_cg2_param_0];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r2, [cp_async_bulk_tensor_g2s_im2colw_3d_cg2_param_1];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd1, [cp_async_bulk_tensor_g2s_im2colw_3d_cg2_param_2];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r3, [cp_async_bulk_tensor_g2s_im2colw_3d_cg2_param_3];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r4, [cp_async_bulk_tensor_g2s_im2colw_3d_cg2_param_4];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r5, [cp_async_bulk_tensor_g2s_im2colw_3d_cg2_param_5];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs1, [cp_async_bulk_tensor_g2s_im2colw_3d_cg2_param_6];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs2, [cp_async_bulk_tensor_g2s_im2colw_3d_cg2_param_7];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs3, [cp_async_bulk_tensor_g2s_im2colw_3d_cg2_param_8];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd2, [cp_async_bulk_tensor_g2s_im2colw_3d_cg2_param_9];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r1, [cp_async_bulk_tensor_g2s_im2colw_3d_cg2_param_0];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r2, [cp_async_bulk_tensor_g2s_im2colw_3d_cg2_param_1];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd1, [cp_async_bulk_tensor_g2s_im2colw_3d_cg2_param_2];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r3, [cp_async_bulk_tensor_g2s_im2colw_3d_cg2_param_3];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r4, [cp_async_bulk_tensor_g2s_im2colw_3d_cg2_param_4];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r5, [cp_async_bulk_tensor_g2s_im2colw_3d_cg2_param_5];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs1, [cp_async_bulk_tensor_g2s_im2colw_3d_cg2_param_6];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs2, [cp_async_bulk_tensor_g2s_im2colw_3d_cg2_param_7];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs3, [cp_async_bulk_tensor_g2s_im2colw_3d_cg2_param_8];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd2, [cp_async_bulk_tensor_g2s_im2colw_3d_cg2_param_9];
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.3d.shared::cluster.global.im2col::w.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint.cta_group::2 [%r1], [%rd1, {%r3, %r4, %r5}], [%r2], {%rs1, %rs2}, %rs3, %rd2;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.3d.shared::cluster.global.im2col::w.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::2 [%r1], [%rd1, {%r3, %r4, %r5}], [%r2], {%rs1, %rs2}, %rs3;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.3d.shared::cluster.global.im2col::w.mbarrier::complete_tx::bytes.L2::cache_hint.cta_group::2 [%r1], [%rd1, {%r3, %r4, %r5}], [%r2], {%rs1, %rs2}, %rd2;
@@ -188,17 +188,17 @@ define void @cp_async_bulk_tensor_g2s_im2colw_4d(ptr addrspace(7) %d, ptr addrsp
; CHECK-PTX64-NEXT: .reg .b64 %rd<5>;
; CHECK-PTX64-EMPTY:
; CHECK-PTX64-NEXT: // %bb.0:
-; CHECK-PTX64-NEXT: ld.param.b64 %rd1, [cp_async_bulk_tensor_g2s_im2colw_4d_param_0];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd2, [cp_async_bulk_tensor_g2s_im2colw_4d_param_1];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd3, [cp_async_bulk_tensor_g2s_im2colw_4d_param_2];
-; CHECK-PTX64-NEXT: ld.param.b32 %r1, [cp_async_bulk_tensor_g2s_im2colw_4d_param_3];
-; CHECK-PTX64-NEXT: ld.param.b32 %r2, [cp_async_bulk_tensor_g2s_im2colw_4d_param_4];
-; CHECK-PTX64-NEXT: ld.param.b32 %r3, [cp_async_bulk_tensor_g2s_im2colw_4d_param_5];
-; CHECK-PTX64-NEXT: ld.param.b32 %r4, [cp_async_bulk_tensor_g2s_im2colw_4d_param_6];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs1, [cp_async_bulk_tensor_g2s_im2colw_4d_param_7];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs2, [cp_async_bulk_tensor_g2s_im2colw_4d_param_8];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs3, [cp_async_bulk_tensor_g2s_im2colw_4d_param_9];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd4, [cp_async_bulk_tensor_g2s_im2colw_4d_param_10];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd1, [cp_async_bulk_tensor_g2s_im2colw_4d_param_0];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd2, [cp_async_bulk_tensor_g2s_im2colw_4d_param_1];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd3, [cp_async_bulk_tensor_g2s_im2colw_4d_param_2];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r1, [cp_async_bulk_tensor_g2s_im2colw_4d_param_3];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r2, [cp_async_bulk_tensor_g2s_im2colw_4d_param_4];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r3, [cp_async_bulk_tensor_g2s_im2colw_4d_param_5];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r4, [cp_async_bulk_tensor_g2s_im2colw_4d_param_6];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs1, [cp_async_bulk_tensor_g2s_im2colw_4d_param_7];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs2, [cp_async_bulk_tensor_g2s_im2colw_4d_param_8];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs3, [cp_async_bulk_tensor_g2s_im2colw_4d_param_9];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd4, [cp_async_bulk_tensor_g2s_im2colw_4d_param_10];
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.4d.shared::cluster.global.im2col::w.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint [%rd1], [%rd3, {%r1, %r2, %r3, %r4}], [%rd2], {%rs1, %rs2}, %rs3, %rd4;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.4d.shared::cluster.global.im2col::w.mbarrier::complete_tx::bytes.multicast::cluster [%rd1], [%rd3, {%r1, %r2, %r3, %r4}], [%rd2], {%rs1, %rs2}, %rs3;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.4d.shared::cluster.global.im2col::w.mbarrier::complete_tx::bytes.L2::cache_hint [%rd1], [%rd3, {%r1, %r2, %r3, %r4}], [%rd2], {%rs1, %rs2}, %rd4;
@@ -212,17 +212,17 @@ define void @cp_async_bulk_tensor_g2s_im2colw_4d(ptr addrspace(7) %d, ptr addrsp
; CHECK-PTX-SHARED32-NEXT: .reg .b64 %rd<3>;
; CHECK-PTX-SHARED32-EMPTY:
; CHECK-PTX-SHARED32-NEXT: // %bb.0:
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r1, [cp_async_bulk_tensor_g2s_im2colw_4d_param_0];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r2, [cp_async_bulk_tensor_g2s_im2colw_4d_param_1];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd1, [cp_async_bulk_tensor_g2s_im2colw_4d_param_2];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r3, [cp_async_bulk_tensor_g2s_im2colw_4d_param_3];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r4, [cp_async_bulk_tensor_g2s_im2colw_4d_param_4];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r5, [cp_async_bulk_tensor_g2s_im2colw_4d_param_5];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r6, [cp_async_bulk_tensor_g2s_im2colw_4d_param_6];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs1, [cp_async_bulk_tensor_g2s_im2colw_4d_param_7];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs2, [cp_async_bulk_tensor_g2s_im2colw_4d_param_8];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs3, [cp_async_bulk_tensor_g2s_im2colw_4d_param_9];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd2, [cp_async_bulk_tensor_g2s_im2colw_4d_param_10];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r1, [cp_async_bulk_tensor_g2s_im2colw_4d_param_0];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r2, [cp_async_bulk_tensor_g2s_im2colw_4d_param_1];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd1, [cp_async_bulk_tensor_g2s_im2colw_4d_param_2];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r3, [cp_async_bulk_tensor_g2s_im2colw_4d_param_3];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r4, [cp_async_bulk_tensor_g2s_im2colw_4d_param_4];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r5, [cp_async_bulk_tensor_g2s_im2colw_4d_param_5];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r6, [cp_async_bulk_tensor_g2s_im2colw_4d_param_6];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs1, [cp_async_bulk_tensor_g2s_im2colw_4d_param_7];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs2, [cp_async_bulk_tensor_g2s_im2colw_4d_param_8];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs3, [cp_async_bulk_tensor_g2s_im2colw_4d_param_9];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd2, [cp_async_bulk_tensor_g2s_im2colw_4d_param_10];
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.4d.shared::cluster.global.im2col::w.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint [%r1], [%rd1, {%r3, %r4, %r5, %r6}], [%r2], {%rs1, %rs2}, %rs3, %rd2;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.4d.shared::cluster.global.im2col::w.mbarrier::complete_tx::bytes.multicast::cluster [%r1], [%rd1, {%r3, %r4, %r5, %r6}], [%r2], {%rs1, %rs2}, %rs3;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.4d.shared::cluster.global.im2col::w.mbarrier::complete_tx::bytes.L2::cache_hint [%r1], [%rd1, {%r3, %r4, %r5, %r6}], [%r2], {%rs1, %rs2}, %rd2;
@@ -245,17 +245,17 @@ define void @cp_async_bulk_tensor_g2s_im2colw_4d_cg1(ptr addrspace(7) %d, ptr ad
; CHECK-PTX64-NEXT: .reg .b64 %rd<5>;
; CHECK-PTX64-EMPTY:
; CHECK-PTX64-NEXT: // %bb.0:
-; CHECK-PTX64-NEXT: ld.param.b64 %rd1, [cp_async_bulk_tensor_g2s_im2colw_4d_cg1_param_0];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd2, [cp_async_bulk_tensor_g2s_im2colw_4d_cg1_param_1];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd3, [cp_async_bulk_tensor_g2s_im2colw_4d_cg1_param_2];
-; CHECK-PTX64-NEXT: ld.param.b32 %r1, [cp_async_bulk_tensor_g2s_im2colw_4d_cg1_param_3];
-; CHECK-PTX64-NEXT: ld.param.b32 %r2, [cp_async_bulk_tensor_g2s_im2colw_4d_cg1_param_4];
-; CHECK-PTX64-NEXT: ld.param.b32 %r3, [cp_async_bulk_tensor_g2s_im2colw_4d_cg1_param_5];
-; CHECK-PTX64-NEXT: ld.param.b32 %r4, [cp_async_bulk_tensor_g2s_im2colw_4d_cg1_param_6];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs1, [cp_async_bulk_tensor_g2s_im2colw_4d_cg1_param_7];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs2, [cp_async_bulk_tensor_g2s_im2colw_4d_cg1_param_8];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs3, [cp_async_bulk_tensor_g2s_im2colw_4d_cg1_param_9];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd4, [cp_async_bulk_tensor_g2s_im2colw_4d_cg1_param_10];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd1, [cp_async_bulk_tensor_g2s_im2colw_4d_cg1_param_0];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd2, [cp_async_bulk_tensor_g2s_im2colw_4d_cg1_param_1];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd3, [cp_async_bulk_tensor_g2s_im2colw_4d_cg1_param_2];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r1, [cp_async_bulk_tensor_g2s_im2colw_4d_cg1_param_3];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r2, [cp_async_bulk_tensor_g2s_im2colw_4d_cg1_param_4];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r3, [cp_async_bulk_tensor_g2s_im2colw_4d_cg1_param_5];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r4, [cp_async_bulk_tensor_g2s_im2colw_4d_cg1_param_6];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs1, [cp_async_bulk_tensor_g2s_im2colw_4d_cg1_param_7];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs2, [cp_async_bulk_tensor_g2s_im2colw_4d_cg1_param_8];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs3, [cp_async_bulk_tensor_g2s_im2colw_4d_cg1_param_9];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd4, [cp_async_bulk_tensor_g2s_im2colw_4d_cg1_param_10];
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.4d.shared::cluster.global.im2col::w.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint.cta_group::1 [%rd1], [%rd3, {%r1, %r2, %r3, %r4}], [%rd2], {%rs1, %rs2}, %rs3, %rd4;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.4d.shared::cluster.global.im2col::w.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::1 [%rd1], [%rd3, {%r1, %r2, %r3, %r4}], [%rd2], {%rs1, %rs2}, %rs3;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.4d.shared::cluster.global.im2col::w.mbarrier::complete_tx::bytes.L2::cache_hint.cta_group::1 [%rd1], [%rd3, {%r1, %r2, %r3, %r4}], [%rd2], {%rs1, %rs2}, %rd4;
@@ -269,17 +269,17 @@ define void @cp_async_bulk_tensor_g2s_im2colw_4d_cg1(ptr addrspace(7) %d, ptr ad
; CHECK-PTX-SHARED32-NEXT: .reg .b64 %rd<3>;
; CHECK-PTX-SHARED32-EMPTY:
; CHECK-PTX-SHARED32-NEXT: // %bb.0:
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r1, [cp_async_bulk_tensor_g2s_im2colw_4d_cg1_param_0];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r2, [cp_async_bulk_tensor_g2s_im2colw_4d_cg1_param_1];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd1, [cp_async_bulk_tensor_g2s_im2colw_4d_cg1_param_2];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r3, [cp_async_bulk_tensor_g2s_im2colw_4d_cg1_param_3];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r4, [cp_async_bulk_tensor_g2s_im2colw_4d_cg1_param_4];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r5, [cp_async_bulk_tensor_g2s_im2colw_4d_cg1_param_5];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r6, [cp_async_bulk_tensor_g2s_im2colw_4d_cg1_param_6];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs1, [cp_async_bulk_tensor_g2s_im2colw_4d_cg1_param_7];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs2, [cp_async_bulk_tensor_g2s_im2colw_4d_cg1_param_8];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs3, [cp_async_bulk_tensor_g2s_im2colw_4d_cg1_param_9];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd2, [cp_async_bulk_tensor_g2s_im2colw_4d_cg1_param_10];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r1, [cp_async_bulk_tensor_g2s_im2colw_4d_cg1_param_0];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r2, [cp_async_bulk_tensor_g2s_im2colw_4d_cg1_param_1];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd1, [cp_async_bulk_tensor_g2s_im2colw_4d_cg1_param_2];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r3, [cp_async_bulk_tensor_g2s_im2colw_4d_cg1_param_3];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r4, [cp_async_bulk_tensor_g2s_im2colw_4d_cg1_param_4];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r5, [cp_async_bulk_tensor_g2s_im2colw_4d_cg1_param_5];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r6, [cp_async_bulk_tensor_g2s_im2colw_4d_cg1_param_6];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs1, [cp_async_bulk_tensor_g2s_im2colw_4d_cg1_param_7];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs2, [cp_async_bulk_tensor_g2s_im2colw_4d_cg1_param_8];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs3, [cp_async_bulk_tensor_g2s_im2colw_4d_cg1_param_9];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd2, [cp_async_bulk_tensor_g2s_im2colw_4d_cg1_param_10];
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.4d.shared::cluster.global.im2col::w.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint.cta_group::1 [%r1], [%rd1, {%r3, %r4, %r5, %r6}], [%r2], {%rs1, %rs2}, %rs3, %rd2;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.4d.shared::cluster.global.im2col::w.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::1 [%r1], [%rd1, {%r3, %r4, %r5, %r6}], [%r2], {%rs1, %rs2}, %rs3;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.4d.shared::cluster.global.im2col::w.mbarrier::complete_tx::bytes.L2::cache_hint.cta_group::1 [%r1], [%rd1, {%r3, %r4, %r5, %r6}], [%r2], {%rs1, %rs2}, %rd2;
@@ -302,17 +302,17 @@ define void @cp_async_bulk_tensor_g2s_im2colw_4d_cg2(ptr addrspace(7) %d, ptr ad
; CHECK-PTX64-NEXT: .reg .b64 %rd<5>;
; CHECK-PTX64-EMPTY:
; CHECK-PTX64-NEXT: // %bb.0:
-; CHECK-PTX64-NEXT: ld.param.b64 %rd1, [cp_async_bulk_tensor_g2s_im2colw_4d_cg2_param_0];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd2, [cp_async_bulk_tensor_g2s_im2colw_4d_cg2_param_1];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd3, [cp_async_bulk_tensor_g2s_im2colw_4d_cg2_param_2];
-; CHECK-PTX64-NEXT: ld.param.b32 %r1, [cp_async_bulk_tensor_g2s_im2colw_4d_cg2_param_3];
-; CHECK-PTX64-NEXT: ld.param.b32 %r2, [cp_async_bulk_tensor_g2s_im2colw_4d_cg2_param_4];
-; CHECK-PTX64-NEXT: ld.param.b32 %r3, [cp_async_bulk_tensor_g2s_im2colw_4d_cg2_param_5];
-; CHECK-PTX64-NEXT: ld.param.b32 %r4, [cp_async_bulk_tensor_g2s_im2colw_4d_cg2_param_6];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs1, [cp_async_bulk_tensor_g2s_im2colw_4d_cg2_param_7];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs2, [cp_async_bulk_tensor_g2s_im2colw_4d_cg2_param_8];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs3, [cp_async_bulk_tensor_g2s_im2colw_4d_cg2_param_9];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd4, [cp_async_bulk_tensor_g2s_im2colw_4d_cg2_param_10];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd1, [cp_async_bulk_tensor_g2s_im2colw_4d_cg2_param_0];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd2, [cp_async_bulk_tensor_g2s_im2colw_4d_cg2_param_1];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd3, [cp_async_bulk_tensor_g2s_im2colw_4d_cg2_param_2];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r1, [cp_async_bulk_tensor_g2s_im2colw_4d_cg2_param_3];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r2, [cp_async_bulk_tensor_g2s_im2colw_4d_cg2_param_4];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r3, [cp_async_bulk_tensor_g2s_im2colw_4d_cg2_param_5];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r4, [cp_async_bulk_tensor_g2s_im2colw_4d_cg2_param_6];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs1, [cp_async_bulk_tensor_g2s_im2colw_4d_cg2_param_7];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs2, [cp_async_bulk_tensor_g2s_im2colw_4d_cg2_param_8];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs3, [cp_async_bulk_tensor_g2s_im2colw_4d_cg2_param_9];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd4, [cp_async_bulk_tensor_g2s_im2colw_4d_cg2_param_10];
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.4d.shared::cluster.global.im2col::w.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint.cta_group::2 [%rd1], [%rd3, {%r1, %r2, %r3, %r4}], [%rd2], {%rs1, %rs2}, %rs3, %rd4;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.4d.shared::cluster.global.im2col::w.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::2 [%rd1], [%rd3, {%r1, %r2, %r3, %r4}], [%rd2], {%rs1, %rs2}, %rs3;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.4d.shared::cluster.global.im2col::w.mbarrier::complete_tx::bytes.L2::cache_hint.cta_group::2 [%rd1], [%rd3, {%r1, %r2, %r3, %r4}], [%rd2], {%rs1, %rs2}, %rd4;
@@ -326,17 +326,17 @@ define void @cp_async_bulk_tensor_g2s_im2colw_4d_cg2(ptr addrspace(7) %d, ptr ad
; CHECK-PTX-SHARED32-NEXT: .reg .b64 %rd<3>;
; CHECK-PTX-SHARED32-EMPTY:
; CHECK-PTX-SHARED32-NEXT: // %bb.0:
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r1, [cp_async_bulk_tensor_g2s_im2colw_4d_cg2_param_0];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r2, [cp_async_bulk_tensor_g2s_im2colw_4d_cg2_param_1];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd1, [cp_async_bulk_tensor_g2s_im2colw_4d_cg2_param_2];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r3, [cp_async_bulk_tensor_g2s_im2colw_4d_cg2_param_3];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r4, [cp_async_bulk_tensor_g2s_im2colw_4d_cg2_param_4];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r5, [cp_async_bulk_tensor_g2s_im2colw_4d_cg2_param_5];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r6, [cp_async_bulk_tensor_g2s_im2colw_4d_cg2_param_6];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs1, [cp_async_bulk_tensor_g2s_im2colw_4d_cg2_param_7];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs2, [cp_async_bulk_tensor_g2s_im2colw_4d_cg2_param_8];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs3, [cp_async_bulk_tensor_g2s_im2colw_4d_cg2_param_9];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd2, [cp_async_bulk_tensor_g2s_im2colw_4d_cg2_param_10];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r1, [cp_async_bulk_tensor_g2s_im2colw_4d_cg2_param_0];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r2, [cp_async_bulk_tensor_g2s_im2colw_4d_cg2_param_1];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd1, [cp_async_bulk_tensor_g2s_im2colw_4d_cg2_param_2];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r3, [cp_async_bulk_tensor_g2s_im2colw_4d_cg2_param_3];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r4, [cp_async_bulk_tensor_g2s_im2colw_4d_cg2_param_4];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r5, [cp_async_bulk_tensor_g2s_im2colw_4d_cg2_param_5];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r6, [cp_async_bulk_tensor_g2s_im2colw_4d_cg2_param_6];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs1, [cp_async_bulk_tensor_g2s_im2colw_4d_cg2_param_7];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs2, [cp_async_bulk_tensor_g2s_im2colw_4d_cg2_param_8];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs3, [cp_async_bulk_tensor_g2s_im2colw_4d_cg2_param_9];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd2, [cp_async_bulk_tensor_g2s_im2colw_4d_cg2_param_10];
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.4d.shared::cluster.global.im2col::w.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint.cta_group::2 [%r1], [%rd1, {%r3, %r4, %r5, %r6}], [%r2], {%rs1, %rs2}, %rs3, %rd2;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.4d.shared::cluster.global.im2col::w.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::2 [%r1], [%rd1, {%r3, %r4, %r5, %r6}], [%r2], {%rs1, %rs2}, %rs3;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.4d.shared::cluster.global.im2col::w.mbarrier::complete_tx::bytes.L2::cache_hint.cta_group::2 [%r1], [%rd1, {%r3, %r4, %r5, %r6}], [%r2], {%rs1, %rs2}, %rd2;
@@ -359,18 +359,18 @@ define void @cp_async_bulk_tensor_g2s_im2colw_5d(ptr addrspace(7) %d, ptr addrsp
; CHECK-PTX64-NEXT: .reg .b64 %rd<5>;
; CHECK-PTX64-EMPTY:
; CHECK-PTX64-NEXT: // %bb.0:
-; CHECK-PTX64-NEXT: ld.param.b64 %rd1, [cp_async_bulk_tensor_g2s_im2colw_5d_param_0];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd2, [cp_async_bulk_tensor_g2s_im2colw_5d_param_1];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd3, [cp_async_bulk_tensor_g2s_im2colw_5d_param_2];
-; CHECK-PTX64-NEXT: ld.param.b32 %r1, [cp_async_bulk_tensor_g2s_im2colw_5d_param_3];
-; CHECK-PTX64-NEXT: ld.param.b32 %r2, [cp_async_bulk_tensor_g2s_im2colw_5d_param_4];
-; CHECK-PTX64-NEXT: ld.param.b32 %r3, [cp_async_bulk_tensor_g2s_im2colw_5d_param_5];
-; CHECK-PTX64-NEXT: ld.param.b32 %r4, [cp_async_bulk_tensor_g2s_im2colw_5d_param_6];
-; CHECK-PTX64-NEXT: ld.param.b32 %r5, [cp_async_bulk_tensor_g2s_im2colw_5d_param_7];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs1, [cp_async_bulk_tensor_g2s_im2colw_5d_param_8];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs2, [cp_async_bulk_tensor_g2s_im2colw_5d_param_9];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs3, [cp_async_bulk_tensor_g2s_im2colw_5d_param_10];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd4, [cp_async_bulk_tensor_g2s_im2colw_5d_param_11];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd1, [cp_async_bulk_tensor_g2s_im2colw_5d_param_0];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd2, [cp_async_bulk_tensor_g2s_im2colw_5d_param_1];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd3, [cp_async_bulk_tensor_g2s_im2colw_5d_param_2];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r1, [cp_async_bulk_tensor_g2s_im2colw_5d_param_3];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r2, [cp_async_bulk_tensor_g2s_im2colw_5d_param_4];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r3, [cp_async_bulk_tensor_g2s_im2colw_5d_param_5];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r4, [cp_async_bulk_tensor_g2s_im2colw_5d_param_6];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r5, [cp_async_bulk_tensor_g2s_im2colw_5d_param_7];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs1, [cp_async_bulk_tensor_g2s_im2colw_5d_param_8];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs2, [cp_async_bulk_tensor_g2s_im2colw_5d_param_9];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs3, [cp_async_bulk_tensor_g2s_im2colw_5d_param_10];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd4, [cp_async_bulk_tensor_g2s_im2colw_5d_param_11];
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.5d.shared::cluster.global.im2col::w.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint [%rd1], [%rd3, {%r1, %r2, %r3, %r4, %r5}], [%rd2], {%rs1, %rs2}, %rs3, %rd4;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.5d.shared::cluster.global.im2col::w.mbarrier::complete_tx::bytes.multicast::cluster [%rd1], [%rd3, {%r1, %r2, %r3, %r4, %r5}], [%rd2], {%rs1, %rs2}, %rs3;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.5d.shared::cluster.global.im2col::w.mbarrier::complete_tx::bytes.L2::cache_hint [%rd1], [%rd3, {%r1, %r2, %r3, %r4, %r5}], [%rd2], {%rs1, %rs2}, %rd4;
@@ -384,18 +384,18 @@ define void @cp_async_bulk_tensor_g2s_im2colw_5d(ptr addrspace(7) %d, ptr addrsp
; CHECK-PTX-SHARED32-NEXT: .reg .b64 %rd<3>;
; CHECK-PTX-SHARED32-EMPTY:
; CHECK-PTX-SHARED32-NEXT: // %bb.0:
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r1, [cp_async_bulk_tensor_g2s_im2colw_5d_param_0];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r2, [cp_async_bulk_tensor_g2s_im2colw_5d_param_1];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd1, [cp_async_bulk_tensor_g2s_im2colw_5d_param_2];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r3, [cp_async_bulk_tensor_g2s_im2colw_5d_param_3];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r4, [cp_async_bulk_tensor_g2s_im2colw_5d_param_4];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r5, [cp_async_bulk_tensor_g2s_im2colw_5d_param_5];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r6, [cp_async_bulk_tensor_g2s_im2colw_5d_param_6];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r7, [cp_async_bulk_tensor_g2s_im2colw_5d_param_7];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs1, [cp_async_bulk_tensor_g2s_im2colw_5d_param_8];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs2, [cp_async_bulk_tensor_g2s_im2colw_5d_param_9];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs3, [cp_async_bulk_tensor_g2s_im2colw_5d_param_10];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd2, [cp_async_bulk_tensor_g2s_im2colw_5d_param_11];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r1, [cp_async_bulk_tensor_g2s_im2colw_5d_param_0];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r2, [cp_async_bulk_tensor_g2s_im2colw_5d_param_1];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd1, [cp_async_bulk_tensor_g2s_im2colw_5d_param_2];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r3, [cp_async_bulk_tensor_g2s_im2colw_5d_param_3];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r4, [cp_async_bulk_tensor_g2s_im2colw_5d_param_4];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r5, [cp_async_bulk_tensor_g2s_im2colw_5d_param_5];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r6, [cp_async_bulk_tensor_g2s_im2colw_5d_param_6];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r7, [cp_async_bulk_tensor_g2s_im2colw_5d_param_7];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs1, [cp_async_bulk_tensor_g2s_im2colw_5d_param_8];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs2, [cp_async_bulk_tensor_g2s_im2colw_5d_param_9];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs3, [cp_async_bulk_tensor_g2s_im2colw_5d_param_10];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd2, [cp_async_bulk_tensor_g2s_im2colw_5d_param_11];
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.5d.shared::cluster.global.im2col::w.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint [%r1], [%rd1, {%r3, %r4, %r5, %r6, %r7}], [%r2], {%rs1, %rs2}, %rs3, %rd2;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.5d.shared::cluster.global.im2col::w.mbarrier::complete_tx::bytes.multicast::cluster [%r1], [%rd1, {%r3, %r4, %r5, %r6, %r7}], [%r2], {%rs1, %rs2}, %rs3;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.5d.shared::cluster.global.im2col::w.mbarrier::complete_tx::bytes.L2::cache_hint [%r1], [%rd1, {%r3, %r4, %r5, %r6, %r7}], [%r2], {%rs1, %rs2}, %rd2;
@@ -418,18 +418,18 @@ define void @cp_async_bulk_tensor_g2s_im2colw_5d_cg1(ptr addrspace(7) %d, ptr ad
; CHECK-PTX64-NEXT: .reg .b64 %rd<5>;
; CHECK-PTX64-EMPTY:
; CHECK-PTX64-NEXT: // %bb.0:
-; CHECK-PTX64-NEXT: ld.param.b64 %rd1, [cp_async_bulk_tensor_g2s_im2colw_5d_cg1_param_0];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd2, [cp_async_bulk_tensor_g2s_im2colw_5d_cg1_param_1];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd3, [cp_async_bulk_tensor_g2s_im2colw_5d_cg1_param_2];
-; CHECK-PTX64-NEXT: ld.param.b32 %r1, [cp_async_bulk_tensor_g2s_im2colw_5d_cg1_param_3];
-; CHECK-PTX64-NEXT: ld.param.b32 %r2, [cp_async_bulk_tensor_g2s_im2colw_5d_cg1_param_4];
-; CHECK-PTX64-NEXT: ld.param.b32 %r3, [cp_async_bulk_tensor_g2s_im2colw_5d_cg1_param_5];
-; CHECK-PTX64-NEXT: ld.param.b32 %r4, [cp_async_bulk_tensor_g2s_im2colw_5d_cg1_param_6];
-; CHECK-PTX64-NEXT: ld.param.b32 %r5, [cp_async_bulk_tensor_g2s_im2colw_5d_cg1_param_7];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs1, [cp_async_bulk_tensor_g2s_im2colw_5d_cg1_param_8];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs2, [cp_async_bulk_tensor_g2s_im2colw_5d_cg1_param_9];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs3, [cp_async_bulk_tensor_g2s_im2colw_5d_cg1_param_10];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd4, [cp_async_bulk_tensor_g2s_im2colw_5d_cg1_param_11];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd1, [cp_async_bulk_tensor_g2s_im2colw_5d_cg1_param_0];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd2, [cp_async_bulk_tensor_g2s_im2colw_5d_cg1_param_1];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd3, [cp_async_bulk_tensor_g2s_im2colw_5d_cg1_param_2];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r1, [cp_async_bulk_tensor_g2s_im2colw_5d_cg1_param_3];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r2, [cp_async_bulk_tensor_g2s_im2colw_5d_cg1_param_4];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r3, [cp_async_bulk_tensor_g2s_im2colw_5d_cg1_param_5];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r4, [cp_async_bulk_tensor_g2s_im2colw_5d_cg1_param_6];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r5, [cp_async_bulk_tensor_g2s_im2colw_5d_cg1_param_7];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs1, [cp_async_bulk_tensor_g2s_im2colw_5d_cg1_param_8];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs2, [cp_async_bulk_tensor_g2s_im2colw_5d_cg1_param_9];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs3, [cp_async_bulk_tensor_g2s_im2colw_5d_cg1_param_10];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd4, [cp_async_bulk_tensor_g2s_im2colw_5d_cg1_param_11];
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.5d.shared::cluster.global.im2col::w.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint.cta_group::1 [%rd1], [%rd3, {%r1, %r2, %r3, %r4, %r5}], [%rd2], {%rs1, %rs2}, %rs3, %rd4;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.5d.shared::cluster.global.im2col::w.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::1 [%rd1], [%rd3, {%r1, %r2, %r3, %r4, %r5}], [%rd2], {%rs1, %rs2}, %rs3;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.5d.shared::cluster.global.im2col::w.mbarrier::complete_tx::bytes.L2::cache_hint.cta_group::1 [%rd1], [%rd3, {%r1, %r2, %r3, %r4, %r5}], [%rd2], {%rs1, %rs2}, %rd4;
@@ -443,18 +443,18 @@ define void @cp_async_bulk_tensor_g2s_im2colw_5d_cg1(ptr addrspace(7) %d, ptr ad
; CHECK-PTX-SHARED32-NEXT: .reg .b64 %rd<3>;
; CHECK-PTX-SHARED32-EMPTY:
; CHECK-PTX-SHARED32-NEXT: // %bb.0:
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r1, [cp_async_bulk_tensor_g2s_im2colw_5d_cg1_param_0];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r2, [cp_async_bulk_tensor_g2s_im2colw_5d_cg1_param_1];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd1, [cp_async_bulk_tensor_g2s_im2colw_5d_cg1_param_2];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r3, [cp_async_bulk_tensor_g2s_im2colw_5d_cg1_param_3];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r4, [cp_async_bulk_tensor_g2s_im2colw_5d_cg1_param_4];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r5, [cp_async_bulk_tensor_g2s_im2colw_5d_cg1_param_5];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r6, [cp_async_bulk_tensor_g2s_im2colw_5d_cg1_param_6];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r7, [cp_async_bulk_tensor_g2s_im2colw_5d_cg1_param_7];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs1, [cp_async_bulk_tensor_g2s_im2colw_5d_cg1_param_8];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs2, [cp_async_bulk_tensor_g2s_im2colw_5d_cg1_param_9];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs3, [cp_async_bulk_tensor_g2s_im2colw_5d_cg1_param_10];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd2, [cp_async_bulk_tensor_g2s_im2colw_5d_cg1_param_11];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r1, [cp_async_bulk_tensor_g2s_im2colw_5d_cg1_param_0];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r2, [cp_async_bulk_tensor_g2s_im2colw_5d_cg1_param_1];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd1, [cp_async_bulk_tensor_g2s_im2colw_5d_cg1_param_2];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r3, [cp_async_bulk_tensor_g2s_im2colw_5d_cg1_param_3];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r4, [cp_async_bulk_tensor_g2s_im2colw_5d_cg1_param_4];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r5, [cp_async_bulk_tensor_g2s_im2colw_5d_cg1_param_5];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r6, [cp_async_bulk_tensor_g2s_im2colw_5d_cg1_param_6];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r7, [cp_async_bulk_tensor_g2s_im2colw_5d_cg1_param_7];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs1, [cp_async_bulk_tensor_g2s_im2colw_5d_cg1_param_8];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs2, [cp_async_bulk_tensor_g2s_im2colw_5d_cg1_param_9];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs3, [cp_async_bulk_tensor_g2s_im2colw_5d_cg1_param_10];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd2, [cp_async_bulk_tensor_g2s_im2colw_5d_cg1_param_11];
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.5d.shared::cluster.global.im2col::w.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint.cta_group::1 [%r1], [%rd1, {%r3, %r4, %r5, %r6, %r7}], [%r2], {%rs1, %rs2}, %rs3, %rd2;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.5d.shared::cluster.global.im2col::w.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::1 [%r1], [%rd1, {%r3, %r4, %r5, %r6, %r7}], [%r2], {%rs1, %rs2}, %rs3;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.5d.shared::cluster.global.im2col::w.mbarrier::complete_tx::bytes.L2::cache_hint.cta_group::1 [%r1], [%rd1, {%r3, %r4, %r5, %r6, %r7}], [%r2], {%rs1, %rs2}, %rd2;
@@ -477,18 +477,18 @@ define void @cp_async_bulk_tensor_g2s_im2colw_5d_cg2(ptr addrspace(7) %d, ptr ad
; CHECK-PTX64-NEXT: .reg .b64 %rd<5>;
; CHECK-PTX64-EMPTY:
; CHECK-PTX64-NEXT: // %bb.0:
-; CHECK-PTX64-NEXT: ld.param.b64 %rd1, [cp_async_bulk_tensor_g2s_im2colw_5d_cg2_param_0];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd2, [cp_async_bulk_tensor_g2s_im2colw_5d_cg2_param_1];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd3, [cp_async_bulk_tensor_g2s_im2colw_5d_cg2_param_2];
-; CHECK-PTX64-NEXT: ld.param.b32 %r1, [cp_async_bulk_tensor_g2s_im2colw_5d_cg2_param_3];
-; CHECK-PTX64-NEXT: ld.param.b32 %r2, [cp_async_bulk_tensor_g2s_im2colw_5d_cg2_param_4];
-; CHECK-PTX64-NEXT: ld.param.b32 %r3, [cp_async_bulk_tensor_g2s_im2colw_5d_cg2_param_5];
-; CHECK-PTX64-NEXT: ld.param.b32 %r4, [cp_async_bulk_tensor_g2s_im2colw_5d_cg2_param_6];
-; CHECK-PTX64-NEXT: ld.param.b32 %r5, [cp_async_bulk_tensor_g2s_im2colw_5d_cg2_param_7];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs1, [cp_async_bulk_tensor_g2s_im2colw_5d_cg2_param_8];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs2, [cp_async_bulk_tensor_g2s_im2colw_5d_cg2_param_9];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs3, [cp_async_bulk_tensor_g2s_im2colw_5d_cg2_param_10];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd4, [cp_async_bulk_tensor_g2s_im2colw_5d_cg2_param_11];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd1, [cp_async_bulk_tensor_g2s_im2colw_5d_cg2_param_0];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd2, [cp_async_bulk_tensor_g2s_im2colw_5d_cg2_param_1];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd3, [cp_async_bulk_tensor_g2s_im2colw_5d_cg2_param_2];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r1, [cp_async_bulk_tensor_g2s_im2colw_5d_cg2_param_3];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r2, [cp_async_bulk_tensor_g2s_im2colw_5d_cg2_param_4];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r3, [cp_async_bulk_tensor_g2s_im2colw_5d_cg2_param_5];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r4, [cp_async_bulk_tensor_g2s_im2colw_5d_cg2_param_6];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r5, [cp_async_bulk_tensor_g2s_im2colw_5d_cg2_param_7];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs1, [cp_async_bulk_tensor_g2s_im2colw_5d_cg2_param_8];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs2, [cp_async_bulk_tensor_g2s_im2colw_5d_cg2_param_9];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs3, [cp_async_bulk_tensor_g2s_im2colw_5d_cg2_param_10];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd4, [cp_async_bulk_tensor_g2s_im2colw_5d_cg2_param_11];
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.5d.shared::cluster.global.im2col::w.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint.cta_group::2 [%rd1], [%rd3, {%r1, %r2, %r3, %r4, %r5}], [%rd2], {%rs1, %rs2}, %rs3, %rd4;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.5d.shared::cluster.global.im2col::w.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::2 [%rd1], [%rd3, {%r1, %r2, %r3, %r4, %r5}], [%rd2], {%rs1, %rs2}, %rs3;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.5d.shared::cluster.global.im2col::w.mbarrier::complete_tx::bytes.L2::cache_hint.cta_group::2 [%rd1], [%rd3, {%r1, %r2, %r3, %r4, %r5}], [%rd2], {%rs1, %rs2}, %rd4;
@@ -502,18 +502,18 @@ define void @cp_async_bulk_tensor_g2s_im2colw_5d_cg2(ptr addrspace(7) %d, ptr ad
; CHECK-PTX-SHARED32-NEXT: .reg .b64 %rd<3>;
; CHECK-PTX-SHARED32-EMPTY:
; CHECK-PTX-SHARED32-NEXT: // %bb.0:
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r1, [cp_async_bulk_tensor_g2s_im2colw_5d_cg2_param_0];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r2, [cp_async_bulk_tensor_g2s_im2colw_5d_cg2_param_1];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd1, [cp_async_bulk_tensor_g2s_im2colw_5d_cg2_param_2];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r3, [cp_async_bulk_tensor_g2s_im2colw_5d_cg2_param_3];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r4, [cp_async_bulk_tensor_g2s_im2colw_5d_cg2_param_4];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r5, [cp_async_bulk_tensor_g2s_im2colw_5d_cg2_param_5];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r6, [cp_async_bulk_tensor_g2s_im2colw_5d_cg2_param_6];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r7, [cp_async_bulk_tensor_g2s_im2colw_5d_cg2_param_7];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs1, [cp_async_bulk_tensor_g2s_im2colw_5d_cg2_param_8];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs2, [cp_async_bulk_tensor_g2s_im2colw_5d_cg2_param_9];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs3, [cp_async_bulk_tensor_g2s_im2colw_5d_cg2_param_10];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd2, [cp_async_bulk_tensor_g2s_im2colw_5d_cg2_param_11];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r1, [cp_async_bulk_tensor_g2s_im2colw_5d_cg2_param_0];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r2, [cp_async_bulk_tensor_g2s_im2colw_5d_cg2_param_1];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd1, [cp_async_bulk_tensor_g2s_im2colw_5d_cg2_param_2];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r3, [cp_async_bulk_tensor_g2s_im2colw_5d_cg2_param_3];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r4, [cp_async_bulk_tensor_g2s_im2colw_5d_cg2_param_4];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r5, [cp_async_bulk_tensor_g2s_im2colw_5d_cg2_param_5];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r6, [cp_async_bulk_tensor_g2s_im2colw_5d_cg2_param_6];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r7, [cp_async_bulk_tensor_g2s_im2colw_5d_cg2_param_7];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs1, [cp_async_bulk_tensor_g2s_im2colw_5d_cg2_param_8];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs2, [cp_async_bulk_tensor_g2s_im2colw_5d_cg2_param_9];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs3, [cp_async_bulk_tensor_g2s_im2colw_5d_cg2_param_10];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd2, [cp_async_bulk_tensor_g2s_im2colw_5d_cg2_param_11];
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.5d.shared::cluster.global.im2col::w.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint.cta_group::2 [%r1], [%rd1, {%r3, %r4, %r5, %r6, %r7}], [%r2], {%rs1, %rs2}, %rs3, %rd2;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.5d.shared::cluster.global.im2col::w.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::2 [%r1], [%rd1, {%r3, %r4, %r5, %r6, %r7}], [%r2], {%rs1, %rs2}, %rs3;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.5d.shared::cluster.global.im2col::w.mbarrier::complete_tx::bytes.L2::cache_hint.cta_group::2 [%r1], [%rd1, {%r3, %r4, %r5, %r6, %r7}], [%r2], {%rs1, %rs2}, %rd2;
diff --git a/llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-im2colw128.ll b/llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-im2colw128.ll
index ad7ccb2b52928..7aafe98c39172 100644
--- a/llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-im2colw128.ll
+++ b/llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s-im2colw128.ll
@@ -23,16 +23,16 @@ define void @cp_async_bulk_tensor_g2s_im2colw_128_3d(ptr addrspace(7) %d, ptr ad
; CHECK-PTX64-NEXT: .reg .b64 %rd<5>;
; CHECK-PTX64-EMPTY:
; CHECK-PTX64-NEXT: // %bb.0:
-; CHECK-PTX64-NEXT: ld.param.b64 %rd1, [cp_async_bulk_tensor_g2s_im2colw_128_3d_param_0];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd2, [cp_async_bulk_tensor_g2s_im2colw_128_3d_param_1];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd3, [cp_async_bulk_tensor_g2s_im2colw_128_3d_param_2];
-; CHECK-PTX64-NEXT: ld.param.b32 %r1, [cp_async_bulk_tensor_g2s_im2colw_128_3d_param_3];
-; CHECK-PTX64-NEXT: ld.param.b32 %r2, [cp_async_bulk_tensor_g2s_im2colw_128_3d_param_4];
-; CHECK-PTX64-NEXT: ld.param.b32 %r3, [cp_async_bulk_tensor_g2s_im2colw_128_3d_param_5];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs1, [cp_async_bulk_tensor_g2s_im2colw_128_3d_param_6];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs2, [cp_async_bulk_tensor_g2s_im2colw_128_3d_param_7];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs3, [cp_async_bulk_tensor_g2s_im2colw_128_3d_param_8];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd4, [cp_async_bulk_tensor_g2s_im2colw_128_3d_param_9];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd1, [cp_async_bulk_tensor_g2s_im2colw_128_3d_param_0];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd2, [cp_async_bulk_tensor_g2s_im2colw_128_3d_param_1];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd3, [cp_async_bulk_tensor_g2s_im2colw_128_3d_param_2];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r1, [cp_async_bulk_tensor_g2s_im2colw_128_3d_param_3];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r2, [cp_async_bulk_tensor_g2s_im2colw_128_3d_param_4];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r3, [cp_async_bulk_tensor_g2s_im2colw_128_3d_param_5];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs1, [cp_async_bulk_tensor_g2s_im2colw_128_3d_param_6];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs2, [cp_async_bulk_tensor_g2s_im2colw_128_3d_param_7];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs3, [cp_async_bulk_tensor_g2s_im2colw_128_3d_param_8];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd4, [cp_async_bulk_tensor_g2s_im2colw_128_3d_param_9];
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.3d.shared::cluster.global.im2col::w::128.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint [%rd1], [%rd3, {%r1, %r2, %r3}], [%rd2], {%rs1, %rs2}, %rs3, %rd4;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.3d.shared::cluster.global.im2col::w::128.mbarrier::complete_tx::bytes.multicast::cluster [%rd1], [%rd3, {%r1, %r2, %r3}], [%rd2], {%rs1, %rs2}, %rs3;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.3d.shared::cluster.global.im2col::w::128.mbarrier::complete_tx::bytes.L2::cache_hint [%rd1], [%rd3, {%r1, %r2, %r3}], [%rd2], {%rs1, %rs2}, %rd4;
@@ -46,16 +46,16 @@ define void @cp_async_bulk_tensor_g2s_im2colw_128_3d(ptr addrspace(7) %d, ptr ad
; CHECK-PTX-SHARED32-NEXT: .reg .b64 %rd<3>;
; CHECK-PTX-SHARED32-EMPTY:
; CHECK-PTX-SHARED32-NEXT: // %bb.0:
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r1, [cp_async_bulk_tensor_g2s_im2colw_128_3d_param_0];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r2, [cp_async_bulk_tensor_g2s_im2colw_128_3d_param_1];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd1, [cp_async_bulk_tensor_g2s_im2colw_128_3d_param_2];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r3, [cp_async_bulk_tensor_g2s_im2colw_128_3d_param_3];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r4, [cp_async_bulk_tensor_g2s_im2colw_128_3d_param_4];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r5, [cp_async_bulk_tensor_g2s_im2colw_128_3d_param_5];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs1, [cp_async_bulk_tensor_g2s_im2colw_128_3d_param_6];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs2, [cp_async_bulk_tensor_g2s_im2colw_128_3d_param_7];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs3, [cp_async_bulk_tensor_g2s_im2colw_128_3d_param_8];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd2, [cp_async_bulk_tensor_g2s_im2colw_128_3d_param_9];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r1, [cp_async_bulk_tensor_g2s_im2colw_128_3d_param_0];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r2, [cp_async_bulk_tensor_g2s_im2colw_128_3d_param_1];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd1, [cp_async_bulk_tensor_g2s_im2colw_128_3d_param_2];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r3, [cp_async_bulk_tensor_g2s_im2colw_128_3d_param_3];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r4, [cp_async_bulk_tensor_g2s_im2colw_128_3d_param_4];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r5, [cp_async_bulk_tensor_g2s_im2colw_128_3d_param_5];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs1, [cp_async_bulk_tensor_g2s_im2colw_128_3d_param_6];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs2, [cp_async_bulk_tensor_g2s_im2colw_128_3d_param_7];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs3, [cp_async_bulk_tensor_g2s_im2colw_128_3d_param_8];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd2, [cp_async_bulk_tensor_g2s_im2colw_128_3d_param_9];
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.3d.shared::cluster.global.im2col::w::128.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint [%r1], [%rd1, {%r3, %r4, %r5}], [%r2], {%rs1, %rs2}, %rs3, %rd2;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.3d.shared::cluster.global.im2col::w::128.mbarrier::complete_tx::bytes.multicast::cluster [%r1], [%rd1, {%r3, %r4, %r5}], [%r2], {%rs1, %rs2}, %rs3;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.3d.shared::cluster.global.im2col::w::128.mbarrier::complete_tx::bytes.L2::cache_hint [%r1], [%rd1, {%r3, %r4, %r5}], [%r2], {%rs1, %rs2}, %rd2;
@@ -78,16 +78,16 @@ define void @cp_async_bulk_tensor_g2s_im2colw_128_3d_cg1(ptr addrspace(7) %d, pt
; CHECK-PTX64-NEXT: .reg .b64 %rd<5>;
; CHECK-PTX64-EMPTY:
; CHECK-PTX64-NEXT: // %bb.0:
-; CHECK-PTX64-NEXT: ld.param.b64 %rd1, [cp_async_bulk_tensor_g2s_im2colw_128_3d_cg1_param_0];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd2, [cp_async_bulk_tensor_g2s_im2colw_128_3d_cg1_param_1];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd3, [cp_async_bulk_tensor_g2s_im2colw_128_3d_cg1_param_2];
-; CHECK-PTX64-NEXT: ld.param.b32 %r1, [cp_async_bulk_tensor_g2s_im2colw_128_3d_cg1_param_3];
-; CHECK-PTX64-NEXT: ld.param.b32 %r2, [cp_async_bulk_tensor_g2s_im2colw_128_3d_cg1_param_4];
-; CHECK-PTX64-NEXT: ld.param.b32 %r3, [cp_async_bulk_tensor_g2s_im2colw_128_3d_cg1_param_5];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs1, [cp_async_bulk_tensor_g2s_im2colw_128_3d_cg1_param_6];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs2, [cp_async_bulk_tensor_g2s_im2colw_128_3d_cg1_param_7];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs3, [cp_async_bulk_tensor_g2s_im2colw_128_3d_cg1_param_8];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd4, [cp_async_bulk_tensor_g2s_im2colw_128_3d_cg1_param_9];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd1, [cp_async_bulk_tensor_g2s_im2colw_128_3d_cg1_param_0];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd2, [cp_async_bulk_tensor_g2s_im2colw_128_3d_cg1_param_1];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd3, [cp_async_bulk_tensor_g2s_im2colw_128_3d_cg1_param_2];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r1, [cp_async_bulk_tensor_g2s_im2colw_128_3d_cg1_param_3];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r2, [cp_async_bulk_tensor_g2s_im2colw_128_3d_cg1_param_4];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r3, [cp_async_bulk_tensor_g2s_im2colw_128_3d_cg1_param_5];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs1, [cp_async_bulk_tensor_g2s_im2colw_128_3d_cg1_param_6];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs2, [cp_async_bulk_tensor_g2s_im2colw_128_3d_cg1_param_7];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs3, [cp_async_bulk_tensor_g2s_im2colw_128_3d_cg1_param_8];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd4, [cp_async_bulk_tensor_g2s_im2colw_128_3d_cg1_param_9];
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.3d.shared::cluster.global.im2col::w::128.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint.cta_group::1 [%rd1], [%rd3, {%r1, %r2, %r3}], [%rd2], {%rs1, %rs2}, %rs3, %rd4;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.3d.shared::cluster.global.im2col::w::128.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::1 [%rd1], [%rd3, {%r1, %r2, %r3}], [%rd2], {%rs1, %rs2}, %rs3;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.3d.shared::cluster.global.im2col::w::128.mbarrier::complete_tx::bytes.L2::cache_hint.cta_group::1 [%rd1], [%rd3, {%r1, %r2, %r3}], [%rd2], {%rs1, %rs2}, %rd4;
@@ -101,16 +101,16 @@ define void @cp_async_bulk_tensor_g2s_im2colw_128_3d_cg1(ptr addrspace(7) %d, pt
; CHECK-PTX-SHARED32-NEXT: .reg .b64 %rd<3>;
; CHECK-PTX-SHARED32-EMPTY:
; CHECK-PTX-SHARED32-NEXT: // %bb.0:
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r1, [cp_async_bulk_tensor_g2s_im2colw_128_3d_cg1_param_0];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r2, [cp_async_bulk_tensor_g2s_im2colw_128_3d_cg1_param_1];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd1, [cp_async_bulk_tensor_g2s_im2colw_128_3d_cg1_param_2];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r3, [cp_async_bulk_tensor_g2s_im2colw_128_3d_cg1_param_3];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r4, [cp_async_bulk_tensor_g2s_im2colw_128_3d_cg1_param_4];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r5, [cp_async_bulk_tensor_g2s_im2colw_128_3d_cg1_param_5];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs1, [cp_async_bulk_tensor_g2s_im2colw_128_3d_cg1_param_6];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs2, [cp_async_bulk_tensor_g2s_im2colw_128_3d_cg1_param_7];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs3, [cp_async_bulk_tensor_g2s_im2colw_128_3d_cg1_param_8];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd2, [cp_async_bulk_tensor_g2s_im2colw_128_3d_cg1_param_9];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r1, [cp_async_bulk_tensor_g2s_im2colw_128_3d_cg1_param_0];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r2, [cp_async_bulk_tensor_g2s_im2colw_128_3d_cg1_param_1];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd1, [cp_async_bulk_tensor_g2s_im2colw_128_3d_cg1_param_2];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r3, [cp_async_bulk_tensor_g2s_im2colw_128_3d_cg1_param_3];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r4, [cp_async_bulk_tensor_g2s_im2colw_128_3d_cg1_param_4];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r5, [cp_async_bulk_tensor_g2s_im2colw_128_3d_cg1_param_5];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs1, [cp_async_bulk_tensor_g2s_im2colw_128_3d_cg1_param_6];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs2, [cp_async_bulk_tensor_g2s_im2colw_128_3d_cg1_param_7];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs3, [cp_async_bulk_tensor_g2s_im2colw_128_3d_cg1_param_8];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd2, [cp_async_bulk_tensor_g2s_im2colw_128_3d_cg1_param_9];
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.3d.shared::cluster.global.im2col::w::128.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint.cta_group::1 [%r1], [%rd1, {%r3, %r4, %r5}], [%r2], {%rs1, %rs2}, %rs3, %rd2;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.3d.shared::cluster.global.im2col::w::128.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::1 [%r1], [%rd1, {%r3, %r4, %r5}], [%r2], {%rs1, %rs2}, %rs3;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.3d.shared::cluster.global.im2col::w::128.mbarrier::complete_tx::bytes.L2::cache_hint.cta_group::1 [%r1], [%rd1, {%r3, %r4, %r5}], [%r2], {%rs1, %rs2}, %rd2;
@@ -133,16 +133,16 @@ define void @cp_async_bulk_tensor_g2s_im2colw_128_3d_cg2(ptr addrspace(7) %d, pt
; CHECK-PTX64-NEXT: .reg .b64 %rd<5>;
; CHECK-PTX64-EMPTY:
; CHECK-PTX64-NEXT: // %bb.0:
-; CHECK-PTX64-NEXT: ld.param.b64 %rd1, [cp_async_bulk_tensor_g2s_im2colw_128_3d_cg2_param_0];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd2, [cp_async_bulk_tensor_g2s_im2colw_128_3d_cg2_param_1];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd3, [cp_async_bulk_tensor_g2s_im2colw_128_3d_cg2_param_2];
-; CHECK-PTX64-NEXT: ld.param.b32 %r1, [cp_async_bulk_tensor_g2s_im2colw_128_3d_cg2_param_3];
-; CHECK-PTX64-NEXT: ld.param.b32 %r2, [cp_async_bulk_tensor_g2s_im2colw_128_3d_cg2_param_4];
-; CHECK-PTX64-NEXT: ld.param.b32 %r3, [cp_async_bulk_tensor_g2s_im2colw_128_3d_cg2_param_5];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs1, [cp_async_bulk_tensor_g2s_im2colw_128_3d_cg2_param_6];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs2, [cp_async_bulk_tensor_g2s_im2colw_128_3d_cg2_param_7];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs3, [cp_async_bulk_tensor_g2s_im2colw_128_3d_cg2_param_8];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd4, [cp_async_bulk_tensor_g2s_im2colw_128_3d_cg2_param_9];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd1, [cp_async_bulk_tensor_g2s_im2colw_128_3d_cg2_param_0];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd2, [cp_async_bulk_tensor_g2s_im2colw_128_3d_cg2_param_1];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd3, [cp_async_bulk_tensor_g2s_im2colw_128_3d_cg2_param_2];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r1, [cp_async_bulk_tensor_g2s_im2colw_128_3d_cg2_param_3];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r2, [cp_async_bulk_tensor_g2s_im2colw_128_3d_cg2_param_4];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r3, [cp_async_bulk_tensor_g2s_im2colw_128_3d_cg2_param_5];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs1, [cp_async_bulk_tensor_g2s_im2colw_128_3d_cg2_param_6];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs2, [cp_async_bulk_tensor_g2s_im2colw_128_3d_cg2_param_7];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs3, [cp_async_bulk_tensor_g2s_im2colw_128_3d_cg2_param_8];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd4, [cp_async_bulk_tensor_g2s_im2colw_128_3d_cg2_param_9];
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.3d.shared::cluster.global.im2col::w::128.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint.cta_group::2 [%rd1], [%rd3, {%r1, %r2, %r3}], [%rd2], {%rs1, %rs2}, %rs3, %rd4;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.3d.shared::cluster.global.im2col::w::128.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::2 [%rd1], [%rd3, {%r1, %r2, %r3}], [%rd2], {%rs1, %rs2}, %rs3;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.3d.shared::cluster.global.im2col::w::128.mbarrier::complete_tx::bytes.L2::cache_hint.cta_group::2 [%rd1], [%rd3, {%r1, %r2, %r3}], [%rd2], {%rs1, %rs2}, %rd4;
@@ -156,16 +156,16 @@ define void @cp_async_bulk_tensor_g2s_im2colw_128_3d_cg2(ptr addrspace(7) %d, pt
; CHECK-PTX-SHARED32-NEXT: .reg .b64 %rd<3>;
; CHECK-PTX-SHARED32-EMPTY:
; CHECK-PTX-SHARED32-NEXT: // %bb.0:
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r1, [cp_async_bulk_tensor_g2s_im2colw_128_3d_cg2_param_0];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r2, [cp_async_bulk_tensor_g2s_im2colw_128_3d_cg2_param_1];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd1, [cp_async_bulk_tensor_g2s_im2colw_128_3d_cg2_param_2];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r3, [cp_async_bulk_tensor_g2s_im2colw_128_3d_cg2_param_3];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r4, [cp_async_bulk_tensor_g2s_im2colw_128_3d_cg2_param_4];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r5, [cp_async_bulk_tensor_g2s_im2colw_128_3d_cg2_param_5];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs1, [cp_async_bulk_tensor_g2s_im2colw_128_3d_cg2_param_6];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs2, [cp_async_bulk_tensor_g2s_im2colw_128_3d_cg2_param_7];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs3, [cp_async_bulk_tensor_g2s_im2colw_128_3d_cg2_param_8];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd2, [cp_async_bulk_tensor_g2s_im2colw_128_3d_cg2_param_9];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r1, [cp_async_bulk_tensor_g2s_im2colw_128_3d_cg2_param_0];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r2, [cp_async_bulk_tensor_g2s_im2colw_128_3d_cg2_param_1];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd1, [cp_async_bulk_tensor_g2s_im2colw_128_3d_cg2_param_2];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r3, [cp_async_bulk_tensor_g2s_im2colw_128_3d_cg2_param_3];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r4, [cp_async_bulk_tensor_g2s_im2colw_128_3d_cg2_param_4];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r5, [cp_async_bulk_tensor_g2s_im2colw_128_3d_cg2_param_5];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs1, [cp_async_bulk_tensor_g2s_im2colw_128_3d_cg2_param_6];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs2, [cp_async_bulk_tensor_g2s_im2colw_128_3d_cg2_param_7];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs3, [cp_async_bulk_tensor_g2s_im2colw_128_3d_cg2_param_8];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd2, [cp_async_bulk_tensor_g2s_im2colw_128_3d_cg2_param_9];
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.3d.shared::cluster.global.im2col::w::128.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint.cta_group::2 [%r1], [%rd1, {%r3, %r4, %r5}], [%r2], {%rs1, %rs2}, %rs3, %rd2;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.3d.shared::cluster.global.im2col::w::128.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::2 [%r1], [%rd1, {%r3, %r4, %r5}], [%r2], {%rs1, %rs2}, %rs3;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.3d.shared::cluster.global.im2col::w::128.mbarrier::complete_tx::bytes.L2::cache_hint.cta_group::2 [%r1], [%rd1, {%r3, %r4, %r5}], [%r2], {%rs1, %rs2}, %rd2;
@@ -188,17 +188,17 @@ define void @cp_async_bulk_tensor_g2s_im2colw_128_4d(ptr addrspace(7) %d, ptr ad
; CHECK-PTX64-NEXT: .reg .b64 %rd<5>;
; CHECK-PTX64-EMPTY:
; CHECK-PTX64-NEXT: // %bb.0:
-; CHECK-PTX64-NEXT: ld.param.b64 %rd1, [cp_async_bulk_tensor_g2s_im2colw_128_4d_param_0];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd2, [cp_async_bulk_tensor_g2s_im2colw_128_4d_param_1];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd3, [cp_async_bulk_tensor_g2s_im2colw_128_4d_param_2];
-; CHECK-PTX64-NEXT: ld.param.b32 %r1, [cp_async_bulk_tensor_g2s_im2colw_128_4d_param_3];
-; CHECK-PTX64-NEXT: ld.param.b32 %r2, [cp_async_bulk_tensor_g2s_im2colw_128_4d_param_4];
-; CHECK-PTX64-NEXT: ld.param.b32 %r3, [cp_async_bulk_tensor_g2s_im2colw_128_4d_param_5];
-; CHECK-PTX64-NEXT: ld.param.b32 %r4, [cp_async_bulk_tensor_g2s_im2colw_128_4d_param_6];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs1, [cp_async_bulk_tensor_g2s_im2colw_128_4d_param_7];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs2, [cp_async_bulk_tensor_g2s_im2colw_128_4d_param_8];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs3, [cp_async_bulk_tensor_g2s_im2colw_128_4d_param_9];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd4, [cp_async_bulk_tensor_g2s_im2colw_128_4d_param_10];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd1, [cp_async_bulk_tensor_g2s_im2colw_128_4d_param_0];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd2, [cp_async_bulk_tensor_g2s_im2colw_128_4d_param_1];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd3, [cp_async_bulk_tensor_g2s_im2colw_128_4d_param_2];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r1, [cp_async_bulk_tensor_g2s_im2colw_128_4d_param_3];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r2, [cp_async_bulk_tensor_g2s_im2colw_128_4d_param_4];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r3, [cp_async_bulk_tensor_g2s_im2colw_128_4d_param_5];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r4, [cp_async_bulk_tensor_g2s_im2colw_128_4d_param_6];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs1, [cp_async_bulk_tensor_g2s_im2colw_128_4d_param_7];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs2, [cp_async_bulk_tensor_g2s_im2colw_128_4d_param_8];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs3, [cp_async_bulk_tensor_g2s_im2colw_128_4d_param_9];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd4, [cp_async_bulk_tensor_g2s_im2colw_128_4d_param_10];
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.4d.shared::cluster.global.im2col::w::128.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint [%rd1], [%rd3, {%r1, %r2, %r3, %r4}], [%rd2], {%rs1, %rs2}, %rs3, %rd4;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.4d.shared::cluster.global.im2col::w::128.mbarrier::complete_tx::bytes.multicast::cluster [%rd1], [%rd3, {%r1, %r2, %r3, %r4}], [%rd2], {%rs1, %rs2}, %rs3;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.4d.shared::cluster.global.im2col::w::128.mbarrier::complete_tx::bytes.L2::cache_hint [%rd1], [%rd3, {%r1, %r2, %r3, %r4}], [%rd2], {%rs1, %rs2}, %rd4;
@@ -212,17 +212,17 @@ define void @cp_async_bulk_tensor_g2s_im2colw_128_4d(ptr addrspace(7) %d, ptr ad
; CHECK-PTX-SHARED32-NEXT: .reg .b64 %rd<3>;
; CHECK-PTX-SHARED32-EMPTY:
; CHECK-PTX-SHARED32-NEXT: // %bb.0:
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r1, [cp_async_bulk_tensor_g2s_im2colw_128_4d_param_0];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r2, [cp_async_bulk_tensor_g2s_im2colw_128_4d_param_1];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd1, [cp_async_bulk_tensor_g2s_im2colw_128_4d_param_2];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r3, [cp_async_bulk_tensor_g2s_im2colw_128_4d_param_3];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r4, [cp_async_bulk_tensor_g2s_im2colw_128_4d_param_4];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r5, [cp_async_bulk_tensor_g2s_im2colw_128_4d_param_5];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r6, [cp_async_bulk_tensor_g2s_im2colw_128_4d_param_6];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs1, [cp_async_bulk_tensor_g2s_im2colw_128_4d_param_7];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs2, [cp_async_bulk_tensor_g2s_im2colw_128_4d_param_8];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs3, [cp_async_bulk_tensor_g2s_im2colw_128_4d_param_9];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd2, [cp_async_bulk_tensor_g2s_im2colw_128_4d_param_10];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r1, [cp_async_bulk_tensor_g2s_im2colw_128_4d_param_0];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r2, [cp_async_bulk_tensor_g2s_im2colw_128_4d_param_1];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd1, [cp_async_bulk_tensor_g2s_im2colw_128_4d_param_2];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r3, [cp_async_bulk_tensor_g2s_im2colw_128_4d_param_3];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r4, [cp_async_bulk_tensor_g2s_im2colw_128_4d_param_4];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r5, [cp_async_bulk_tensor_g2s_im2colw_128_4d_param_5];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r6, [cp_async_bulk_tensor_g2s_im2colw_128_4d_param_6];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs1, [cp_async_bulk_tensor_g2s_im2colw_128_4d_param_7];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs2, [cp_async_bulk_tensor_g2s_im2colw_128_4d_param_8];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs3, [cp_async_bulk_tensor_g2s_im2colw_128_4d_param_9];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd2, [cp_async_bulk_tensor_g2s_im2colw_128_4d_param_10];
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.4d.shared::cluster.global.im2col::w::128.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint [%r1], [%rd1, {%r3, %r4, %r5, %r6}], [%r2], {%rs1, %rs2}, %rs3, %rd2;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.4d.shared::cluster.global.im2col::w::128.mbarrier::complete_tx::bytes.multicast::cluster [%r1], [%rd1, {%r3, %r4, %r5, %r6}], [%r2], {%rs1, %rs2}, %rs3;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.4d.shared::cluster.global.im2col::w::128.mbarrier::complete_tx::bytes.L2::cache_hint [%r1], [%rd1, {%r3, %r4, %r5, %r6}], [%r2], {%rs1, %rs2}, %rd2;
@@ -245,17 +245,17 @@ define void @cp_async_bulk_tensor_g2s_im2colw_128_4d_cg1(ptr addrspace(7) %d, pt
; CHECK-PTX64-NEXT: .reg .b64 %rd<5>;
; CHECK-PTX64-EMPTY:
; CHECK-PTX64-NEXT: // %bb.0:
-; CHECK-PTX64-NEXT: ld.param.b64 %rd1, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg1_param_0];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd2, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg1_param_1];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd3, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg1_param_2];
-; CHECK-PTX64-NEXT: ld.param.b32 %r1, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg1_param_3];
-; CHECK-PTX64-NEXT: ld.param.b32 %r2, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg1_param_4];
-; CHECK-PTX64-NEXT: ld.param.b32 %r3, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg1_param_5];
-; CHECK-PTX64-NEXT: ld.param.b32 %r4, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg1_param_6];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs1, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg1_param_7];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs2, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg1_param_8];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs3, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg1_param_9];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd4, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg1_param_10];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd1, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg1_param_0];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd2, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg1_param_1];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd3, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg1_param_2];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r1, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg1_param_3];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r2, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg1_param_4];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r3, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg1_param_5];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r4, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg1_param_6];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs1, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg1_param_7];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs2, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg1_param_8];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs3, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg1_param_9];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd4, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg1_param_10];
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.4d.shared::cluster.global.im2col::w::128.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint.cta_group::1 [%rd1], [%rd3, {%r1, %r2, %r3, %r4}], [%rd2], {%rs1, %rs2}, %rs3, %rd4;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.4d.shared::cluster.global.im2col::w::128.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::1 [%rd1], [%rd3, {%r1, %r2, %r3, %r4}], [%rd2], {%rs1, %rs2}, %rs3;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.4d.shared::cluster.global.im2col::w::128.mbarrier::complete_tx::bytes.L2::cache_hint.cta_group::1 [%rd1], [%rd3, {%r1, %r2, %r3, %r4}], [%rd2], {%rs1, %rs2}, %rd4;
@@ -269,17 +269,17 @@ define void @cp_async_bulk_tensor_g2s_im2colw_128_4d_cg1(ptr addrspace(7) %d, pt
; CHECK-PTX-SHARED32-NEXT: .reg .b64 %rd<3>;
; CHECK-PTX-SHARED32-EMPTY:
; CHECK-PTX-SHARED32-NEXT: // %bb.0:
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r1, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg1_param_0];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r2, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg1_param_1];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd1, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg1_param_2];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r3, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg1_param_3];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r4, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg1_param_4];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r5, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg1_param_5];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r6, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg1_param_6];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs1, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg1_param_7];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs2, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg1_param_8];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs3, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg1_param_9];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd2, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg1_param_10];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r1, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg1_param_0];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r2, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg1_param_1];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd1, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg1_param_2];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r3, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg1_param_3];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r4, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg1_param_4];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r5, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg1_param_5];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r6, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg1_param_6];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs1, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg1_param_7];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs2, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg1_param_8];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs3, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg1_param_9];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd2, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg1_param_10];
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.4d.shared::cluster.global.im2col::w::128.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint.cta_group::1 [%r1], [%rd1, {%r3, %r4, %r5, %r6}], [%r2], {%rs1, %rs2}, %rs3, %rd2;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.4d.shared::cluster.global.im2col::w::128.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::1 [%r1], [%rd1, {%r3, %r4, %r5, %r6}], [%r2], {%rs1, %rs2}, %rs3;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.4d.shared::cluster.global.im2col::w::128.mbarrier::complete_tx::bytes.L2::cache_hint.cta_group::1 [%r1], [%rd1, {%r3, %r4, %r5, %r6}], [%r2], {%rs1, %rs2}, %rd2;
@@ -302,17 +302,17 @@ define void @cp_async_bulk_tensor_g2s_im2colw_128_4d_cg2(ptr addrspace(7) %d, pt
; CHECK-PTX64-NEXT: .reg .b64 %rd<5>;
; CHECK-PTX64-EMPTY:
; CHECK-PTX64-NEXT: // %bb.0:
-; CHECK-PTX64-NEXT: ld.param.b64 %rd1, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg2_param_0];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd2, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg2_param_1];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd3, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg2_param_2];
-; CHECK-PTX64-NEXT: ld.param.b32 %r1, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg2_param_3];
-; CHECK-PTX64-NEXT: ld.param.b32 %r2, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg2_param_4];
-; CHECK-PTX64-NEXT: ld.param.b32 %r3, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg2_param_5];
-; CHECK-PTX64-NEXT: ld.param.b32 %r4, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg2_param_6];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs1, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg2_param_7];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs2, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg2_param_8];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs3, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg2_param_9];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd4, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg2_param_10];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd1, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg2_param_0];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd2, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg2_param_1];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd3, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg2_param_2];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r1, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg2_param_3];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r2, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg2_param_4];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r3, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg2_param_5];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r4, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg2_param_6];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs1, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg2_param_7];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs2, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg2_param_8];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs3, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg2_param_9];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd4, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg2_param_10];
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.4d.shared::cluster.global.im2col::w::128.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint.cta_group::2 [%rd1], [%rd3, {%r1, %r2, %r3, %r4}], [%rd2], {%rs1, %rs2}, %rs3, %rd4;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.4d.shared::cluster.global.im2col::w::128.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::2 [%rd1], [%rd3, {%r1, %r2, %r3, %r4}], [%rd2], {%rs1, %rs2}, %rs3;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.4d.shared::cluster.global.im2col::w::128.mbarrier::complete_tx::bytes.L2::cache_hint.cta_group::2 [%rd1], [%rd3, {%r1, %r2, %r3, %r4}], [%rd2], {%rs1, %rs2}, %rd4;
@@ -326,17 +326,17 @@ define void @cp_async_bulk_tensor_g2s_im2colw_128_4d_cg2(ptr addrspace(7) %d, pt
; CHECK-PTX-SHARED32-NEXT: .reg .b64 %rd<3>;
; CHECK-PTX-SHARED32-EMPTY:
; CHECK-PTX-SHARED32-NEXT: // %bb.0:
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r1, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg2_param_0];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r2, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg2_param_1];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd1, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg2_param_2];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r3, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg2_param_3];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r4, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg2_param_4];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r5, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg2_param_5];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r6, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg2_param_6];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs1, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg2_param_7];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs2, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg2_param_8];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs3, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg2_param_9];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd2, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg2_param_10];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r1, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg2_param_0];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r2, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg2_param_1];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd1, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg2_param_2];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r3, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg2_param_3];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r4, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg2_param_4];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r5, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg2_param_5];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r6, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg2_param_6];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs1, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg2_param_7];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs2, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg2_param_8];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs3, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg2_param_9];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd2, [cp_async_bulk_tensor_g2s_im2colw_128_4d_cg2_param_10];
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.4d.shared::cluster.global.im2col::w::128.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint.cta_group::2 [%r1], [%rd1, {%r3, %r4, %r5, %r6}], [%r2], {%rs1, %rs2}, %rs3, %rd2;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.4d.shared::cluster.global.im2col::w::128.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::2 [%r1], [%rd1, {%r3, %r4, %r5, %r6}], [%r2], {%rs1, %rs2}, %rs3;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.4d.shared::cluster.global.im2col::w::128.mbarrier::complete_tx::bytes.L2::cache_hint.cta_group::2 [%r1], [%rd1, {%r3, %r4, %r5, %r6}], [%r2], {%rs1, %rs2}, %rd2;
@@ -359,18 +359,18 @@ define void @cp_async_bulk_tensor_g2s_im2colw_128_5d(ptr addrspace(7) %d, ptr ad
; CHECK-PTX64-NEXT: .reg .b64 %rd<5>;
; CHECK-PTX64-EMPTY:
; CHECK-PTX64-NEXT: // %bb.0:
-; CHECK-PTX64-NEXT: ld.param.b64 %rd1, [cp_async_bulk_tensor_g2s_im2colw_128_5d_param_0];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd2, [cp_async_bulk_tensor_g2s_im2colw_128_5d_param_1];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd3, [cp_async_bulk_tensor_g2s_im2colw_128_5d_param_2];
-; CHECK-PTX64-NEXT: ld.param.b32 %r1, [cp_async_bulk_tensor_g2s_im2colw_128_5d_param_3];
-; CHECK-PTX64-NEXT: ld.param.b32 %r2, [cp_async_bulk_tensor_g2s_im2colw_128_5d_param_4];
-; CHECK-PTX64-NEXT: ld.param.b32 %r3, [cp_async_bulk_tensor_g2s_im2colw_128_5d_param_5];
-; CHECK-PTX64-NEXT: ld.param.b32 %r4, [cp_async_bulk_tensor_g2s_im2colw_128_5d_param_6];
-; CHECK-PTX64-NEXT: ld.param.b32 %r5, [cp_async_bulk_tensor_g2s_im2colw_128_5d_param_7];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs1, [cp_async_bulk_tensor_g2s_im2colw_128_5d_param_8];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs2, [cp_async_bulk_tensor_g2s_im2colw_128_5d_param_9];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs3, [cp_async_bulk_tensor_g2s_im2colw_128_5d_param_10];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd4, [cp_async_bulk_tensor_g2s_im2colw_128_5d_param_11];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd1, [cp_async_bulk_tensor_g2s_im2colw_128_5d_param_0];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd2, [cp_async_bulk_tensor_g2s_im2colw_128_5d_param_1];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd3, [cp_async_bulk_tensor_g2s_im2colw_128_5d_param_2];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r1, [cp_async_bulk_tensor_g2s_im2colw_128_5d_param_3];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r2, [cp_async_bulk_tensor_g2s_im2colw_128_5d_param_4];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r3, [cp_async_bulk_tensor_g2s_im2colw_128_5d_param_5];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r4, [cp_async_bulk_tensor_g2s_im2colw_128_5d_param_6];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r5, [cp_async_bulk_tensor_g2s_im2colw_128_5d_param_7];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs1, [cp_async_bulk_tensor_g2s_im2colw_128_5d_param_8];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs2, [cp_async_bulk_tensor_g2s_im2colw_128_5d_param_9];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs3, [cp_async_bulk_tensor_g2s_im2colw_128_5d_param_10];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd4, [cp_async_bulk_tensor_g2s_im2colw_128_5d_param_11];
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.5d.shared::cluster.global.im2col::w::128.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint [%rd1], [%rd3, {%r1, %r2, %r3, %r4, %r5}], [%rd2], {%rs1, %rs2}, %rs3, %rd4;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.5d.shared::cluster.global.im2col::w::128.mbarrier::complete_tx::bytes.multicast::cluster [%rd1], [%rd3, {%r1, %r2, %r3, %r4, %r5}], [%rd2], {%rs1, %rs2}, %rs3;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.5d.shared::cluster.global.im2col::w::128.mbarrier::complete_tx::bytes.L2::cache_hint [%rd1], [%rd3, {%r1, %r2, %r3, %r4, %r5}], [%rd2], {%rs1, %rs2}, %rd4;
@@ -384,18 +384,18 @@ define void @cp_async_bulk_tensor_g2s_im2colw_128_5d(ptr addrspace(7) %d, ptr ad
; CHECK-PTX-SHARED32-NEXT: .reg .b64 %rd<3>;
; CHECK-PTX-SHARED32-EMPTY:
; CHECK-PTX-SHARED32-NEXT: // %bb.0:
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r1, [cp_async_bulk_tensor_g2s_im2colw_128_5d_param_0];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r2, [cp_async_bulk_tensor_g2s_im2colw_128_5d_param_1];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd1, [cp_async_bulk_tensor_g2s_im2colw_128_5d_param_2];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r3, [cp_async_bulk_tensor_g2s_im2colw_128_5d_param_3];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r4, [cp_async_bulk_tensor_g2s_im2colw_128_5d_param_4];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r5, [cp_async_bulk_tensor_g2s_im2colw_128_5d_param_5];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r6, [cp_async_bulk_tensor_g2s_im2colw_128_5d_param_6];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r7, [cp_async_bulk_tensor_g2s_im2colw_128_5d_param_7];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs1, [cp_async_bulk_tensor_g2s_im2colw_128_5d_param_8];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs2, [cp_async_bulk_tensor_g2s_im2colw_128_5d_param_9];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs3, [cp_async_bulk_tensor_g2s_im2colw_128_5d_param_10];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd2, [cp_async_bulk_tensor_g2s_im2colw_128_5d_param_11];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r1, [cp_async_bulk_tensor_g2s_im2colw_128_5d_param_0];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r2, [cp_async_bulk_tensor_g2s_im2colw_128_5d_param_1];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd1, [cp_async_bulk_tensor_g2s_im2colw_128_5d_param_2];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r3, [cp_async_bulk_tensor_g2s_im2colw_128_5d_param_3];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r4, [cp_async_bulk_tensor_g2s_im2colw_128_5d_param_4];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r5, [cp_async_bulk_tensor_g2s_im2colw_128_5d_param_5];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r6, [cp_async_bulk_tensor_g2s_im2colw_128_5d_param_6];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r7, [cp_async_bulk_tensor_g2s_im2colw_128_5d_param_7];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs1, [cp_async_bulk_tensor_g2s_im2colw_128_5d_param_8];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs2, [cp_async_bulk_tensor_g2s_im2colw_128_5d_param_9];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs3, [cp_async_bulk_tensor_g2s_im2colw_128_5d_param_10];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd2, [cp_async_bulk_tensor_g2s_im2colw_128_5d_param_11];
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.5d.shared::cluster.global.im2col::w::128.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint [%r1], [%rd1, {%r3, %r4, %r5, %r6, %r7}], [%r2], {%rs1, %rs2}, %rs3, %rd2;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.5d.shared::cluster.global.im2col::w::128.mbarrier::complete_tx::bytes.multicast::cluster [%r1], [%rd1, {%r3, %r4, %r5, %r6, %r7}], [%r2], {%rs1, %rs2}, %rs3;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.5d.shared::cluster.global.im2col::w::128.mbarrier::complete_tx::bytes.L2::cache_hint [%r1], [%rd1, {%r3, %r4, %r5, %r6, %r7}], [%r2], {%rs1, %rs2}, %rd2;
@@ -418,18 +418,18 @@ define void @cp_async_bulk_tensor_g2s_im2colw_128_5d_cg1(ptr addrspace(7) %d, pt
; CHECK-PTX64-NEXT: .reg .b64 %rd<5>;
; CHECK-PTX64-EMPTY:
; CHECK-PTX64-NEXT: // %bb.0:
-; CHECK-PTX64-NEXT: ld.param.b64 %rd1, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg1_param_0];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd2, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg1_param_1];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd3, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg1_param_2];
-; CHECK-PTX64-NEXT: ld.param.b32 %r1, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg1_param_3];
-; CHECK-PTX64-NEXT: ld.param.b32 %r2, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg1_param_4];
-; CHECK-PTX64-NEXT: ld.param.b32 %r3, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg1_param_5];
-; CHECK-PTX64-NEXT: ld.param.b32 %r4, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg1_param_6];
-; CHECK-PTX64-NEXT: ld.param.b32 %r5, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg1_param_7];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs1, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg1_param_8];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs2, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg1_param_9];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs3, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg1_param_10];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd4, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg1_param_11];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd1, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg1_param_0];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd2, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg1_param_1];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd3, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg1_param_2];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r1, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg1_param_3];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r2, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg1_param_4];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r3, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg1_param_5];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r4, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg1_param_6];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r5, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg1_param_7];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs1, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg1_param_8];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs2, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg1_param_9];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs3, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg1_param_10];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd4, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg1_param_11];
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.5d.shared::cluster.global.im2col::w::128.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint.cta_group::1 [%rd1], [%rd3, {%r1, %r2, %r3, %r4, %r5}], [%rd2], {%rs1, %rs2}, %rs3, %rd4;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.5d.shared::cluster.global.im2col::w::128.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::1 [%rd1], [%rd3, {%r1, %r2, %r3, %r4, %r5}], [%rd2], {%rs1, %rs2}, %rs3;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.5d.shared::cluster.global.im2col::w::128.mbarrier::complete_tx::bytes.L2::cache_hint.cta_group::1 [%rd1], [%rd3, {%r1, %r2, %r3, %r4, %r5}], [%rd2], {%rs1, %rs2}, %rd4;
@@ -443,18 +443,18 @@ define void @cp_async_bulk_tensor_g2s_im2colw_128_5d_cg1(ptr addrspace(7) %d, pt
; CHECK-PTX-SHARED32-NEXT: .reg .b64 %rd<3>;
; CHECK-PTX-SHARED32-EMPTY:
; CHECK-PTX-SHARED32-NEXT: // %bb.0:
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r1, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg1_param_0];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r2, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg1_param_1];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd1, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg1_param_2];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r3, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg1_param_3];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r4, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg1_param_4];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r5, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg1_param_5];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r6, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg1_param_6];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r7, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg1_param_7];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs1, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg1_param_8];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs2, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg1_param_9];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs3, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg1_param_10];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd2, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg1_param_11];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r1, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg1_param_0];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r2, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg1_param_1];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd1, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg1_param_2];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r3, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg1_param_3];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r4, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg1_param_4];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r5, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg1_param_5];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r6, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg1_param_6];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r7, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg1_param_7];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs1, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg1_param_8];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs2, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg1_param_9];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs3, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg1_param_10];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd2, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg1_param_11];
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.5d.shared::cluster.global.im2col::w::128.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint.cta_group::1 [%r1], [%rd1, {%r3, %r4, %r5, %r6, %r7}], [%r2], {%rs1, %rs2}, %rs3, %rd2;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.5d.shared::cluster.global.im2col::w::128.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::1 [%r1], [%rd1, {%r3, %r4, %r5, %r6, %r7}], [%r2], {%rs1, %rs2}, %rs3;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.5d.shared::cluster.global.im2col::w::128.mbarrier::complete_tx::bytes.L2::cache_hint.cta_group::1 [%r1], [%rd1, {%r3, %r4, %r5, %r6, %r7}], [%r2], {%rs1, %rs2}, %rd2;
@@ -477,18 +477,18 @@ define void @cp_async_bulk_tensor_g2s_im2colw_128_5d_cg2(ptr addrspace(7) %d, pt
; CHECK-PTX64-NEXT: .reg .b64 %rd<5>;
; CHECK-PTX64-EMPTY:
; CHECK-PTX64-NEXT: // %bb.0:
-; CHECK-PTX64-NEXT: ld.param.b64 %rd1, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg2_param_0];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd2, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg2_param_1];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd3, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg2_param_2];
-; CHECK-PTX64-NEXT: ld.param.b32 %r1, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg2_param_3];
-; CHECK-PTX64-NEXT: ld.param.b32 %r2, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg2_param_4];
-; CHECK-PTX64-NEXT: ld.param.b32 %r3, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg2_param_5];
-; CHECK-PTX64-NEXT: ld.param.b32 %r4, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg2_param_6];
-; CHECK-PTX64-NEXT: ld.param.b32 %r5, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg2_param_7];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs1, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg2_param_8];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs2, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg2_param_9];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs3, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg2_param_10];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd4, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg2_param_11];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd1, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg2_param_0];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd2, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg2_param_1];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd3, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg2_param_2];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r1, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg2_param_3];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r2, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg2_param_4];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r3, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg2_param_5];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r4, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg2_param_6];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r5, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg2_param_7];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs1, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg2_param_8];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs2, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg2_param_9];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs3, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg2_param_10];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd4, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg2_param_11];
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.5d.shared::cluster.global.im2col::w::128.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint.cta_group::2 [%rd1], [%rd3, {%r1, %r2, %r3, %r4, %r5}], [%rd2], {%rs1, %rs2}, %rs3, %rd4;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.5d.shared::cluster.global.im2col::w::128.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::2 [%rd1], [%rd3, {%r1, %r2, %r3, %r4, %r5}], [%rd2], {%rs1, %rs2}, %rs3;
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.5d.shared::cluster.global.im2col::w::128.mbarrier::complete_tx::bytes.L2::cache_hint.cta_group::2 [%rd1], [%rd3, {%r1, %r2, %r3, %r4, %r5}], [%rd2], {%rs1, %rs2}, %rd4;
@@ -502,18 +502,18 @@ define void @cp_async_bulk_tensor_g2s_im2colw_128_5d_cg2(ptr addrspace(7) %d, pt
; CHECK-PTX-SHARED32-NEXT: .reg .b64 %rd<3>;
; CHECK-PTX-SHARED32-EMPTY:
; CHECK-PTX-SHARED32-NEXT: // %bb.0:
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r1, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg2_param_0];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r2, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg2_param_1];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd1, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg2_param_2];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r3, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg2_param_3];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r4, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg2_param_4];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r5, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg2_param_5];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r6, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg2_param_6];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r7, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg2_param_7];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs1, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg2_param_8];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs2, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg2_param_9];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs3, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg2_param_10];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd2, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg2_param_11];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r1, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg2_param_0];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r2, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg2_param_1];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd1, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg2_param_2];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r3, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg2_param_3];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r4, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg2_param_4];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r5, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg2_param_5];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r6, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg2_param_6];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r7, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg2_param_7];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs1, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg2_param_8];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs2, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg2_param_9];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs3, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg2_param_10];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd2, [cp_async_bulk_tensor_g2s_im2colw_128_5d_cg2_param_11];
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.5d.shared::cluster.global.im2col::w::128.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint.cta_group::2 [%r1], [%rd1, {%r3, %r4, %r5, %r6, %r7}], [%r2], {%rs1, %rs2}, %rs3, %rd2;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.5d.shared::cluster.global.im2col::w::128.mbarrier::complete_tx::bytes.multicast::cluster.cta_group::2 [%r1], [%rd1, {%r3, %r4, %r5, %r6, %r7}], [%r2], {%rs1, %rs2}, %rs3;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.5d.shared::cluster.global.im2col::w::128.mbarrier::complete_tx::bytes.L2::cache_hint.cta_group::2 [%r1], [%rd1, {%r3, %r4, %r5, %r6, %r7}], [%r2], {%rs1, %rs2}, %rd2;
diff --git a/llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s.ll b/llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s.ll
index 289716325b328..dd95134bb7573 100644
--- a/llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s.ll
+++ b/llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-g2s.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_90 -mattr=+ptx80| FileCheck --check-prefixes=CHECK-PTX64 %s
; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_90 -mattr=+ptx80 -target-abi=shortptr| FileCheck --check-prefixes=CHECK-PTX-SHARED32 %s
-; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_100f -mattr=+ptx88 | FileCheck --check-prefixes=CHECK-PTX64 %s
-; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_110f -mattr=+ptx90 | FileCheck --check-prefixes=CHECK-PTX64 %s
+; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_100f -mattr=+ptx88 | FileCheck --check-prefixes=CHECK-PTX64-PTX88 %s
+; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_110f -mattr=+ptx90 | FileCheck --check-prefixes=CHECK-PTX64-PTX88 %s
; RUN: %if ptxas-sm_90 && ptxas-isa-8.0 %{ llc < %s -mtriple=nvptx64 -mcpu=sm_90 -mattr=+ptx80| %ptxas-verify -arch=sm_90 %}
; RUN: %if ptxas-sm_90 && ptxas-isa-8.0 %{ llc < %s -mtriple=nvptx64 -mcpu=sm_90 -mattr=+ptx80 -target-abi=shortptr| %ptxas-verify -arch=sm_90 %}
; RUN: %if ptxas-sm_100f && ptxas-isa-8.8 %{ llc < %s -mtriple=nvptx64 -mcpu=sm_100f -mattr=+ptx88 | %ptxas-verify -arch=sm_100f %}
@@ -59,6 +59,25 @@ define void @cp_async_bulk_tensor_g2s_tile_1d(ptr addrspace(7) %d, ptr addrspace
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.1d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster [%r1], [%rd1, {%r3}], [%r2], %rs1;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.1d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint [%r1], [%rd1, {%r3}], [%r2], %rs1, %rd2;
; CHECK-PTX-SHARED32-NEXT: ret;
+;
+; CHECK-PTX64-PTX88-LABEL: cp_async_bulk_tensor_g2s_tile_1d(
+; CHECK-PTX64-PTX88: {
+; CHECK-PTX64-PTX88-NEXT: .reg .b16 %rs<2>;
+; CHECK-PTX64-PTX88-NEXT: .reg .b32 %r<2>;
+; CHECK-PTX64-PTX88-NEXT: .reg .b64 %rd<5>;
+; CHECK-PTX64-PTX88-EMPTY:
+; CHECK-PTX64-PTX88-NEXT: // %bb.0:
+; CHECK-PTX64-PTX88-NEXT: ld.param::func.b64 %rd1, [cp_async_bulk_tensor_g2s_tile_1d_param_0];
+; CHECK-PTX64-PTX88-NEXT: ld.param::func.b64 %rd2, [cp_async_bulk_tensor_g2s_tile_1d_param_1];
+; CHECK-PTX64-PTX88-NEXT: ld.param::func.b64 %rd3, [cp_async_bulk_tensor_g2s_tile_1d_param_2];
+; CHECK-PTX64-PTX88-NEXT: ld.param::func.b32 %r1, [cp_async_bulk_tensor_g2s_tile_1d_param_3];
+; CHECK-PTX64-PTX88-NEXT: ld.param::func.b16 %rs1, [cp_async_bulk_tensor_g2s_tile_1d_param_4];
+; CHECK-PTX64-PTX88-NEXT: ld.param::func.b64 %rd4, [cp_async_bulk_tensor_g2s_tile_1d_param_5];
+; CHECK-PTX64-PTX88-NEXT: cp.async.bulk.tensor.1d.shared::cluster.global.tile.mbarrier::complete_tx::bytes [%rd1], [%rd3, {%r1}], [%rd2];
+; CHECK-PTX64-PTX88-NEXT: cp.async.bulk.tensor.1d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.L2::cache_hint [%rd1], [%rd3, {%r1}], [%rd2], %rd4;
+; CHECK-PTX64-PTX88-NEXT: cp.async.bulk.tensor.1d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster [%rd1], [%rd3, {%r1}], [%rd2], %rs1;
+; CHECK-PTX64-PTX88-NEXT: cp.async.bulk.tensor.1d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint [%rd1], [%rd3, {%r1}], [%rd2], %rs1, %rd4;
+; CHECK-PTX64-PTX88-NEXT: ret;
tail call void @llvm.nvvm.cp.async.bulk.tensor.g2s.tile.1d(ptr addrspace(7) %d, ptr addrspace(3) %bar, ptr %tmap, i32 %d0, i16 %mc, i64 %ch, i1 0, i1 0)
tail call void @llvm.nvvm.cp.async.bulk.tensor.g2s.tile.1d(ptr addrspace(7) %d, ptr addrspace(3) %bar, ptr %tmap, i32 %d0, i16 %mc, i64 %ch, i1 0, i1 1)
@@ -110,6 +129,26 @@ define void @cp_async_bulk_tensor_g2s_tile_2d(ptr addrspace(7) %d, ptr addrspace
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.2d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster [%r1], [%rd1, {%r3, %r4}], [%r2], %rs1;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.2d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint [%r1], [%rd1, {%r3, %r4}], [%r2], %rs1, %rd2;
; CHECK-PTX-SHARED32-NEXT: ret;
+;
+; CHECK-PTX64-PTX88-LABEL: cp_async_bulk_tensor_g2s_tile_2d(
+; CHECK-PTX64-PTX88: {
+; CHECK-PTX64-PTX88-NEXT: .reg .b16 %rs<2>;
+; CHECK-PTX64-PTX88-NEXT: .reg .b32 %r<3>;
+; CHECK-PTX64-PTX88-NEXT: .reg .b64 %rd<5>;
+; CHECK-PTX64-PTX88-EMPTY:
+; CHECK-PTX64-PTX88-NEXT: // %bb.0:
+; CHECK-PTX64-PTX88-NEXT: ld.param::func.b64 %rd1, [cp_async_bulk_tensor_g2s_tile_2d_param_0];
+; CHECK-PTX64-PTX88-NEXT: ld.param::func.b64 %rd2, [cp_async_bulk_tensor_g2s_tile_2d_param_1];
+; CHECK-PTX64-PTX88-NEXT: ld.param::func.b64 %rd3, [cp_async_bulk_tensor_g2s_tile_2d_param_2];
+; CHECK-PTX64-PTX88-NEXT: ld.param::func.b32 %r1, [cp_async_bulk_tensor_g2s_tile_2d_param_3];
+; CHECK-PTX64-PTX88-NEXT: ld.param::func.b32 %r2, [cp_async_bulk_tensor_g2s_tile_2d_param_4];
+; CHECK-PTX64-PTX88-NEXT: ld.param::func.b16 %rs1, [cp_async_bulk_tensor_g2s_tile_2d_param_5];
+; CHECK-PTX64-PTX88-NEXT: ld.param::func.b64 %rd4, [cp_async_bulk_tensor_g2s_tile_2d_param_6];
+; CHECK-PTX64-PTX88-NEXT: cp.async.bulk.tensor.2d.shared::cluster.global.tile.mbarrier::complete_tx::bytes [%rd1], [%rd3, {%r1, %r2}], [%rd2];
+; CHECK-PTX64-PTX88-NEXT: cp.async.bulk.tensor.2d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.L2::cache_hint [%rd1], [%rd3, {%r1, %r2}], [%rd2], %rd4;
+; CHECK-PTX64-PTX88-NEXT: cp.async.bulk.tensor.2d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster [%rd1], [%rd3, {%r1, %r2}], [%rd2], %rs1;
+; CHECK-PTX64-PTX88-NEXT: cp.async.bulk.tensor.2d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint [%rd1], [%rd3, {%r1, %r2}], [%rd2], %rs1, %rd4;
+; CHECK-PTX64-PTX88-NEXT: ret;
tail call void @llvm.nvvm.cp.async.bulk.tensor.g2s.tile.2d(ptr addrspace(7) %d, ptr addrspace(3) %bar, ptr %tmap, i32 %d0, i32 %d1, i16 %mc, i64 %ch, i1 0, i1 0)
tail call void @llvm.nvvm.cp.async.bulk.tensor.g2s.tile.2d(ptr addrspace(7) %d, ptr addrspace(3) %bar, ptr %tmap, i32 %d0, i32 %d1, i16 %mc, i64 %ch, i1 0, i1 1)
@@ -163,6 +202,27 @@ define void @cp_async_bulk_tensor_g2s_tile_3d(ptr addrspace(7) %d, ptr addrspace
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.3d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster [%r1], [%rd1, {%r3, %r4, %r5}], [%r2], %rs1;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.3d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint [%r1], [%rd1, {%r3, %r4, %r5}], [%r2], %rs1, %rd2;
; CHECK-PTX-SHARED32-NEXT: ret;
+;
+; CHECK-PTX64-PTX88-LABEL: cp_async_bulk_tensor_g2s_tile_3d(
+; CHECK-PTX64-PTX88: {
+; CHECK-PTX64-PTX88-NEXT: .reg .b16 %rs<2>;
+; CHECK-PTX64-PTX88-NEXT: .reg .b32 %r<4>;
+; CHECK-PTX64-PTX88-NEXT: .reg .b64 %rd<5>;
+; CHECK-PTX64-PTX88-EMPTY:
+; CHECK-PTX64-PTX88-NEXT: // %bb.0:
+; CHECK-PTX64-PTX88-NEXT: ld.param::func.b64 %rd1, [cp_async_bulk_tensor_g2s_tile_3d_param_0];
+; CHECK-PTX64-PTX88-NEXT: ld.param::func.b64 %rd2, [cp_async_bulk_tensor_g2s_tile_3d_param_1];
+; CHECK-PTX64-PTX88-NEXT: ld.param::func.b64 %rd3, [cp_async_bulk_tensor_g2s_tile_3d_param_2];
+; CHECK-PTX64-PTX88-NEXT: ld.param::func.b32 %r1, [cp_async_bulk_tensor_g2s_tile_3d_param_3];
+; CHECK-PTX64-PTX88-NEXT: ld.param::func.b32 %r2, [cp_async_bulk_tensor_g2s_tile_3d_param_4];
+; CHECK-PTX64-PTX88-NEXT: ld.param::func.b32 %r3, [cp_async_bulk_tensor_g2s_tile_3d_param_5];
+; CHECK-PTX64-PTX88-NEXT: ld.param::func.b16 %rs1, [cp_async_bulk_tensor_g2s_tile_3d_param_6];
+; CHECK-PTX64-PTX88-NEXT: ld.param::func.b64 %rd4, [cp_async_bulk_tensor_g2s_tile_3d_param_7];
+; CHECK-PTX64-PTX88-NEXT: cp.async.bulk.tensor.3d.shared::cluster.global.tile.mbarrier::complete_tx::bytes [%rd1], [%rd3, {%r1, %r2, %r3}], [%rd2];
+; CHECK-PTX64-PTX88-NEXT: cp.async.bulk.tensor.3d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.L2::cache_hint [%rd1], [%rd3, {%r1, %r2, %r3}], [%rd2], %rd4;
+; CHECK-PTX64-PTX88-NEXT: cp.async.bulk.tensor.3d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster [%rd1], [%rd3, {%r1, %r2, %r3}], [%rd2], %rs1;
+; CHECK-PTX64-PTX88-NEXT: cp.async.bulk.tensor.3d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint [%rd1], [%rd3, {%r1, %r2, %r3}], [%rd2], %rs1, %rd4;
+; CHECK-PTX64-PTX88-NEXT: ret;
tail call void @llvm.nvvm.cp.async.bulk.tensor.g2s.tile.3d(ptr addrspace(7) %d, ptr addrspace(3) %bar, ptr %tmap, i32 %d0, i32 %d1, i32 %d2, i16 %mc, i64 %ch, i1 0, i1 0)
tail call void @llvm.nvvm.cp.async.bulk.tensor.g2s.tile.3d(ptr addrspace(7) %d, ptr addrspace(3) %bar, ptr %tmap, i32 %d0, i32 %d1, i32 %d2, i16 %mc, i64 %ch, i1 0, i1 1)
@@ -218,6 +278,28 @@ define void @cp_async_bulk_tensor_g2s_tile_4d(ptr addrspace(7) %d, ptr addrspace
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.4d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster [%r1], [%rd1, {%r3, %r4, %r5, %r6}], [%r2], %rs1;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.4d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint [%r1], [%rd1, {%r3, %r4, %r5, %r6}], [%r2], %rs1, %rd2;
; CHECK-PTX-SHARED32-NEXT: ret;
+;
+; CHECK-PTX64-PTX88-LABEL: cp_async_bulk_tensor_g2s_tile_4d(
+; CHECK-PTX64-PTX88: {
+; CHECK-PTX64-PTX88-NEXT: .reg .b16 %rs<2>;
+; CHECK-PTX64-PTX88-NEXT: .reg .b32 %r<5>;
+; CHECK-PTX64-PTX88-NEXT: .reg .b64 %rd<5>;
+; CHECK-PTX64-PTX88-EMPTY:
+; CHECK-PTX64-PTX88-NEXT: // %bb.0:
+; CHECK-PTX64-PTX88-NEXT: ld.param::func.b64 %rd1, [cp_async_bulk_tensor_g2s_tile_4d_param_0];
+; CHECK-PTX64-PTX88-NEXT: ld.param::func.b64 %rd2, [cp_async_bulk_tensor_g2s_tile_4d_param_1];
+; CHECK-PTX64-PTX88-NEXT: ld.param::func.b64 %rd3, [cp_async_bulk_tensor_g2s_tile_4d_param_2];
+; CHECK-PTX64-PTX88-NEXT: ld.param::func.b32 %r1, [cp_async_bulk_tensor_g2s_tile_4d_param_3];
+; CHECK-PTX64-PTX88-NEXT: ld.param::func.b32 %r2, [cp_async_bulk_tensor_g2s_tile_4d_param_4];
+; CHECK-PTX64-PTX88-NEXT: ld.param::func.b32 %r3, [cp_async_bulk_tensor_g2s_tile_4d_param_5];
+; CHECK-PTX64-PTX88-NEXT: ld.param::func.b32 %r4, [cp_async_bulk_tensor_g2s_tile_4d_param_6];
+; CHECK-PTX64-PTX88-NEXT: ld.param::func.b16 %rs1, [cp_async_bulk_tensor_g2s_tile_4d_param_7];
+; CHECK-PTX64-PTX88-NEXT: ld.param::func.b64 %rd4, [cp_async_bulk_tensor_g2s_tile_4d_param_8];
+; CHECK-PTX64-PTX88-NEXT: cp.async.bulk.tensor.4d.shared::cluster.global.tile.mbarrier::complete_tx::bytes [%rd1], [%rd3, {%r1, %r2, %r3, %r4}], [%rd2];
+; CHECK-PTX64-PTX88-NEXT: cp.async.bulk.tensor.4d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.L2::cache_hint [%rd1], [%rd3, {%r1, %r2, %r3, %r4}], [%rd2], %rd4;
+; CHECK-PTX64-PTX88-NEXT: cp.async.bulk.tensor.4d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster [%rd1], [%rd3, {%r1, %r2, %r3, %r4}], [%rd2], %rs1;
+; CHECK-PTX64-PTX88-NEXT: cp.async.bulk.tensor.4d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint [%rd1], [%rd3, {%r1, %r2, %r3, %r4}], [%rd2], %rs1, %rd4;
+; CHECK-PTX64-PTX88-NEXT: ret;
tail call void @llvm.nvvm.cp.async.bulk.tensor.g2s.tile.4d(ptr addrspace(7) %d, ptr addrspace(3) %bar, ptr %tmap, i32 %d0, i32 %d1, i32 %d2, i32 %d3, i16 %mc, i64 %ch, i1 0, i1 0)
tail call void @llvm.nvvm.cp.async.bulk.tensor.g2s.tile.4d(ptr addrspace(7) %d, ptr addrspace(3) %bar, ptr %tmap, i32 %d0, i32 %d1, i32 %d2, i32 %d3, i16 %mc, i64 %ch, i1 0, i1 1)
@@ -275,6 +357,29 @@ define void @cp_async_bulk_tensor_g2s_tile_5d(ptr addrspace(7) %d, ptr addrspace
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.5d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster [%r1], [%rd1, {%r3, %r4, %r5, %r6, %r7}], [%r2], %rs1;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.5d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint [%r1], [%rd1, {%r3, %r4, %r5, %r6, %r7}], [%r2], %rs1, %rd2;
; CHECK-PTX-SHARED32-NEXT: ret;
+;
+; CHECK-PTX64-PTX88-LABEL: cp_async_bulk_tensor_g2s_tile_5d(
+; CHECK-PTX64-PTX88: {
+; CHECK-PTX64-PTX88-NEXT: .reg .b16 %rs<2>;
+; CHECK-PTX64-PTX88-NEXT: .reg .b32 %r<6>;
+; CHECK-PTX64-PTX88-NEXT: .reg .b64 %rd<5>;
+; CHECK-PTX64-PTX88-EMPTY:
+; CHECK-PTX64-PTX88-NEXT: // %bb.0:
+; CHECK-PTX64-PTX88-NEXT: ld.param::func.b64 %rd1, [cp_async_bulk_tensor_g2s_tile_5d_param_0];
+; CHECK-PTX64-PTX88-NEXT: ld.param::func.b64 %rd2, [cp_async_bulk_tensor_g2s_tile_5d_param_1];
+; CHECK-PTX64-PTX88-NEXT: ld.param::func.b64 %rd3, [cp_async_bulk_tensor_g2s_tile_5d_param_2];
+; CHECK-PTX64-PTX88-NEXT: ld.param::func.b32 %r1, [cp_async_bulk_tensor_g2s_tile_5d_param_3];
+; CHECK-PTX64-PTX88-NEXT: ld.param::func.b32 %r2, [cp_async_bulk_tensor_g2s_tile_5d_param_4];
+; CHECK-PTX64-PTX88-NEXT: ld.param::func.b32 %r3, [cp_async_bulk_tensor_g2s_tile_5d_param_5];
+; CHECK-PTX64-PTX88-NEXT: ld.param::func.b32 %r4, [cp_async_bulk_tensor_g2s_tile_5d_param_6];
+; CHECK-PTX64-PTX88-NEXT: ld.param::func.b32 %r5, [cp_async_bulk_tensor_g2s_tile_5d_param_7];
+; CHECK-PTX64-PTX88-NEXT: ld.param::func.b16 %rs1, [cp_async_bulk_tensor_g2s_tile_5d_param_8];
+; CHECK-PTX64-PTX88-NEXT: ld.param::func.b64 %rd4, [cp_async_bulk_tensor_g2s_tile_5d_param_9];
+; CHECK-PTX64-PTX88-NEXT: cp.async.bulk.tensor.5d.shared::cluster.global.tile.mbarrier::complete_tx::bytes [%rd1], [%rd3, {%r1, %r2, %r3, %r4, %r5}], [%rd2];
+; CHECK-PTX64-PTX88-NEXT: cp.async.bulk.tensor.5d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.L2::cache_hint [%rd1], [%rd3, {%r1, %r2, %r3, %r4, %r5}], [%rd2], %rd4;
+; CHECK-PTX64-PTX88-NEXT: cp.async.bulk.tensor.5d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster [%rd1], [%rd3, {%r1, %r2, %r3, %r4, %r5}], [%rd2], %rs1;
+; CHECK-PTX64-PTX88-NEXT: cp.async.bulk.tensor.5d.shared::cluster.global.tile.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint [%rd1], [%rd3, {%r1, %r2, %r3, %r4, %r5}], [%rd2], %rs1, %rd4;
+; CHECK-PTX64-PTX88-NEXT: ret;
tail call void @llvm.nvvm.cp.async.bulk.tensor.g2s.tile.5d(ptr addrspace(7) %d, ptr addrspace(3) %bar, ptr %tmap, i32 %d0, i32 %d1, i32 %d2, i32 %d3, i32 %d4, i16 %mc, i64 %ch, i1 0, i1 0)
tail call void @llvm.nvvm.cp.async.bulk.tensor.g2s.tile.5d(ptr addrspace(7) %d, ptr addrspace(3) %bar, ptr %tmap, i32 %d0, i32 %d1, i32 %d2, i32 %d3, i32 %d4, i16 %mc, i64 %ch, i1 0, i1 1)
@@ -330,6 +435,28 @@ define void @cp_async_bulk_tensor_g2s_im2col_3d(ptr addrspace(7) %d, ptr addrspa
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.3d.shared::cluster.global.im2col.mbarrier::complete_tx::bytes.multicast::cluster [%r1], [%rd1, {%r3, %r4, %r5}], [%r2], {%rs1}, %rs2;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.3d.shared::cluster.global.im2col.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint [%r1], [%rd1, {%r3, %r4, %r5}], [%r2], {%rs1}, %rs2, %rd2;
; CHECK-PTX-SHARED32-NEXT: ret;
+;
+; CHECK-PTX64-PTX88-LABEL: cp_async_bulk_tensor_g2s_im2col_3d(
+; CHECK-PTX64-PTX88: {
+; CHECK-PTX64-PTX88-NEXT: .reg .b16 %rs<3>;
+; CHECK-PTX64-PTX88-NEXT: .reg .b32 %r<4>;
+; CHECK-PTX64-PTX88-NEXT: .reg .b64 %rd<5>;
+; CHECK-PTX64-PTX88-EMPTY:
+; CHECK-PTX64-PTX88-NEXT: // %bb.0:
+; CHECK-PTX64-PTX88-NEXT: ld.param::func.b64 %rd1, [cp_async_bulk_tensor_g2s_im2col_3d_param_0];
+; CHECK-PTX64-PTX88-NEXT: ld.param::func.b64 %rd2, [cp_async_bulk_tensor_g2s_im2col_3d_param_1];
+; CHECK-PTX64-PTX88-NEXT: ld.param::func.b64 %rd3, [cp_async_bulk_tensor_g2s_im2col_3d_param_2];
+; CHECK-PTX64-PTX88-NEXT: ld.param::func.b32 %r1, [cp_async_bulk_tensor_g2s_im2col_3d_param_3];
+; CHECK-PTX64-PTX88-NEXT: ld.param::func.b32 %r2, [cp_async_bulk_tensor_g2s_im2col_3d_param_4];
+; CHECK-PTX64-PTX88-NEXT: ld.param::func.b32 %r3, [cp_async_bulk_tensor_g2s_im2col_3d_param_5];
+; CHECK-PTX64-PTX88-NEXT: ld.param::func.b16 %rs1, [cp_async_bulk_tensor_g2s_im2col_3d_param_6];
+; CHECK-PTX64-PTX88-NEXT: ld.param::func.b16 %rs2, [cp_async_bulk_tensor_g2s_im2col_3d_param_7];
+; CHECK-PTX64-PTX88-NEXT: ld.param::func.b64 %rd4, [cp_async_bulk_tensor_g2s_im2col_3d_param_8];
+; CHECK-PTX64-PTX88-NEXT: cp.async.bulk.tensor.3d.shared::cluster.global.im2col.mbarrier::complete_tx::bytes [%rd1], [%rd3, {%r1, %r2, %r3}], [%rd2], {%rs1};
+; CHECK-PTX64-PTX88-NEXT: cp.async.bulk.tensor.3d.shared::cluster.global.im2col.mbarrier::complete_tx::bytes.L2::cache_hint [%rd1], [%rd3, {%r1, %r2, %r3}], [%rd2], {%rs1}, %rd4;
+; CHECK-PTX64-PTX88-NEXT: cp.async.bulk.tensor.3d.shared::cluster.global.im2col.mbarrier::complete_tx::bytes.multicast::cluster [%rd1], [%rd3, {%r1, %r2, %r3}], [%rd2], {%rs1}, %rs2;
+; CHECK-PTX64-PTX88-NEXT: cp.async.bulk.tensor.3d.shared::cluster.global.im2col.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint [%rd1], [%rd3, {%r1, %r2, %r3}], [%rd2], {%rs1}, %rs2, %rd4;
+; CHECK-PTX64-PTX88-NEXT: ret;
tail call void @llvm.nvvm.cp.async.bulk.tensor.g2s.im2col.3d(ptr addrspace(7) %d, ptr addrspace(3) %bar, ptr %tmap, i32 %d0, i32 %d1, i32 %d2, i16 %im2col0, i16 %mc, i64 %ch, i1 0, i1 0)
tail call void @llvm.nvvm.cp.async.bulk.tensor.g2s.im2col.3d(ptr addrspace(7) %d, ptr addrspace(3) %bar, ptr %tmap, i32 %d0, i32 %d1, i32 %d2, i16 %im2col0, i16 %mc, i64 %ch, i1 0, i1 1)
@@ -389,6 +516,30 @@ define void @cp_async_bulk_tensor_g2s_im2col_4d(ptr addrspace(7) %d, ptr addrspa
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.4d.shared::cluster.global.im2col.mbarrier::complete_tx::bytes.multicast::cluster [%r1], [%rd1, {%r3, %r4, %r5, %r6}], [%r2], {%rs1, %rs2}, %rs3;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.4d.shared::cluster.global.im2col.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint [%r1], [%rd1, {%r3, %r4, %r5, %r6}], [%r2], {%rs1, %rs2}, %rs3, %rd2;
; CHECK-PTX-SHARED32-NEXT: ret;
+;
+; CHECK-PTX64-PTX88-LABEL: cp_async_bulk_tensor_g2s_im2col_4d(
+; CHECK-PTX64-PTX88: {
+; CHECK-PTX64-PTX88-NEXT: .reg .b16 %rs<4>;
+; CHECK-PTX64-PTX88-NEXT: .reg .b32 %r<5>;
+; CHECK-PTX64-PTX88-NEXT: .reg .b64 %rd<5>;
+; CHECK-PTX64-PTX88-EMPTY:
+; CHECK-PTX64-PTX88-NEXT: // %bb.0:
+; CHECK-PTX64-PTX88-NEXT: ld.param::func.b64 %rd1, [cp_async_bulk_tensor_g2s_im2col_4d_param_0];
+; CHECK-PTX64-PTX88-NEXT: ld.param::func.b64 %rd2, [cp_async_bulk_tensor_g2s_im2col_4d_param_1];
+; CHECK-PTX64-PTX88-NEXT: ld.param::func.b64 %rd3, [cp_async_bulk_tensor_g2s_im2col_4d_param_2];
+; CHECK-PTX64-PTX88-NEXT: ld.param::func.b32 %r1, [cp_async_bulk_tensor_g2s_im2col_4d_param_3];
+; CHECK-PTX64-PTX88-NEXT: ld.param::func.b32 %r2, [cp_async_bulk_tensor_g2s_im2col_4d_param_4];
+; CHECK-PTX64-PTX88-NEXT: ld.param::func.b32 %r3, [cp_async_bulk_tensor_g2s_im2col_4d_param_5];
+; CHECK-PTX64-PTX88-NEXT: ld.param::func.b32 %r4, [cp_async_bulk_tensor_g2s_im2col_4d_param_6];
+; CHECK-PTX64-PTX88-NEXT: ld.param::func.b16 %rs1, [cp_async_bulk_tensor_g2s_im2col_4d_param_7];
+; CHECK-PTX64-PTX88-NEXT: ld.param::func.b16 %rs2, [cp_async_bulk_tensor_g2s_im2col_4d_param_8];
+; CHECK-PTX64-PTX88-NEXT: ld.param::func.b16 %rs3, [cp_async_bulk_tensor_g2s_im2col_4d_param_9];
+; CHECK-PTX64-PTX88-NEXT: ld.param::func.b64 %rd4, [cp_async_bulk_tensor_g2s_im2col_4d_param_10];
+; CHECK-PTX64-PTX88-NEXT: cp.async.bulk.tensor.4d.shared::cluster.global.im2col.mbarrier::complete_tx::bytes [%rd1], [%rd3, {%r1, %r2, %r3, %r4}], [%rd2], {%rs1, %rs2};
+; CHECK-PTX64-PTX88-NEXT: cp.async.bulk.tensor.4d.shared::cluster.global.im2col.mbarrier::complete_tx::bytes.L2::cache_hint [%rd1], [%rd3, {%r1, %r2, %r3, %r4}], [%rd2], {%rs1, %rs2}, %rd4;
+; CHECK-PTX64-PTX88-NEXT: cp.async.bulk.tensor.4d.shared::cluster.global.im2col.mbarrier::complete_tx::bytes.multicast::cluster [%rd1], [%rd3, {%r1, %r2, %r3, %r4}], [%rd2], {%rs1, %rs2}, %rs3;
+; CHECK-PTX64-PTX88-NEXT: cp.async.bulk.tensor.4d.shared::cluster.global.im2col.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint [%rd1], [%rd3, {%r1, %r2, %r3, %r4}], [%rd2], {%rs1, %rs2}, %rs3, %rd4;
+; CHECK-PTX64-PTX88-NEXT: ret;
tail call void @llvm.nvvm.cp.async.bulk.tensor.g2s.im2col.4d(ptr addrspace(7) %d, ptr addrspace(3) %bar, ptr %tmap, i32 %d0, i32 %d1, i32 %d2, i32 %d3, i16 %im2col0, i16 %im2col1, i16 %mc, i64 %ch, i1 0, i1 0)
tail call void @llvm.nvvm.cp.async.bulk.tensor.g2s.im2col.4d(ptr addrspace(7) %d, ptr addrspace(3) %bar, ptr %tmap, i32 %d0, i32 %d1, i32 %d2, i32 %d3, i16 %im2col0, i16 %im2col1, i16 %mc, i64 %ch, i1 0, i1 1)
@@ -452,6 +603,32 @@ define void @cp_async_bulk_tensor_g2s_im2col_5d(ptr addrspace(7) %d, ptr addrspa
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.5d.shared::cluster.global.im2col.mbarrier::complete_tx::bytes.multicast::cluster [%r1], [%rd1, {%r3, %r4, %r5, %r6, %r7}], [%r2], {%rs1, %rs2, %rs3}, %rs4;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.5d.shared::cluster.global.im2col.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint [%r1], [%rd1, {%r3, %r4, %r5, %r6, %r7}], [%r2], {%rs1, %rs2, %rs3}, %rs4, %rd2;
; CHECK-PTX-SHARED32-NEXT: ret;
+;
+; CHECK-PTX64-PTX88-LABEL: cp_async_bulk_tensor_g2s_im2col_5d(
+; CHECK-PTX64-PTX88: {
+; CHECK-PTX64-PTX88-NEXT: .reg .b16 %rs<5>;
+; CHECK-PTX64-PTX88-NEXT: .reg .b32 %r<6>;
+; CHECK-PTX64-PTX88-NEXT: .reg .b64 %rd<5>;
+; CHECK-PTX64-PTX88-EMPTY:
+; CHECK-PTX64-PTX88-NEXT: // %bb.0:
+; CHECK-PTX64-PTX88-NEXT: ld.param::func.b64 %rd1, [cp_async_bulk_tensor_g2s_im2col_5d_param_0];
+; CHECK-PTX64-PTX88-NEXT: ld.param::func.b64 %rd2, [cp_async_bulk_tensor_g2s_im2col_5d_param_1];
+; CHECK-PTX64-PTX88-NEXT: ld.param::func.b64 %rd3, [cp_async_bulk_tensor_g2s_im2col_5d_param_2];
+; CHECK-PTX64-PTX88-NEXT: ld.param::func.b32 %r1, [cp_async_bulk_tensor_g2s_im2col_5d_param_3];
+; CHECK-PTX64-PTX88-NEXT: ld.param::func.b32 %r2, [cp_async_bulk_tensor_g2s_im2col_5d_param_4];
+; CHECK-PTX64-PTX88-NEXT: ld.param::func.b32 %r3, [cp_async_bulk_tensor_g2s_im2col_5d_param_5];
+; CHECK-PTX64-PTX88-NEXT: ld.param::func.b32 %r4, [cp_async_bulk_tensor_g2s_im2col_5d_param_6];
+; CHECK-PTX64-PTX88-NEXT: ld.param::func.b32 %r5, [cp_async_bulk_tensor_g2s_im2col_5d_param_7];
+; CHECK-PTX64-PTX88-NEXT: ld.param::func.b16 %rs1, [cp_async_bulk_tensor_g2s_im2col_5d_param_8];
+; CHECK-PTX64-PTX88-NEXT: ld.param::func.b16 %rs2, [cp_async_bulk_tensor_g2s_im2col_5d_param_9];
+; CHECK-PTX64-PTX88-NEXT: ld.param::func.b16 %rs3, [cp_async_bulk_tensor_g2s_im2col_5d_param_10];
+; CHECK-PTX64-PTX88-NEXT: ld.param::func.b16 %rs4, [cp_async_bulk_tensor_g2s_im2col_5d_param_11];
+; CHECK-PTX64-PTX88-NEXT: ld.param::func.b64 %rd4, [cp_async_bulk_tensor_g2s_im2col_5d_param_12];
+; CHECK-PTX64-PTX88-NEXT: cp.async.bulk.tensor.5d.shared::cluster.global.im2col.mbarrier::complete_tx::bytes [%rd1], [%rd3, {%r1, %r2, %r3, %r4, %r5}], [%rd2], {%rs1, %rs2, %rs3};
+; CHECK-PTX64-PTX88-NEXT: cp.async.bulk.tensor.5d.shared::cluster.global.im2col.mbarrier::complete_tx::bytes.L2::cache_hint [%rd1], [%rd3, {%r1, %r2, %r3, %r4, %r5}], [%rd2], {%rs1, %rs2, %rs3}, %rd4;
+; CHECK-PTX64-PTX88-NEXT: cp.async.bulk.tensor.5d.shared::cluster.global.im2col.mbarrier::complete_tx::bytes.multicast::cluster [%rd1], [%rd3, {%r1, %r2, %r3, %r4, %r5}], [%rd2], {%rs1, %rs2, %rs3}, %rs4;
+; CHECK-PTX64-PTX88-NEXT: cp.async.bulk.tensor.5d.shared::cluster.global.im2col.mbarrier::complete_tx::bytes.multicast::cluster.L2::cache_hint [%rd1], [%rd3, {%r1, %r2, %r3, %r4, %r5}], [%rd2], {%rs1, %rs2, %rs3}, %rs4, %rd4;
+; CHECK-PTX64-PTX88-NEXT: ret;
tail call void @llvm.nvvm.cp.async.bulk.tensor.g2s.im2col.5d(ptr addrspace(7) %d, ptr addrspace(3) %bar, ptr %tmap, i32 %d0, i32 %d1, i32 %d2, i32 %d3, i32 %d4, i16 %im2col0, i16 %im2col1, i16 %im2col2, i16 %mc, i64 %ch, i1 0, i1 0)
tail call void @llvm.nvvm.cp.async.bulk.tensor.g2s.im2col.5d(ptr addrspace(7) %d, ptr addrspace(3) %bar, ptr %tmap, i32 %d0, i32 %d1, i32 %d2, i32 %d3, i32 %d4, i16 %im2col0, i16 %im2col1, i16 %im2col2, i16 %mc, i64 %ch, i1 0, i1 1)
diff --git a/llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-prefetch-sm100a.ll b/llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-prefetch-sm100a.ll
index 246d4c1d64240..17d1226a916b9 100644
--- a/llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-prefetch-sm100a.ll
+++ b/llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-prefetch-sm100a.ll
@@ -22,13 +22,13 @@ define void @test_cp_async_bulk_tensor_prefetch_3d(i32 %flag, ptr %tmap, i32 %d0
; CHECK-PTX64-NEXT: .reg .b64 %rd<3>;
; CHECK-PTX64-EMPTY:
; CHECK-PTX64-NEXT: // %bb.0:
-; CHECK-PTX64-NEXT: ld.param.b64 %rd1, [test_cp_async_bulk_tensor_prefetch_3d_param_1];
-; CHECK-PTX64-NEXT: ld.param.b32 %r1, [test_cp_async_bulk_tensor_prefetch_3d_param_2];
-; CHECK-PTX64-NEXT: ld.param.b32 %r2, [test_cp_async_bulk_tensor_prefetch_3d_param_3];
-; CHECK-PTX64-NEXT: ld.param.b32 %r3, [test_cp_async_bulk_tensor_prefetch_3d_param_4];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs1, [test_cp_async_bulk_tensor_prefetch_3d_param_5];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs2, [test_cp_async_bulk_tensor_prefetch_3d_param_6];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd2, [test_cp_async_bulk_tensor_prefetch_3d_param_7];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd1, [test_cp_async_bulk_tensor_prefetch_3d_param_1];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r1, [test_cp_async_bulk_tensor_prefetch_3d_param_2];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r2, [test_cp_async_bulk_tensor_prefetch_3d_param_3];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r3, [test_cp_async_bulk_tensor_prefetch_3d_param_4];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs1, [test_cp_async_bulk_tensor_prefetch_3d_param_5];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs2, [test_cp_async_bulk_tensor_prefetch_3d_param_6];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd2, [test_cp_async_bulk_tensor_prefetch_3d_param_7];
; CHECK-PTX64-NEXT: cp.async.bulk.prefetch.tensor.3d.L2.global.im2col::w [%rd1, {%r1, %r2, %r3}], {%rs1, %rs2};
; CHECK-PTX64-NEXT: cp.async.bulk.prefetch.tensor.3d.L2.global.im2col::w.L2::cache_hint [%rd1, {%r1, %r2, %r3}], {%rs1, %rs2}, %rd2;
; CHECK-PTX64-NEXT: cp.async.bulk.prefetch.tensor.3d.L2.global.im2col::w::128 [%rd1, {%r1, %r2, %r3}], {%rs1, %rs2};
@@ -42,13 +42,13 @@ define void @test_cp_async_bulk_tensor_prefetch_3d(i32 %flag, ptr %tmap, i32 %d0
; CHECK-PTX-SHARED32-NEXT: .reg .b64 %rd<3>;
; CHECK-PTX-SHARED32-EMPTY:
; CHECK-PTX-SHARED32-NEXT: // %bb.0:
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd1, [test_cp_async_bulk_tensor_prefetch_3d_param_1];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r1, [test_cp_async_bulk_tensor_prefetch_3d_param_2];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r2, [test_cp_async_bulk_tensor_prefetch_3d_param_3];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r3, [test_cp_async_bulk_tensor_prefetch_3d_param_4];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs1, [test_cp_async_bulk_tensor_prefetch_3d_param_5];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs2, [test_cp_async_bulk_tensor_prefetch_3d_param_6];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd2, [test_cp_async_bulk_tensor_prefetch_3d_param_7];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd1, [test_cp_async_bulk_tensor_prefetch_3d_param_1];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r1, [test_cp_async_bulk_tensor_prefetch_3d_param_2];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r2, [test_cp_async_bulk_tensor_prefetch_3d_param_3];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r3, [test_cp_async_bulk_tensor_prefetch_3d_param_4];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs1, [test_cp_async_bulk_tensor_prefetch_3d_param_5];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs2, [test_cp_async_bulk_tensor_prefetch_3d_param_6];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd2, [test_cp_async_bulk_tensor_prefetch_3d_param_7];
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.prefetch.tensor.3d.L2.global.im2col::w [%rd1, {%r1, %r2, %r3}], {%rs1, %rs2};
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.prefetch.tensor.3d.L2.global.im2col::w.L2::cache_hint [%rd1, {%r1, %r2, %r3}], {%rs1, %rs2}, %rd2;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.prefetch.tensor.3d.L2.global.im2col::w::128 [%rd1, {%r1, %r2, %r3}], {%rs1, %rs2};
@@ -70,14 +70,14 @@ define void @test_cp_async_bulk_tensor_prefetch_4d(i32 %flag, ptr %tmap, i32 %d0
; CHECK-PTX64-NEXT: .reg .b64 %rd<3>;
; CHECK-PTX64-EMPTY:
; CHECK-PTX64-NEXT: // %bb.0:
-; CHECK-PTX64-NEXT: ld.param.b64 %rd1, [test_cp_async_bulk_tensor_prefetch_4d_param_1];
-; CHECK-PTX64-NEXT: ld.param.b32 %r1, [test_cp_async_bulk_tensor_prefetch_4d_param_2];
-; CHECK-PTX64-NEXT: ld.param.b32 %r2, [test_cp_async_bulk_tensor_prefetch_4d_param_3];
-; CHECK-PTX64-NEXT: ld.param.b32 %r3, [test_cp_async_bulk_tensor_prefetch_4d_param_4];
-; CHECK-PTX64-NEXT: ld.param.b32 %r4, [test_cp_async_bulk_tensor_prefetch_4d_param_5];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs1, [test_cp_async_bulk_tensor_prefetch_4d_param_6];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs2, [test_cp_async_bulk_tensor_prefetch_4d_param_7];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd2, [test_cp_async_bulk_tensor_prefetch_4d_param_8];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd1, [test_cp_async_bulk_tensor_prefetch_4d_param_1];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r1, [test_cp_async_bulk_tensor_prefetch_4d_param_2];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r2, [test_cp_async_bulk_tensor_prefetch_4d_param_3];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r3, [test_cp_async_bulk_tensor_prefetch_4d_param_4];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r4, [test_cp_async_bulk_tensor_prefetch_4d_param_5];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs1, [test_cp_async_bulk_tensor_prefetch_4d_param_6];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs2, [test_cp_async_bulk_tensor_prefetch_4d_param_7];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd2, [test_cp_async_bulk_tensor_prefetch_4d_param_8];
; CHECK-PTX64-NEXT: cp.async.bulk.prefetch.tensor.4d.L2.global.im2col::w [%rd1, {%r1, %r2, %r3, %r4}], {%rs1, %rs2};
; CHECK-PTX64-NEXT: cp.async.bulk.prefetch.tensor.4d.L2.global.im2col::w.L2::cache_hint [%rd1, {%r1, %r2, %r3, %r4}], {%rs1, %rs2}, %rd2;
; CHECK-PTX64-NEXT: cp.async.bulk.prefetch.tensor.4d.L2.global.im2col::w::128 [%rd1, {%r1, %r2, %r3, %r4}], {%rs1, %rs2};
@@ -91,14 +91,14 @@ define void @test_cp_async_bulk_tensor_prefetch_4d(i32 %flag, ptr %tmap, i32 %d0
; CHECK-PTX-SHARED32-NEXT: .reg .b64 %rd<3>;
; CHECK-PTX-SHARED32-EMPTY:
; CHECK-PTX-SHARED32-NEXT: // %bb.0:
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd1, [test_cp_async_bulk_tensor_prefetch_4d_param_1];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r1, [test_cp_async_bulk_tensor_prefetch_4d_param_2];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r2, [test_cp_async_bulk_tensor_prefetch_4d_param_3];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r3, [test_cp_async_bulk_tensor_prefetch_4d_param_4];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r4, [test_cp_async_bulk_tensor_prefetch_4d_param_5];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs1, [test_cp_async_bulk_tensor_prefetch_4d_param_6];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs2, [test_cp_async_bulk_tensor_prefetch_4d_param_7];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd2, [test_cp_async_bulk_tensor_prefetch_4d_param_8];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd1, [test_cp_async_bulk_tensor_prefetch_4d_param_1];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r1, [test_cp_async_bulk_tensor_prefetch_4d_param_2];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r2, [test_cp_async_bulk_tensor_prefetch_4d_param_3];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r3, [test_cp_async_bulk_tensor_prefetch_4d_param_4];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r4, [test_cp_async_bulk_tensor_prefetch_4d_param_5];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs1, [test_cp_async_bulk_tensor_prefetch_4d_param_6];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs2, [test_cp_async_bulk_tensor_prefetch_4d_param_7];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd2, [test_cp_async_bulk_tensor_prefetch_4d_param_8];
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.prefetch.tensor.4d.L2.global.im2col::w [%rd1, {%r1, %r2, %r3, %r4}], {%rs1, %rs2};
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.prefetch.tensor.4d.L2.global.im2col::w.L2::cache_hint [%rd1, {%r1, %r2, %r3, %r4}], {%rs1, %rs2}, %rd2;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.prefetch.tensor.4d.L2.global.im2col::w::128 [%rd1, {%r1, %r2, %r3, %r4}], {%rs1, %rs2};
@@ -120,15 +120,15 @@ define void @test_cp_async_bulk_tensor_prefetch_5d(i32 %flag, ptr %tmap, i32 %d0
; CHECK-PTX64-NEXT: .reg .b64 %rd<3>;
; CHECK-PTX64-EMPTY:
; CHECK-PTX64-NEXT: // %bb.0:
-; CHECK-PTX64-NEXT: ld.param.b64 %rd1, [test_cp_async_bulk_tensor_prefetch_5d_param_1];
-; CHECK-PTX64-NEXT: ld.param.b32 %r1, [test_cp_async_bulk_tensor_prefetch_5d_param_2];
-; CHECK-PTX64-NEXT: ld.param.b32 %r2, [test_cp_async_bulk_tensor_prefetch_5d_param_3];
-; CHECK-PTX64-NEXT: ld.param.b32 %r3, [test_cp_async_bulk_tensor_prefetch_5d_param_4];
-; CHECK-PTX64-NEXT: ld.param.b32 %r4, [test_cp_async_bulk_tensor_prefetch_5d_param_5];
-; CHECK-PTX64-NEXT: ld.param.b32 %r5, [test_cp_async_bulk_tensor_prefetch_5d_param_6];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs1, [test_cp_async_bulk_tensor_prefetch_5d_param_7];
-; CHECK-PTX64-NEXT: ld.param.b16 %rs2, [test_cp_async_bulk_tensor_prefetch_5d_param_8];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd2, [test_cp_async_bulk_tensor_prefetch_5d_param_9];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd1, [test_cp_async_bulk_tensor_prefetch_5d_param_1];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r1, [test_cp_async_bulk_tensor_prefetch_5d_param_2];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r2, [test_cp_async_bulk_tensor_prefetch_5d_param_3];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r3, [test_cp_async_bulk_tensor_prefetch_5d_param_4];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r4, [test_cp_async_bulk_tensor_prefetch_5d_param_5];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r5, [test_cp_async_bulk_tensor_prefetch_5d_param_6];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs1, [test_cp_async_bulk_tensor_prefetch_5d_param_7];
+; CHECK-PTX64-NEXT: ld.param::func.b16 %rs2, [test_cp_async_bulk_tensor_prefetch_5d_param_8];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd2, [test_cp_async_bulk_tensor_prefetch_5d_param_9];
; CHECK-PTX64-NEXT: cp.async.bulk.prefetch.tensor.5d.L2.global.im2col::w [%rd1, {%r1, %r2, %r3, %r4, %r5}], {%rs1, %rs2};
; CHECK-PTX64-NEXT: cp.async.bulk.prefetch.tensor.5d.L2.global.im2col::w.L2::cache_hint [%rd1, {%r1, %r2, %r3, %r4, %r5}], {%rs1, %rs2}, %rd2;
; CHECK-PTX64-NEXT: cp.async.bulk.prefetch.tensor.5d.L2.global.im2col::w::128 [%rd1, {%r1, %r2, %r3, %r4, %r5}], {%rs1, %rs2};
@@ -142,15 +142,15 @@ define void @test_cp_async_bulk_tensor_prefetch_5d(i32 %flag, ptr %tmap, i32 %d0
; CHECK-PTX-SHARED32-NEXT: .reg .b64 %rd<3>;
; CHECK-PTX-SHARED32-EMPTY:
; CHECK-PTX-SHARED32-NEXT: // %bb.0:
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd1, [test_cp_async_bulk_tensor_prefetch_5d_param_1];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r1, [test_cp_async_bulk_tensor_prefetch_5d_param_2];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r2, [test_cp_async_bulk_tensor_prefetch_5d_param_3];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r3, [test_cp_async_bulk_tensor_prefetch_5d_param_4];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r4, [test_cp_async_bulk_tensor_prefetch_5d_param_5];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r5, [test_cp_async_bulk_tensor_prefetch_5d_param_6];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs1, [test_cp_async_bulk_tensor_prefetch_5d_param_7];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b16 %rs2, [test_cp_async_bulk_tensor_prefetch_5d_param_8];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd2, [test_cp_async_bulk_tensor_prefetch_5d_param_9];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd1, [test_cp_async_bulk_tensor_prefetch_5d_param_1];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r1, [test_cp_async_bulk_tensor_prefetch_5d_param_2];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r2, [test_cp_async_bulk_tensor_prefetch_5d_param_3];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r3, [test_cp_async_bulk_tensor_prefetch_5d_param_4];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r4, [test_cp_async_bulk_tensor_prefetch_5d_param_5];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r5, [test_cp_async_bulk_tensor_prefetch_5d_param_6];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs1, [test_cp_async_bulk_tensor_prefetch_5d_param_7];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b16 %rs2, [test_cp_async_bulk_tensor_prefetch_5d_param_8];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd2, [test_cp_async_bulk_tensor_prefetch_5d_param_9];
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.prefetch.tensor.5d.L2.global.im2col::w [%rd1, {%r1, %r2, %r3, %r4, %r5}], {%rs1, %rs2};
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.prefetch.tensor.5d.L2.global.im2col::w.L2::cache_hint [%rd1, {%r1, %r2, %r3, %r4, %r5}], {%rs1, %rs2}, %rd2;
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.prefetch.tensor.5d.L2.global.im2col::w::128 [%rd1, {%r1, %r2, %r3, %r4, %r5}], {%rs1, %rs2};
@@ -165,6 +165,39 @@ define void @test_cp_async_bulk_tensor_prefetch_5d(i32 %flag, ptr %tmap, i32 %d0
}
define void @test_cp_async_bulk_tensor_prefetch_tile_gather4_2d(ptr %tmap, i32 %d0, i32 %d1, i32 %d2, i32 %d3, i32 %d4, i64 %ch) {
+; CHECK-PTX64-LABEL: test_cp_async_bulk_tensor_prefetch_tile_gather4_2d(
+; CHECK-PTX64: {
+; CHECK-PTX64-NEXT: .reg .b32 %r<6>;
+; CHECK-PTX64-NEXT: .reg .b64 %rd<3>;
+; CHECK-PTX64-EMPTY:
+; CHECK-PTX64-NEXT: // %bb.0:
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd1, [test_cp_async_bulk_tensor_prefetch_tile_gather4_2d_param_0];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r1, [test_cp_async_bulk_tensor_prefetch_tile_gather4_2d_param_1];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r2, [test_cp_async_bulk_tensor_prefetch_tile_gather4_2d_param_2];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r3, [test_cp_async_bulk_tensor_prefetch_tile_gather4_2d_param_3];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r4, [test_cp_async_bulk_tensor_prefetch_tile_gather4_2d_param_4];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r5, [test_cp_async_bulk_tensor_prefetch_tile_gather4_2d_param_5];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd2, [test_cp_async_bulk_tensor_prefetch_tile_gather4_2d_param_6];
+; CHECK-PTX64-NEXT: cp.async.bulk.prefetch.tensor.2d.L2.global.tile::gather4 [%rd1, {%r1, %r2, %r3, %r4, %r5}];
+; CHECK-PTX64-NEXT: cp.async.bulk.prefetch.tensor.2d.L2.global.tile::gather4.L2::cache_hint [%rd1, {%r1, %r2, %r3, %r4, %r5}], %rd2;
+; CHECK-PTX64-NEXT: ret;
+;
+; CHECK-PTX-SHARED32-LABEL: test_cp_async_bulk_tensor_prefetch_tile_gather4_2d(
+; CHECK-PTX-SHARED32: {
+; CHECK-PTX-SHARED32-NEXT: .reg .b32 %r<6>;
+; CHECK-PTX-SHARED32-NEXT: .reg .b64 %rd<3>;
+; CHECK-PTX-SHARED32-EMPTY:
+; CHECK-PTX-SHARED32-NEXT: // %bb.0:
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd1, [test_cp_async_bulk_tensor_prefetch_tile_gather4_2d_param_0];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r1, [test_cp_async_bulk_tensor_prefetch_tile_gather4_2d_param_1];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r2, [test_cp_async_bulk_tensor_prefetch_tile_gather4_2d_param_2];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r3, [test_cp_async_bulk_tensor_prefetch_tile_gather4_2d_param_3];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r4, [test_cp_async_bulk_tensor_prefetch_tile_gather4_2d_param_4];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r5, [test_cp_async_bulk_tensor_prefetch_tile_gather4_2d_param_5];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd2, [test_cp_async_bulk_tensor_prefetch_tile_gather4_2d_param_6];
+; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.prefetch.tensor.2d.L2.global.tile::gather4 [%rd1, {%r1, %r2, %r3, %r4, %r5}];
+; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.prefetch.tensor.2d.L2.global.tile::gather4.L2::cache_hint [%rd1, {%r1, %r2, %r3, %r4, %r5}], %rd2;
+; CHECK-PTX-SHARED32-NEXT: ret;
tail call void @llvm.nvvm.cp.async.bulk.tensor.prefetch.tile.gather4.2d(ptr %tmap, i32 %d0, i32 %d1, i32 %d2, i32 %d3, i32 %d4, i64 %ch, i1 0)
tail call void @llvm.nvvm.cp.async.bulk.tensor.prefetch.tile.gather4.2d(ptr %tmap, i32 %d0, i32 %d1, i32 %d2, i32 %d3, i32 %d4, i64 %ch, i1 1)
ret void
diff --git a/llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-reduce-im2colw.ll b/llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-reduce-im2colw.ll
index ab14ad8bbb133..d863b1c47f931 100644
--- a/llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-reduce-im2colw.ll
+++ b/llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-reduce-im2colw.ll
@@ -12,12 +12,12 @@ define void @cp_async_bulk_tensor_reduce_im2colw_3d(ptr addrspace(3) %src, ptr %
; CHECK-PTX64-NEXT: .reg .b64 %rd<4>;
; CHECK-PTX64-EMPTY:
; CHECK-PTX64-NEXT: // %bb.0:
-; CHECK-PTX64-NEXT: ld.param.b64 %rd1, [cp_async_bulk_tensor_reduce_im2colw_3d_param_0];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd2, [cp_async_bulk_tensor_reduce_im2colw_3d_param_1];
-; CHECK-PTX64-NEXT: ld.param.b32 %r1, [cp_async_bulk_tensor_reduce_im2colw_3d_param_2];
-; CHECK-PTX64-NEXT: ld.param.b32 %r2, [cp_async_bulk_tensor_reduce_im2colw_3d_param_3];
-; CHECK-PTX64-NEXT: ld.param.b32 %r3, [cp_async_bulk_tensor_reduce_im2colw_3d_param_4];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd3, [cp_async_bulk_tensor_reduce_im2colw_3d_param_5];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd1, [cp_async_bulk_tensor_reduce_im2colw_3d_param_0];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd2, [cp_async_bulk_tensor_reduce_im2colw_3d_param_1];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r1, [cp_async_bulk_tensor_reduce_im2colw_3d_param_2];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r2, [cp_async_bulk_tensor_reduce_im2colw_3d_param_3];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r3, [cp_async_bulk_tensor_reduce_im2colw_3d_param_4];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd3, [cp_async_bulk_tensor_reduce_im2colw_3d_param_5];
; CHECK-PTX64-NEXT: cp.reduce.async.bulk.tensor.3d.global.shared::cta.add.im2col_no_offs::w.bulk_group.L2::cache_hint [%rd2, {%r1, %r2, %r3}], [%rd1], %rd3;
; CHECK-PTX64-NEXT: cp.reduce.async.bulk.tensor.3d.global.shared::cta.min.im2col_no_offs::w.bulk_group.L2::cache_hint [%rd2, {%r1, %r2, %r3}], [%rd1], %rd3;
; CHECK-PTX64-NEXT: cp.reduce.async.bulk.tensor.3d.global.shared::cta.max.im2col_no_offs::w.bulk_group.L2::cache_hint [%rd2, {%r1, %r2, %r3}], [%rd1], %rd3;
@@ -42,12 +42,12 @@ define void @cp_async_bulk_tensor_reduce_im2colw_3d(ptr addrspace(3) %src, ptr %
; CHECK-PTX-SHARED32-NEXT: .reg .b64 %rd<3>;
; CHECK-PTX-SHARED32-EMPTY:
; CHECK-PTX-SHARED32-NEXT: // %bb.0:
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r1, [cp_async_bulk_tensor_reduce_im2colw_3d_param_0];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd1, [cp_async_bulk_tensor_reduce_im2colw_3d_param_1];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r2, [cp_async_bulk_tensor_reduce_im2colw_3d_param_2];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r3, [cp_async_bulk_tensor_reduce_im2colw_3d_param_3];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r4, [cp_async_bulk_tensor_reduce_im2colw_3d_param_4];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd2, [cp_async_bulk_tensor_reduce_im2colw_3d_param_5];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r1, [cp_async_bulk_tensor_reduce_im2colw_3d_param_0];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd1, [cp_async_bulk_tensor_reduce_im2colw_3d_param_1];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r2, [cp_async_bulk_tensor_reduce_im2colw_3d_param_2];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r3, [cp_async_bulk_tensor_reduce_im2colw_3d_param_3];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r4, [cp_async_bulk_tensor_reduce_im2colw_3d_param_4];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd2, [cp_async_bulk_tensor_reduce_im2colw_3d_param_5];
; CHECK-PTX-SHARED32-NEXT: cp.reduce.async.bulk.tensor.3d.global.shared::cta.add.im2col_no_offs::w.bulk_group.L2::cache_hint [%rd1, {%r2, %r3, %r4}], [%r1], %rd2;
; CHECK-PTX-SHARED32-NEXT: cp.reduce.async.bulk.tensor.3d.global.shared::cta.min.im2col_no_offs::w.bulk_group.L2::cache_hint [%rd1, {%r2, %r3, %r4}], [%r1], %rd2;
; CHECK-PTX-SHARED32-NEXT: cp.reduce.async.bulk.tensor.3d.global.shared::cta.max.im2col_no_offs::w.bulk_group.L2::cache_hint [%rd1, {%r2, %r3, %r4}], [%r1], %rd2;
@@ -109,13 +109,13 @@ define void @cp_async_bulk_tensor_reduce_im2colw_4d(ptr addrspace(3) %src, ptr %
; CHECK-PTX64-NEXT: .reg .b64 %rd<4>;
; CHECK-PTX64-EMPTY:
; CHECK-PTX64-NEXT: // %bb.0:
-; CHECK-PTX64-NEXT: ld.param.b64 %rd1, [cp_async_bulk_tensor_reduce_im2colw_4d_param_0];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd2, [cp_async_bulk_tensor_reduce_im2colw_4d_param_1];
-; CHECK-PTX64-NEXT: ld.param.b32 %r1, [cp_async_bulk_tensor_reduce_im2colw_4d_param_2];
-; CHECK-PTX64-NEXT: ld.param.b32 %r2, [cp_async_bulk_tensor_reduce_im2colw_4d_param_3];
-; CHECK-PTX64-NEXT: ld.param.b32 %r3, [cp_async_bulk_tensor_reduce_im2colw_4d_param_4];
-; CHECK-PTX64-NEXT: ld.param.b32 %r4, [cp_async_bulk_tensor_reduce_im2colw_4d_param_5];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd3, [cp_async_bulk_tensor_reduce_im2colw_4d_param_6];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd1, [cp_async_bulk_tensor_reduce_im2colw_4d_param_0];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd2, [cp_async_bulk_tensor_reduce_im2colw_4d_param_1];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r1, [cp_async_bulk_tensor_reduce_im2colw_4d_param_2];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r2, [cp_async_bulk_tensor_reduce_im2colw_4d_param_3];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r3, [cp_async_bulk_tensor_reduce_im2colw_4d_param_4];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r4, [cp_async_bulk_tensor_reduce_im2colw_4d_param_5];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd3, [cp_async_bulk_tensor_reduce_im2colw_4d_param_6];
; CHECK-PTX64-NEXT: cp.reduce.async.bulk.tensor.4d.global.shared::cta.add.im2col_no_offs::w.bulk_group.L2::cache_hint [%rd2, {%r1, %r2, %r3, %r4}], [%rd1], %rd3;
; CHECK-PTX64-NEXT: cp.reduce.async.bulk.tensor.4d.global.shared::cta.min.im2col_no_offs::w.bulk_group.L2::cache_hint [%rd2, {%r1, %r2, %r3, %r4}], [%rd1], %rd3;
; CHECK-PTX64-NEXT: cp.reduce.async.bulk.tensor.4d.global.shared::cta.max.im2col_no_offs::w.bulk_group.L2::cache_hint [%rd2, {%r1, %r2, %r3, %r4}], [%rd1], %rd3;
@@ -140,13 +140,13 @@ define void @cp_async_bulk_tensor_reduce_im2colw_4d(ptr addrspace(3) %src, ptr %
; CHECK-PTX-SHARED32-NEXT: .reg .b64 %rd<3>;
; CHECK-PTX-SHARED32-EMPTY:
; CHECK-PTX-SHARED32-NEXT: // %bb.0:
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r1, [cp_async_bulk_tensor_reduce_im2colw_4d_param_0];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd1, [cp_async_bulk_tensor_reduce_im2colw_4d_param_1];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r2, [cp_async_bulk_tensor_reduce_im2colw_4d_param_2];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r3, [cp_async_bulk_tensor_reduce_im2colw_4d_param_3];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r4, [cp_async_bulk_tensor_reduce_im2colw_4d_param_4];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r5, [cp_async_bulk_tensor_reduce_im2colw_4d_param_5];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd2, [cp_async_bulk_tensor_reduce_im2colw_4d_param_6];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r1, [cp_async_bulk_tensor_reduce_im2colw_4d_param_0];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd1, [cp_async_bulk_tensor_reduce_im2colw_4d_param_1];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r2, [cp_async_bulk_tensor_reduce_im2colw_4d_param_2];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r3, [cp_async_bulk_tensor_reduce_im2colw_4d_param_3];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r4, [cp_async_bulk_tensor_reduce_im2colw_4d_param_4];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r5, [cp_async_bulk_tensor_reduce_im2colw_4d_param_5];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd2, [cp_async_bulk_tensor_reduce_im2colw_4d_param_6];
; CHECK-PTX-SHARED32-NEXT: cp.reduce.async.bulk.tensor.4d.global.shared::cta.add.im2col_no_offs::w.bulk_group.L2::cache_hint [%rd1, {%r2, %r3, %r4, %r5}], [%r1], %rd2;
; CHECK-PTX-SHARED32-NEXT: cp.reduce.async.bulk.tensor.4d.global.shared::cta.min.im2col_no_offs::w.bulk_group.L2::cache_hint [%rd1, {%r2, %r3, %r4, %r5}], [%r1], %rd2;
; CHECK-PTX-SHARED32-NEXT: cp.reduce.async.bulk.tensor.4d.global.shared::cta.max.im2col_no_offs::w.bulk_group.L2::cache_hint [%rd1, {%r2, %r3, %r4, %r5}], [%r1], %rd2;
@@ -208,14 +208,14 @@ define void @cp_async_bulk_tensor_reduce_im2colw_5d(ptr addrspace(3) %src, ptr %
; CHECK-PTX64-NEXT: .reg .b64 %rd<4>;
; CHECK-PTX64-EMPTY:
; CHECK-PTX64-NEXT: // %bb.0:
-; CHECK-PTX64-NEXT: ld.param.b64 %rd1, [cp_async_bulk_tensor_reduce_im2colw_5d_param_0];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd2, [cp_async_bulk_tensor_reduce_im2colw_5d_param_1];
-; CHECK-PTX64-NEXT: ld.param.b32 %r1, [cp_async_bulk_tensor_reduce_im2colw_5d_param_2];
-; CHECK-PTX64-NEXT: ld.param.b32 %r2, [cp_async_bulk_tensor_reduce_im2colw_5d_param_3];
-; CHECK-PTX64-NEXT: ld.param.b32 %r3, [cp_async_bulk_tensor_reduce_im2colw_5d_param_4];
-; CHECK-PTX64-NEXT: ld.param.b32 %r4, [cp_async_bulk_tensor_reduce_im2colw_5d_param_5];
-; CHECK-PTX64-NEXT: ld.param.b32 %r5, [cp_async_bulk_tensor_reduce_im2colw_5d_param_6];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd3, [cp_async_bulk_tensor_reduce_im2colw_5d_param_7];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd1, [cp_async_bulk_tensor_reduce_im2colw_5d_param_0];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd2, [cp_async_bulk_tensor_reduce_im2colw_5d_param_1];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r1, [cp_async_bulk_tensor_reduce_im2colw_5d_param_2];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r2, [cp_async_bulk_tensor_reduce_im2colw_5d_param_3];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r3, [cp_async_bulk_tensor_reduce_im2colw_5d_param_4];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r4, [cp_async_bulk_tensor_reduce_im2colw_5d_param_5];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r5, [cp_async_bulk_tensor_reduce_im2colw_5d_param_6];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd3, [cp_async_bulk_tensor_reduce_im2colw_5d_param_7];
; CHECK-PTX64-NEXT: cp.reduce.async.bulk.tensor.5d.global.shared::cta.add.im2col_no_offs::w.bulk_group.L2::cache_hint [%rd2, {%r1, %r2, %r3, %r4, %r5}], [%rd1], %rd3;
; CHECK-PTX64-NEXT: cp.reduce.async.bulk.tensor.5d.global.shared::cta.min.im2col_no_offs::w.bulk_group.L2::cache_hint [%rd2, {%r1, %r2, %r3, %r4, %r5}], [%rd1], %rd3;
; CHECK-PTX64-NEXT: cp.reduce.async.bulk.tensor.5d.global.shared::cta.max.im2col_no_offs::w.bulk_group.L2::cache_hint [%rd2, {%r1, %r2, %r3, %r4, %r5}], [%rd1], %rd3;
@@ -240,14 +240,14 @@ define void @cp_async_bulk_tensor_reduce_im2colw_5d(ptr addrspace(3) %src, ptr %
; CHECK-PTX-SHARED32-NEXT: .reg .b64 %rd<3>;
; CHECK-PTX-SHARED32-EMPTY:
; CHECK-PTX-SHARED32-NEXT: // %bb.0:
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r1, [cp_async_bulk_tensor_reduce_im2colw_5d_param_0];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd1, [cp_async_bulk_tensor_reduce_im2colw_5d_param_1];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r2, [cp_async_bulk_tensor_reduce_im2colw_5d_param_2];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r3, [cp_async_bulk_tensor_reduce_im2colw_5d_param_3];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r4, [cp_async_bulk_tensor_reduce_im2colw_5d_param_4];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r5, [cp_async_bulk_tensor_reduce_im2colw_5d_param_5];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r6, [cp_async_bulk_tensor_reduce_im2colw_5d_param_6];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd2, [cp_async_bulk_tensor_reduce_im2colw_5d_param_7];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r1, [cp_async_bulk_tensor_reduce_im2colw_5d_param_0];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd1, [cp_async_bulk_tensor_reduce_im2colw_5d_param_1];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r2, [cp_async_bulk_tensor_reduce_im2colw_5d_param_2];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r3, [cp_async_bulk_tensor_reduce_im2colw_5d_param_3];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r4, [cp_async_bulk_tensor_reduce_im2colw_5d_param_4];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r5, [cp_async_bulk_tensor_reduce_im2colw_5d_param_5];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r6, [cp_async_bulk_tensor_reduce_im2colw_5d_param_6];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd2, [cp_async_bulk_tensor_reduce_im2colw_5d_param_7];
; CHECK-PTX-SHARED32-NEXT: cp.reduce.async.bulk.tensor.5d.global.shared::cta.add.im2col_no_offs::w.bulk_group.L2::cache_hint [%rd1, {%r2, %r3, %r4, %r5, %r6}], [%r1], %rd2;
; CHECK-PTX-SHARED32-NEXT: cp.reduce.async.bulk.tensor.5d.global.shared::cta.min.im2col_no_offs::w.bulk_group.L2::cache_hint [%rd1, {%r2, %r3, %r4, %r5, %r6}], [%r1], %rd2;
; CHECK-PTX-SHARED32-NEXT: cp.reduce.async.bulk.tensor.5d.global.shared::cta.max.im2col_no_offs::w.bulk_group.L2::cache_hint [%rd1, {%r2, %r3, %r4, %r5, %r6}], [%r1], %rd2;
diff --git a/llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-s2g-im2colw.ll b/llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-s2g-im2colw.ll
index 528f9a2302cc8..5e63a312afee8 100644
--- a/llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-s2g-im2colw.ll
+++ b/llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-s2g-im2colw.ll
@@ -11,12 +11,12 @@ define void @cp_async_bulk_tensor_s2g_im2colw_3d(ptr addrspace(3) %src, ptr %tma
; CHECK-PTX64-NEXT: .reg .b64 %rd<4>;
; CHECK-PTX64-EMPTY:
; CHECK-PTX64-NEXT: // %bb.0:
-; CHECK-PTX64-NEXT: ld.param.b64 %rd1, [cp_async_bulk_tensor_s2g_im2colw_3d_param_0];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd2, [cp_async_bulk_tensor_s2g_im2colw_3d_param_1];
-; CHECK-PTX64-NEXT: ld.param.b32 %r1, [cp_async_bulk_tensor_s2g_im2colw_3d_param_2];
-; CHECK-PTX64-NEXT: ld.param.b32 %r2, [cp_async_bulk_tensor_s2g_im2colw_3d_param_3];
-; CHECK-PTX64-NEXT: ld.param.b32 %r3, [cp_async_bulk_tensor_s2g_im2colw_3d_param_4];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd3, [cp_async_bulk_tensor_s2g_im2colw_3d_param_5];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd1, [cp_async_bulk_tensor_s2g_im2colw_3d_param_0];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd2, [cp_async_bulk_tensor_s2g_im2colw_3d_param_1];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r1, [cp_async_bulk_tensor_s2g_im2colw_3d_param_2];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r2, [cp_async_bulk_tensor_s2g_im2colw_3d_param_3];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r3, [cp_async_bulk_tensor_s2g_im2colw_3d_param_4];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd3, [cp_async_bulk_tensor_s2g_im2colw_3d_param_5];
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.3d.global.shared::cta.im2col_no_offs::w.bulk_group [%rd2, {%r1, %r2, %r3}], [%rd1];
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.3d.global.shared::cta.im2col_no_offs::w.bulk_group.L2::cache_hint [%rd2, {%r1, %r2, %r3}], [%rd1], %rd3;
; CHECK-PTX64-NEXT: ret;
@@ -27,12 +27,12 @@ define void @cp_async_bulk_tensor_s2g_im2colw_3d(ptr addrspace(3) %src, ptr %tma
; CHECK-PTX-SHARED32-NEXT: .reg .b64 %rd<3>;
; CHECK-PTX-SHARED32-EMPTY:
; CHECK-PTX-SHARED32-NEXT: // %bb.0:
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r1, [cp_async_bulk_tensor_s2g_im2colw_3d_param_0];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd1, [cp_async_bulk_tensor_s2g_im2colw_3d_param_1];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r2, [cp_async_bulk_tensor_s2g_im2colw_3d_param_2];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r3, [cp_async_bulk_tensor_s2g_im2colw_3d_param_3];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r4, [cp_async_bulk_tensor_s2g_im2colw_3d_param_4];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd2, [cp_async_bulk_tensor_s2g_im2colw_3d_param_5];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r1, [cp_async_bulk_tensor_s2g_im2colw_3d_param_0];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd1, [cp_async_bulk_tensor_s2g_im2colw_3d_param_1];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r2, [cp_async_bulk_tensor_s2g_im2colw_3d_param_2];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r3, [cp_async_bulk_tensor_s2g_im2colw_3d_param_3];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r4, [cp_async_bulk_tensor_s2g_im2colw_3d_param_4];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd2, [cp_async_bulk_tensor_s2g_im2colw_3d_param_5];
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.3d.global.shared::cta.im2col_no_offs::w.bulk_group [%rd1, {%r2, %r3, %r4}], [%r1];
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.3d.global.shared::cta.im2col_no_offs::w.bulk_group.L2::cache_hint [%rd1, {%r2, %r3, %r4}], [%r1], %rd2;
; CHECK-PTX-SHARED32-NEXT: ret;
@@ -48,13 +48,13 @@ define void @cp_async_bulk_tensor_s2g_im2colw_4d(ptr addrspace(3) %src, ptr %tma
; CHECK-PTX64-NEXT: .reg .b64 %rd<4>;
; CHECK-PTX64-EMPTY:
; CHECK-PTX64-NEXT: // %bb.0:
-; CHECK-PTX64-NEXT: ld.param.b64 %rd1, [cp_async_bulk_tensor_s2g_im2colw_4d_param_0];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd2, [cp_async_bulk_tensor_s2g_im2colw_4d_param_1];
-; CHECK-PTX64-NEXT: ld.param.b32 %r1, [cp_async_bulk_tensor_s2g_im2colw_4d_param_2];
-; CHECK-PTX64-NEXT: ld.param.b32 %r2, [cp_async_bulk_tensor_s2g_im2colw_4d_param_3];
-; CHECK-PTX64-NEXT: ld.param.b32 %r3, [cp_async_bulk_tensor_s2g_im2colw_4d_param_4];
-; CHECK-PTX64-NEXT: ld.param.b32 %r4, [cp_async_bulk_tensor_s2g_im2colw_4d_param_5];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd3, [cp_async_bulk_tensor_s2g_im2colw_4d_param_6];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd1, [cp_async_bulk_tensor_s2g_im2colw_4d_param_0];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd2, [cp_async_bulk_tensor_s2g_im2colw_4d_param_1];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r1, [cp_async_bulk_tensor_s2g_im2colw_4d_param_2];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r2, [cp_async_bulk_tensor_s2g_im2colw_4d_param_3];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r3, [cp_async_bulk_tensor_s2g_im2colw_4d_param_4];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r4, [cp_async_bulk_tensor_s2g_im2colw_4d_param_5];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd3, [cp_async_bulk_tensor_s2g_im2colw_4d_param_6];
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.4d.global.shared::cta.im2col_no_offs::w.bulk_group [%rd2, {%r1, %r2, %r3, %r4}], [%rd1];
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.4d.global.shared::cta.im2col_no_offs::w.bulk_group.L2::cache_hint [%rd2, {%r1, %r2, %r3, %r4}], [%rd1], %rd3;
; CHECK-PTX64-NEXT: ret;
@@ -65,13 +65,13 @@ define void @cp_async_bulk_tensor_s2g_im2colw_4d(ptr addrspace(3) %src, ptr %tma
; CHECK-PTX-SHARED32-NEXT: .reg .b64 %rd<3>;
; CHECK-PTX-SHARED32-EMPTY:
; CHECK-PTX-SHARED32-NEXT: // %bb.0:
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r1, [cp_async_bulk_tensor_s2g_im2colw_4d_param_0];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd1, [cp_async_bulk_tensor_s2g_im2colw_4d_param_1];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r2, [cp_async_bulk_tensor_s2g_im2colw_4d_param_2];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r3, [cp_async_bulk_tensor_s2g_im2colw_4d_param_3];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r4, [cp_async_bulk_tensor_s2g_im2colw_4d_param_4];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r5, [cp_async_bulk_tensor_s2g_im2colw_4d_param_5];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd2, [cp_async_bulk_tensor_s2g_im2colw_4d_param_6];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r1, [cp_async_bulk_tensor_s2g_im2colw_4d_param_0];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd1, [cp_async_bulk_tensor_s2g_im2colw_4d_param_1];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r2, [cp_async_bulk_tensor_s2g_im2colw_4d_param_2];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r3, [cp_async_bulk_tensor_s2g_im2colw_4d_param_3];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r4, [cp_async_bulk_tensor_s2g_im2colw_4d_param_4];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r5, [cp_async_bulk_tensor_s2g_im2colw_4d_param_5];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd2, [cp_async_bulk_tensor_s2g_im2colw_4d_param_6];
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.4d.global.shared::cta.im2col_no_offs::w.bulk_group [%rd1, {%r2, %r3, %r4, %r5}], [%r1];
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.4d.global.shared::cta.im2col_no_offs::w.bulk_group.L2::cache_hint [%rd1, {%r2, %r3, %r4, %r5}], [%r1], %rd2;
; CHECK-PTX-SHARED32-NEXT: ret;
@@ -87,14 +87,14 @@ define void @cp_async_bulk_tensor_s2g_im2colw_5d(ptr addrspace(3) %src, ptr %tma
; CHECK-PTX64-NEXT: .reg .b64 %rd<4>;
; CHECK-PTX64-EMPTY:
; CHECK-PTX64-NEXT: // %bb.0:
-; CHECK-PTX64-NEXT: ld.param.b64 %rd1, [cp_async_bulk_tensor_s2g_im2colw_5d_param_0];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd2, [cp_async_bulk_tensor_s2g_im2colw_5d_param_1];
-; CHECK-PTX64-NEXT: ld.param.b32 %r1, [cp_async_bulk_tensor_s2g_im2colw_5d_param_2];
-; CHECK-PTX64-NEXT: ld.param.b32 %r2, [cp_async_bulk_tensor_s2g_im2colw_5d_param_3];
-; CHECK-PTX64-NEXT: ld.param.b32 %r3, [cp_async_bulk_tensor_s2g_im2colw_5d_param_4];
-; CHECK-PTX64-NEXT: ld.param.b32 %r4, [cp_async_bulk_tensor_s2g_im2colw_5d_param_5];
-; CHECK-PTX64-NEXT: ld.param.b32 %r5, [cp_async_bulk_tensor_s2g_im2colw_5d_param_6];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd3, [cp_async_bulk_tensor_s2g_im2colw_5d_param_7];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd1, [cp_async_bulk_tensor_s2g_im2colw_5d_param_0];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd2, [cp_async_bulk_tensor_s2g_im2colw_5d_param_1];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r1, [cp_async_bulk_tensor_s2g_im2colw_5d_param_2];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r2, [cp_async_bulk_tensor_s2g_im2colw_5d_param_3];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r3, [cp_async_bulk_tensor_s2g_im2colw_5d_param_4];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r4, [cp_async_bulk_tensor_s2g_im2colw_5d_param_5];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r5, [cp_async_bulk_tensor_s2g_im2colw_5d_param_6];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd3, [cp_async_bulk_tensor_s2g_im2colw_5d_param_7];
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.5d.global.shared::cta.im2col_no_offs::w.bulk_group [%rd2, {%r1, %r2, %r3, %r4, %r5}], [%rd1];
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.5d.global.shared::cta.im2col_no_offs::w.bulk_group.L2::cache_hint [%rd2, {%r1, %r2, %r3, %r4, %r5}], [%rd1], %rd3;
; CHECK-PTX64-NEXT: ret;
@@ -105,14 +105,14 @@ define void @cp_async_bulk_tensor_s2g_im2colw_5d(ptr addrspace(3) %src, ptr %tma
; CHECK-PTX-SHARED32-NEXT: .reg .b64 %rd<3>;
; CHECK-PTX-SHARED32-EMPTY:
; CHECK-PTX-SHARED32-NEXT: // %bb.0:
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r1, [cp_async_bulk_tensor_s2g_im2colw_5d_param_0];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd1, [cp_async_bulk_tensor_s2g_im2colw_5d_param_1];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r2, [cp_async_bulk_tensor_s2g_im2colw_5d_param_2];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r3, [cp_async_bulk_tensor_s2g_im2colw_5d_param_3];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r4, [cp_async_bulk_tensor_s2g_im2colw_5d_param_4];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r5, [cp_async_bulk_tensor_s2g_im2colw_5d_param_5];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r6, [cp_async_bulk_tensor_s2g_im2colw_5d_param_6];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd2, [cp_async_bulk_tensor_s2g_im2colw_5d_param_7];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r1, [cp_async_bulk_tensor_s2g_im2colw_5d_param_0];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd1, [cp_async_bulk_tensor_s2g_im2colw_5d_param_1];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r2, [cp_async_bulk_tensor_s2g_im2colw_5d_param_2];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r3, [cp_async_bulk_tensor_s2g_im2colw_5d_param_3];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r4, [cp_async_bulk_tensor_s2g_im2colw_5d_param_4];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r5, [cp_async_bulk_tensor_s2g_im2colw_5d_param_5];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r6, [cp_async_bulk_tensor_s2g_im2colw_5d_param_6];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd2, [cp_async_bulk_tensor_s2g_im2colw_5d_param_7];
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.5d.global.shared::cta.im2col_no_offs::w.bulk_group [%rd1, {%r2, %r3, %r4, %r5, %r6}], [%r1];
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.5d.global.shared::cta.im2col_no_offs::w.bulk_group.L2::cache_hint [%rd1, {%r2, %r3, %r4, %r5, %r6}], [%r1], %rd2;
; CHECK-PTX-SHARED32-NEXT: ret;
diff --git a/llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-s2g-scatter4.ll b/llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-s2g-scatter4.ll
index ee0e41bcb80c3..c5c56b00d4119 100644
--- a/llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-s2g-scatter4.ll
+++ b/llvm/test/CodeGen/NVPTX/cp-async-bulk-tensor-s2g-scatter4.ll
@@ -16,14 +16,14 @@ define void @cp_async_bulk_tensor_s2g_tile_scatter4_2d(i32 %flag, ptr addrspace(
; CHECK-PTX64-NEXT: .reg .b64 %rd<4>;
; CHECK-PTX64-EMPTY:
; CHECK-PTX64-NEXT: // %bb.0:
-; CHECK-PTX64-NEXT: ld.param.b64 %rd1, [cp_async_bulk_tensor_s2g_tile_scatter4_2d_param_1];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd2, [cp_async_bulk_tensor_s2g_tile_scatter4_2d_param_2];
-; CHECK-PTX64-NEXT: ld.param.b32 %r1, [cp_async_bulk_tensor_s2g_tile_scatter4_2d_param_3];
-; CHECK-PTX64-NEXT: ld.param.b32 %r2, [cp_async_bulk_tensor_s2g_tile_scatter4_2d_param_4];
-; CHECK-PTX64-NEXT: ld.param.b32 %r3, [cp_async_bulk_tensor_s2g_tile_scatter4_2d_param_5];
-; CHECK-PTX64-NEXT: ld.param.b32 %r4, [cp_async_bulk_tensor_s2g_tile_scatter4_2d_param_6];
-; CHECK-PTX64-NEXT: ld.param.b32 %r5, [cp_async_bulk_tensor_s2g_tile_scatter4_2d_param_7];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd3, [cp_async_bulk_tensor_s2g_tile_scatter4_2d_param_8];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd1, [cp_async_bulk_tensor_s2g_tile_scatter4_2d_param_1];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd2, [cp_async_bulk_tensor_s2g_tile_scatter4_2d_param_2];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r1, [cp_async_bulk_tensor_s2g_tile_scatter4_2d_param_3];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r2, [cp_async_bulk_tensor_s2g_tile_scatter4_2d_param_4];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r3, [cp_async_bulk_tensor_s2g_tile_scatter4_2d_param_5];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r4, [cp_async_bulk_tensor_s2g_tile_scatter4_2d_param_6];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r5, [cp_async_bulk_tensor_s2g_tile_scatter4_2d_param_7];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd3, [cp_async_bulk_tensor_s2g_tile_scatter4_2d_param_8];
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.2d.global.shared::cta.tile::scatter4.bulk_group [%rd2, {%r1, %r2, %r3, %r4, %r5}], [%rd1];
; CHECK-PTX64-NEXT: cp.async.bulk.tensor.2d.global.shared::cta.tile::scatter4.bulk_group.L2::cache_hint [%rd2, {%r1, %r2, %r3, %r4, %r5}], [%rd1], %rd3;
; CHECK-PTX64-NEXT: ret;
@@ -34,14 +34,14 @@ define void @cp_async_bulk_tensor_s2g_tile_scatter4_2d(i32 %flag, ptr addrspace(
; CHECK-PTX-SHARED32-NEXT: .reg .b64 %rd<3>;
; CHECK-PTX-SHARED32-EMPTY:
; CHECK-PTX-SHARED32-NEXT: // %bb.0:
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r1, [cp_async_bulk_tensor_s2g_tile_scatter4_2d_param_1];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd1, [cp_async_bulk_tensor_s2g_tile_scatter4_2d_param_2];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r2, [cp_async_bulk_tensor_s2g_tile_scatter4_2d_param_3];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r3, [cp_async_bulk_tensor_s2g_tile_scatter4_2d_param_4];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r4, [cp_async_bulk_tensor_s2g_tile_scatter4_2d_param_5];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r5, [cp_async_bulk_tensor_s2g_tile_scatter4_2d_param_6];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r6, [cp_async_bulk_tensor_s2g_tile_scatter4_2d_param_7];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd2, [cp_async_bulk_tensor_s2g_tile_scatter4_2d_param_8];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r1, [cp_async_bulk_tensor_s2g_tile_scatter4_2d_param_1];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd1, [cp_async_bulk_tensor_s2g_tile_scatter4_2d_param_2];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r2, [cp_async_bulk_tensor_s2g_tile_scatter4_2d_param_3];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r3, [cp_async_bulk_tensor_s2g_tile_scatter4_2d_param_4];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r4, [cp_async_bulk_tensor_s2g_tile_scatter4_2d_param_5];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r5, [cp_async_bulk_tensor_s2g_tile_scatter4_2d_param_6];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r6, [cp_async_bulk_tensor_s2g_tile_scatter4_2d_param_7];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd2, [cp_async_bulk_tensor_s2g_tile_scatter4_2d_param_8];
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.2d.global.shared::cta.tile::scatter4.bulk_group [%rd1, {%r2, %r3, %r4, %r5, %r6}], [%r1];
; CHECK-PTX-SHARED32-NEXT: cp.async.bulk.tensor.2d.global.shared::cta.tile::scatter4.bulk_group.L2::cache_hint [%rd1, {%r2, %r3, %r4, %r5, %r6}], [%r1], %rd2;
; CHECK-PTX-SHARED32-NEXT: ret;
diff --git a/llvm/test/CodeGen/NVPTX/f32x2-convert-i32x2.ll b/llvm/test/CodeGen/NVPTX/f32x2-convert-i32x2.ll
index f89687ef339c1..d075bd90b80fc 100644
--- a/llvm/test/CodeGen/NVPTX/f32x2-convert-i32x2.ll
+++ b/llvm/test/CodeGen/NVPTX/f32x2-convert-i32x2.ll
@@ -46,14 +46,14 @@ define ptx_kernel void @store_i32x2(i32 %0, ptr %p) {
; CHECK-SM100-NEXT: .reg .b64 %rd<4>;
; CHECK-SM100-EMPTY:
; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param.b64 %rd1, [store_i32x2_param_1];
-; CHECK-SM100-NEXT: ld.param.b32 %r1, [store_i32x2_param_0];
+; CHECK-SM100-NEXT: ld.param::entry.b64 %rd1, [store_i32x2_param_1];
+; CHECK-SM100-NEXT: ld.param::entry.b32 %r1, [store_i32x2_param_0];
; CHECK-SM100-NEXT: { // callseq 0, 0
; CHECK-SM100-NEXT: .param .b32 param0;
; CHECK-SM100-NEXT: .param .align 8 .b8 retval0[8];
-; CHECK-SM100-NEXT: st.param.b32 [param0], %r1;
+; CHECK-SM100-NEXT: st.param::func.b32 [param0], %r1;
; CHECK-SM100-NEXT: call.uni (retval0), return_i32x2, (param0);
-; CHECK-SM100-NEXT: ld.param.b64 %rd2, [retval0];
+; CHECK-SM100-NEXT: ld.param::func.b64 %rd2, [retval0];
; CHECK-SM100-NEXT: } // callseq 0
; CHECK-SM100-NEXT: add.rn.f32x2 %rd3, %rd2, %rd2;
; CHECK-SM100-NEXT: st.b64 [%rd1], %rd3;
@@ -93,7 +93,7 @@ define ptx_kernel void @inlineasm(ptr %p) {
; CHECK-SM100-NEXT: .reg .b64 %rd<5>;
; CHECK-SM100-EMPTY:
; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param.b64 %rd1, [inlineasm_param_0];
+; CHECK-SM100-NEXT: ld.param::entry.b64 %rd1, [inlineasm_param_0];
; CHECK-SM100-NEXT: mov.b32 %r3, 0;
; CHECK-SM100-NEXT: mov.b32 %r4, %r3;
; CHECK-SM100-NEXT: mov.b32 %r2, %r4;
@@ -138,7 +138,7 @@ define ptx_kernel void @trunc_v2i32(<2 x i32> %0) {
; CHECK-SM100-NEXT: .reg .b64 %rd<3>;
; CHECK-SM100-EMPTY:
; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param.b64 %rd1, [trunc_v2i32_param_0];
+; CHECK-SM100-NEXT: ld.param::entry.b64 %rd1, [trunc_v2i32_param_0];
; CHECK-SM100-NEXT: mov.b64 {%r1, %r2}, %rd1;
; CHECK-SM100-NEXT: mov.b32 %r3, 0;
; CHECK-SM100-NEXT: prmt.b32 %r4, %r3, 0, 0x3340U;
@@ -182,7 +182,7 @@ define ptx_kernel void @zextend_to_v2i32(<2 x i8> %0) {
; CHECK-SM100-NEXT: .reg .b64 %rd<8>;
; CHECK-SM100-EMPTY:
; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param.v2.b8 {%rs1, %rs2}, [zextend_to_v2i32_param_0];
+; CHECK-SM100-NEXT: ld.param::entry.v2.b8 {%rs1, %rs2}, [zextend_to_v2i32_param_0];
; CHECK-SM100-NEXT: mov.b32 %r1, {%rs1, %rs2};
; CHECK-SM100-NEXT: cvt.u32.u16 %r2, %rs2;
; CHECK-SM100-NEXT: cvt.u32.u16 %r3, %rs1;
@@ -236,7 +236,7 @@ define ptx_kernel void @sextend_to_v2i32(<2 x i8> %0) {
; CHECK-SM100-NEXT: .reg .b64 %rd<7>;
; CHECK-SM100-EMPTY:
; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param.v2.b8 {%rs1, %rs2}, [sextend_to_v2i32_param_0];
+; CHECK-SM100-NEXT: ld.param::entry.v2.b8 {%rs1, %rs2}, [sextend_to_v2i32_param_0];
; CHECK-SM100-NEXT: mov.b32 %r1, {%rs1, %rs2};
; CHECK-SM100-NEXT: cvt.u32.u16 %r2, %rs2;
; CHECK-SM100-NEXT: cvt.s32.s8 %r3, %r2;
diff --git a/llvm/test/CodeGen/NVPTX/f32x2-instructions.ll b/llvm/test/CodeGen/NVPTX/f32x2-instructions.ll
index 0b43ce6670d6d..2779cf265c58a 100644
--- a/llvm/test/CodeGen/NVPTX/f32x2-instructions.ll
+++ b/llvm/test/CodeGen/NVPTX/f32x2-instructions.ll
@@ -17,12 +17,19 @@ target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
target triple = "nvptx64-nvidia-cuda"
define <2 x float> @test_ret_const() #0 {
-; CHECK-LABEL: test_ret_const(
-; CHECK: {
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: st.param.v2.b32 [func_retval0], {0f3F800000, 0f40000000};
-; CHECK-NEXT: ret;
+; CHECK-NOF32X2-LABEL: test_ret_const(
+; CHECK-NOF32X2: {
+; CHECK-NOF32X2-EMPTY:
+; CHECK-NOF32X2-NEXT: // %bb.0:
+; CHECK-NOF32X2-NEXT: st.param.v2.b32 [func_retval0], {0f3F800000, 0f40000000};
+; CHECK-NOF32X2-NEXT: ret;
+;
+; CHECK-F32X2-LABEL: test_ret_const(
+; CHECK-F32X2: {
+; CHECK-F32X2-EMPTY:
+; CHECK-F32X2-NEXT: // %bb.0:
+; CHECK-F32X2-NEXT: st.param::func.v2.b32 [func_retval0], {0f3F800000, 0f40000000};
+; CHECK-F32X2-NEXT: ret;
ret <2 x float> <float 1.0, float 2.0>
}
@@ -42,9 +49,9 @@ define float @test_extract_0(<2 x float> %a) #0 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param.b64 %rd1, [test_extract_0_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_extract_0_param_0];
; CHECK-F32X2-NEXT: mov.b64 {%r1, _}, %rd1;
-; CHECK-F32X2-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-F32X2-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-F32X2-NEXT: ret;
%e = extractelement <2 x float> %a, i32 0
ret float %e
@@ -66,9 +73,9 @@ define float @test_extract_1(<2 x float> %a) #0 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param.b64 %rd1, [test_extract_1_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_extract_1_param_0];
; CHECK-F32X2-NEXT: mov.b64 {_, %r1}, %rd1;
-; CHECK-F32X2-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-F32X2-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-F32X2-NEXT: ret;
%e = extractelement <2 x float> %a, i32 1
ret float %e
@@ -104,12 +111,12 @@ define float @test_extract_i(<2 x float> %a, i64 %idx) #0 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<3>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param.b64 %rd2, [test_extract_i_param_1];
-; CHECK-F32X2-NEXT: ld.param.b64 %rd1, [test_extract_i_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_extract_i_param_1];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_extract_i_param_0];
; CHECK-F32X2-NEXT: setp.eq.b64 %p1, %rd2, 0;
; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
; CHECK-F32X2-NEXT: selp.f32 %r3, %r1, %r2, %p1;
-; CHECK-F32X2-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-F32X2-NEXT: st.param::func.b32 [func_retval0], %r3;
; CHECK-F32X2-NEXT: ret;
%e = extractelement <2 x float> %a, i64 %idx
ret float %e
@@ -133,10 +140,10 @@ define <2 x float> @test_fadd(<2 x float> %a, <2 x float> %b) #0 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<4>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param.b64 %rd2, [test_fadd_param_1];
-; CHECK-F32X2-NEXT: ld.param.b64 %rd1, [test_fadd_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_fadd_param_1];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_fadd_param_0];
; CHECK-F32X2-NEXT: add.rn.f32x2 %rd3, %rd1, %rd2;
-; CHECK-F32X2-NEXT: st.param.b64 [func_retval0], %rd3;
+; CHECK-F32X2-NEXT: st.param::func.b64 [func_retval0], %rd3;
; CHECK-F32X2-NEXT: ret;
%r = fadd <2 x float> %a, %b
ret <2 x float> %r
@@ -160,12 +167,12 @@ define <2 x float> @test_fadd_imm_0(<2 x float> %a) #0 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<4>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param.b64 %rd1, [test_fadd_imm_0_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_fadd_imm_0_param_0];
; CHECK-F32X2-NEXT: mov.b32 %r1, 0f40000000;
; CHECK-F32X2-NEXT: mov.b32 %r2, 0f3F800000;
; CHECK-F32X2-NEXT: mov.b64 %rd2, {%r2, %r1};
; CHECK-F32X2-NEXT: add.rn.f32x2 %rd3, %rd1, %rd2;
-; CHECK-F32X2-NEXT: st.param.b64 [func_retval0], %rd3;
+; CHECK-F32X2-NEXT: st.param::func.b64 [func_retval0], %rd3;
; CHECK-F32X2-NEXT: ret;
%r = fadd <2 x float> <float 1.0, float 2.0>, %a
ret <2 x float> %r
@@ -189,12 +196,12 @@ define <2 x float> @test_fadd_imm_1(<2 x float> %a) #0 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<4>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param.b64 %rd1, [test_fadd_imm_1_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_fadd_imm_1_param_0];
; CHECK-F32X2-NEXT: mov.b32 %r1, 0f40000000;
; CHECK-F32X2-NEXT: mov.b32 %r2, 0f3F800000;
; CHECK-F32X2-NEXT: mov.b64 %rd2, {%r2, %r1};
; CHECK-F32X2-NEXT: add.rn.f32x2 %rd3, %rd1, %rd2;
-; CHECK-F32X2-NEXT: st.param.b64 [func_retval0], %rd3;
+; CHECK-F32X2-NEXT: st.param::func.b64 [func_retval0], %rd3;
; CHECK-F32X2-NEXT: ret;
%r = fadd <2 x float> %a, <float 1.0, float 2.0>
ret <2 x float> %r
@@ -220,11 +227,11 @@ define <4 x float> @test_fadd_v4(<4 x float> %a, <4 x float> %b) #0 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<7>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param.v2.b64 {%rd3, %rd4}, [test_fadd_v4_param_1];
-; CHECK-F32X2-NEXT: ld.param.v2.b64 {%rd1, %rd2}, [test_fadd_v4_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.v2.b64 {%rd3, %rd4}, [test_fadd_v4_param_1];
+; CHECK-F32X2-NEXT: ld.param::func.v2.b64 {%rd1, %rd2}, [test_fadd_v4_param_0];
; CHECK-F32X2-NEXT: add.rn.f32x2 %rd5, %rd2, %rd4;
; CHECK-F32X2-NEXT: add.rn.f32x2 %rd6, %rd1, %rd3;
-; CHECK-F32X2-NEXT: st.param.v2.b64 [func_retval0], {%rd6, %rd5};
+; CHECK-F32X2-NEXT: st.param::func.v2.b64 [func_retval0], {%rd6, %rd5};
; CHECK-F32X2-NEXT: ret;
%r = fadd <4 x float> %a, %b
ret <4 x float> %r
@@ -250,7 +257,7 @@ define <4 x float> @test_fadd_imm_0_v4(<4 x float> %a) #0 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<7>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param.v2.b64 {%rd1, %rd2}, [test_fadd_imm_0_v4_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.v2.b64 {%rd1, %rd2}, [test_fadd_imm_0_v4_param_0];
; CHECK-F32X2-NEXT: mov.b32 %r1, 0f40800000;
; CHECK-F32X2-NEXT: mov.b32 %r2, 0f40400000;
; CHECK-F32X2-NEXT: mov.b64 %rd3, {%r2, %r1};
@@ -259,7 +266,7 @@ define <4 x float> @test_fadd_imm_0_v4(<4 x float> %a) #0 {
; CHECK-F32X2-NEXT: mov.b32 %r4, 0f3F800000;
; CHECK-F32X2-NEXT: mov.b64 %rd5, {%r4, %r3};
; CHECK-F32X2-NEXT: add.rn.f32x2 %rd6, %rd1, %rd5;
-; CHECK-F32X2-NEXT: st.param.v2.b64 [func_retval0], {%rd6, %rd4};
+; CHECK-F32X2-NEXT: st.param::func.v2.b64 [func_retval0], {%rd6, %rd4};
; CHECK-F32X2-NEXT: ret;
%r = fadd <4 x float> <float 1.0, float 2.0, float 3.0, float 4.0>, %a
ret <4 x float> %r
@@ -285,7 +292,7 @@ define <4 x float> @test_fadd_imm_1_v4(<4 x float> %a) #0 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<7>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param.v2.b64 {%rd1, %rd2}, [test_fadd_imm_1_v4_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.v2.b64 {%rd1, %rd2}, [test_fadd_imm_1_v4_param_0];
; CHECK-F32X2-NEXT: mov.b32 %r1, 0f40800000;
; CHECK-F32X2-NEXT: mov.b32 %r2, 0f40400000;
; CHECK-F32X2-NEXT: mov.b64 %rd3, {%r2, %r1};
@@ -294,7 +301,7 @@ define <4 x float> @test_fadd_imm_1_v4(<4 x float> %a) #0 {
; CHECK-F32X2-NEXT: mov.b32 %r4, 0f3F800000;
; CHECK-F32X2-NEXT: mov.b64 %rd5, {%r4, %r3};
; CHECK-F32X2-NEXT: add.rn.f32x2 %rd6, %rd1, %rd5;
-; CHECK-F32X2-NEXT: st.param.v2.b64 [func_retval0], {%rd6, %rd4};
+; CHECK-F32X2-NEXT: st.param::func.v2.b64 [func_retval0], {%rd6, %rd4};
; CHECK-F32X2-NEXT: ret;
%r = fadd <4 x float> %a, <float 1.0, float 2.0, float 3.0, float 4.0>
ret <4 x float> %r
@@ -318,10 +325,10 @@ define <2 x float> @test_fsub(<2 x float> %a, <2 x float> %b) #0 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<4>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param.b64 %rd2, [test_fsub_param_1];
-; CHECK-F32X2-NEXT: ld.param.b64 %rd1, [test_fsub_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_fsub_param_1];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_fsub_param_0];
; CHECK-F32X2-NEXT: sub.rn.f32x2 %rd3, %rd1, %rd2;
-; CHECK-F32X2-NEXT: st.param.b64 [func_retval0], %rd3;
+; CHECK-F32X2-NEXT: st.param::func.b64 [func_retval0], %rd3;
; CHECK-F32X2-NEXT: ret;
%r = fsub <2 x float> %a, %b
ret <2 x float> %r
@@ -345,11 +352,11 @@ define <2 x float> @test_fneg(<2 x float> %a) #0 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param.b64 %rd1, [test_fneg_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_fneg_param_0];
; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
; CHECK-F32X2-NEXT: neg.f32 %r3, %r2;
; CHECK-F32X2-NEXT: neg.f32 %r4, %r1;
-; CHECK-F32X2-NEXT: st.param.v2.b32 [func_retval0], {%r4, %r3};
+; CHECK-F32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r4, %r3};
; CHECK-F32X2-NEXT: ret;
%r = fneg <2 x float> %a
ret <2 x float> %r
@@ -373,10 +380,10 @@ define <2 x float> @test_fmul(<2 x float> %a, <2 x float> %b) #0 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<4>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param.b64 %rd2, [test_fmul_param_1];
-; CHECK-F32X2-NEXT: ld.param.b64 %rd1, [test_fmul_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_fmul_param_1];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_fmul_param_0];
; CHECK-F32X2-NEXT: mul.rn.f32x2 %rd3, %rd1, %rd2;
-; CHECK-F32X2-NEXT: st.param.b64 [func_retval0], %rd3;
+; CHECK-F32X2-NEXT: st.param::func.b64 [func_retval0], %rd3;
; CHECK-F32X2-NEXT: ret;
%r = fmul <2 x float> %a, %b
ret <2 x float> %r
@@ -401,13 +408,13 @@ define <2 x float> @test_fdiv(<2 x float> %a, <2 x float> %b) #0 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<3>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param.b64 %rd2, [test_fdiv_param_1];
-; CHECK-F32X2-NEXT: ld.param.b64 %rd1, [test_fdiv_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_fdiv_param_1];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_fdiv_param_0];
; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd2;
; CHECK-F32X2-NEXT: mov.b64 {%r3, %r4}, %rd1;
; CHECK-F32X2-NEXT: div.rn.f32 %r5, %r4, %r2;
; CHECK-F32X2-NEXT: div.rn.f32 %r6, %r3, %r1;
-; CHECK-F32X2-NEXT: st.param.v2.b32 [func_retval0], {%r6, %r5};
+; CHECK-F32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r6, %r5};
; CHECK-F32X2-NEXT: ret;
%r = fdiv <2 x float> %a, %b
ret <2 x float> %r
@@ -444,8 +451,8 @@ define <2 x float> @test_frem(<2 x float> %a, <2 x float> %b) #0 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<3>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param.b64 %rd2, [test_frem_param_1];
-; CHECK-F32X2-NEXT: ld.param.b64 %rd1, [test_frem_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_frem_param_1];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_frem_param_0];
; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd2;
; CHECK-F32X2-NEXT: mov.b64 {%r3, %r4}, %rd1;
; CHECK-F32X2-NEXT: div.rn.f32 %r5, %r4, %r2;
@@ -460,7 +467,7 @@ define <2 x float> @test_frem(<2 x float> %a, <2 x float> %b) #0 {
; CHECK-F32X2-NEXT: fma.rn.f32 %r13, %r12, %r1, %r3;
; CHECK-F32X2-NEXT: testp.infinite.f32 %p2, %r1;
; CHECK-F32X2-NEXT: selp.f32 %r14, %r3, %r13, %p2;
-; CHECK-F32X2-NEXT: st.param.v2.b32 [func_retval0], {%r14, %r9};
+; CHECK-F32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r14, %r9};
; CHECK-F32X2-NEXT: ret;
%r = frem <2 x float> %a, %b
ret <2 x float> %r
@@ -484,10 +491,10 @@ define <2 x float> @test_fadd_ftz(<2 x float> %a, <2 x float> %b) #2 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<4>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param.b64 %rd2, [test_fadd_ftz_param_1];
-; CHECK-F32X2-NEXT: ld.param.b64 %rd1, [test_fadd_ftz_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_fadd_ftz_param_1];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_fadd_ftz_param_0];
; CHECK-F32X2-NEXT: add.rn.ftz.f32x2 %rd3, %rd1, %rd2;
-; CHECK-F32X2-NEXT: st.param.b64 [func_retval0], %rd3;
+; CHECK-F32X2-NEXT: st.param::func.b64 [func_retval0], %rd3;
; CHECK-F32X2-NEXT: ret;
%r = fadd <2 x float> %a, %b
ret <2 x float> %r
@@ -511,12 +518,12 @@ define <2 x float> @test_fadd_imm_0_ftz(<2 x float> %a) #2 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<4>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param.b64 %rd1, [test_fadd_imm_0_ftz_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_fadd_imm_0_ftz_param_0];
; CHECK-F32X2-NEXT: mov.b32 %r1, 0f40000000;
; CHECK-F32X2-NEXT: mov.b32 %r2, 0f3F800000;
; CHECK-F32X2-NEXT: mov.b64 %rd2, {%r2, %r1};
; CHECK-F32X2-NEXT: add.rn.ftz.f32x2 %rd3, %rd1, %rd2;
-; CHECK-F32X2-NEXT: st.param.b64 [func_retval0], %rd3;
+; CHECK-F32X2-NEXT: st.param::func.b64 [func_retval0], %rd3;
; CHECK-F32X2-NEXT: ret;
%r = fadd <2 x float> <float 1.0, float 2.0>, %a
ret <2 x float> %r
@@ -540,12 +547,12 @@ define <2 x float> @test_fadd_imm_1_ftz(<2 x float> %a) #2 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<4>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param.b64 %rd1, [test_fadd_imm_1_ftz_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_fadd_imm_1_ftz_param_0];
; CHECK-F32X2-NEXT: mov.b32 %r1, 0f40000000;
; CHECK-F32X2-NEXT: mov.b32 %r2, 0f3F800000;
; CHECK-F32X2-NEXT: mov.b64 %rd2, {%r2, %r1};
; CHECK-F32X2-NEXT: add.rn.ftz.f32x2 %rd3, %rd1, %rd2;
-; CHECK-F32X2-NEXT: st.param.b64 [func_retval0], %rd3;
+; CHECK-F32X2-NEXT: st.param::func.b64 [func_retval0], %rd3;
; CHECK-F32X2-NEXT: ret;
%r = fadd <2 x float> %a, <float 1.0, float 2.0>
ret <2 x float> %r
@@ -571,11 +578,11 @@ define <4 x float> @test_fadd_v4_ftz(<4 x float> %a, <4 x float> %b) #2 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<7>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param.v2.b64 {%rd3, %rd4}, [test_fadd_v4_ftz_param_1];
-; CHECK-F32X2-NEXT: ld.param.v2.b64 {%rd1, %rd2}, [test_fadd_v4_ftz_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.v2.b64 {%rd3, %rd4}, [test_fadd_v4_ftz_param_1];
+; CHECK-F32X2-NEXT: ld.param::func.v2.b64 {%rd1, %rd2}, [test_fadd_v4_ftz_param_0];
; CHECK-F32X2-NEXT: add.rn.ftz.f32x2 %rd5, %rd2, %rd4;
; CHECK-F32X2-NEXT: add.rn.ftz.f32x2 %rd6, %rd1, %rd3;
-; CHECK-F32X2-NEXT: st.param.v2.b64 [func_retval0], {%rd6, %rd5};
+; CHECK-F32X2-NEXT: st.param::func.v2.b64 [func_retval0], {%rd6, %rd5};
; CHECK-F32X2-NEXT: ret;
%r = fadd <4 x float> %a, %b
ret <4 x float> %r
@@ -601,7 +608,7 @@ define <4 x float> @test_fadd_imm_0_v4_ftz(<4 x float> %a) #2 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<7>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param.v2.b64 {%rd1, %rd2}, [test_fadd_imm_0_v4_ftz_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.v2.b64 {%rd1, %rd2}, [test_fadd_imm_0_v4_ftz_param_0];
; CHECK-F32X2-NEXT: mov.b32 %r1, 0f40800000;
; CHECK-F32X2-NEXT: mov.b32 %r2, 0f40400000;
; CHECK-F32X2-NEXT: mov.b64 %rd3, {%r2, %r1};
@@ -610,7 +617,7 @@ define <4 x float> @test_fadd_imm_0_v4_ftz(<4 x float> %a) #2 {
; CHECK-F32X2-NEXT: mov.b32 %r4, 0f3F800000;
; CHECK-F32X2-NEXT: mov.b64 %rd5, {%r4, %r3};
; CHECK-F32X2-NEXT: add.rn.ftz.f32x2 %rd6, %rd1, %rd5;
-; CHECK-F32X2-NEXT: st.param.v2.b64 [func_retval0], {%rd6, %rd4};
+; CHECK-F32X2-NEXT: st.param::func.v2.b64 [func_retval0], {%rd6, %rd4};
; CHECK-F32X2-NEXT: ret;
%r = fadd <4 x float> <float 1.0, float 2.0, float 3.0, float 4.0>, %a
ret <4 x float> %r
@@ -636,7 +643,7 @@ define <4 x float> @test_fadd_imm_1_v4_ftz(<4 x float> %a) #2 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<7>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param.v2.b64 {%rd1, %rd2}, [test_fadd_imm_1_v4_ftz_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.v2.b64 {%rd1, %rd2}, [test_fadd_imm_1_v4_ftz_param_0];
; CHECK-F32X2-NEXT: mov.b32 %r1, 0f40800000;
; CHECK-F32X2-NEXT: mov.b32 %r2, 0f40400000;
; CHECK-F32X2-NEXT: mov.b64 %rd3, {%r2, %r1};
@@ -645,7 +652,7 @@ define <4 x float> @test_fadd_imm_1_v4_ftz(<4 x float> %a) #2 {
; CHECK-F32X2-NEXT: mov.b32 %r4, 0f3F800000;
; CHECK-F32X2-NEXT: mov.b64 %rd5, {%r4, %r3};
; CHECK-F32X2-NEXT: add.rn.ftz.f32x2 %rd6, %rd1, %rd5;
-; CHECK-F32X2-NEXT: st.param.v2.b64 [func_retval0], {%rd6, %rd4};
+; CHECK-F32X2-NEXT: st.param::func.v2.b64 [func_retval0], {%rd6, %rd4};
; CHECK-F32X2-NEXT: ret;
%r = fadd <4 x float> %a, <float 1.0, float 2.0, float 3.0, float 4.0>
ret <4 x float> %r
@@ -669,10 +676,10 @@ define <2 x float> @test_fsub_ftz(<2 x float> %a, <2 x float> %b) #2 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<4>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param.b64 %rd2, [test_fsub_ftz_param_1];
-; CHECK-F32X2-NEXT: ld.param.b64 %rd1, [test_fsub_ftz_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_fsub_ftz_param_1];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_fsub_ftz_param_0];
; CHECK-F32X2-NEXT: sub.rn.ftz.f32x2 %rd3, %rd1, %rd2;
-; CHECK-F32X2-NEXT: st.param.b64 [func_retval0], %rd3;
+; CHECK-F32X2-NEXT: st.param::func.b64 [func_retval0], %rd3;
; CHECK-F32X2-NEXT: ret;
%r = fsub <2 x float> %a, %b
ret <2 x float> %r
@@ -696,11 +703,11 @@ define <2 x float> @test_fneg_ftz(<2 x float> %a) #2 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param.b64 %rd1, [test_fneg_ftz_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_fneg_ftz_param_0];
; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
; CHECK-F32X2-NEXT: neg.ftz.f32 %r3, %r2;
; CHECK-F32X2-NEXT: neg.ftz.f32 %r4, %r1;
-; CHECK-F32X2-NEXT: st.param.v2.b32 [func_retval0], {%r4, %r3};
+; CHECK-F32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r4, %r3};
; CHECK-F32X2-NEXT: ret;
%r = fneg <2 x float> %a
ret <2 x float> %r
@@ -724,10 +731,10 @@ define <2 x float> @test_fmul_ftz(<2 x float> %a, <2 x float> %b) #2 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<4>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param.b64 %rd2, [test_fmul_ftz_param_1];
-; CHECK-F32X2-NEXT: ld.param.b64 %rd1, [test_fmul_ftz_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_fmul_ftz_param_1];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_fmul_ftz_param_0];
; CHECK-F32X2-NEXT: mul.rn.ftz.f32x2 %rd3, %rd1, %rd2;
-; CHECK-F32X2-NEXT: st.param.b64 [func_retval0], %rd3;
+; CHECK-F32X2-NEXT: st.param::func.b64 [func_retval0], %rd3;
; CHECK-F32X2-NEXT: ret;
%r = fmul <2 x float> %a, %b
ret <2 x float> %r
@@ -752,11 +759,11 @@ define <2 x float> @test_fma_ftz(<2 x float> %a, <2 x float> %b, <2 x float> %c)
; CHECK-F32X2-NEXT: .reg .b64 %rd<5>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param.b64 %rd3, [test_fma_ftz_param_2];
-; CHECK-F32X2-NEXT: ld.param.b64 %rd2, [test_fma_ftz_param_1];
-; CHECK-F32X2-NEXT: ld.param.b64 %rd1, [test_fma_ftz_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd3, [test_fma_ftz_param_2];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_fma_ftz_param_1];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_fma_ftz_param_0];
; CHECK-F32X2-NEXT: fma.rn.ftz.f32x2 %rd4, %rd1, %rd2, %rd3;
-; CHECK-F32X2-NEXT: st.param.b64 [func_retval0], %rd4;
+; CHECK-F32X2-NEXT: st.param::func.b64 [func_retval0], %rd4;
; CHECK-F32X2-NEXT: ret;
%r = call <2 x float> @llvm.fma(<2 x float> %a, <2 x float> %b, <2 x float> %c)
ret <2 x float> %r
@@ -781,13 +788,13 @@ define <2 x float> @test_fdiv_ftz(<2 x float> %a, <2 x float> %b) #2 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<3>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param.b64 %rd2, [test_fdiv_ftz_param_1];
-; CHECK-F32X2-NEXT: ld.param.b64 %rd1, [test_fdiv_ftz_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_fdiv_ftz_param_1];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_fdiv_ftz_param_0];
; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd2;
; CHECK-F32X2-NEXT: mov.b64 {%r3, %r4}, %rd1;
; CHECK-F32X2-NEXT: div.rn.ftz.f32 %r5, %r4, %r2;
; CHECK-F32X2-NEXT: div.rn.ftz.f32 %r6, %r3, %r1;
-; CHECK-F32X2-NEXT: st.param.v2.b32 [func_retval0], {%r6, %r5};
+; CHECK-F32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r6, %r5};
; CHECK-F32X2-NEXT: ret;
%r = fdiv <2 x float> %a, %b
ret <2 x float> %r
@@ -824,8 +831,8 @@ define <2 x float> @test_frem_ftz(<2 x float> %a, <2 x float> %b) #2 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<3>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param.b64 %rd2, [test_frem_ftz_param_1];
-; CHECK-F32X2-NEXT: ld.param.b64 %rd1, [test_frem_ftz_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_frem_ftz_param_1];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_frem_ftz_param_0];
; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd2;
; CHECK-F32X2-NEXT: mov.b64 {%r3, %r4}, %rd1;
; CHECK-F32X2-NEXT: div.rn.ftz.f32 %r5, %r4, %r2;
@@ -840,7 +847,7 @@ define <2 x float> @test_frem_ftz(<2 x float> %a, <2 x float> %b) #2 {
; CHECK-F32X2-NEXT: fma.rn.ftz.f32 %r13, %r12, %r1, %r3;
; CHECK-F32X2-NEXT: testp.infinite.f32 %p2, %r1;
; CHECK-F32X2-NEXT: selp.f32 %r14, %r3, %r13, %p2;
-; CHECK-F32X2-NEXT: st.param.v2.b32 [func_retval0], {%r14, %r9};
+; CHECK-F32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r14, %r9};
; CHECK-F32X2-NEXT: ret;
%r = frem <2 x float> %a, %b
ret <2 x float> %r
@@ -864,8 +871,8 @@ define void @test_ldst_v2f32(ptr %a, ptr %b) #0 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<4>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param.b64 %rd2, [test_ldst_v2f32_param_1];
-; CHECK-F32X2-NEXT: ld.param.b64 %rd1, [test_ldst_v2f32_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_ldst_v2f32_param_1];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_ldst_v2f32_param_0];
; CHECK-F32X2-NEXT: ld.b64 %rd3, [%rd1];
; CHECK-F32X2-NEXT: st.b64 [%rd2], %rd3;
; CHECK-F32X2-NEXT: ret;
@@ -875,19 +882,33 @@ define void @test_ldst_v2f32(ptr %a, ptr %b) #0 {
}
define void @test_ldst_v3f32(ptr %a, ptr %b) #0 {
-; CHECK-LABEL: test_ldst_v3f32(
-; CHECK: {
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-NEXT: .reg .b64 %rd<4>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd2, [test_ldst_v3f32_param_1];
-; CHECK-NEXT: ld.param.b64 %rd1, [test_ldst_v3f32_param_0];
-; CHECK-NEXT: ld.b64 %rd3, [%rd1];
-; CHECK-NEXT: ld.b32 %r1, [%rd1+8];
-; CHECK-NEXT: st.b32 [%rd2+8], %r1;
-; CHECK-NEXT: st.b64 [%rd2], %rd3;
-; CHECK-NEXT: ret;
+; CHECK-NOF32X2-LABEL: test_ldst_v3f32(
+; CHECK-NOF32X2: {
+; CHECK-NOF32X2-NEXT: .reg .b32 %r<2>;
+; CHECK-NOF32X2-NEXT: .reg .b64 %rd<4>;
+; CHECK-NOF32X2-EMPTY:
+; CHECK-NOF32X2-NEXT: // %bb.0:
+; CHECK-NOF32X2-NEXT: ld.param.b64 %rd2, [test_ldst_v3f32_param_1];
+; CHECK-NOF32X2-NEXT: ld.param.b64 %rd1, [test_ldst_v3f32_param_0];
+; CHECK-NOF32X2-NEXT: ld.b64 %rd3, [%rd1];
+; CHECK-NOF32X2-NEXT: ld.b32 %r1, [%rd1+8];
+; CHECK-NOF32X2-NEXT: st.b32 [%rd2+8], %r1;
+; CHECK-NOF32X2-NEXT: st.b64 [%rd2], %rd3;
+; CHECK-NOF32X2-NEXT: ret;
+;
+; CHECK-F32X2-LABEL: test_ldst_v3f32(
+; CHECK-F32X2: {
+; CHECK-F32X2-NEXT: .reg .b32 %r<2>;
+; CHECK-F32X2-NEXT: .reg .b64 %rd<4>;
+; CHECK-F32X2-EMPTY:
+; CHECK-F32X2-NEXT: // %bb.0:
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_ldst_v3f32_param_1];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_ldst_v3f32_param_0];
+; CHECK-F32X2-NEXT: ld.b64 %rd3, [%rd1];
+; CHECK-F32X2-NEXT: ld.b32 %r1, [%rd1+8];
+; CHECK-F32X2-NEXT: st.b32 [%rd2+8], %r1;
+; CHECK-F32X2-NEXT: st.b64 [%rd2], %rd3;
+; CHECK-F32X2-NEXT: ret;
%t1 = load <3 x float>, ptr %a
store <3 x float> %t1, ptr %b, align 32
ret void
@@ -911,8 +932,8 @@ define void @test_ldst_v4f32(ptr %a, ptr %b) #0 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<5>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param.b64 %rd2, [test_ldst_v4f32_param_1];
-; CHECK-F32X2-NEXT: ld.param.b64 %rd1, [test_ldst_v4f32_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_ldst_v4f32_param_1];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_ldst_v4f32_param_0];
; CHECK-F32X2-NEXT: ld.v2.b64 {%rd3, %rd4}, [%rd1];
; CHECK-F32X2-NEXT: st.v2.b64 [%rd2], {%rd3, %rd4};
; CHECK-F32X2-NEXT: ret;
@@ -941,8 +962,8 @@ define void @test_ldst_v8f32(ptr %a, ptr %b) #0 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<7>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param.b64 %rd2, [test_ldst_v8f32_param_1];
-; CHECK-F32X2-NEXT: ld.param.b64 %rd1, [test_ldst_v8f32_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_ldst_v8f32_param_1];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_ldst_v8f32_param_0];
; CHECK-F32X2-NEXT: ld.v2.b64 {%rd3, %rd4}, [%rd1];
; CHECK-F32X2-NEXT: ld.v2.b64 {%rd5, %rd6}, [%rd1+16];
; CHECK-F32X2-NEXT: st.v2.b64 [%rd2+16], {%rd5, %rd6};
@@ -980,18 +1001,18 @@ define <2 x float> @test_call(<2 x float> %a, <2 x float> %b) #0 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<4>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param.b64 %rd2, [test_call_param_1];
-; CHECK-F32X2-NEXT: ld.param.b64 %rd1, [test_call_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_call_param_1];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_call_param_0];
; CHECK-F32X2-NEXT: { // callseq 0, 0
; CHECK-F32X2-NEXT: .param .align 8 .b8 param0[8];
; CHECK-F32X2-NEXT: .param .align 8 .b8 param1[8];
; CHECK-F32X2-NEXT: .param .align 8 .b8 retval0[8];
-; CHECK-F32X2-NEXT: st.param.b64 [param1], %rd2;
-; CHECK-F32X2-NEXT: st.param.b64 [param0], %rd1;
+; CHECK-F32X2-NEXT: st.param::func.b64 [param1], %rd2;
+; CHECK-F32X2-NEXT: st.param::func.b64 [param0], %rd1;
; CHECK-F32X2-NEXT: call.uni (retval0), test_callee, (param0, param1);
-; CHECK-F32X2-NEXT: ld.param.b64 %rd3, [retval0];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd3, [retval0];
; CHECK-F32X2-NEXT: } // callseq 0
-; CHECK-F32X2-NEXT: st.param.b64 [func_retval0], %rd3;
+; CHECK-F32X2-NEXT: st.param::func.b64 [func_retval0], %rd3;
; CHECK-F32X2-NEXT: ret;
%r = call <2 x float> @test_callee(<2 x float> %a, <2 x float> %b)
ret <2 x float> %r
@@ -1022,18 +1043,18 @@ define <2 x float> @test_call_flipped(<2 x float> %a, <2 x float> %b) #0 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<4>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param.b64 %rd2, [test_call_flipped_param_1];
-; CHECK-F32X2-NEXT: ld.param.b64 %rd1, [test_call_flipped_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_call_flipped_param_1];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_call_flipped_param_0];
; CHECK-F32X2-NEXT: { // callseq 1, 0
; CHECK-F32X2-NEXT: .param .align 8 .b8 param0[8];
; CHECK-F32X2-NEXT: .param .align 8 .b8 param1[8];
; CHECK-F32X2-NEXT: .param .align 8 .b8 retval0[8];
-; CHECK-F32X2-NEXT: st.param.b64 [param1], %rd1;
-; CHECK-F32X2-NEXT: st.param.b64 [param0], %rd2;
+; CHECK-F32X2-NEXT: st.param::func.b64 [param1], %rd1;
+; CHECK-F32X2-NEXT: st.param::func.b64 [param0], %rd2;
; CHECK-F32X2-NEXT: call.uni (retval0), test_callee, (param0, param1);
-; CHECK-F32X2-NEXT: ld.param.b64 %rd3, [retval0];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd3, [retval0];
; CHECK-F32X2-NEXT: } // callseq 1
-; CHECK-F32X2-NEXT: st.param.b64 [func_retval0], %rd3;
+; CHECK-F32X2-NEXT: st.param::func.b64 [func_retval0], %rd3;
; CHECK-F32X2-NEXT: ret;
%r = call <2 x float> @test_callee(<2 x float> %b, <2 x float> %a)
ret <2 x float> %r
@@ -1064,18 +1085,18 @@ define <2 x float> @test_tailcall_flipped(<2 x float> %a, <2 x float> %b) #0 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<4>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param.b64 %rd2, [test_tailcall_flipped_param_1];
-; CHECK-F32X2-NEXT: ld.param.b64 %rd1, [test_tailcall_flipped_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_tailcall_flipped_param_1];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_tailcall_flipped_param_0];
; CHECK-F32X2-NEXT: { // callseq 2, 0
; CHECK-F32X2-NEXT: .param .align 8 .b8 param0[8];
; CHECK-F32X2-NEXT: .param .align 8 .b8 param1[8];
; CHECK-F32X2-NEXT: .param .align 8 .b8 retval0[8];
-; CHECK-F32X2-NEXT: st.param.b64 [param1], %rd1;
-; CHECK-F32X2-NEXT: st.param.b64 [param0], %rd2;
+; CHECK-F32X2-NEXT: st.param::func.b64 [param1], %rd1;
+; CHECK-F32X2-NEXT: st.param::func.b64 [param0], %rd2;
; CHECK-F32X2-NEXT: call.uni (retval0), test_callee, (param0, param1);
-; CHECK-F32X2-NEXT: ld.param.b64 %rd3, [retval0];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd3, [retval0];
; CHECK-F32X2-NEXT: } // callseq 2
-; CHECK-F32X2-NEXT: st.param.b64 [func_retval0], %rd3;
+; CHECK-F32X2-NEXT: st.param::func.b64 [func_retval0], %rd3;
; CHECK-F32X2-NEXT: ret;
%r = tail call <2 x float> @test_callee(<2 x float> %b, <2 x float> %a)
ret <2 x float> %r
@@ -1106,13 +1127,13 @@ define <2 x float> @test_select(<2 x float> %a, <2 x float> %b, i1 zeroext %c) #
; CHECK-F32X2-NEXT: .reg .b64 %rd<4>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param.b8 %rs1, [test_select_param_2];
+; CHECK-F32X2-NEXT: ld.param::func.b8 %rs1, [test_select_param_2];
; CHECK-F32X2-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-F32X2-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-F32X2-NEXT: ld.param.b64 %rd2, [test_select_param_1];
-; CHECK-F32X2-NEXT: ld.param.b64 %rd1, [test_select_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_select_param_1];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_select_param_0];
; CHECK-F32X2-NEXT: selp.b64 %rd3, %rd1, %rd2, %p1;
-; CHECK-F32X2-NEXT: st.param.b64 [func_retval0], %rd3;
+; CHECK-F32X2-NEXT: st.param::func.b64 [func_retval0], %rd3;
; CHECK-F32X2-NEXT: ret;
%r = select i1 %c, <2 x float> %a, <2 x float> %b
ret <2 x float> %r
@@ -1143,10 +1164,10 @@ define <2 x float> @test_select_cc(<2 x float> %a, <2 x float> %b, <2 x float> %
; CHECK-F32X2-NEXT: .reg .b64 %rd<5>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param.b64 %rd4, [test_select_cc_param_3];
-; CHECK-F32X2-NEXT: ld.param.b64 %rd3, [test_select_cc_param_2];
-; CHECK-F32X2-NEXT: ld.param.b64 %rd2, [test_select_cc_param_1];
-; CHECK-F32X2-NEXT: ld.param.b64 %rd1, [test_select_cc_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd4, [test_select_cc_param_3];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd3, [test_select_cc_param_2];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_select_cc_param_1];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_select_cc_param_0];
; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd4;
; CHECK-F32X2-NEXT: mov.b64 {%r3, %r4}, %rd3;
; CHECK-F32X2-NEXT: setp.neu.f32 %p1, %r3, %r1;
@@ -1155,7 +1176,7 @@ define <2 x float> @test_select_cc(<2 x float> %a, <2 x float> %b, <2 x float> %
; CHECK-F32X2-NEXT: mov.b64 {%r7, %r8}, %rd1;
; CHECK-F32X2-NEXT: selp.f32 %r9, %r8, %r6, %p2;
; CHECK-F32X2-NEXT: selp.f32 %r10, %r7, %r5, %p1;
-; CHECK-F32X2-NEXT: st.param.v2.b32 [func_retval0], {%r10, %r9};
+; CHECK-F32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r10, %r9};
; CHECK-F32X2-NEXT: ret;
%cc = fcmp une <2 x float> %c, %d
%r = select <2 x i1> %cc, <2 x float> %a, <2 x float> %b
@@ -1188,17 +1209,17 @@ define <2 x double> @test_select_cc_f64_f32(<2 x double> %a, <2 x double> %b, <2
; CHECK-F32X2-NEXT: .reg .b64 %rd<9>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param.v2.b64 {%rd3, %rd4}, [test_select_cc_f64_f32_param_1];
-; CHECK-F32X2-NEXT: ld.param.v2.b64 {%rd1, %rd2}, [test_select_cc_f64_f32_param_0];
-; CHECK-F32X2-NEXT: ld.param.b64 %rd6, [test_select_cc_f64_f32_param_3];
-; CHECK-F32X2-NEXT: ld.param.b64 %rd5, [test_select_cc_f64_f32_param_2];
+; CHECK-F32X2-NEXT: ld.param::func.v2.b64 {%rd3, %rd4}, [test_select_cc_f64_f32_param_1];
+; CHECK-F32X2-NEXT: ld.param::func.v2.b64 {%rd1, %rd2}, [test_select_cc_f64_f32_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd6, [test_select_cc_f64_f32_param_3];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd5, [test_select_cc_f64_f32_param_2];
; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd6;
; CHECK-F32X2-NEXT: mov.b64 {%r3, %r4}, %rd5;
; CHECK-F32X2-NEXT: setp.neu.f32 %p1, %r3, %r1;
; CHECK-F32X2-NEXT: setp.neu.f32 %p2, %r4, %r2;
; CHECK-F32X2-NEXT: selp.f64 %rd7, %rd2, %rd4, %p2;
; CHECK-F32X2-NEXT: selp.f64 %rd8, %rd1, %rd3, %p1;
-; CHECK-F32X2-NEXT: st.param.v2.b64 [func_retval0], {%rd8, %rd7};
+; CHECK-F32X2-NEXT: st.param::func.v2.b64 [func_retval0], {%rd8, %rd7};
; CHECK-F32X2-NEXT: ret;
%cc = fcmp une <2 x float> %c, %d
%r = select <2 x i1> %cc, <2 x double> %a, <2 x double> %b
@@ -1231,17 +1252,17 @@ define <2 x float> @test_select_cc_f32_f64(<2 x float> %a, <2 x float> %b, <2 x
; CHECK-F32X2-NEXT: .reg .b64 %rd<7>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param.v2.b64 {%rd5, %rd6}, [test_select_cc_f32_f64_param_3];
-; CHECK-F32X2-NEXT: ld.param.v2.b64 {%rd3, %rd4}, [test_select_cc_f32_f64_param_2];
-; CHECK-F32X2-NEXT: ld.param.b64 %rd2, [test_select_cc_f32_f64_param_1];
-; CHECK-F32X2-NEXT: ld.param.b64 %rd1, [test_select_cc_f32_f64_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.v2.b64 {%rd5, %rd6}, [test_select_cc_f32_f64_param_3];
+; CHECK-F32X2-NEXT: ld.param::func.v2.b64 {%rd3, %rd4}, [test_select_cc_f32_f64_param_2];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_select_cc_f32_f64_param_1];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_select_cc_f32_f64_param_0];
; CHECK-F32X2-NEXT: setp.neu.f64 %p1, %rd3, %rd5;
; CHECK-F32X2-NEXT: setp.neu.f64 %p2, %rd4, %rd6;
; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd2;
; CHECK-F32X2-NEXT: mov.b64 {%r3, %r4}, %rd1;
; CHECK-F32X2-NEXT: selp.f32 %r5, %r4, %r2, %p2;
; CHECK-F32X2-NEXT: selp.f32 %r6, %r3, %r1, %p1;
-; CHECK-F32X2-NEXT: st.param.v2.b32 [func_retval0], {%r6, %r5};
+; CHECK-F32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r6, %r5};
; CHECK-F32X2-NEXT: ret;
%cc = fcmp une <2 x double> %c, %d
%r = select <2 x i1> %cc, <2 x float> %a, <2 x float> %b
@@ -1274,16 +1295,16 @@ define <2 x i1> @test_fcmp_une(<2 x float> %a, <2 x float> %b) #0 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<3>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param.b64 %rd2, [test_fcmp_une_param_1];
-; CHECK-F32X2-NEXT: ld.param.b64 %rd1, [test_fcmp_une_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_fcmp_une_param_1];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_fcmp_une_param_0];
; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd2;
; CHECK-F32X2-NEXT: mov.b64 {%r3, %r4}, %rd1;
; CHECK-F32X2-NEXT: setp.neu.f32 %p1, %r4, %r2;
; CHECK-F32X2-NEXT: setp.neu.f32 %p2, %r3, %r1;
; CHECK-F32X2-NEXT: selp.b16 %rs1, -1, 0, %p2;
-; CHECK-F32X2-NEXT: st.param.b8 [func_retval0], %rs1;
+; CHECK-F32X2-NEXT: st.param::func.b8 [func_retval0], %rs1;
; CHECK-F32X2-NEXT: selp.b16 %rs2, -1, 0, %p1;
-; CHECK-F32X2-NEXT: st.param.b8 [func_retval0+1], %rs2;
+; CHECK-F32X2-NEXT: st.param::func.b8 [func_retval0+1], %rs2;
; CHECK-F32X2-NEXT: ret;
%r = fcmp une <2 x float> %a, %b
ret <2 x i1> %r
@@ -1315,16 +1336,16 @@ define <2 x i1> @test_fcmp_ueq(<2 x float> %a, <2 x float> %b) #0 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<3>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param.b64 %rd2, [test_fcmp_ueq_param_1];
-; CHECK-F32X2-NEXT: ld.param.b64 %rd1, [test_fcmp_ueq_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_fcmp_ueq_param_1];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_fcmp_ueq_param_0];
; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd2;
; CHECK-F32X2-NEXT: mov.b64 {%r3, %r4}, %rd1;
; CHECK-F32X2-NEXT: setp.equ.f32 %p1, %r4, %r2;
; CHECK-F32X2-NEXT: setp.equ.f32 %p2, %r3, %r1;
; CHECK-F32X2-NEXT: selp.b16 %rs1, -1, 0, %p2;
-; CHECK-F32X2-NEXT: st.param.b8 [func_retval0], %rs1;
+; CHECK-F32X2-NEXT: st.param::func.b8 [func_retval0], %rs1;
; CHECK-F32X2-NEXT: selp.b16 %rs2, -1, 0, %p1;
-; CHECK-F32X2-NEXT: st.param.b8 [func_retval0+1], %rs2;
+; CHECK-F32X2-NEXT: st.param::func.b8 [func_retval0+1], %rs2;
; CHECK-F32X2-NEXT: ret;
%r = fcmp ueq <2 x float> %a, %b
ret <2 x i1> %r
@@ -1356,16 +1377,16 @@ define <2 x i1> @test_fcmp_ugt(<2 x float> %a, <2 x float> %b) #0 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<3>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param.b64 %rd2, [test_fcmp_ugt_param_1];
-; CHECK-F32X2-NEXT: ld.param.b64 %rd1, [test_fcmp_ugt_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_fcmp_ugt_param_1];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_fcmp_ugt_param_0];
; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd2;
; CHECK-F32X2-NEXT: mov.b64 {%r3, %r4}, %rd1;
; CHECK-F32X2-NEXT: setp.gtu.f32 %p1, %r4, %r2;
; CHECK-F32X2-NEXT: setp.gtu.f32 %p2, %r3, %r1;
; CHECK-F32X2-NEXT: selp.b16 %rs1, -1, 0, %p2;
-; CHECK-F32X2-NEXT: st.param.b8 [func_retval0], %rs1;
+; CHECK-F32X2-NEXT: st.param::func.b8 [func_retval0], %rs1;
; CHECK-F32X2-NEXT: selp.b16 %rs2, -1, 0, %p1;
-; CHECK-F32X2-NEXT: st.param.b8 [func_retval0+1], %rs2;
+; CHECK-F32X2-NEXT: st.param::func.b8 [func_retval0+1], %rs2;
; CHECK-F32X2-NEXT: ret;
%r = fcmp ugt <2 x float> %a, %b
ret <2 x i1> %r
@@ -1397,16 +1418,16 @@ define <2 x i1> @test_fcmp_uge(<2 x float> %a, <2 x float> %b) #0 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<3>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param.b64 %rd2, [test_fcmp_uge_param_1];
-; CHECK-F32X2-NEXT: ld.param.b64 %rd1, [test_fcmp_uge_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_fcmp_uge_param_1];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_fcmp_uge_param_0];
; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd2;
; CHECK-F32X2-NEXT: mov.b64 {%r3, %r4}, %rd1;
; CHECK-F32X2-NEXT: setp.geu.f32 %p1, %r4, %r2;
; CHECK-F32X2-NEXT: setp.geu.f32 %p2, %r3, %r1;
; CHECK-F32X2-NEXT: selp.b16 %rs1, -1, 0, %p2;
-; CHECK-F32X2-NEXT: st.param.b8 [func_retval0], %rs1;
+; CHECK-F32X2-NEXT: st.param::func.b8 [func_retval0], %rs1;
; CHECK-F32X2-NEXT: selp.b16 %rs2, -1, 0, %p1;
-; CHECK-F32X2-NEXT: st.param.b8 [func_retval0+1], %rs2;
+; CHECK-F32X2-NEXT: st.param::func.b8 [func_retval0+1], %rs2;
; CHECK-F32X2-NEXT: ret;
%r = fcmp uge <2 x float> %a, %b
ret <2 x i1> %r
@@ -1438,16 +1459,16 @@ define <2 x i1> @test_fcmp_ult(<2 x float> %a, <2 x float> %b) #0 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<3>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param.b64 %rd2, [test_fcmp_ult_param_1];
-; CHECK-F32X2-NEXT: ld.param.b64 %rd1, [test_fcmp_ult_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_fcmp_ult_param_1];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_fcmp_ult_param_0];
; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd2;
; CHECK-F32X2-NEXT: mov.b64 {%r3, %r4}, %rd1;
; CHECK-F32X2-NEXT: setp.ltu.f32 %p1, %r4, %r2;
; CHECK-F32X2-NEXT: setp.ltu.f32 %p2, %r3, %r1;
; CHECK-F32X2-NEXT: selp.b16 %rs1, -1, 0, %p2;
-; CHECK-F32X2-NEXT: st.param.b8 [func_retval0], %rs1;
+; CHECK-F32X2-NEXT: st.param::func.b8 [func_retval0], %rs1;
; CHECK-F32X2-NEXT: selp.b16 %rs2, -1, 0, %p1;
-; CHECK-F32X2-NEXT: st.param.b8 [func_retval0+1], %rs2;
+; CHECK-F32X2-NEXT: st.param::func.b8 [func_retval0+1], %rs2;
; CHECK-F32X2-NEXT: ret;
%r = fcmp ult <2 x float> %a, %b
ret <2 x i1> %r
@@ -1479,16 +1500,16 @@ define <2 x i1> @test_fcmp_ule(<2 x float> %a, <2 x float> %b) #0 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<3>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param.b64 %rd2, [test_fcmp_ule_param_1];
-; CHECK-F32X2-NEXT: ld.param.b64 %rd1, [test_fcmp_ule_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_fcmp_ule_param_1];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_fcmp_ule_param_0];
; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd2;
; CHECK-F32X2-NEXT: mov.b64 {%r3, %r4}, %rd1;
; CHECK-F32X2-NEXT: setp.leu.f32 %p1, %r4, %r2;
; CHECK-F32X2-NEXT: setp.leu.f32 %p2, %r3, %r1;
; CHECK-F32X2-NEXT: selp.b16 %rs1, -1, 0, %p2;
-; CHECK-F32X2-NEXT: st.param.b8 [func_retval0], %rs1;
+; CHECK-F32X2-NEXT: st.param::func.b8 [func_retval0], %rs1;
; CHECK-F32X2-NEXT: selp.b16 %rs2, -1, 0, %p1;
-; CHECK-F32X2-NEXT: st.param.b8 [func_retval0+1], %rs2;
+; CHECK-F32X2-NEXT: st.param::func.b8 [func_retval0+1], %rs2;
; CHECK-F32X2-NEXT: ret;
%r = fcmp ule <2 x float> %a, %b
ret <2 x i1> %r
@@ -1520,16 +1541,16 @@ define <2 x i1> @test_fcmp_uno(<2 x float> %a, <2 x float> %b) #0 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<3>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param.b64 %rd2, [test_fcmp_uno_param_1];
-; CHECK-F32X2-NEXT: ld.param.b64 %rd1, [test_fcmp_uno_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_fcmp_uno_param_1];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_fcmp_uno_param_0];
; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd2;
; CHECK-F32X2-NEXT: mov.b64 {%r3, %r4}, %rd1;
; CHECK-F32X2-NEXT: setp.nan.f32 %p1, %r4, %r2;
; CHECK-F32X2-NEXT: setp.nan.f32 %p2, %r3, %r1;
; CHECK-F32X2-NEXT: selp.b16 %rs1, -1, 0, %p2;
-; CHECK-F32X2-NEXT: st.param.b8 [func_retval0], %rs1;
+; CHECK-F32X2-NEXT: st.param::func.b8 [func_retval0], %rs1;
; CHECK-F32X2-NEXT: selp.b16 %rs2, -1, 0, %p1;
-; CHECK-F32X2-NEXT: st.param.b8 [func_retval0+1], %rs2;
+; CHECK-F32X2-NEXT: st.param::func.b8 [func_retval0+1], %rs2;
; CHECK-F32X2-NEXT: ret;
%r = fcmp uno <2 x float> %a, %b
ret <2 x i1> %r
@@ -1561,16 +1582,16 @@ define <2 x i1> @test_fcmp_one(<2 x float> %a, <2 x float> %b) #0 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<3>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param.b64 %rd2, [test_fcmp_one_param_1];
-; CHECK-F32X2-NEXT: ld.param.b64 %rd1, [test_fcmp_one_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_fcmp_one_param_1];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_fcmp_one_param_0];
; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd2;
; CHECK-F32X2-NEXT: mov.b64 {%r3, %r4}, %rd1;
; CHECK-F32X2-NEXT: setp.ne.f32 %p1, %r4, %r2;
; CHECK-F32X2-NEXT: setp.ne.f32 %p2, %r3, %r1;
; CHECK-F32X2-NEXT: selp.b16 %rs1, -1, 0, %p2;
-; CHECK-F32X2-NEXT: st.param.b8 [func_retval0], %rs1;
+; CHECK-F32X2-NEXT: st.param::func.b8 [func_retval0], %rs1;
; CHECK-F32X2-NEXT: selp.b16 %rs2, -1, 0, %p1;
-; CHECK-F32X2-NEXT: st.param.b8 [func_retval0+1], %rs2;
+; CHECK-F32X2-NEXT: st.param::func.b8 [func_retval0+1], %rs2;
; CHECK-F32X2-NEXT: ret;
%r = fcmp one <2 x float> %a, %b
ret <2 x i1> %r
@@ -1602,16 +1623,16 @@ define <2 x i1> @test_fcmp_oeq(<2 x float> %a, <2 x float> %b) #0 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<3>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param.b64 %rd2, [test_fcmp_oeq_param_1];
-; CHECK-F32X2-NEXT: ld.param.b64 %rd1, [test_fcmp_oeq_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_fcmp_oeq_param_1];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_fcmp_oeq_param_0];
; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd2;
; CHECK-F32X2-NEXT: mov.b64 {%r3, %r4}, %rd1;
; CHECK-F32X2-NEXT: setp.eq.f32 %p1, %r4, %r2;
; CHECK-F32X2-NEXT: setp.eq.f32 %p2, %r3, %r1;
; CHECK-F32X2-NEXT: selp.b16 %rs1, -1, 0, %p2;
-; CHECK-F32X2-NEXT: st.param.b8 [func_retval0], %rs1;
+; CHECK-F32X2-NEXT: st.param::func.b8 [func_retval0], %rs1;
; CHECK-F32X2-NEXT: selp.b16 %rs2, -1, 0, %p1;
-; CHECK-F32X2-NEXT: st.param.b8 [func_retval0+1], %rs2;
+; CHECK-F32X2-NEXT: st.param::func.b8 [func_retval0+1], %rs2;
; CHECK-F32X2-NEXT: ret;
%r = fcmp oeq <2 x float> %a, %b
ret <2 x i1> %r
@@ -1643,16 +1664,16 @@ define <2 x i1> @test_fcmp_ogt(<2 x float> %a, <2 x float> %b) #0 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<3>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param.b64 %rd2, [test_fcmp_ogt_param_1];
-; CHECK-F32X2-NEXT: ld.param.b64 %rd1, [test_fcmp_ogt_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_fcmp_ogt_param_1];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_fcmp_ogt_param_0];
; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd2;
; CHECK-F32X2-NEXT: mov.b64 {%r3, %r4}, %rd1;
; CHECK-F32X2-NEXT: setp.gt.f32 %p1, %r4, %r2;
; CHECK-F32X2-NEXT: setp.gt.f32 %p2, %r3, %r1;
; CHECK-F32X2-NEXT: selp.b16 %rs1, -1, 0, %p2;
-; CHECK-F32X2-NEXT: st.param.b8 [func_retval0], %rs1;
+; CHECK-F32X2-NEXT: st.param::func.b8 [func_retval0], %rs1;
; CHECK-F32X2-NEXT: selp.b16 %rs2, -1, 0, %p1;
-; CHECK-F32X2-NEXT: st.param.b8 [func_retval0+1], %rs2;
+; CHECK-F32X2-NEXT: st.param::func.b8 [func_retval0+1], %rs2;
; CHECK-F32X2-NEXT: ret;
%r = fcmp ogt <2 x float> %a, %b
ret <2 x i1> %r
@@ -1684,16 +1705,16 @@ define <2 x i1> @test_fcmp_oge(<2 x float> %a, <2 x float> %b) #0 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<3>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param.b64 %rd2, [test_fcmp_oge_param_1];
-; CHECK-F32X2-NEXT: ld.param.b64 %rd1, [test_fcmp_oge_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_fcmp_oge_param_1];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_fcmp_oge_param_0];
; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd2;
; CHECK-F32X2-NEXT: mov.b64 {%r3, %r4}, %rd1;
; CHECK-F32X2-NEXT: setp.ge.f32 %p1, %r4, %r2;
; CHECK-F32X2-NEXT: setp.ge.f32 %p2, %r3, %r1;
; CHECK-F32X2-NEXT: selp.b16 %rs1, -1, 0, %p2;
-; CHECK-F32X2-NEXT: st.param.b8 [func_retval0], %rs1;
+; CHECK-F32X2-NEXT: st.param::func.b8 [func_retval0], %rs1;
; CHECK-F32X2-NEXT: selp.b16 %rs2, -1, 0, %p1;
-; CHECK-F32X2-NEXT: st.param.b8 [func_retval0+1], %rs2;
+; CHECK-F32X2-NEXT: st.param::func.b8 [func_retval0+1], %rs2;
; CHECK-F32X2-NEXT: ret;
%r = fcmp oge <2 x float> %a, %b
ret <2 x i1> %r
@@ -1725,16 +1746,16 @@ define <2 x i1> @test_fcmp_olt(<2 x float> %a, <2 x float> %b) #0 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<3>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param.b64 %rd2, [test_fcmp_olt_param_1];
-; CHECK-F32X2-NEXT: ld.param.b64 %rd1, [test_fcmp_olt_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_fcmp_olt_param_1];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_fcmp_olt_param_0];
; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd2;
; CHECK-F32X2-NEXT: mov.b64 {%r3, %r4}, %rd1;
; CHECK-F32X2-NEXT: setp.lt.f32 %p1, %r4, %r2;
; CHECK-F32X2-NEXT: setp.lt.f32 %p2, %r3, %r1;
; CHECK-F32X2-NEXT: selp.b16 %rs1, -1, 0, %p2;
-; CHECK-F32X2-NEXT: st.param.b8 [func_retval0], %rs1;
+; CHECK-F32X2-NEXT: st.param::func.b8 [func_retval0], %rs1;
; CHECK-F32X2-NEXT: selp.b16 %rs2, -1, 0, %p1;
-; CHECK-F32X2-NEXT: st.param.b8 [func_retval0+1], %rs2;
+; CHECK-F32X2-NEXT: st.param::func.b8 [func_retval0+1], %rs2;
; CHECK-F32X2-NEXT: ret;
%r = fcmp olt <2 x float> %a, %b
ret <2 x i1> %r
@@ -1766,16 +1787,16 @@ define <2 x i1> @test_fcmp_ole(<2 x float> %a, <2 x float> %b) #0 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<3>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param.b64 %rd2, [test_fcmp_ole_param_1];
-; CHECK-F32X2-NEXT: ld.param.b64 %rd1, [test_fcmp_ole_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_fcmp_ole_param_1];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_fcmp_ole_param_0];
; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd2;
; CHECK-F32X2-NEXT: mov.b64 {%r3, %r4}, %rd1;
; CHECK-F32X2-NEXT: setp.le.f32 %p1, %r4, %r2;
; CHECK-F32X2-NEXT: setp.le.f32 %p2, %r3, %r1;
; CHECK-F32X2-NEXT: selp.b16 %rs1, -1, 0, %p2;
-; CHECK-F32X2-NEXT: st.param.b8 [func_retval0], %rs1;
+; CHECK-F32X2-NEXT: st.param::func.b8 [func_retval0], %rs1;
; CHECK-F32X2-NEXT: selp.b16 %rs2, -1, 0, %p1;
-; CHECK-F32X2-NEXT: st.param.b8 [func_retval0+1], %rs2;
+; CHECK-F32X2-NEXT: st.param::func.b8 [func_retval0+1], %rs2;
; CHECK-F32X2-NEXT: ret;
%r = fcmp ole <2 x float> %a, %b
ret <2 x i1> %r
@@ -1807,16 +1828,16 @@ define <2 x i1> @test_fcmp_ord(<2 x float> %a, <2 x float> %b) #0 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<3>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param.b64 %rd2, [test_fcmp_ord_param_1];
-; CHECK-F32X2-NEXT: ld.param.b64 %rd1, [test_fcmp_ord_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_fcmp_ord_param_1];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_fcmp_ord_param_0];
; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd2;
; CHECK-F32X2-NEXT: mov.b64 {%r3, %r4}, %rd1;
; CHECK-F32X2-NEXT: setp.num.f32 %p1, %r4, %r2;
; CHECK-F32X2-NEXT: setp.num.f32 %p2, %r3, %r1;
; CHECK-F32X2-NEXT: selp.b16 %rs1, -1, 0, %p2;
-; CHECK-F32X2-NEXT: st.param.b8 [func_retval0], %rs1;
+; CHECK-F32X2-NEXT: st.param::func.b8 [func_retval0], %rs1;
; CHECK-F32X2-NEXT: selp.b16 %rs2, -1, 0, %p1;
-; CHECK-F32X2-NEXT: st.param.b8 [func_retval0+1], %rs2;
+; CHECK-F32X2-NEXT: st.param::func.b8 [func_retval0+1], %rs2;
; CHECK-F32X2-NEXT: ret;
%r = fcmp ord <2 x float> %a, %b
ret <2 x i1> %r
@@ -1840,11 +1861,11 @@ define <2 x i32> @test_fptosi_i32(<2 x float> %a) #0 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param.b64 %rd1, [test_fptosi_i32_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_fptosi_i32_param_0];
; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
; CHECK-F32X2-NEXT: cvt.rzi.s32.f32 %r3, %r2;
; CHECK-F32X2-NEXT: cvt.rzi.s32.f32 %r4, %r1;
-; CHECK-F32X2-NEXT: st.param.v2.b32 [func_retval0], {%r4, %r3};
+; CHECK-F32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r4, %r3};
; CHECK-F32X2-NEXT: ret;
%r = fptosi <2 x float> %a to <2 x i32>
ret <2 x i32> %r
@@ -1869,11 +1890,11 @@ define <2 x i64> @test_fptosi_i64(<2 x float> %a) #0 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<4>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param.b64 %rd1, [test_fptosi_i64_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_fptosi_i64_param_0];
; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
; CHECK-F32X2-NEXT: cvt.rzi.s64.f32 %rd2, %r2;
; CHECK-F32X2-NEXT: cvt.rzi.s64.f32 %rd3, %r1;
-; CHECK-F32X2-NEXT: st.param.v2.b64 [func_retval0], {%rd3, %rd2};
+; CHECK-F32X2-NEXT: st.param::func.v2.b64 [func_retval0], {%rd3, %rd2};
; CHECK-F32X2-NEXT: ret;
%r = fptosi <2 x float> %a to <2 x i64>
ret <2 x i64> %r
@@ -1897,11 +1918,11 @@ define <2 x i32> @test_fptoui_2xi32(<2 x float> %a) #0 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param.b64 %rd1, [test_fptoui_2xi32_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_fptoui_2xi32_param_0];
; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
; CHECK-F32X2-NEXT: cvt.rzi.u32.f32 %r3, %r2;
; CHECK-F32X2-NEXT: cvt.rzi.u32.f32 %r4, %r1;
-; CHECK-F32X2-NEXT: st.param.v2.b32 [func_retval0], {%r4, %r3};
+; CHECK-F32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r4, %r3};
; CHECK-F32X2-NEXT: ret;
%r = fptoui <2 x float> %a to <2 x i32>
ret <2 x i32> %r
@@ -1926,11 +1947,11 @@ define <2 x i64> @test_fptoui_2xi64(<2 x float> %a) #0 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<4>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param.b64 %rd1, [test_fptoui_2xi64_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_fptoui_2xi64_param_0];
; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
; CHECK-F32X2-NEXT: cvt.rzi.u64.f32 %rd2, %r2;
; CHECK-F32X2-NEXT: cvt.rzi.u64.f32 %rd3, %r1;
-; CHECK-F32X2-NEXT: st.param.v2.b64 [func_retval0], {%rd3, %rd2};
+; CHECK-F32X2-NEXT: st.param::func.v2.b64 [func_retval0], {%rd3, %rd2};
; CHECK-F32X2-NEXT: ret;
%r = fptoui <2 x float> %a to <2 x i64>
ret <2 x i64> %r
@@ -1954,28 +1975,40 @@ define <2 x float> @test_uitofp_2xi32(<2 x i32> %a) #0 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param.b64 %rd1, [test_uitofp_2xi32_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_uitofp_2xi32_param_0];
; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
; CHECK-F32X2-NEXT: cvt.rn.f32.u32 %r3, %r2;
; CHECK-F32X2-NEXT: cvt.rn.f32.u32 %r4, %r1;
-; CHECK-F32X2-NEXT: st.param.v2.b32 [func_retval0], {%r4, %r3};
+; CHECK-F32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r4, %r3};
; CHECK-F32X2-NEXT: ret;
%r = uitofp <2 x i32> %a to <2 x float>
ret <2 x float> %r
}
define <2 x float> @test_uitofp_2xi64(<2 x i64> %a) #0 {
-; CHECK-LABEL: test_uitofp_2xi64(
-; CHECK: {
-; CHECK-NEXT: .reg .b32 %r<3>;
-; CHECK-NEXT: .reg .b64 %rd<3>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.v2.b64 {%rd1, %rd2}, [test_uitofp_2xi64_param_0];
-; CHECK-NEXT: cvt.rn.f32.u64 %r1, %rd2;
-; CHECK-NEXT: cvt.rn.f32.u64 %r2, %rd1;
-; CHECK-NEXT: st.param.v2.b32 [func_retval0], {%r2, %r1};
-; CHECK-NEXT: ret;
+; CHECK-NOF32X2-LABEL: test_uitofp_2xi64(
+; CHECK-NOF32X2: {
+; CHECK-NOF32X2-NEXT: .reg .b32 %r<3>;
+; CHECK-NOF32X2-NEXT: .reg .b64 %rd<3>;
+; CHECK-NOF32X2-EMPTY:
+; CHECK-NOF32X2-NEXT: // %bb.0:
+; CHECK-NOF32X2-NEXT: ld.param.v2.b64 {%rd1, %rd2}, [test_uitofp_2xi64_param_0];
+; CHECK-NOF32X2-NEXT: cvt.rn.f32.u64 %r1, %rd2;
+; CHECK-NOF32X2-NEXT: cvt.rn.f32.u64 %r2, %rd1;
+; CHECK-NOF32X2-NEXT: st.param.v2.b32 [func_retval0], {%r2, %r1};
+; CHECK-NOF32X2-NEXT: ret;
+;
+; CHECK-F32X2-LABEL: test_uitofp_2xi64(
+; CHECK-F32X2: {
+; CHECK-F32X2-NEXT: .reg .b32 %r<3>;
+; CHECK-F32X2-NEXT: .reg .b64 %rd<3>;
+; CHECK-F32X2-EMPTY:
+; CHECK-F32X2-NEXT: // %bb.0:
+; CHECK-F32X2-NEXT: ld.param::func.v2.b64 {%rd1, %rd2}, [test_uitofp_2xi64_param_0];
+; CHECK-F32X2-NEXT: cvt.rn.f32.u64 %r1, %rd2;
+; CHECK-F32X2-NEXT: cvt.rn.f32.u64 %r2, %rd1;
+; CHECK-F32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r2, %r1};
+; CHECK-F32X2-NEXT: ret;
%r = uitofp <2 x i64> %a to <2 x float>
ret <2 x float> %r
}
@@ -1998,28 +2031,40 @@ define <2 x float> @test_sitofp_2xi32(<2 x i32> %a) #0 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param.b64 %rd1, [test_sitofp_2xi32_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_sitofp_2xi32_param_0];
; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
; CHECK-F32X2-NEXT: cvt.rn.f32.s32 %r3, %r2;
; CHECK-F32X2-NEXT: cvt.rn.f32.s32 %r4, %r1;
-; CHECK-F32X2-NEXT: st.param.v2.b32 [func_retval0], {%r4, %r3};
+; CHECK-F32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r4, %r3};
; CHECK-F32X2-NEXT: ret;
%r = sitofp <2 x i32> %a to <2 x float>
ret <2 x float> %r
}
define <2 x float> @test_sitofp_2xi64(<2 x i64> %a) #0 {
-; CHECK-LABEL: test_sitofp_2xi64(
-; CHECK: {
-; CHECK-NEXT: .reg .b32 %r<3>;
-; CHECK-NEXT: .reg .b64 %rd<3>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.v2.b64 {%rd1, %rd2}, [test_sitofp_2xi64_param_0];
-; CHECK-NEXT: cvt.rn.f32.s64 %r1, %rd2;
-; CHECK-NEXT: cvt.rn.f32.s64 %r2, %rd1;
-; CHECK-NEXT: st.param.v2.b32 [func_retval0], {%r2, %r1};
-; CHECK-NEXT: ret;
+; CHECK-NOF32X2-LABEL: test_sitofp_2xi64(
+; CHECK-NOF32X2: {
+; CHECK-NOF32X2-NEXT: .reg .b32 %r<3>;
+; CHECK-NOF32X2-NEXT: .reg .b64 %rd<3>;
+; CHECK-NOF32X2-EMPTY:
+; CHECK-NOF32X2-NEXT: // %bb.0:
+; CHECK-NOF32X2-NEXT: ld.param.v2.b64 {%rd1, %rd2}, [test_sitofp_2xi64_param_0];
+; CHECK-NOF32X2-NEXT: cvt.rn.f32.s64 %r1, %rd2;
+; CHECK-NOF32X2-NEXT: cvt.rn.f32.s64 %r2, %rd1;
+; CHECK-NOF32X2-NEXT: st.param.v2.b32 [func_retval0], {%r2, %r1};
+; CHECK-NOF32X2-NEXT: ret;
+;
+; CHECK-F32X2-LABEL: test_sitofp_2xi64(
+; CHECK-F32X2: {
+; CHECK-F32X2-NEXT: .reg .b32 %r<3>;
+; CHECK-F32X2-NEXT: .reg .b64 %rd<3>;
+; CHECK-F32X2-EMPTY:
+; CHECK-F32X2-NEXT: // %bb.0:
+; CHECK-F32X2-NEXT: ld.param::func.v2.b64 {%rd1, %rd2}, [test_sitofp_2xi64_param_0];
+; CHECK-F32X2-NEXT: cvt.rn.f32.s64 %r1, %rd2;
+; CHECK-F32X2-NEXT: cvt.rn.f32.s64 %r2, %rd1;
+; CHECK-F32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r2, %r1};
+; CHECK-F32X2-NEXT: ret;
%r = sitofp <2 x i64> %a to <2 x float>
ret <2 x float> %r
}
@@ -2045,14 +2090,14 @@ define <2 x float> @test_uitofp_2xi32_fadd(<2 x i32> %a, <2 x float> %b) #0 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<5>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param.b64 %rd2, [test_uitofp_2xi32_fadd_param_1];
-; CHECK-F32X2-NEXT: ld.param.b64 %rd1, [test_uitofp_2xi32_fadd_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_uitofp_2xi32_fadd_param_1];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_uitofp_2xi32_fadd_param_0];
; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
; CHECK-F32X2-NEXT: cvt.rn.f32.u32 %r3, %r2;
; CHECK-F32X2-NEXT: cvt.rn.f32.u32 %r4, %r1;
; CHECK-F32X2-NEXT: mov.b64 %rd3, {%r4, %r3};
; CHECK-F32X2-NEXT: add.rn.f32x2 %rd4, %rd2, %rd3;
-; CHECK-F32X2-NEXT: st.param.b64 [func_retval0], %rd4;
+; CHECK-F32X2-NEXT: st.param::func.b64 [func_retval0], %rd4;
; CHECK-F32X2-NEXT: ret;
%c = uitofp <2 x i32> %a to <2 x float>
%r = fadd <2 x float> %b, %c
@@ -2078,11 +2123,11 @@ define <2 x float> @test_fptrunc_2xdouble(<2 x double> %a) #0 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<4>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param.v2.b64 {%rd1, %rd2}, [test_fptrunc_2xdouble_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.v2.b64 {%rd1, %rd2}, [test_fptrunc_2xdouble_param_0];
; CHECK-F32X2-NEXT: cvt.rn.f32.f64 %r1, %rd2;
; CHECK-F32X2-NEXT: cvt.rn.f32.f64 %r2, %rd1;
; CHECK-F32X2-NEXT: mov.b64 %rd3, {%r2, %r1};
-; CHECK-F32X2-NEXT: st.param.b64 [func_retval0], %rd3;
+; CHECK-F32X2-NEXT: st.param::func.b64 [func_retval0], %rd3;
; CHECK-F32X2-NEXT: ret;
%r = fptrunc <2 x double> %a to <2 x float>
ret <2 x float> %r
@@ -2107,11 +2152,11 @@ define <2 x double> @test_fpext_2xdouble(<2 x float> %a) #0 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<4>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param.b64 %rd1, [test_fpext_2xdouble_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_fpext_2xdouble_param_0];
; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
; CHECK-F32X2-NEXT: cvt.f64.f32 %rd2, %r2;
; CHECK-F32X2-NEXT: cvt.f64.f32 %rd3, %r1;
-; CHECK-F32X2-NEXT: st.param.v2.b64 [func_retval0], {%rd3, %rd2};
+; CHECK-F32X2-NEXT: st.param::func.v2.b64 [func_retval0], {%rd3, %rd2};
; CHECK-F32X2-NEXT: ret;
%r = fpext <2 x float> %a to <2 x double>
ret <2 x double> %r
@@ -2132,8 +2177,8 @@ define <2 x i32> @test_bitcast_2xfloat_to_2xi32(<2 x float> %a) #0 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param.b64 %rd1, [test_bitcast_2xfloat_to_2xi32_param_0];
-; CHECK-F32X2-NEXT: st.param.b64 [func_retval0], %rd1;
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_bitcast_2xfloat_to_2xi32_param_0];
+; CHECK-F32X2-NEXT: st.param::func.b64 [func_retval0], %rd1;
; CHECK-F32X2-NEXT: ret;
%r = bitcast <2 x float> %a to <2 x i32>
ret <2 x i32> %r
@@ -2154,22 +2199,31 @@ define <2 x float> @test_bitcast_2xi32_to_2xfloat(<2 x i32> %a) #0 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param.b64 %rd1, [test_bitcast_2xi32_to_2xfloat_param_0];
-; CHECK-F32X2-NEXT: st.param.b64 [func_retval0], %rd1;
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_bitcast_2xi32_to_2xfloat_param_0];
+; CHECK-F32X2-NEXT: st.param::func.b64 [func_retval0], %rd1;
; CHECK-F32X2-NEXT: ret;
%r = bitcast <2 x i32> %a to <2 x float>
ret <2 x float> %r
}
define <2 x float> @test_bitcast_double_to_2xfloat(double %a) #0 {
-; CHECK-LABEL: test_bitcast_double_to_2xfloat(
-; CHECK: {
-; CHECK-NEXT: .reg .b64 %rd<2>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [test_bitcast_double_to_2xfloat_param_0];
-; CHECK-NEXT: st.param.b64 [func_retval0], %rd1;
-; CHECK-NEXT: ret;
+; CHECK-NOF32X2-LABEL: test_bitcast_double_to_2xfloat(
+; CHECK-NOF32X2: {
+; CHECK-NOF32X2-NEXT: .reg .b64 %rd<2>;
+; CHECK-NOF32X2-EMPTY:
+; CHECK-NOF32X2-NEXT: // %bb.0:
+; CHECK-NOF32X2-NEXT: ld.param.b64 %rd1, [test_bitcast_double_to_2xfloat_param_0];
+; CHECK-NOF32X2-NEXT: st.param.b64 [func_retval0], %rd1;
+; CHECK-NOF32X2-NEXT: ret;
+;
+; CHECK-F32X2-LABEL: test_bitcast_double_to_2xfloat(
+; CHECK-F32X2: {
+; CHECK-F32X2-NEXT: .reg .b64 %rd<2>;
+; CHECK-F32X2-EMPTY:
+; CHECK-F32X2-NEXT: // %bb.0:
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_bitcast_double_to_2xfloat_param_0];
+; CHECK-F32X2-NEXT: st.param::func.b64 [func_retval0], %rd1;
+; CHECK-F32X2-NEXT: ret;
%r = bitcast double %a to <2 x float>
ret <2 x float> %r
}
@@ -2189,8 +2243,8 @@ define double @test_bitcast_2xfloat_to_double(<2 x float> %a) #0 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param.b64 %rd1, [test_bitcast_2xfloat_to_double_param_0];
-; CHECK-F32X2-NEXT: st.param.b64 [func_retval0], %rd1;
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_bitcast_2xfloat_to_double_param_0];
+; CHECK-F32X2-NEXT: st.param::func.b64 [func_retval0], %rd1;
; CHECK-F32X2-NEXT: ret;
%r = bitcast <2 x float> %a to double
ret double %r
@@ -2214,11 +2268,11 @@ define <2 x float> @test_sqrt(<2 x float> %a) #0 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param.b64 %rd1, [test_sqrt_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_sqrt_param_0];
; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
; CHECK-F32X2-NEXT: sqrt.rn.f32 %r3, %r2;
; CHECK-F32X2-NEXT: sqrt.rn.f32 %r4, %r1;
-; CHECK-F32X2-NEXT: st.param.v2.b32 [func_retval0], {%r4, %r3};
+; CHECK-F32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r4, %r3};
; CHECK-F32X2-NEXT: ret;
%r = call <2 x float> @llvm.sqrt(<2 x float> %a)
ret <2 x float> %r
@@ -2249,11 +2303,11 @@ define <2 x float> @test_sin(<2 x float> %a) #0 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param.b64 %rd1, [test_sin_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_sin_param_0];
; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
; CHECK-F32X2-NEXT: sin.approx.f32 %r3, %r2;
; CHECK-F32X2-NEXT: sin.approx.f32 %r4, %r1;
-; CHECK-F32X2-NEXT: st.param.v2.b32 [func_retval0], {%r4, %r3};
+; CHECK-F32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r4, %r3};
; CHECK-F32X2-NEXT: ret;
%r = call afn <2 x float> @llvm.sin(<2 x float> %a)
ret <2 x float> %r
@@ -2277,11 +2331,11 @@ define <2 x float> @test_cos(<2 x float> %a) #0 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param.b64 %rd1, [test_cos_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_cos_param_0];
; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
; CHECK-F32X2-NEXT: cos.approx.f32 %r3, %r2;
; CHECK-F32X2-NEXT: cos.approx.f32 %r4, %r1;
-; CHECK-F32X2-NEXT: st.param.v2.b32 [func_retval0], {%r4, %r3};
+; CHECK-F32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r4, %r3};
; CHECK-F32X2-NEXT: ret;
%r = call afn <2 x float> @llvm.cos(<2 x float> %a)
ret <2 x float> %r
@@ -2349,11 +2403,11 @@ define <2 x float> @test_fma(<2 x float> %a, <2 x float> %b, <2 x float> %c) #0
; CHECK-F32X2-NEXT: .reg .b64 %rd<5>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param.b64 %rd3, [test_fma_param_2];
-; CHECK-F32X2-NEXT: ld.param.b64 %rd2, [test_fma_param_1];
-; CHECK-F32X2-NEXT: ld.param.b64 %rd1, [test_fma_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd3, [test_fma_param_2];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_fma_param_1];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_fma_param_0];
; CHECK-F32X2-NEXT: fma.rn.f32x2 %rd4, %rd1, %rd2, %rd3;
-; CHECK-F32X2-NEXT: st.param.b64 [func_retval0], %rd4;
+; CHECK-F32X2-NEXT: st.param::func.b64 [func_retval0], %rd4;
; CHECK-F32X2-NEXT: ret;
%r = call <2 x float> @llvm.fma(<2 x float> %a, <2 x float> %b, <2 x float> %c)
ret <2 x float> %r
@@ -2377,11 +2431,11 @@ define <2 x float> @test_fabs(<2 x float> %a) #0 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param.b64 %rd1, [test_fabs_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_fabs_param_0];
; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
; CHECK-F32X2-NEXT: abs.f32 %r3, %r2;
; CHECK-F32X2-NEXT: abs.f32 %r4, %r1;
-; CHECK-F32X2-NEXT: st.param.v2.b32 [func_retval0], {%r4, %r3};
+; CHECK-F32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r4, %r3};
; CHECK-F32X2-NEXT: ret;
%r = call <2 x float> @llvm.fabs(<2 x float> %a)
ret <2 x float> %r
@@ -2406,13 +2460,13 @@ define <2 x float> @test_minnum(<2 x float> %a, <2 x float> %b) #0 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<3>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param.b64 %rd2, [test_minnum_param_1];
-; CHECK-F32X2-NEXT: ld.param.b64 %rd1, [test_minnum_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_minnum_param_1];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_minnum_param_0];
; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd2;
; CHECK-F32X2-NEXT: mov.b64 {%r3, %r4}, %rd1;
; CHECK-F32X2-NEXT: min.f32 %r5, %r4, %r2;
; CHECK-F32X2-NEXT: min.f32 %r6, %r3, %r1;
-; CHECK-F32X2-NEXT: st.param.v2.b32 [func_retval0], {%r6, %r5};
+; CHECK-F32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r6, %r5};
; CHECK-F32X2-NEXT: ret;
%r = call <2 x float> @llvm.minnum(<2 x float> %a, <2 x float> %b)
ret <2 x float> %r
@@ -2437,13 +2491,13 @@ define <2 x float> @test_maxnum(<2 x float> %a, <2 x float> %b) #0 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<3>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param.b64 %rd2, [test_maxnum_param_1];
-; CHECK-F32X2-NEXT: ld.param.b64 %rd1, [test_maxnum_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_maxnum_param_1];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_maxnum_param_0];
; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd2;
; CHECK-F32X2-NEXT: mov.b64 {%r3, %r4}, %rd1;
; CHECK-F32X2-NEXT: max.f32 %r5, %r4, %r2;
; CHECK-F32X2-NEXT: max.f32 %r6, %r3, %r1;
-; CHECK-F32X2-NEXT: st.param.v2.b32 [func_retval0], {%r6, %r5};
+; CHECK-F32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r6, %r5};
; CHECK-F32X2-NEXT: ret;
%r = call <2 x float> @llvm.maxnum(<2 x float> %a, <2 x float> %b)
ret <2 x float> %r
@@ -2468,13 +2522,13 @@ define <2 x float> @test_copysign(<2 x float> %a, <2 x float> %b) #0 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<3>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param.b64 %rd2, [test_copysign_param_1];
-; CHECK-F32X2-NEXT: ld.param.b64 %rd1, [test_copysign_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_copysign_param_1];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_copysign_param_0];
; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
; CHECK-F32X2-NEXT: mov.b64 {%r3, %r4}, %rd2;
; CHECK-F32X2-NEXT: copysign.f32 %r5, %r4, %r2;
; CHECK-F32X2-NEXT: copysign.f32 %r6, %r3, %r1;
-; CHECK-F32X2-NEXT: st.param.v2.b32 [func_retval0], {%r6, %r5};
+; CHECK-F32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r6, %r5};
; CHECK-F32X2-NEXT: ret;
%r = call <2 x float> @llvm.copysign(<2 x float> %a, <2 x float> %b)
ret <2 x float> %r
@@ -2512,8 +2566,8 @@ define <2 x float> @test_copysign_f64(<2 x float> %a, <2 x double> %b) #0 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<8>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param.v2.b64 {%rd2, %rd3}, [test_copysign_f64_param_1];
-; CHECK-F32X2-NEXT: ld.param.b64 %rd1, [test_copysign_f64_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.v2.b64 {%rd2, %rd3}, [test_copysign_f64_param_1];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_copysign_f64_param_0];
; CHECK-F32X2-NEXT: shr.u64 %rd4, %rd3, 63;
; CHECK-F32X2-NEXT: and.b64 %rd5, %rd4, 1;
; CHECK-F32X2-NEXT: setp.ne.b64 %p1, %rd5, 0;
@@ -2527,7 +2581,7 @@ define <2 x float> @test_copysign_f64(<2 x float> %a, <2 x double> %b) #0 {
; CHECK-F32X2-NEXT: abs.f32 %r6, %r1;
; CHECK-F32X2-NEXT: neg.f32 %r7, %r6;
; CHECK-F32X2-NEXT: selp.f32 %r8, %r7, %r6, %p2;
-; CHECK-F32X2-NEXT: st.param.v2.b32 [func_retval0], {%r8, %r5};
+; CHECK-F32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r8, %r5};
; CHECK-F32X2-NEXT: ret;
%tb = fptrunc <2 x double> %b to <2 x float>
%r = call <2 x float> @llvm.copysign(<2 x float> %a, <2 x float> %tb)
@@ -2556,15 +2610,15 @@ define <2 x double> @test_copysign_extended(<2 x float> %a, <2 x float> %b) #0 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<5>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param.b64 %rd2, [test_copysign_extended_param_1];
-; CHECK-F32X2-NEXT: ld.param.b64 %rd1, [test_copysign_extended_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_copysign_extended_param_1];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_copysign_extended_param_0];
; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
; CHECK-F32X2-NEXT: mov.b64 {%r3, %r4}, %rd2;
; CHECK-F32X2-NEXT: copysign.f32 %r5, %r3, %r1;
; CHECK-F32X2-NEXT: copysign.f32 %r6, %r4, %r2;
; CHECK-F32X2-NEXT: cvt.f64.f32 %rd3, %r6;
; CHECK-F32X2-NEXT: cvt.f64.f32 %rd4, %r5;
-; CHECK-F32X2-NEXT: st.param.v2.b64 [func_retval0], {%rd4, %rd3};
+; CHECK-F32X2-NEXT: st.param::func.v2.b64 [func_retval0], {%rd4, %rd3};
; CHECK-F32X2-NEXT: ret;
%r = call <2 x float> @llvm.copysign(<2 x float> %a, <2 x float> %b)
%xr = fpext <2 x float> %r to <2 x double>
@@ -2589,11 +2643,11 @@ define <2 x float> @test_floor(<2 x float> %a) #0 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param.b64 %rd1, [test_floor_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_floor_param_0];
; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
; CHECK-F32X2-NEXT: cvt.rmi.f32.f32 %r3, %r2;
; CHECK-F32X2-NEXT: cvt.rmi.f32.f32 %r4, %r1;
-; CHECK-F32X2-NEXT: st.param.v2.b32 [func_retval0], {%r4, %r3};
+; CHECK-F32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r4, %r3};
; CHECK-F32X2-NEXT: ret;
%r = call <2 x float> @llvm.floor(<2 x float> %a)
ret <2 x float> %r
@@ -2617,11 +2671,11 @@ define <2 x float> @test_ceil(<2 x float> %a) #0 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param.b64 %rd1, [test_ceil_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_ceil_param_0];
; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
; CHECK-F32X2-NEXT: cvt.rpi.f32.f32 %r3, %r2;
; CHECK-F32X2-NEXT: cvt.rpi.f32.f32 %r4, %r1;
-; CHECK-F32X2-NEXT: st.param.v2.b32 [func_retval0], {%r4, %r3};
+; CHECK-F32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r4, %r3};
; CHECK-F32X2-NEXT: ret;
%r = call <2 x float> @llvm.ceil(<2 x float> %a)
ret <2 x float> %r
@@ -2645,11 +2699,11 @@ define <2 x float> @test_trunc(<2 x float> %a) #0 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param.b64 %rd1, [test_trunc_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_trunc_param_0];
; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
; CHECK-F32X2-NEXT: cvt.rzi.f32.f32 %r3, %r2;
; CHECK-F32X2-NEXT: cvt.rzi.f32.f32 %r4, %r1;
-; CHECK-F32X2-NEXT: st.param.v2.b32 [func_retval0], {%r4, %r3};
+; CHECK-F32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r4, %r3};
; CHECK-F32X2-NEXT: ret;
%r = call <2 x float> @llvm.trunc(<2 x float> %a)
ret <2 x float> %r
@@ -2673,11 +2727,11 @@ define <2 x float> @test_rint(<2 x float> %a) #0 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param.b64 %rd1, [test_rint_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_rint_param_0];
; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
; CHECK-F32X2-NEXT: cvt.rni.f32.f32 %r3, %r2;
; CHECK-F32X2-NEXT: cvt.rni.f32.f32 %r4, %r1;
-; CHECK-F32X2-NEXT: st.param.v2.b32 [func_retval0], {%r4, %r3};
+; CHECK-F32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r4, %r3};
; CHECK-F32X2-NEXT: ret;
%r = call <2 x float> @llvm.rint(<2 x float> %a)
ret <2 x float> %r
@@ -2701,11 +2755,11 @@ define <2 x float> @test_nearbyint(<2 x float> %a) #0 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param.b64 %rd1, [test_nearbyint_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_nearbyint_param_0];
; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
; CHECK-F32X2-NEXT: cvt.rni.f32.f32 %r3, %r2;
; CHECK-F32X2-NEXT: cvt.rni.f32.f32 %r4, %r1;
-; CHECK-F32X2-NEXT: st.param.v2.b32 [func_retval0], {%r4, %r3};
+; CHECK-F32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r4, %r3};
; CHECK-F32X2-NEXT: ret;
%r = call <2 x float> @llvm.nearbyint(<2 x float> %a)
ret <2 x float> %r
@@ -2729,11 +2783,11 @@ define <2 x float> @test_roundeven(<2 x float> %a) #0 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param.b64 %rd1, [test_roundeven_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_roundeven_param_0];
; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
; CHECK-F32X2-NEXT: cvt.rni.f32.f32 %r3, %r2;
; CHECK-F32X2-NEXT: cvt.rni.f32.f32 %r4, %r1;
-; CHECK-F32X2-NEXT: st.param.v2.b32 [func_retval0], {%r4, %r3};
+; CHECK-F32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r4, %r3};
; CHECK-F32X2-NEXT: ret;
%r = call <2 x float> @llvm.roundeven(<2 x float> %a)
ret <2 x float> %r
@@ -2778,7 +2832,7 @@ define <2 x float> @test_round(<2 x float> %a) #0 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param.b64 %rd1, [test_round_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_round_param_0];
; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
; CHECK-F32X2-NEXT: and.b32 %r3, %r2, -2147483648;
; CHECK-F32X2-NEXT: or.b32 %r4, %r3, 1056964608;
@@ -2800,7 +2854,7 @@ define <2 x float> @test_round(<2 x float> %a) #0 {
; CHECK-F32X2-NEXT: cvt.rzi.f32.f32 %r17, %r1;
; CHECK-F32X2-NEXT: setp.lt.f32 %p4, %r15, 0f3F000000;
; CHECK-F32X2-NEXT: selp.f32 %r18, %r17, %r16, %p4;
-; CHECK-F32X2-NEXT: st.param.v2.b32 [func_retval0], {%r18, %r10};
+; CHECK-F32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r18, %r10};
; CHECK-F32X2-NEXT: ret;
%r = call <2 x float> @llvm.round(<2 x float> %a)
ret <2 x float> %r
@@ -2825,11 +2879,11 @@ define <2 x float> @test_fmuladd(<2 x float> %a, <2 x float> %b, <2 x float> %c)
; CHECK-F32X2-NEXT: .reg .b64 %rd<5>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param.b64 %rd3, [test_fmuladd_param_2];
-; CHECK-F32X2-NEXT: ld.param.b64 %rd2, [test_fmuladd_param_1];
-; CHECK-F32X2-NEXT: ld.param.b64 %rd1, [test_fmuladd_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd3, [test_fmuladd_param_2];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_fmuladd_param_1];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_fmuladd_param_0];
; CHECK-F32X2-NEXT: fma.rn.f32x2 %rd4, %rd1, %rd2, %rd3;
-; CHECK-F32X2-NEXT: st.param.b64 [func_retval0], %rd4;
+; CHECK-F32X2-NEXT: st.param::func.b64 [func_retval0], %rd4;
; CHECK-F32X2-NEXT: ret;
%r = call <2 x float> @llvm.fmuladd(<2 x float> %a, <2 x float> %b, <2 x float> %c)
ret <2 x float> %r
@@ -2851,9 +2905,9 @@ define <2 x float> @test_shufflevector(<2 x float> %a) #0 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param.b64 %rd1, [test_shufflevector_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_shufflevector_param_0];
; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
-; CHECK-F32X2-NEXT: st.param.v2.b32 [func_retval0], {%r2, %r1};
+; CHECK-F32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r2, %r1};
; CHECK-F32X2-NEXT: ret;
%s = shufflevector <2 x float> %a, <2 x float> poison, <2 x i32> <i32 1, i32 0>
ret <2 x float> %s
@@ -2876,10 +2930,10 @@ define <2 x float> @test_insertelement(<2 x float> %a, float %x) #0 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param.b32 %r1, [test_insertelement_param_1];
-; CHECK-F32X2-NEXT: ld.param.b64 %rd1, [test_insertelement_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.b32 %r1, [test_insertelement_param_1];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_insertelement_param_0];
; CHECK-F32X2-NEXT: mov.b64 {%r2, _}, %rd1;
-; CHECK-F32X2-NEXT: st.param.v2.b32 [func_retval0], {%r2, %r1};
+; CHECK-F32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r2, %r1};
; CHECK-F32X2-NEXT: ret;
%i = insertelement <2 x float> %a, float %x, i64 1
ret <2 x float> %i
@@ -2903,11 +2957,11 @@ define <2 x float> @test_sitofp_2xi32_to_2xfloat(<2 x i32> %a) #0 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param.b64 %rd1, [test_sitofp_2xi32_to_2xfloat_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_sitofp_2xi32_to_2xfloat_param_0];
; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
; CHECK-F32X2-NEXT: cvt.rn.f32.s32 %r3, %r2;
; CHECK-F32X2-NEXT: cvt.rn.f32.s32 %r4, %r1;
-; CHECK-F32X2-NEXT: st.param.v2.b32 [func_retval0], {%r4, %r3};
+; CHECK-F32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r4, %r3};
; CHECK-F32X2-NEXT: ret;
%r = sitofp <2 x i32> %a to <2 x float>
ret <2 x float> %r
@@ -2931,11 +2985,11 @@ define <2 x float> @test_uitofp_2xi32_to_2xfloat(<2 x i32> %a) #0 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param.b64 %rd1, [test_uitofp_2xi32_to_2xfloat_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_uitofp_2xi32_to_2xfloat_param_0];
; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
; CHECK-F32X2-NEXT: cvt.rn.f32.u32 %r3, %r2;
; CHECK-F32X2-NEXT: cvt.rn.f32.u32 %r4, %r1;
-; CHECK-F32X2-NEXT: st.param.v2.b32 [func_retval0], {%r4, %r3};
+; CHECK-F32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r4, %r3};
; CHECK-F32X2-NEXT: ret;
%r = uitofp <2 x i32> %a to <2 x float>
ret <2 x float> %r
@@ -2960,8 +3014,8 @@ define void @test_trunc_to_v2bf16(<2 x float> %a, ptr %p) {
; CHECK-F32X2-NEXT: .reg .b64 %rd<3>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param.b64 %rd2, [test_trunc_to_v2bf16_param_1];
-; CHECK-F32X2-NEXT: ld.param.b64 %rd1, [test_trunc_to_v2bf16_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_trunc_to_v2bf16_param_1];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_trunc_to_v2bf16_param_0];
; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
; CHECK-F32X2-NEXT: cvt.rn.bf16x2.f32 %r3, %r2, %r1;
; CHECK-F32X2-NEXT: st.b32 [%rd2], %r3;
@@ -2990,8 +3044,8 @@ define void @test_trunc_to_v2f16(<2 x float> %a, ptr %p) {
; CHECK-F32X2-NEXT: .reg .b64 %rd<3>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param.b64 %rd2, [test_trunc_to_v2f16_param_1];
-; CHECK-F32X2-NEXT: ld.param.b64 %rd1, [test_trunc_to_v2f16_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_trunc_to_v2f16_param_1];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_trunc_to_v2f16_param_0];
; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
; CHECK-F32X2-NEXT: cvt.rn.f16x2.f32 %r3, %r2, %r1;
; CHECK-F32X2-NEXT: st.b32 [%rd2], %r3;
@@ -3004,3 +3058,5 @@ define void @test_trunc_to_v2f16(<2 x float> %a, ptr %p) {
attributes #0 = { nounwind }
attributes #2 = { denormal_fpenv(preservesign) }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK: {{.*}}
diff --git a/llvm/test/CodeGen/NVPTX/fmax3.ll b/llvm/test/CodeGen/NVPTX/fmax3.ll
index 9339b2e247af4..e58328e5fdf00 100644
--- a/llvm/test/CodeGen/NVPTX/fmax3.ll
+++ b/llvm/test/CodeGen/NVPTX/fmax3.ll
@@ -11,11 +11,11 @@ define void @test_fmaxnum3(float %a, float %b, float %c, ptr addrspace(1) %outpu
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b32 %r1, [test_fmaxnum3_param_0];
-; CHECK-NEXT: ld.param.b32 %r2, [test_fmaxnum3_param_1];
-; CHECK-NEXT: ld.param.b32 %r3, [test_fmaxnum3_param_2];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_fmaxnum3_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r2, [test_fmaxnum3_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r3, [test_fmaxnum3_param_2];
; CHECK-NEXT: max.f32 %r4, %r1, %r2, %r3;
-; CHECK-NEXT: ld.param.b64 %rd1, [test_fmaxnum3_param_3];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_fmaxnum3_param_3];
; CHECK-NEXT: st.global.b32 [%rd1], %r4;
; CHECK-NEXT: ret;
entry:
@@ -32,11 +32,11 @@ define void @test_fminnum3(float %a, float %b, float %c, ptr addrspace(1) %outpu
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b32 %r1, [test_fminnum3_param_0];
-; CHECK-NEXT: ld.param.b32 %r2, [test_fminnum3_param_1];
-; CHECK-NEXT: ld.param.b32 %r3, [test_fminnum3_param_2];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_fminnum3_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r2, [test_fminnum3_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r3, [test_fminnum3_param_2];
; CHECK-NEXT: min.f32 %r4, %r1, %r2, %r3;
-; CHECK-NEXT: ld.param.b64 %rd1, [test_fminnum3_param_3];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_fminnum3_param_3];
; CHECK-NEXT: st.global.b32 [%rd1], %r4;
; CHECK-NEXT: ret;
entry:
@@ -53,11 +53,11 @@ define void @test_fmaximum3(float %a, float %b, float %c, ptr addrspace(1) %outp
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b32 %r1, [test_fmaximum3_param_0];
-; CHECK-NEXT: ld.param.b32 %r2, [test_fmaximum3_param_1];
-; CHECK-NEXT: ld.param.b32 %r3, [test_fmaximum3_param_2];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_fmaximum3_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r2, [test_fmaximum3_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r3, [test_fmaximum3_param_2];
; CHECK-NEXT: max.NaN.f32 %r4, %r1, %r2, %r3;
-; CHECK-NEXT: ld.param.b64 %rd1, [test_fmaximum3_param_3];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_fmaximum3_param_3];
; CHECK-NEXT: st.global.b32 [%rd1], %r4;
; CHECK-NEXT: ret;
entry:
@@ -74,11 +74,11 @@ define void @test_fminimum3(float %a, float %b, float %c, ptr addrspace(1) %outp
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b32 %r1, [test_fminimum3_param_0];
-; CHECK-NEXT: ld.param.b32 %r2, [test_fminimum3_param_1];
-; CHECK-NEXT: ld.param.b32 %r3, [test_fminimum3_param_2];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_fminimum3_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r2, [test_fminimum3_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r3, [test_fminimum3_param_2];
; CHECK-NEXT: min.NaN.f32 %r4, %r1, %r2, %r3;
-; CHECK-NEXT: ld.param.b64 %rd1, [test_fminimum3_param_3];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_fminimum3_param_3];
; CHECK-NEXT: st.global.b32 [%rd1], %r4;
; CHECK-NEXT: ret;
entry:
@@ -95,11 +95,11 @@ define void @test_fmaximumnum3(float %a, float %b, float %c, ptr addrspace(1) %o
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b32 %r1, [test_fmaximumnum3_param_0];
-; CHECK-NEXT: ld.param.b32 %r2, [test_fmaximumnum3_param_1];
-; CHECK-NEXT: ld.param.b32 %r3, [test_fmaximumnum3_param_2];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_fmaximumnum3_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r2, [test_fmaximumnum3_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r3, [test_fmaximumnum3_param_2];
; CHECK-NEXT: max.f32 %r4, %r1, %r2, %r3;
-; CHECK-NEXT: ld.param.b64 %rd1, [test_fmaximumnum3_param_3];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_fmaximumnum3_param_3];
; CHECK-NEXT: st.global.b32 [%rd1], %r4;
; CHECK-NEXT: ret;
entry:
@@ -116,11 +116,11 @@ define void @test_fminimumnum3(float %a, float %b, float %c, ptr addrspace(1) %o
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b32 %r1, [test_fminimumnum3_param_0];
-; CHECK-NEXT: ld.param.b32 %r2, [test_fminimumnum3_param_1];
-; CHECK-NEXT: ld.param.b32 %r3, [test_fminimumnum3_param_2];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_fminimumnum3_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r2, [test_fminimumnum3_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r3, [test_fminimumnum3_param_2];
; CHECK-NEXT: min.f32 %r4, %r1, %r2, %r3;
-; CHECK-NEXT: ld.param.b64 %rd1, [test_fminimumnum3_param_3];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_fminimumnum3_param_3];
; CHECK-NEXT: st.global.b32 [%rd1], %r4;
; CHECK-NEXT: ret;
entry:
@@ -138,11 +138,11 @@ define void @test_fmaxnum3_commuted(float %a, float %b, float %c, ptr addrspace(
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b32 %r1, [test_fmaxnum3_commuted_param_0];
-; CHECK-NEXT: ld.param.b32 %r2, [test_fmaxnum3_commuted_param_1];
-; CHECK-NEXT: ld.param.b32 %r3, [test_fmaxnum3_commuted_param_2];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_fmaxnum3_commuted_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r2, [test_fmaxnum3_commuted_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r3, [test_fmaxnum3_commuted_param_2];
; CHECK-NEXT: max.f32 %r4, %r1, %r2, %r3;
-; CHECK-NEXT: ld.param.b64 %rd1, [test_fmaxnum3_commuted_param_3];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_fmaxnum3_commuted_param_3];
; CHECK-NEXT: st.global.b32 [%rd1], %r4;
; CHECK-NEXT: ret;
entry:
@@ -160,12 +160,12 @@ define void @test_mixed_minmax_no_combine(float %a, float %b, float %c, ptr addr
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b32 %r1, [test_mixed_minmax_no_combine_param_0];
-; CHECK-NEXT: ld.param.b32 %r2, [test_mixed_minmax_no_combine_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_mixed_minmax_no_combine_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r2, [test_mixed_minmax_no_combine_param_1];
; CHECK-NEXT: min.f32 %r3, %r1, %r2;
-; CHECK-NEXT: ld.param.b32 %r4, [test_mixed_minmax_no_combine_param_2];
+; CHECK-NEXT: ld.param::func.b32 %r4, [test_mixed_minmax_no_combine_param_2];
; CHECK-NEXT: max.f32 %r5, %r3, %r4;
-; CHECK-NEXT: ld.param.b64 %rd1, [test_mixed_minmax_no_combine_param_3];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_mixed_minmax_no_combine_param_3];
; CHECK-NEXT: st.global.b32 [%rd1], %r5;
; CHECK-NEXT: ret;
entry:
@@ -183,12 +183,12 @@ define void @test_mixed_maxnum_maximum_no_combine(float %a, float %b, float %c,
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b32 %r1, [test_mixed_maxnum_maximum_no_combine_param_0];
-; CHECK-NEXT: ld.param.b32 %r2, [test_mixed_maxnum_maximum_no_combine_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_mixed_maxnum_maximum_no_combine_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r2, [test_mixed_maxnum_maximum_no_combine_param_1];
; CHECK-NEXT: max.f32 %r3, %r1, %r2;
-; CHECK-NEXT: ld.param.b32 %r4, [test_mixed_maxnum_maximum_no_combine_param_2];
+; CHECK-NEXT: ld.param::func.b32 %r4, [test_mixed_maxnum_maximum_no_combine_param_2];
; CHECK-NEXT: max.NaN.f32 %r5, %r3, %r4;
-; CHECK-NEXT: ld.param.b64 %rd1, [test_mixed_maxnum_maximum_no_combine_param_3];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_mixed_maxnum_maximum_no_combine_param_3];
; CHECK-NEXT: st.global.b32 [%rd1], %r5;
; CHECK-NEXT: ret;
entry:
@@ -206,12 +206,12 @@ define void @test_f16_no_combine(half %a, half %b, half %c, ptr addrspace(1) %ou
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs1, [test_f16_no_combine_param_0];
-; CHECK-NEXT: ld.param.b16 %rs2, [test_f16_no_combine_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_f16_no_combine_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs2, [test_f16_no_combine_param_1];
; CHECK-NEXT: max.f16 %rs3, %rs1, %rs2;
-; CHECK-NEXT: ld.param.b16 %rs4, [test_f16_no_combine_param_2];
+; CHECK-NEXT: ld.param::func.b16 %rs4, [test_f16_no_combine_param_2];
; CHECK-NEXT: max.f16 %rs5, %rs3, %rs4;
-; CHECK-NEXT: ld.param.b64 %rd1, [test_f16_no_combine_param_3];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_f16_no_combine_param_3];
; CHECK-NEXT: st.global.b16 [%rd1], %rs5;
; CHECK-NEXT: ret;
entry:
@@ -229,14 +229,14 @@ define void @test_multiple_uses_no_combine(float %a, float %b, float %c, ptr add
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b32 %r1, [test_multiple_uses_no_combine_param_0];
-; CHECK-NEXT: ld.param.b32 %r2, [test_multiple_uses_no_combine_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_multiple_uses_no_combine_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r2, [test_multiple_uses_no_combine_param_1];
; CHECK-NEXT: max.f32 %r3, %r1, %r2;
-; CHECK-NEXT: ld.param.b32 %r4, [test_multiple_uses_no_combine_param_2];
+; CHECK-NEXT: ld.param::func.b32 %r4, [test_multiple_uses_no_combine_param_2];
; CHECK-NEXT: max.f32 %r5, %r3, %r4;
-; CHECK-NEXT: ld.param.b64 %rd1, [test_multiple_uses_no_combine_param_3];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_multiple_uses_no_combine_param_3];
; CHECK-NEXT: st.global.b32 [%rd1], %r3;
-; CHECK-NEXT: ld.param.b64 %rd2, [test_multiple_uses_no_combine_param_4];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [test_multiple_uses_no_combine_param_4];
; CHECK-NEXT: st.global.b32 [%rd2], %r5;
; CHECK-NEXT: ret;
entry:
diff --git a/llvm/test/CodeGen/NVPTX/fold-movs.ll b/llvm/test/CodeGen/NVPTX/fold-movs.ll
index 10e31f5d97efe..dd6204321e7f2 100644
--- a/llvm/test/CodeGen/NVPTX/fold-movs.ll
+++ b/llvm/test/CodeGen/NVPTX/fold-movs.ll
@@ -17,19 +17,19 @@ define void @writevec(<8 x float> %v1, <8 x float> %v2, ptr addrspace(1) %p) {
; CHECK-F32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [writevec_param_0];
-; CHECK-F32X2-NEXT: ld.param.v4.b32 {%r5, %r6, %r7, %r8}, [writevec_param_0+16];
-; CHECK-F32X2-NEXT: ld.param.v4.b32 {%r9, %r10, %r11, %r12}, [writevec_param_1+16];
+; CHECK-F32X2-NEXT: ld.param::func.v4.b32 {%r1, %r2, %r3, %r4}, [writevec_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.v4.b32 {%r5, %r6, %r7, %r8}, [writevec_param_0+16];
+; CHECK-F32X2-NEXT: ld.param::func.v4.b32 {%r9, %r10, %r11, %r12}, [writevec_param_1+16];
; CHECK-F32X2-NEXT: div.rn.f32 %r13, %r8, %r12;
; CHECK-F32X2-NEXT: div.rn.f32 %r14, %r7, %r11;
; CHECK-F32X2-NEXT: div.rn.f32 %r15, %r6, %r10;
; CHECK-F32X2-NEXT: div.rn.f32 %r16, %r5, %r9;
-; CHECK-F32X2-NEXT: ld.param.v4.b32 {%r17, %r18, %r19, %r20}, [writevec_param_1];
+; CHECK-F32X2-NEXT: ld.param::func.v4.b32 {%r17, %r18, %r19, %r20}, [writevec_param_1];
; CHECK-F32X2-NEXT: div.rn.f32 %r21, %r4, %r20;
; CHECK-F32X2-NEXT: div.rn.f32 %r22, %r3, %r19;
; CHECK-F32X2-NEXT: div.rn.f32 %r23, %r2, %r18;
; CHECK-F32X2-NEXT: div.rn.f32 %r24, %r1, %r17;
-; CHECK-F32X2-NEXT: ld.param.b64 %rd1, [writevec_param_2];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [writevec_param_2];
; CHECK-F32X2-NEXT: st.global.v8.b32 [%rd1], {%r24, %r23, %r22, %r21, %r16, %r15, %r14, %r13};
; CHECK-F32X2-NEXT: ret;
%v = fdiv <8 x float> %v1, %v2
diff --git a/llvm/test/CodeGen/NVPTX/fp-contract-f32x2.ll b/llvm/test/CodeGen/NVPTX/fp-contract-f32x2.ll
index 67ac240be3318..09c3027dcc347 100644
--- a/llvm/test/CodeGen/NVPTX/fp-contract-f32x2.ll
+++ b/llvm/test/CodeGen/NVPTX/fp-contract-f32x2.ll
@@ -14,11 +14,11 @@ define <2 x float> @t0(<2 x float> %a, <2 x float> %b, <2 x float> %c) {
; FAST-NEXT: .reg .b64 %rd<5>;
; FAST-EMPTY:
; FAST-NEXT: // %bb.0:
-; FAST-NEXT: ld.param.b64 %rd1, [t0_param_0];
-; FAST-NEXT: ld.param.b64 %rd2, [t0_param_1];
-; FAST-NEXT: ld.param.b64 %rd3, [t0_param_2];
+; FAST-NEXT: ld.param::func.b64 %rd1, [t0_param_0];
+; FAST-NEXT: ld.param::func.b64 %rd2, [t0_param_1];
+; FAST-NEXT: ld.param::func.b64 %rd3, [t0_param_2];
; FAST-NEXT: fma.rn.f32x2 %rd4, %rd1, %rd2, %rd3;
-; FAST-NEXT: st.param.b64 [func_retval0], %rd4;
+; FAST-NEXT: st.param::func.b64 [func_retval0], %rd4;
; FAST-NEXT: ret;
;
; DEFAULT-LABEL: t0(
@@ -26,12 +26,12 @@ define <2 x float> @t0(<2 x float> %a, <2 x float> %b, <2 x float> %c) {
; DEFAULT-NEXT: .reg .b64 %rd<6>;
; DEFAULT-EMPTY:
; DEFAULT-NEXT: // %bb.0:
-; DEFAULT-NEXT: ld.param.b64 %rd1, [t0_param_0];
-; DEFAULT-NEXT: ld.param.b64 %rd2, [t0_param_1];
+; DEFAULT-NEXT: ld.param::func.b64 %rd1, [t0_param_0];
+; DEFAULT-NEXT: ld.param::func.b64 %rd2, [t0_param_1];
; DEFAULT-NEXT: mul.rn.f32x2 %rd3, %rd1, %rd2;
-; DEFAULT-NEXT: ld.param.b64 %rd4, [t0_param_2];
+; DEFAULT-NEXT: ld.param::func.b64 %rd4, [t0_param_2];
; DEFAULT-NEXT: add.rn.f32x2 %rd5, %rd3, %rd4;
-; DEFAULT-NEXT: st.param.b64 [func_retval0], %rd5;
+; DEFAULT-NEXT: st.param::func.b64 [func_retval0], %rd5;
; DEFAULT-NEXT: ret;
%v0 = fmul <2 x float> %a, %b
%v1 = fadd <2 x float> %v0, %c
@@ -46,12 +46,12 @@ define <2 x float> @t1(<2 x float> %a, <2 x float> %b) {
; FAST-NEXT: .reg .b64 %rd<6>;
; FAST-EMPTY:
; FAST-NEXT: // %bb.0:
-; FAST-NEXT: ld.param.b64 %rd1, [t1_param_0];
-; FAST-NEXT: ld.param.b64 %rd2, [t1_param_1];
+; FAST-NEXT: ld.param::func.b64 %rd1, [t1_param_0];
+; FAST-NEXT: ld.param::func.b64 %rd2, [t1_param_1];
; FAST-NEXT: add.f32x2 %rd3, %rd1, %rd2;
; FAST-NEXT: sub.f32x2 %rd4, %rd1, %rd2;
; FAST-NEXT: mul.f32x2 %rd5, %rd3, %rd4;
-; FAST-NEXT: st.param.b64 [func_retval0], %rd5;
+; FAST-NEXT: st.param::func.b64 [func_retval0], %rd5;
; FAST-NEXT: ret;
;
; DEFAULT-LABEL: t1(
@@ -59,12 +59,12 @@ define <2 x float> @t1(<2 x float> %a, <2 x float> %b) {
; DEFAULT-NEXT: .reg .b64 %rd<6>;
; DEFAULT-EMPTY:
; DEFAULT-NEXT: // %bb.0:
-; DEFAULT-NEXT: ld.param.b64 %rd1, [t1_param_0];
-; DEFAULT-NEXT: ld.param.b64 %rd2, [t1_param_1];
+; DEFAULT-NEXT: ld.param::func.b64 %rd1, [t1_param_0];
+; DEFAULT-NEXT: ld.param::func.b64 %rd2, [t1_param_1];
; DEFAULT-NEXT: add.rn.f32x2 %rd3, %rd1, %rd2;
; DEFAULT-NEXT: sub.rn.f32x2 %rd4, %rd1, %rd2;
; DEFAULT-NEXT: mul.rn.f32x2 %rd5, %rd3, %rd4;
-; DEFAULT-NEXT: st.param.b64 [func_retval0], %rd5;
+; DEFAULT-NEXT: st.param::func.b64 [func_retval0], %rd5;
; DEFAULT-NEXT: ret;
%v1 = fadd <2 x float> %a, %b
%v2 = fsub <2 x float> %a, %b
@@ -80,12 +80,12 @@ define <2 x float> @t2(<2 x float> %a, <2 x float> %b) {
; CHECK-NEXT: .reg .b64 %rd<6>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [t2_param_0];
-; CHECK-NEXT: ld.param.b64 %rd2, [t2_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [t2_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [t2_param_1];
; CHECK-NEXT: add.f32x2 %rd3, %rd1, %rd2;
; CHECK-NEXT: sub.f32x2 %rd4, %rd1, %rd2;
; CHECK-NEXT: mul.f32x2 %rd5, %rd3, %rd4;
-; CHECK-NEXT: st.param.b64 [func_retval0], %rd5;
+; CHECK-NEXT: st.param::func.b64 [func_retval0], %rd5;
; CHECK-NEXT: ret;
%v1 = fadd contract <2 x float> %a, %b
%v2 = fsub contract <2 x float> %a, %b
@@ -100,11 +100,11 @@ define <2 x float> @t3(<2 x float> %a, <2 x float> %b, <2 x float> %c) {
; CHECK-NEXT: .reg .b64 %rd<5>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [t3_param_0];
-; CHECK-NEXT: ld.param.b64 %rd2, [t3_param_1];
-; CHECK-NEXT: ld.param.b64 %rd3, [t3_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [t3_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [t3_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd3, [t3_param_2];
; CHECK-NEXT: fma.rn.f32x2 %rd4, %rd1, %rd2, %rd3;
-; CHECK-NEXT: st.param.b64 [func_retval0], %rd4;
+; CHECK-NEXT: st.param::func.b64 [func_retval0], %rd4;
; CHECK-NEXT: ret;
%v0 = fmul contract <2 x float> %a, %b
%v1 = fadd contract <2 x float> %v0, %c
@@ -119,10 +119,10 @@ define float @dot_reduce_contract(<8 x float> %a, <8 x float> %b) {
; CHECK-NEXT: .reg .b32 %r<25>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [dot_reduce_contract_param_0+16];
-; CHECK-NEXT: ld.param.v4.b32 {%r5, %r6, %r7, %r8}, [dot_reduce_contract_param_0];
-; CHECK-NEXT: ld.param.v4.b32 {%r9, %r10, %r11, %r12}, [dot_reduce_contract_param_1+16];
-; CHECK-NEXT: ld.param.v4.b32 {%r13, %r14, %r15, %r16}, [dot_reduce_contract_param_1];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r1, %r2, %r3, %r4}, [dot_reduce_contract_param_0+16];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r5, %r6, %r7, %r8}, [dot_reduce_contract_param_0];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r9, %r10, %r11, %r12}, [dot_reduce_contract_param_1+16];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r13, %r14, %r15, %r16}, [dot_reduce_contract_param_1];
; CHECK-NEXT: fma.rn.f32 %r17, %r5, %r13, 0f00000000;
; CHECK-NEXT: fma.rn.f32 %r18, %r6, %r14, %r17;
; CHECK-NEXT: fma.rn.f32 %r19, %r7, %r15, %r18;
@@ -131,7 +131,7 @@ define float @dot_reduce_contract(<8 x float> %a, <8 x float> %b) {
; CHECK-NEXT: fma.rn.f32 %r22, %r2, %r10, %r21;
; CHECK-NEXT: fma.rn.f32 %r23, %r3, %r11, %r22;
; CHECK-NEXT: fma.rn.f32 %r24, %r4, %r12, %r23;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r24;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r24;
; CHECK-NEXT: ret;
%mul = fmul contract <8 x float> %a, %b
%red = call contract float @llvm.vector.reduce.fadd.v8f32(float 0.0, <8 x float> %mul)
diff --git a/llvm/test/CodeGen/NVPTX/gvn-scalar-pre-reg-pressure.ll b/llvm/test/CodeGen/NVPTX/gvn-scalar-pre-reg-pressure.ll
index 5b7f893889744..3a4ff8e280b3a 100644
--- a/llvm/test/CodeGen/NVPTX/gvn-scalar-pre-reg-pressure.ll
+++ b/llvm/test/CodeGen/NVPTX/gvn-scalar-pre-reg-pressure.ll
@@ -15,8 +15,8 @@ define void @test_scalar_pre_option(ptr %arr, i8 %cond) {
; PIPELINE-NEXT: .reg .b64 %rd<2>;
; PIPELINE-EMPTY:
; PIPELINE-NEXT: // %bb.0: // %entry
-; PIPELINE-NEXT: ld.param.b64 %rd1, [test_scalar_pre_option_param_0];
-; PIPELINE-NEXT: ld.param.b8 %rs1, [test_scalar_pre_option_param_1];
+; PIPELINE-NEXT: ld.param::func.b64 %rd1, [test_scalar_pre_option_param_0];
+; PIPELINE-NEXT: ld.param::func.b8 %rs1, [test_scalar_pre_option_param_1];
; PIPELINE-NEXT: setp.eq.b16 %p1, %rs1, 0;
; PIPELINE-NEXT: ld.b32 %r2, [%rd1];
; PIPELINE-NEXT: add.s32 %r1, %r2, 2;
@@ -35,8 +35,8 @@ define void @test_scalar_pre_option(ptr %arr, i8 %cond) {
; NO-SCALAR-PRE-NEXT: .reg .b64 %rd<2>;
; NO-SCALAR-PRE-EMPTY:
; NO-SCALAR-PRE-NEXT: // %bb.0: // %entry
-; NO-SCALAR-PRE-NEXT: ld.param.b8 %rs1, [test_scalar_pre_option_param_1];
-; NO-SCALAR-PRE-NEXT: ld.param.b64 %rd1, [test_scalar_pre_option_param_0];
+; NO-SCALAR-PRE-NEXT: ld.param::func.b8 %rs1, [test_scalar_pre_option_param_1];
+; NO-SCALAR-PRE-NEXT: ld.param::func.b64 %rd1, [test_scalar_pre_option_param_0];
; NO-SCALAR-PRE-NEXT: setp.eq.b16 %p1, %rs1, 0;
; NO-SCALAR-PRE-NEXT: ld.b32 %r1, [%rd1];
; NO-SCALAR-PRE-NEXT: @%p1 bra $L__BB0_2;
@@ -58,8 +58,8 @@ define void @test_scalar_pre_option(ptr %arr, i8 %cond) {
; SCALAR-PRE-NEXT: .reg .b64 %rd<2>;
; SCALAR-PRE-EMPTY:
; SCALAR-PRE-NEXT: // %bb.0: // %entry
-; SCALAR-PRE-NEXT: ld.param.b8 %rs1, [test_scalar_pre_option_param_1];
-; SCALAR-PRE-NEXT: ld.param.b64 %rd1, [test_scalar_pre_option_param_0];
+; SCALAR-PRE-NEXT: ld.param::func.b8 %rs1, [test_scalar_pre_option_param_1];
+; SCALAR-PRE-NEXT: ld.param::func.b64 %rd1, [test_scalar_pre_option_param_0];
; SCALAR-PRE-NEXT: setp.ne.b16 %p1, %rs1, 0;
; SCALAR-PRE-NEXT: ld.b32 %r1, [%rd1];
; SCALAR-PRE-NEXT: @%p1 bra $L__BB0_2;
diff --git a/llvm/test/CodeGen/NVPTX/i32x2-instructions.ll b/llvm/test/CodeGen/NVPTX/i32x2-instructions.ll
index 5f500dd5d9185..01bcfcbda0d53 100644
--- a/llvm/test/CodeGen/NVPTX/i32x2-instructions.ll
+++ b/llvm/test/CodeGen/NVPTX/i32x2-instructions.ll
@@ -16,12 +16,19 @@ target triple = "nvptx64-nvidia-cuda"
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
define <2 x i32> @test_ret_const() #0 {
-; CHECK-LABEL: test_ret_const(
-; CHECK: {
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: st.param.v2.b32 [func_retval0], {-1, 2};
-; CHECK-NEXT: ret;
+; CHECK-NOI32X2-LABEL: test_ret_const(
+; CHECK-NOI32X2: {
+; CHECK-NOI32X2-EMPTY:
+; CHECK-NOI32X2-NEXT: // %bb.0:
+; CHECK-NOI32X2-NEXT: st.param.v2.b32 [func_retval0], {-1, 2};
+; CHECK-NOI32X2-NEXT: ret;
+;
+; CHECK-I32X2-LABEL: test_ret_const(
+; CHECK-I32X2: {
+; CHECK-I32X2-EMPTY:
+; CHECK-I32X2-NEXT: // %bb.0:
+; CHECK-I32X2-NEXT: st.param::func.v2.b32 [func_retval0], {-1, 2};
+; CHECK-I32X2-NEXT: ret;
ret <2 x i32> <i32 -1, i32 2>
}
@@ -41,9 +48,9 @@ define i32 @test_extract_0(<2 x i32> %a) #0 {
; CHECK-I32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param.b64 %rd1, [test_extract_0_param_0];
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_extract_0_param_0];
; CHECK-I32X2-NEXT: mov.b64 {%r1, _}, %rd1;
-; CHECK-I32X2-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-I32X2-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-I32X2-NEXT: ret;
%e = extractelement <2 x i32> %a, i32 0
ret i32 %e
@@ -65,9 +72,9 @@ define i32 @test_extract_1(<2 x i32> %a) #0 {
; CHECK-I32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param.b64 %rd1, [test_extract_1_param_0];
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_extract_1_param_0];
; CHECK-I32X2-NEXT: mov.b64 {_, %r1}, %rd1;
-; CHECK-I32X2-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-I32X2-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-I32X2-NEXT: ret;
%e = extractelement <2 x i32> %a, i32 1
ret i32 %e
@@ -103,12 +110,12 @@ define i32 @test_extract_i(<2 x i32> %a, i64 %idx) #0 {
; CHECK-I32X2-NEXT: .reg .b64 %rd<3>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param.b64 %rd2, [test_extract_i_param_1];
-; CHECK-I32X2-NEXT: ld.param.b64 %rd1, [test_extract_i_param_0];
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd2, [test_extract_i_param_1];
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_extract_i_param_0];
; CHECK-I32X2-NEXT: setp.eq.b64 %p1, %rd2, 0;
; CHECK-I32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
; CHECK-I32X2-NEXT: selp.b32 %r3, %r1, %r2, %p1;
-; CHECK-I32X2-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-I32X2-NEXT: st.param::func.b32 [func_retval0], %r3;
; CHECK-I32X2-NEXT: ret;
%e = extractelement <2 x i32> %a, i64 %idx
ret i32 %e
@@ -133,13 +140,13 @@ define <2 x i32> @test_add(<2 x i32> %a, <2 x i32> %b) #0 {
; CHECK-I32X2-NEXT: .reg .b64 %rd<3>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param.b64 %rd2, [test_add_param_1];
-; CHECK-I32X2-NEXT: ld.param.b64 %rd1, [test_add_param_0];
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd2, [test_add_param_1];
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_add_param_0];
; CHECK-I32X2-NEXT: mov.b64 {%r1, %r2}, %rd2;
; CHECK-I32X2-NEXT: mov.b64 {%r3, %r4}, %rd1;
; CHECK-I32X2-NEXT: add.s32 %r5, %r4, %r2;
; CHECK-I32X2-NEXT: add.s32 %r6, %r3, %r1;
-; CHECK-I32X2-NEXT: st.param.v2.b32 [func_retval0], {%r6, %r5};
+; CHECK-I32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r6, %r5};
; CHECK-I32X2-NEXT: ret;
%r = add <2 x i32> %a, %b
ret <2 x i32> %r
@@ -163,11 +170,11 @@ define <2 x i32> @test_add_imm_0(<2 x i32> %a) #0 {
; CHECK-I32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param.b64 %rd1, [test_add_imm_0_param_0];
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_add_imm_0_param_0];
; CHECK-I32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
; CHECK-I32X2-NEXT: add.s32 %r3, %r2, 2;
; CHECK-I32X2-NEXT: add.s32 %r4, %r1, 1;
-; CHECK-I32X2-NEXT: st.param.v2.b32 [func_retval0], {%r4, %r3};
+; CHECK-I32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r4, %r3};
; CHECK-I32X2-NEXT: ret;
%r = add <2 x i32> <i32 1, i32 2>, %a
ret <2 x i32> %r
@@ -191,11 +198,11 @@ define <2 x i32> @test_add_imm_1(<2 x i32> %a) #0 {
; CHECK-I32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param.b64 %rd1, [test_add_imm_1_param_0];
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_add_imm_1_param_0];
; CHECK-I32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
; CHECK-I32X2-NEXT: add.s32 %r3, %r2, 2;
; CHECK-I32X2-NEXT: add.s32 %r4, %r1, 1;
-; CHECK-I32X2-NEXT: st.param.v2.b32 [func_retval0], {%r4, %r3};
+; CHECK-I32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r4, %r3};
; CHECK-I32X2-NEXT: ret;
%r = add <2 x i32> %a, <i32 1, i32 2>
ret <2 x i32> %r
@@ -220,13 +227,13 @@ define <2 x i32> @test_sub(<2 x i32> %a, <2 x i32> %b) #0 {
; CHECK-I32X2-NEXT: .reg .b64 %rd<3>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param.b64 %rd2, [test_sub_param_1];
-; CHECK-I32X2-NEXT: ld.param.b64 %rd1, [test_sub_param_0];
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd2, [test_sub_param_1];
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_sub_param_0];
; CHECK-I32X2-NEXT: mov.b64 {%r1, %r2}, %rd2;
; CHECK-I32X2-NEXT: mov.b64 {%r3, %r4}, %rd1;
; CHECK-I32X2-NEXT: sub.s32 %r5, %r4, %r2;
; CHECK-I32X2-NEXT: sub.s32 %r6, %r3, %r1;
-; CHECK-I32X2-NEXT: st.param.v2.b32 [func_retval0], {%r6, %r5};
+; CHECK-I32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r6, %r5};
; CHECK-I32X2-NEXT: ret;
%r = sub <2 x i32> %a, %b
ret <2 x i32> %r
@@ -251,13 +258,13 @@ define <2 x i32> @test_smax(<2 x i32> %a, <2 x i32> %b) #0 {
; CHECK-I32X2-NEXT: .reg .b64 %rd<3>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param.b64 %rd2, [test_smax_param_1];
-; CHECK-I32X2-NEXT: ld.param.b64 %rd1, [test_smax_param_0];
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd2, [test_smax_param_1];
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_smax_param_0];
; CHECK-I32X2-NEXT: mov.b64 {%r1, %r2}, %rd2;
; CHECK-I32X2-NEXT: mov.b64 {%r3, %r4}, %rd1;
; CHECK-I32X2-NEXT: max.s32 %r5, %r4, %r2;
; CHECK-I32X2-NEXT: max.s32 %r6, %r3, %r1;
-; CHECK-I32X2-NEXT: st.param.v2.b32 [func_retval0], {%r6, %r5};
+; CHECK-I32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r6, %r5};
; CHECK-I32X2-NEXT: ret;
%cmp = icmp sgt <2 x i32> %a, %b
%r = select <2 x i1> %cmp, <2 x i32> %a, <2 x i32> %b
@@ -283,13 +290,13 @@ define <2 x i32> @test_umax(<2 x i32> %a, <2 x i32> %b) #0 {
; CHECK-I32X2-NEXT: .reg .b64 %rd<3>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param.b64 %rd2, [test_umax_param_1];
-; CHECK-I32X2-NEXT: ld.param.b64 %rd1, [test_umax_param_0];
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd2, [test_umax_param_1];
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_umax_param_0];
; CHECK-I32X2-NEXT: mov.b64 {%r1, %r2}, %rd2;
; CHECK-I32X2-NEXT: mov.b64 {%r3, %r4}, %rd1;
; CHECK-I32X2-NEXT: max.u32 %r5, %r4, %r2;
; CHECK-I32X2-NEXT: max.u32 %r6, %r3, %r1;
-; CHECK-I32X2-NEXT: st.param.v2.b32 [func_retval0], {%r6, %r5};
+; CHECK-I32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r6, %r5};
; CHECK-I32X2-NEXT: ret;
%cmp = icmp ugt <2 x i32> %a, %b
%r = select <2 x i1> %cmp, <2 x i32> %a, <2 x i32> %b
@@ -315,13 +322,13 @@ define <2 x i32> @test_smin(<2 x i32> %a, <2 x i32> %b) #0 {
; CHECK-I32X2-NEXT: .reg .b64 %rd<3>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param.b64 %rd2, [test_smin_param_1];
-; CHECK-I32X2-NEXT: ld.param.b64 %rd1, [test_smin_param_0];
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd2, [test_smin_param_1];
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_smin_param_0];
; CHECK-I32X2-NEXT: mov.b64 {%r1, %r2}, %rd2;
; CHECK-I32X2-NEXT: mov.b64 {%r3, %r4}, %rd1;
; CHECK-I32X2-NEXT: min.s32 %r5, %r4, %r2;
; CHECK-I32X2-NEXT: min.s32 %r6, %r3, %r1;
-; CHECK-I32X2-NEXT: st.param.v2.b32 [func_retval0], {%r6, %r5};
+; CHECK-I32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r6, %r5};
; CHECK-I32X2-NEXT: ret;
%cmp = icmp sle <2 x i32> %a, %b
%r = select <2 x i1> %cmp, <2 x i32> %a, <2 x i32> %b
@@ -347,13 +354,13 @@ define <2 x i32> @test_umin(<2 x i32> %a, <2 x i32> %b) #0 {
; CHECK-I32X2-NEXT: .reg .b64 %rd<3>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param.b64 %rd2, [test_umin_param_1];
-; CHECK-I32X2-NEXT: ld.param.b64 %rd1, [test_umin_param_0];
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd2, [test_umin_param_1];
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_umin_param_0];
; CHECK-I32X2-NEXT: mov.b64 {%r1, %r2}, %rd2;
; CHECK-I32X2-NEXT: mov.b64 {%r3, %r4}, %rd1;
; CHECK-I32X2-NEXT: min.u32 %r5, %r4, %r2;
; CHECK-I32X2-NEXT: min.u32 %r6, %r3, %r1;
-; CHECK-I32X2-NEXT: st.param.v2.b32 [func_retval0], {%r6, %r5};
+; CHECK-I32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r6, %r5};
; CHECK-I32X2-NEXT: ret;
%cmp = icmp ule <2 x i32> %a, %b
%r = select <2 x i1> %cmp, <2 x i32> %a, <2 x i32> %b
@@ -384,9 +391,9 @@ define <2 x i32> @test_eq(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) #0 {
; CHECK-I32X2-NEXT: .reg .b64 %rd<4>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param.b64 %rd3, [test_eq_param_2];
-; CHECK-I32X2-NEXT: ld.param.b64 %rd2, [test_eq_param_1];
-; CHECK-I32X2-NEXT: ld.param.b64 %rd1, [test_eq_param_0];
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd3, [test_eq_param_2];
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd2, [test_eq_param_1];
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_eq_param_0];
; CHECK-I32X2-NEXT: mov.b64 {%r1, %r2}, %rd2;
; CHECK-I32X2-NEXT: mov.b64 {%r3, %r4}, %rd1;
; CHECK-I32X2-NEXT: setp.eq.b32 %p1, %r3, %r1;
@@ -394,7 +401,7 @@ define <2 x i32> @test_eq(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) #0 {
; CHECK-I32X2-NEXT: mov.b64 {%r5, %r6}, %rd3;
; CHECK-I32X2-NEXT: selp.b32 %r7, %r4, %r6, %p2;
; CHECK-I32X2-NEXT: selp.b32 %r8, %r3, %r5, %p1;
-; CHECK-I32X2-NEXT: st.param.v2.b32 [func_retval0], {%r8, %r7};
+; CHECK-I32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r8, %r7};
; CHECK-I32X2-NEXT: ret;
%cmp = icmp eq <2 x i32> %a, %b
%r = select <2 x i1> %cmp, <2 x i32> %a, <2 x i32> %c
@@ -425,9 +432,9 @@ define <2 x i32> @test_ne(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) #0 {
; CHECK-I32X2-NEXT: .reg .b64 %rd<4>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param.b64 %rd3, [test_ne_param_2];
-; CHECK-I32X2-NEXT: ld.param.b64 %rd2, [test_ne_param_1];
-; CHECK-I32X2-NEXT: ld.param.b64 %rd1, [test_ne_param_0];
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd3, [test_ne_param_2];
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd2, [test_ne_param_1];
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_ne_param_0];
; CHECK-I32X2-NEXT: mov.b64 {%r1, %r2}, %rd2;
; CHECK-I32X2-NEXT: mov.b64 {%r3, %r4}, %rd1;
; CHECK-I32X2-NEXT: setp.ne.b32 %p1, %r3, %r1;
@@ -435,7 +442,7 @@ define <2 x i32> @test_ne(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) #0 {
; CHECK-I32X2-NEXT: mov.b64 {%r5, %r6}, %rd3;
; CHECK-I32X2-NEXT: selp.b32 %r7, %r4, %r6, %p2;
; CHECK-I32X2-NEXT: selp.b32 %r8, %r3, %r5, %p1;
-; CHECK-I32X2-NEXT: st.param.v2.b32 [func_retval0], {%r8, %r7};
+; CHECK-I32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r8, %r7};
; CHECK-I32X2-NEXT: ret;
%cmp = icmp ne <2 x i32> %a, %b
%r = select <2 x i1> %cmp, <2 x i32> %a, <2 x i32> %c
@@ -461,13 +468,13 @@ define <2 x i32> @test_mul(<2 x i32> %a, <2 x i32> %b) #0 {
; CHECK-I32X2-NEXT: .reg .b64 %rd<3>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param.b64 %rd2, [test_mul_param_1];
-; CHECK-I32X2-NEXT: ld.param.b64 %rd1, [test_mul_param_0];
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd2, [test_mul_param_1];
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_mul_param_0];
; CHECK-I32X2-NEXT: mov.b64 {%r1, %r2}, %rd2;
; CHECK-I32X2-NEXT: mov.b64 {%r3, %r4}, %rd1;
; CHECK-I32X2-NEXT: mul.lo.s32 %r5, %r4, %r2;
; CHECK-I32X2-NEXT: mul.lo.s32 %r6, %r3, %r1;
-; CHECK-I32X2-NEXT: st.param.v2.b32 [func_retval0], {%r6, %r5};
+; CHECK-I32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r6, %r5};
; CHECK-I32X2-NEXT: ret;
%r = mul <2 x i32> %a, %b
ret <2 x i32> %r
@@ -492,27 +499,36 @@ define <2 x i32> @test_or(<2 x i32> %a, <2 x i32> %b) #0 {
; CHECK-I32X2-NEXT: .reg .b64 %rd<3>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param.b64 %rd2, [test_or_param_1];
-; CHECK-I32X2-NEXT: ld.param.b64 %rd1, [test_or_param_0];
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd2, [test_or_param_1];
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_or_param_0];
; CHECK-I32X2-NEXT: mov.b64 {%r1, %r2}, %rd2;
; CHECK-I32X2-NEXT: mov.b64 {%r3, %r4}, %rd1;
; CHECK-I32X2-NEXT: or.b32 %r5, %r4, %r2;
; CHECK-I32X2-NEXT: or.b32 %r6, %r3, %r1;
-; CHECK-I32X2-NEXT: st.param.v2.b32 [func_retval0], {%r6, %r5};
+; CHECK-I32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r6, %r5};
; CHECK-I32X2-NEXT: ret;
%r = or <2 x i32> %a, %b
ret <2 x i32> %r
}
define <2 x i32> @test_or_computed(i32 %a) {
-; CHECK-LABEL: test_or_computed(
-; CHECK: {
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [test_or_computed_param_0];
-; CHECK-NEXT: st.param.v2.b32 [func_retval0], {%r1, 5};
-; CHECK-NEXT: ret;
+; CHECK-NOI32X2-LABEL: test_or_computed(
+; CHECK-NOI32X2: {
+; CHECK-NOI32X2-NEXT: .reg .b32 %r<2>;
+; CHECK-NOI32X2-EMPTY:
+; CHECK-NOI32X2-NEXT: // %bb.0:
+; CHECK-NOI32X2-NEXT: ld.param.b32 %r1, [test_or_computed_param_0];
+; CHECK-NOI32X2-NEXT: st.param.v2.b32 [func_retval0], {%r1, 5};
+; CHECK-NOI32X2-NEXT: ret;
+;
+; CHECK-I32X2-LABEL: test_or_computed(
+; CHECK-I32X2: {
+; CHECK-I32X2-NEXT: .reg .b32 %r<2>;
+; CHECK-I32X2-EMPTY:
+; CHECK-I32X2-NEXT: // %bb.0:
+; CHECK-I32X2-NEXT: ld.param::func.b32 %r1, [test_or_computed_param_0];
+; CHECK-I32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r1, 5};
+; CHECK-I32X2-NEXT: ret;
%ins.0 = insertelement <2 x i32> zeroinitializer, i32 %a, i32 0
%ins.1 = insertelement <2 x i32> %ins.0, i32 5, i32 1
%r = or <2 x i32> %ins.1, %ins.0
@@ -537,11 +553,11 @@ define <2 x i32> @test_or_imm_0(<2 x i32> %a) #0 {
; CHECK-I32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param.b64 %rd1, [test_or_imm_0_param_0];
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_or_imm_0_param_0];
; CHECK-I32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
; CHECK-I32X2-NEXT: or.b32 %r3, %r2, 2;
; CHECK-I32X2-NEXT: or.b32 %r4, %r1, 1;
-; CHECK-I32X2-NEXT: st.param.v2.b32 [func_retval0], {%r4, %r3};
+; CHECK-I32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r4, %r3};
; CHECK-I32X2-NEXT: ret;
%r = or <2 x i32> <i32 1, i32 2>, %a
ret <2 x i32> %r
@@ -565,11 +581,11 @@ define <2 x i32> @test_or_imm_1(<2 x i32> %a) #0 {
; CHECK-I32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param.b64 %rd1, [test_or_imm_1_param_0];
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_or_imm_1_param_0];
; CHECK-I32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
; CHECK-I32X2-NEXT: or.b32 %r3, %r2, 2;
; CHECK-I32X2-NEXT: or.b32 %r4, %r1, 1;
-; CHECK-I32X2-NEXT: st.param.v2.b32 [func_retval0], {%r4, %r3};
+; CHECK-I32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r4, %r3};
; CHECK-I32X2-NEXT: ret;
%r = or <2 x i32> %a, <i32 1, i32 2>
ret <2 x i32> %r
@@ -594,27 +610,36 @@ define <2 x i32> @test_xor(<2 x i32> %a, <2 x i32> %b) #0 {
; CHECK-I32X2-NEXT: .reg .b64 %rd<3>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param.b64 %rd2, [test_xor_param_1];
-; CHECK-I32X2-NEXT: ld.param.b64 %rd1, [test_xor_param_0];
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd2, [test_xor_param_1];
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_xor_param_0];
; CHECK-I32X2-NEXT: mov.b64 {%r1, %r2}, %rd2;
; CHECK-I32X2-NEXT: mov.b64 {%r3, %r4}, %rd1;
; CHECK-I32X2-NEXT: xor.b32 %r5, %r4, %r2;
; CHECK-I32X2-NEXT: xor.b32 %r6, %r3, %r1;
-; CHECK-I32X2-NEXT: st.param.v2.b32 [func_retval0], {%r6, %r5};
+; CHECK-I32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r6, %r5};
; CHECK-I32X2-NEXT: ret;
%r = xor <2 x i32> %a, %b
ret <2 x i32> %r
}
define <2 x i32> @test_xor_computed(i32 %a) {
-; CHECK-LABEL: test_xor_computed(
-; CHECK: {
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [test_xor_computed_param_0];
-; CHECK-NEXT: st.param.v2.b32 [func_retval0], {0, 5};
-; CHECK-NEXT: ret;
+; CHECK-NOI32X2-LABEL: test_xor_computed(
+; CHECK-NOI32X2: {
+; CHECK-NOI32X2-NEXT: .reg .b32 %r<2>;
+; CHECK-NOI32X2-EMPTY:
+; CHECK-NOI32X2-NEXT: // %bb.0:
+; CHECK-NOI32X2-NEXT: ld.param.b32 %r1, [test_xor_computed_param_0];
+; CHECK-NOI32X2-NEXT: st.param.v2.b32 [func_retval0], {0, 5};
+; CHECK-NOI32X2-NEXT: ret;
+;
+; CHECK-I32X2-LABEL: test_xor_computed(
+; CHECK-I32X2: {
+; CHECK-I32X2-NEXT: .reg .b32 %r<2>;
+; CHECK-I32X2-EMPTY:
+; CHECK-I32X2-NEXT: // %bb.0:
+; CHECK-I32X2-NEXT: ld.param::func.b32 %r1, [test_xor_computed_param_0];
+; CHECK-I32X2-NEXT: st.param::func.v2.b32 [func_retval0], {0, 5};
+; CHECK-I32X2-NEXT: ret;
%ins.0 = insertelement <2 x i32> zeroinitializer, i32 %a, i32 0
%ins.1 = insertelement <2 x i32> %ins.0, i32 5, i32 1
%r = xor <2 x i32> %ins.1, %ins.0
@@ -639,11 +664,11 @@ define <2 x i32> @test_xor_imm_0(<2 x i32> %a) #0 {
; CHECK-I32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param.b64 %rd1, [test_xor_imm_0_param_0];
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_xor_imm_0_param_0];
; CHECK-I32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
; CHECK-I32X2-NEXT: xor.b32 %r3, %r2, 2;
; CHECK-I32X2-NEXT: xor.b32 %r4, %r1, 1;
-; CHECK-I32X2-NEXT: st.param.v2.b32 [func_retval0], {%r4, %r3};
+; CHECK-I32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r4, %r3};
; CHECK-I32X2-NEXT: ret;
%r = xor <2 x i32> <i32 1, i32 2>, %a
ret <2 x i32> %r
@@ -667,11 +692,11 @@ define <2 x i32> @test_xor_imm_1(<2 x i32> %a) #0 {
; CHECK-I32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param.b64 %rd1, [test_xor_imm_1_param_0];
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_xor_imm_1_param_0];
; CHECK-I32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
; CHECK-I32X2-NEXT: xor.b32 %r3, %r2, 2;
; CHECK-I32X2-NEXT: xor.b32 %r4, %r1, 1;
-; CHECK-I32X2-NEXT: st.param.v2.b32 [func_retval0], {%r4, %r3};
+; CHECK-I32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r4, %r3};
; CHECK-I32X2-NEXT: ret;
%r = xor <2 x i32> %a, <i32 1, i32 2>
ret <2 x i32> %r
@@ -696,27 +721,36 @@ define <2 x i32> @test_and(<2 x i32> %a, <2 x i32> %b) #0 {
; CHECK-I32X2-NEXT: .reg .b64 %rd<3>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param.b64 %rd2, [test_and_param_1];
-; CHECK-I32X2-NEXT: ld.param.b64 %rd1, [test_and_param_0];
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd2, [test_and_param_1];
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_and_param_0];
; CHECK-I32X2-NEXT: mov.b64 {%r1, %r2}, %rd2;
; CHECK-I32X2-NEXT: mov.b64 {%r3, %r4}, %rd1;
; CHECK-I32X2-NEXT: and.b32 %r5, %r4, %r2;
; CHECK-I32X2-NEXT: and.b32 %r6, %r3, %r1;
-; CHECK-I32X2-NEXT: st.param.v2.b32 [func_retval0], {%r6, %r5};
+; CHECK-I32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r6, %r5};
; CHECK-I32X2-NEXT: ret;
%r = and <2 x i32> %a, %b
ret <2 x i32> %r
}
define <2 x i32> @test_and_computed(i32 %a) {
-; CHECK-LABEL: test_and_computed(
-; CHECK: {
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [test_and_computed_param_0];
-; CHECK-NEXT: st.param.v2.b32 [func_retval0], {%r1, 0};
-; CHECK-NEXT: ret;
+; CHECK-NOI32X2-LABEL: test_and_computed(
+; CHECK-NOI32X2: {
+; CHECK-NOI32X2-NEXT: .reg .b32 %r<2>;
+; CHECK-NOI32X2-EMPTY:
+; CHECK-NOI32X2-NEXT: // %bb.0:
+; CHECK-NOI32X2-NEXT: ld.param.b32 %r1, [test_and_computed_param_0];
+; CHECK-NOI32X2-NEXT: st.param.v2.b32 [func_retval0], {%r1, 0};
+; CHECK-NOI32X2-NEXT: ret;
+;
+; CHECK-I32X2-LABEL: test_and_computed(
+; CHECK-I32X2: {
+; CHECK-I32X2-NEXT: .reg .b32 %r<2>;
+; CHECK-I32X2-EMPTY:
+; CHECK-I32X2-NEXT: // %bb.0:
+; CHECK-I32X2-NEXT: ld.param::func.b32 %r1, [test_and_computed_param_0];
+; CHECK-I32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r1, 0};
+; CHECK-I32X2-NEXT: ret;
%ins.0 = insertelement <2 x i32> zeroinitializer, i32 %a, i32 0
%ins.1 = insertelement <2 x i32> %ins.0, i32 5, i32 1
%r = and <2 x i32> %ins.1, %ins.0
@@ -741,11 +775,11 @@ define <2 x i32> @test_and_imm_0(<2 x i32> %a) #0 {
; CHECK-I32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param.b64 %rd1, [test_and_imm_0_param_0];
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_and_imm_0_param_0];
; CHECK-I32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
; CHECK-I32X2-NEXT: and.b32 %r3, %r2, 2;
; CHECK-I32X2-NEXT: and.b32 %r4, %r1, 1;
-; CHECK-I32X2-NEXT: st.param.v2.b32 [func_retval0], {%r4, %r3};
+; CHECK-I32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r4, %r3};
; CHECK-I32X2-NEXT: ret;
%r = and <2 x i32> <i32 1, i32 2>, %a
ret <2 x i32> %r
@@ -769,11 +803,11 @@ define <2 x i32> @test_and_imm_1(<2 x i32> %a) #0 {
; CHECK-I32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param.b64 %rd1, [test_and_imm_1_param_0];
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_and_imm_1_param_0];
; CHECK-I32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
; CHECK-I32X2-NEXT: and.b32 %r3, %r2, 2;
; CHECK-I32X2-NEXT: and.b32 %r4, %r1, 1;
-; CHECK-I32X2-NEXT: st.param.v2.b32 [func_retval0], {%r4, %r3};
+; CHECK-I32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r4, %r3};
; CHECK-I32X2-NEXT: ret;
%r = and <2 x i32> %a, <i32 1, i32 2>
ret <2 x i32> %r
@@ -797,8 +831,8 @@ define void @test_ldst_v2i32(ptr %a, ptr %b) {
; CHECK-I32X2-NEXT: .reg .b64 %rd<4>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param.b64 %rd2, [test_ldst_v2i32_param_1];
-; CHECK-I32X2-NEXT: ld.param.b64 %rd1, [test_ldst_v2i32_param_0];
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd2, [test_ldst_v2i32_param_1];
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_ldst_v2i32_param_0];
; CHECK-I32X2-NEXT: ld.b64 %rd3, [%rd1];
; CHECK-I32X2-NEXT: st.b64 [%rd2], %rd3;
; CHECK-I32X2-NEXT: ret;
@@ -808,19 +842,33 @@ define void @test_ldst_v2i32(ptr %a, ptr %b) {
}
define void @test_ldst_v3i32(ptr %a, ptr %b) {
-; CHECK-LABEL: test_ldst_v3i32(
-; CHECK: {
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-NEXT: .reg .b64 %rd<4>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd2, [test_ldst_v3i32_param_1];
-; CHECK-NEXT: ld.param.b64 %rd1, [test_ldst_v3i32_param_0];
-; CHECK-NEXT: ld.b64 %rd3, [%rd1];
-; CHECK-NEXT: ld.b32 %r1, [%rd1+8];
-; CHECK-NEXT: st.b32 [%rd2+8], %r1;
-; CHECK-NEXT: st.b64 [%rd2], %rd3;
-; CHECK-NEXT: ret;
+; CHECK-NOI32X2-LABEL: test_ldst_v3i32(
+; CHECK-NOI32X2: {
+; CHECK-NOI32X2-NEXT: .reg .b32 %r<2>;
+; CHECK-NOI32X2-NEXT: .reg .b64 %rd<4>;
+; CHECK-NOI32X2-EMPTY:
+; CHECK-NOI32X2-NEXT: // %bb.0:
+; CHECK-NOI32X2-NEXT: ld.param.b64 %rd2, [test_ldst_v3i32_param_1];
+; CHECK-NOI32X2-NEXT: ld.param.b64 %rd1, [test_ldst_v3i32_param_0];
+; CHECK-NOI32X2-NEXT: ld.b64 %rd3, [%rd1];
+; CHECK-NOI32X2-NEXT: ld.b32 %r1, [%rd1+8];
+; CHECK-NOI32X2-NEXT: st.b32 [%rd2+8], %r1;
+; CHECK-NOI32X2-NEXT: st.b64 [%rd2], %rd3;
+; CHECK-NOI32X2-NEXT: ret;
+;
+; CHECK-I32X2-LABEL: test_ldst_v3i32(
+; CHECK-I32X2: {
+; CHECK-I32X2-NEXT: .reg .b32 %r<2>;
+; CHECK-I32X2-NEXT: .reg .b64 %rd<4>;
+; CHECK-I32X2-EMPTY:
+; CHECK-I32X2-NEXT: // %bb.0:
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd2, [test_ldst_v3i32_param_1];
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_ldst_v3i32_param_0];
+; CHECK-I32X2-NEXT: ld.b64 %rd3, [%rd1];
+; CHECK-I32X2-NEXT: ld.b32 %r1, [%rd1+8];
+; CHECK-I32X2-NEXT: st.b32 [%rd2+8], %r1;
+; CHECK-I32X2-NEXT: st.b64 [%rd2], %rd3;
+; CHECK-I32X2-NEXT: ret;
%t1 = load <3 x i32>, ptr %a
store <3 x i32> %t1, ptr %b, align 16
ret void
@@ -844,8 +892,8 @@ define void @test_ldst_v4i32(ptr %a, ptr %b) {
; CHECK-I32X2-NEXT: .reg .b64 %rd<5>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param.b64 %rd2, [test_ldst_v4i32_param_1];
-; CHECK-I32X2-NEXT: ld.param.b64 %rd1, [test_ldst_v4i32_param_0];
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd2, [test_ldst_v4i32_param_1];
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_ldst_v4i32_param_0];
; CHECK-I32X2-NEXT: ld.v2.b64 {%rd3, %rd4}, [%rd1];
; CHECK-I32X2-NEXT: st.v2.b64 [%rd2], {%rd3, %rd4};
; CHECK-I32X2-NEXT: ret;
@@ -890,8 +938,8 @@ define void @test_ldst_v2i32_unaligned(ptr %a, ptr %b) {
; CHECK-I32X2-NEXT: .reg .b64 %rd<28>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param.b64 %rd2, [test_ldst_v2i32_unaligned_param_1];
-; CHECK-I32X2-NEXT: ld.param.b64 %rd1, [test_ldst_v2i32_unaligned_param_0];
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd2, [test_ldst_v2i32_unaligned_param_1];
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_ldst_v2i32_unaligned_param_0];
; CHECK-I32X2-NEXT: ld.b8 %rd3, [%rd1];
; CHECK-I32X2-NEXT: ld.b8 %rd4, [%rd1+1];
; CHECK-I32X2-NEXT: shl.b64 %rd5, %rd4, 8;
@@ -958,18 +1006,18 @@ define <2 x i32> @test_call(<2 x i32> %a, <2 x i32> %b) #0 {
; CHECK-I32X2-NEXT: .reg .b64 %rd<4>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param.b64 %rd2, [test_call_param_1];
-; CHECK-I32X2-NEXT: ld.param.b64 %rd1, [test_call_param_0];
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd2, [test_call_param_1];
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_call_param_0];
; CHECK-I32X2-NEXT: { // callseq 0, 0
; CHECK-I32X2-NEXT: .param .align 8 .b8 param0[8];
; CHECK-I32X2-NEXT: .param .align 8 .b8 param1[8];
; CHECK-I32X2-NEXT: .param .align 8 .b8 retval0[8];
-; CHECK-I32X2-NEXT: st.param.b64 [param1], %rd2;
-; CHECK-I32X2-NEXT: st.param.b64 [param0], %rd1;
+; CHECK-I32X2-NEXT: st.param::func.b64 [param1], %rd2;
+; CHECK-I32X2-NEXT: st.param::func.b64 [param0], %rd1;
; CHECK-I32X2-NEXT: call.uni (retval0), test_callee, (param0, param1);
-; CHECK-I32X2-NEXT: ld.param.b64 %rd3, [retval0];
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd3, [retval0];
; CHECK-I32X2-NEXT: } // callseq 0
-; CHECK-I32X2-NEXT: st.param.b64 [func_retval0], %rd3;
+; CHECK-I32X2-NEXT: st.param::func.b64 [func_retval0], %rd3;
; CHECK-I32X2-NEXT: ret;
%r = call <2 x i32> @test_callee(<2 x i32> %a, <2 x i32> %b)
ret <2 x i32> %r
@@ -1000,18 +1048,18 @@ define <2 x i32> @test_call_flipped(<2 x i32> %a, <2 x i32> %b) #0 {
; CHECK-I32X2-NEXT: .reg .b64 %rd<4>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param.b64 %rd2, [test_call_flipped_param_1];
-; CHECK-I32X2-NEXT: ld.param.b64 %rd1, [test_call_flipped_param_0];
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd2, [test_call_flipped_param_1];
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_call_flipped_param_0];
; CHECK-I32X2-NEXT: { // callseq 1, 0
; CHECK-I32X2-NEXT: .param .align 8 .b8 param0[8];
; CHECK-I32X2-NEXT: .param .align 8 .b8 param1[8];
; CHECK-I32X2-NEXT: .param .align 8 .b8 retval0[8];
-; CHECK-I32X2-NEXT: st.param.b64 [param1], %rd1;
-; CHECK-I32X2-NEXT: st.param.b64 [param0], %rd2;
+; CHECK-I32X2-NEXT: st.param::func.b64 [param1], %rd1;
+; CHECK-I32X2-NEXT: st.param::func.b64 [param0], %rd2;
; CHECK-I32X2-NEXT: call.uni (retval0), test_callee, (param0, param1);
-; CHECK-I32X2-NEXT: ld.param.b64 %rd3, [retval0];
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd3, [retval0];
; CHECK-I32X2-NEXT: } // callseq 1
-; CHECK-I32X2-NEXT: st.param.b64 [func_retval0], %rd3;
+; CHECK-I32X2-NEXT: st.param::func.b64 [func_retval0], %rd3;
; CHECK-I32X2-NEXT: ret;
%r = call <2 x i32> @test_callee(<2 x i32> %b, <2 x i32> %a)
ret <2 x i32> %r
@@ -1042,18 +1090,18 @@ define <2 x i32> @test_tailcall_flipped(<2 x i32> %a, <2 x i32> %b) #0 {
; CHECK-I32X2-NEXT: .reg .b64 %rd<4>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param.b64 %rd2, [test_tailcall_flipped_param_1];
-; CHECK-I32X2-NEXT: ld.param.b64 %rd1, [test_tailcall_flipped_param_0];
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd2, [test_tailcall_flipped_param_1];
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_tailcall_flipped_param_0];
; CHECK-I32X2-NEXT: { // callseq 2, 0
; CHECK-I32X2-NEXT: .param .align 8 .b8 param0[8];
; CHECK-I32X2-NEXT: .param .align 8 .b8 param1[8];
; CHECK-I32X2-NEXT: .param .align 8 .b8 retval0[8];
-; CHECK-I32X2-NEXT: st.param.b64 [param1], %rd1;
-; CHECK-I32X2-NEXT: st.param.b64 [param0], %rd2;
+; CHECK-I32X2-NEXT: st.param::func.b64 [param1], %rd1;
+; CHECK-I32X2-NEXT: st.param::func.b64 [param0], %rd2;
; CHECK-I32X2-NEXT: call.uni (retval0), test_callee, (param0, param1);
-; CHECK-I32X2-NEXT: ld.param.b64 %rd3, [retval0];
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd3, [retval0];
; CHECK-I32X2-NEXT: } // callseq 2
-; CHECK-I32X2-NEXT: st.param.b64 [func_retval0], %rd3;
+; CHECK-I32X2-NEXT: st.param::func.b64 [func_retval0], %rd3;
; CHECK-I32X2-NEXT: ret;
%r = tail call <2 x i32> @test_callee(<2 x i32> %b, <2 x i32> %a)
ret <2 x i32> %r
@@ -1084,13 +1132,13 @@ define <2 x i32> @test_select(<2 x i32> %a, <2 x i32> %b, i1 zeroext %c) #0 {
; CHECK-I32X2-NEXT: .reg .b64 %rd<4>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param.b8 %rs1, [test_select_param_2];
+; CHECK-I32X2-NEXT: ld.param::func.b8 %rs1, [test_select_param_2];
; CHECK-I32X2-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-I32X2-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-I32X2-NEXT: ld.param.b64 %rd2, [test_select_param_1];
-; CHECK-I32X2-NEXT: ld.param.b64 %rd1, [test_select_param_0];
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd2, [test_select_param_1];
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_select_param_0];
; CHECK-I32X2-NEXT: selp.b64 %rd3, %rd1, %rd2, %p1;
-; CHECK-I32X2-NEXT: st.param.b64 [func_retval0], %rd3;
+; CHECK-I32X2-NEXT: st.param::func.b64 [func_retval0], %rd3;
; CHECK-I32X2-NEXT: ret;
%r = select i1 %c, <2 x i32> %a, <2 x i32> %b
ret <2 x i32> %r
@@ -1121,10 +1169,10 @@ define <2 x i32> @test_select_cc(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c, <2 x
; CHECK-I32X2-NEXT: .reg .b64 %rd<5>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param.b64 %rd4, [test_select_cc_param_3];
-; CHECK-I32X2-NEXT: ld.param.b64 %rd3, [test_select_cc_param_2];
-; CHECK-I32X2-NEXT: ld.param.b64 %rd2, [test_select_cc_param_1];
-; CHECK-I32X2-NEXT: ld.param.b64 %rd1, [test_select_cc_param_0];
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd4, [test_select_cc_param_3];
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd3, [test_select_cc_param_2];
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd2, [test_select_cc_param_1];
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_select_cc_param_0];
; CHECK-I32X2-NEXT: mov.b64 {%r1, %r2}, %rd4;
; CHECK-I32X2-NEXT: mov.b64 {%r3, %r4}, %rd3;
; CHECK-I32X2-NEXT: setp.ne.b32 %p1, %r3, %r1;
@@ -1133,7 +1181,7 @@ define <2 x i32> @test_select_cc(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c, <2 x
; CHECK-I32X2-NEXT: mov.b64 {%r7, %r8}, %rd1;
; CHECK-I32X2-NEXT: selp.b32 %r9, %r8, %r6, %p2;
; CHECK-I32X2-NEXT: selp.b32 %r10, %r7, %r5, %p1;
-; CHECK-I32X2-NEXT: st.param.v2.b32 [func_retval0], {%r10, %r9};
+; CHECK-I32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r10, %r9};
; CHECK-I32X2-NEXT: ret;
%cc = icmp ne <2 x i32> %c, %d
%r = select <2 x i1> %cc, <2 x i32> %a, <2 x i32> %b
@@ -1157,10 +1205,10 @@ define <2 x i16> @test_trunc_2xi32_to_2xi16(<2 x i32> %a) #0 {
; CHECK-I32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param.b64 %rd1, [test_trunc_2xi32_to_2xi16_param_0];
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_trunc_2xi32_to_2xi16_param_0];
; CHECK-I32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
; CHECK-I32X2-NEXT: prmt.b32 %r3, %r1, %r2, 0x5410U;
-; CHECK-I32X2-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-I32X2-NEXT: st.param::func.b32 [func_retval0], %r3;
; CHECK-I32X2-NEXT: ret;
%r = trunc <2 x i32> %a to <2 x i16>
ret <2 x i16> %r
@@ -1186,11 +1234,11 @@ define <2 x i8> @test_trunc_2xi32_to_2xi8(<2 x i32> %a) #0 {
; CHECK-I32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param.b64 %rd1, [test_trunc_2xi32_to_2xi8_param_0];
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_trunc_2xi32_to_2xi8_param_0];
; CHECK-I32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
; CHECK-I32X2-NEXT: cvt.u16.u32 %rs1, %r2;
; CHECK-I32X2-NEXT: cvt.u16.u32 %rs2, %r1;
-; CHECK-I32X2-NEXT: st.param.v2.b8 [func_retval0], {%rs2, %rs1};
+; CHECK-I32X2-NEXT: st.param::func.v2.b8 [func_retval0], {%rs2, %rs1};
; CHECK-I32X2-NEXT: ret;
%r = trunc <2 x i32> %a to <2 x i8>
ret <2 x i8> %r
@@ -1213,85 +1261,143 @@ define <2 x i1> @test_trunc_2xi32_to_2xi1(<2 x i32> %a) #0 {
; CHECK-I32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param.b64 %rd1, [test_trunc_2xi32_to_2xi1_param_0];
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_trunc_2xi32_to_2xi1_param_0];
; CHECK-I32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
-; CHECK-I32X2-NEXT: st.param.b8 [func_retval0], %r1;
-; CHECK-I32X2-NEXT: st.param.b8 [func_retval0+1], %r2;
+; CHECK-I32X2-NEXT: st.param::func.b8 [func_retval0], %r1;
+; CHECK-I32X2-NEXT: st.param::func.b8 [func_retval0+1], %r2;
; CHECK-I32X2-NEXT: ret;
%r = trunc <2 x i32> %a to <2 x i1>
ret <2 x i1> %r
}
define <2 x i32> @test_trunc_2xi64(<2 x i64> %a) #0 {
-; CHECK-LABEL: test_trunc_2xi64(
-; CHECK: {
-; CHECK-NEXT: .reg .b32 %r<3>;
-; CHECK-NEXT: .reg .b64 %rd<3>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.v2.b64 {%rd1, %rd2}, [test_trunc_2xi64_param_0];
-; CHECK-NEXT: cvt.u32.u64 %r1, %rd2;
-; CHECK-NEXT: cvt.u32.u64 %r2, %rd1;
-; CHECK-NEXT: st.param.v2.b32 [func_retval0], {%r2, %r1};
-; CHECK-NEXT: ret;
+; CHECK-NOI32X2-LABEL: test_trunc_2xi64(
+; CHECK-NOI32X2: {
+; CHECK-NOI32X2-NEXT: .reg .b32 %r<3>;
+; CHECK-NOI32X2-NEXT: .reg .b64 %rd<3>;
+; CHECK-NOI32X2-EMPTY:
+; CHECK-NOI32X2-NEXT: // %bb.0:
+; CHECK-NOI32X2-NEXT: ld.param.v2.b64 {%rd1, %rd2}, [test_trunc_2xi64_param_0];
+; CHECK-NOI32X2-NEXT: cvt.u32.u64 %r1, %rd2;
+; CHECK-NOI32X2-NEXT: cvt.u32.u64 %r2, %rd1;
+; CHECK-NOI32X2-NEXT: st.param.v2.b32 [func_retval0], {%r2, %r1};
+; CHECK-NOI32X2-NEXT: ret;
+;
+; CHECK-I32X2-LABEL: test_trunc_2xi64(
+; CHECK-I32X2: {
+; CHECK-I32X2-NEXT: .reg .b32 %r<3>;
+; CHECK-I32X2-NEXT: .reg .b64 %rd<3>;
+; CHECK-I32X2-EMPTY:
+; CHECK-I32X2-NEXT: // %bb.0:
+; CHECK-I32X2-NEXT: ld.param::func.v2.b64 {%rd1, %rd2}, [test_trunc_2xi64_param_0];
+; CHECK-I32X2-NEXT: cvt.u32.u64 %r1, %rd2;
+; CHECK-I32X2-NEXT: cvt.u32.u64 %r2, %rd1;
+; CHECK-I32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r2, %r1};
+; CHECK-I32X2-NEXT: ret;
%r = trunc <2 x i64> %a to <2 x i32>
ret <2 x i32> %r
}
define <2 x i32> @test_zext_2xi16_to_2xi32(<2 x i16> %a) #0 {
-; CHECK-LABEL: test_zext_2xi16_to_2xi32(
-; CHECK: {
-; CHECK-NEXT: .reg .b16 %rs<3>;
-; CHECK-NEXT: .reg .b32 %r<4>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [test_zext_2xi16_to_2xi32_param_0];
-; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r1;
-; CHECK-NEXT: cvt.u32.u16 %r2, %rs2;
-; CHECK-NEXT: cvt.u32.u16 %r3, %rs1;
-; CHECK-NEXT: st.param.v2.b32 [func_retval0], {%r3, %r2};
-; CHECK-NEXT: ret;
+; CHECK-NOI32X2-LABEL: test_zext_2xi16_to_2xi32(
+; CHECK-NOI32X2: {
+; CHECK-NOI32X2-NEXT: .reg .b16 %rs<3>;
+; CHECK-NOI32X2-NEXT: .reg .b32 %r<4>;
+; CHECK-NOI32X2-EMPTY:
+; CHECK-NOI32X2-NEXT: // %bb.0:
+; CHECK-NOI32X2-NEXT: ld.param.b32 %r1, [test_zext_2xi16_to_2xi32_param_0];
+; CHECK-NOI32X2-NEXT: mov.b32 {%rs1, %rs2}, %r1;
+; CHECK-NOI32X2-NEXT: cvt.u32.u16 %r2, %rs2;
+; CHECK-NOI32X2-NEXT: cvt.u32.u16 %r3, %rs1;
+; CHECK-NOI32X2-NEXT: st.param.v2.b32 [func_retval0], {%r3, %r2};
+; CHECK-NOI32X2-NEXT: ret;
+;
+; CHECK-I32X2-LABEL: test_zext_2xi16_to_2xi32(
+; CHECK-I32X2: {
+; CHECK-I32X2-NEXT: .reg .b16 %rs<3>;
+; CHECK-I32X2-NEXT: .reg .b32 %r<4>;
+; CHECK-I32X2-EMPTY:
+; CHECK-I32X2-NEXT: // %bb.0:
+; CHECK-I32X2-NEXT: ld.param::func.b32 %r1, [test_zext_2xi16_to_2xi32_param_0];
+; CHECK-I32X2-NEXT: mov.b32 {%rs1, %rs2}, %r1;
+; CHECK-I32X2-NEXT: cvt.u32.u16 %r2, %rs2;
+; CHECK-I32X2-NEXT: cvt.u32.u16 %r3, %rs1;
+; CHECK-I32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r3, %r2};
+; CHECK-I32X2-NEXT: ret;
%r = zext <2 x i16> %a to <2 x i32>
ret <2 x i32> %r
}
define <2 x i32> @test_zext_2xi8_to_2xi32(<2 x i8> %a) #0 {
-; CHECK-LABEL: test_zext_2xi8_to_2xi32(
-; CHECK: {
-; CHECK-NEXT: .reg .b16 %rs<3>;
-; CHECK-NEXT: .reg .b32 %r<4>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.v2.b8 {%rs1, %rs2}, [test_zext_2xi8_to_2xi32_param_0];
-; CHECK-NEXT: mov.b32 %r1, {%rs1, %rs2};
-; CHECK-NEXT: cvt.u32.u16 %r2, %rs2;
-; CHECK-NEXT: cvt.u32.u16 %r3, %rs1;
-; CHECK-NEXT: st.param.v2.b32 [func_retval0], {%r3, %r2};
-; CHECK-NEXT: ret;
+; CHECK-NOI32X2-LABEL: test_zext_2xi8_to_2xi32(
+; CHECK-NOI32X2: {
+; CHECK-NOI32X2-NEXT: .reg .b16 %rs<3>;
+; CHECK-NOI32X2-NEXT: .reg .b32 %r<4>;
+; CHECK-NOI32X2-EMPTY:
+; CHECK-NOI32X2-NEXT: // %bb.0:
+; CHECK-NOI32X2-NEXT: ld.param.v2.b8 {%rs1, %rs2}, [test_zext_2xi8_to_2xi32_param_0];
+; CHECK-NOI32X2-NEXT: mov.b32 %r1, {%rs1, %rs2};
+; CHECK-NOI32X2-NEXT: cvt.u32.u16 %r2, %rs2;
+; CHECK-NOI32X2-NEXT: cvt.u32.u16 %r3, %rs1;
+; CHECK-NOI32X2-NEXT: st.param.v2.b32 [func_retval0], {%r3, %r2};
+; CHECK-NOI32X2-NEXT: ret;
+;
+; CHECK-I32X2-LABEL: test_zext_2xi8_to_2xi32(
+; CHECK-I32X2: {
+; CHECK-I32X2-NEXT: .reg .b16 %rs<3>;
+; CHECK-I32X2-NEXT: .reg .b32 %r<4>;
+; CHECK-I32X2-EMPTY:
+; CHECK-I32X2-NEXT: // %bb.0:
+; CHECK-I32X2-NEXT: ld.param::func.v2.b8 {%rs1, %rs2}, [test_zext_2xi8_to_2xi32_param_0];
+; CHECK-I32X2-NEXT: mov.b32 %r1, {%rs1, %rs2};
+; CHECK-I32X2-NEXT: cvt.u32.u16 %r2, %rs2;
+; CHECK-I32X2-NEXT: cvt.u32.u16 %r3, %rs1;
+; CHECK-I32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r3, %r2};
+; CHECK-I32X2-NEXT: ret;
%r = zext <2 x i8> %a to <2 x i32>
ret <2 x i32> %r
}
define <2 x i32> @test_zext_2xi1_to_2xi32(<2 x i1> %a) #0 {
-; CHECK-LABEL: test_zext_2xi1_to_2xi32(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<3>;
-; CHECK-NEXT: .reg .b16 %rs<5>;
-; CHECK-NEXT: .reg .b32 %r<5>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [test_zext_2xi1_to_2xi32_param_0+1];
-; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
-; CHECK-NEXT: setp.ne.b16 %p2, %rs2, 0;
-; CHECK-NEXT: ld.param.b8 %rs3, [test_zext_2xi1_to_2xi32_param_0];
-; CHECK-NEXT: and.b16 %rs4, %rs3, 1;
-; CHECK-NEXT: setp.ne.b16 %p1, %rs4, 0;
-; CHECK-NEXT: cvt.u32.u16 %r1, %rs1;
-; CHECK-NEXT: and.b32 %r2, %r1, 1;
-; CHECK-NEXT: cvt.u32.u16 %r3, %rs3;
-; CHECK-NEXT: and.b32 %r4, %r3, 1;
-; CHECK-NEXT: st.param.v2.b32 [func_retval0], {%r4, %r2};
-; CHECK-NEXT: ret;
+; CHECK-NOI32X2-LABEL: test_zext_2xi1_to_2xi32(
+; CHECK-NOI32X2: {
+; CHECK-NOI32X2-NEXT: .reg .pred %p<3>;
+; CHECK-NOI32X2-NEXT: .reg .b16 %rs<5>;
+; CHECK-NOI32X2-NEXT: .reg .b32 %r<5>;
+; CHECK-NOI32X2-EMPTY:
+; CHECK-NOI32X2-NEXT: // %bb.0:
+; CHECK-NOI32X2-NEXT: ld.param.b8 %rs1, [test_zext_2xi1_to_2xi32_param_0+1];
+; CHECK-NOI32X2-NEXT: and.b16 %rs2, %rs1, 1;
+; CHECK-NOI32X2-NEXT: setp.ne.b16 %p2, %rs2, 0;
+; CHECK-NOI32X2-NEXT: ld.param.b8 %rs3, [test_zext_2xi1_to_2xi32_param_0];
+; CHECK-NOI32X2-NEXT: and.b16 %rs4, %rs3, 1;
+; CHECK-NOI32X2-NEXT: setp.ne.b16 %p1, %rs4, 0;
+; CHECK-NOI32X2-NEXT: cvt.u32.u16 %r1, %rs1;
+; CHECK-NOI32X2-NEXT: and.b32 %r2, %r1, 1;
+; CHECK-NOI32X2-NEXT: cvt.u32.u16 %r3, %rs3;
+; CHECK-NOI32X2-NEXT: and.b32 %r4, %r3, 1;
+; CHECK-NOI32X2-NEXT: st.param.v2.b32 [func_retval0], {%r4, %r2};
+; CHECK-NOI32X2-NEXT: ret;
+;
+; CHECK-I32X2-LABEL: test_zext_2xi1_to_2xi32(
+; CHECK-I32X2: {
+; CHECK-I32X2-NEXT: .reg .pred %p<3>;
+; CHECK-I32X2-NEXT: .reg .b16 %rs<5>;
+; CHECK-I32X2-NEXT: .reg .b32 %r<5>;
+; CHECK-I32X2-EMPTY:
+; CHECK-I32X2-NEXT: // %bb.0:
+; CHECK-I32X2-NEXT: ld.param::func.b8 %rs1, [test_zext_2xi1_to_2xi32_param_0+1];
+; CHECK-I32X2-NEXT: and.b16 %rs2, %rs1, 1;
+; CHECK-I32X2-NEXT: setp.ne.b16 %p2, %rs2, 0;
+; CHECK-I32X2-NEXT: ld.param::func.b8 %rs3, [test_zext_2xi1_to_2xi32_param_0];
+; CHECK-I32X2-NEXT: and.b16 %rs4, %rs3, 1;
+; CHECK-I32X2-NEXT: setp.ne.b16 %p1, %rs4, 0;
+; CHECK-I32X2-NEXT: cvt.u32.u16 %r1, %rs1;
+; CHECK-I32X2-NEXT: and.b32 %r2, %r1, 1;
+; CHECK-I32X2-NEXT: cvt.u32.u16 %r3, %rs3;
+; CHECK-I32X2-NEXT: and.b32 %r4, %r3, 1;
+; CHECK-I32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r4, %r2};
+; CHECK-I32X2-NEXT: ret;
%r = zext <2 x i1> %a to <2 x i32>
ret <2 x i32> %r
}
@@ -1315,38 +1421,56 @@ define <2 x i64> @test_zext_2xi64(<2 x i32> %a) #0 {
; CHECK-I32X2-NEXT: .reg .b64 %rd<4>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param.b64 %rd1, [test_zext_2xi64_param_0];
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_zext_2xi64_param_0];
; CHECK-I32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
; CHECK-I32X2-NEXT: cvt.u64.u32 %rd2, %r2;
; CHECK-I32X2-NEXT: cvt.u64.u32 %rd3, %r1;
-; CHECK-I32X2-NEXT: st.param.v2.b64 [func_retval0], {%rd3, %rd2};
+; CHECK-I32X2-NEXT: st.param::func.v2.b64 [func_retval0], {%rd3, %rd2};
; CHECK-I32X2-NEXT: ret;
%r = zext <2 x i32> %a to <2 x i64>
ret <2 x i64> %r
}
define <2 x i32> @test_bitcast_i64_to_2xi32(i64 %a) #0 {
-; CHECK-LABEL: test_bitcast_i64_to_2xi32(
-; CHECK: {
-; CHECK-NEXT: .reg .b64 %rd<2>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [test_bitcast_i64_to_2xi32_param_0];
-; CHECK-NEXT: st.param.b64 [func_retval0], %rd1;
-; CHECK-NEXT: ret;
+; CHECK-NOI32X2-LABEL: test_bitcast_i64_to_2xi32(
+; CHECK-NOI32X2: {
+; CHECK-NOI32X2-NEXT: .reg .b64 %rd<2>;
+; CHECK-NOI32X2-EMPTY:
+; CHECK-NOI32X2-NEXT: // %bb.0:
+; CHECK-NOI32X2-NEXT: ld.param.b64 %rd1, [test_bitcast_i64_to_2xi32_param_0];
+; CHECK-NOI32X2-NEXT: st.param.b64 [func_retval0], %rd1;
+; CHECK-NOI32X2-NEXT: ret;
+;
+; CHECK-I32X2-LABEL: test_bitcast_i64_to_2xi32(
+; CHECK-I32X2: {
+; CHECK-I32X2-NEXT: .reg .b64 %rd<2>;
+; CHECK-I32X2-EMPTY:
+; CHECK-I32X2-NEXT: // %bb.0:
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_bitcast_i64_to_2xi32_param_0];
+; CHECK-I32X2-NEXT: st.param::func.b64 [func_retval0], %rd1;
+; CHECK-I32X2-NEXT: ret;
%r = bitcast i64 %a to <2 x i32>
ret <2 x i32> %r
}
define <2 x i32> @test_bitcast_double_to_2xi32(double %a) #0 {
-; CHECK-LABEL: test_bitcast_double_to_2xi32(
-; CHECK: {
-; CHECK-NEXT: .reg .b64 %rd<2>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [test_bitcast_double_to_2xi32_param_0];
-; CHECK-NEXT: st.param.b64 [func_retval0], %rd1;
-; CHECK-NEXT: ret;
+; CHECK-NOI32X2-LABEL: test_bitcast_double_to_2xi32(
+; CHECK-NOI32X2: {
+; CHECK-NOI32X2-NEXT: .reg .b64 %rd<2>;
+; CHECK-NOI32X2-EMPTY:
+; CHECK-NOI32X2-NEXT: // %bb.0:
+; CHECK-NOI32X2-NEXT: ld.param.b64 %rd1, [test_bitcast_double_to_2xi32_param_0];
+; CHECK-NOI32X2-NEXT: st.param.b64 [func_retval0], %rd1;
+; CHECK-NOI32X2-NEXT: ret;
+;
+; CHECK-I32X2-LABEL: test_bitcast_double_to_2xi32(
+; CHECK-I32X2: {
+; CHECK-I32X2-NEXT: .reg .b64 %rd<2>;
+; CHECK-I32X2-EMPTY:
+; CHECK-I32X2-NEXT: // %bb.0:
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_bitcast_double_to_2xi32_param_0];
+; CHECK-I32X2-NEXT: st.param::func.b64 [func_retval0], %rd1;
+; CHECK-I32X2-NEXT: ret;
%r = bitcast double %a to <2 x i32>
ret <2 x i32> %r
}
@@ -1366,8 +1490,8 @@ define i64 @test_bitcast_2xi32_to_i64(<2 x i32> %a) #0 {
; CHECK-I32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param.b64 %rd1, [test_bitcast_2xi32_to_i64_param_0];
-; CHECK-I32X2-NEXT: st.param.b64 [func_retval0], %rd1;
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_bitcast_2xi32_to_i64_param_0];
+; CHECK-I32X2-NEXT: st.param::func.b64 [func_retval0], %rd1;
; CHECK-I32X2-NEXT: ret;
%r = bitcast <2 x i32> %a to i64
ret i64 %r
@@ -1388,8 +1512,8 @@ define double @test_bitcast_2xi32_to_double(<2 x i32> %a) #0 {
; CHECK-I32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param.b64 %rd1, [test_bitcast_2xi32_to_double_param_0];
-; CHECK-I32X2-NEXT: st.param.b64 [func_retval0], %rd1;
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_bitcast_2xi32_to_double_param_0];
+; CHECK-I32X2-NEXT: st.param::func.b64 [func_retval0], %rd1;
; CHECK-I32X2-NEXT: ret;
%r = bitcast <2 x i32> %a to double
ret double %r
@@ -1397,14 +1521,23 @@ define double @test_bitcast_2xi32_to_double(<2 x i32> %a) #0 {
define <4 x half> @test_bitcast_2xi32_to_4xhalf(i32 %a) #0 {
-; CHECK-LABEL: test_bitcast_2xi32_to_4xhalf(
-; CHECK: {
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [test_bitcast_2xi32_to_4xhalf_param_0];
-; CHECK-NEXT: st.param.v2.b32 [func_retval0], {%r1, 5};
-; CHECK-NEXT: ret;
+; CHECK-NOI32X2-LABEL: test_bitcast_2xi32_to_4xhalf(
+; CHECK-NOI32X2: {
+; CHECK-NOI32X2-NEXT: .reg .b32 %r<2>;
+; CHECK-NOI32X2-EMPTY:
+; CHECK-NOI32X2-NEXT: // %bb.0:
+; CHECK-NOI32X2-NEXT: ld.param.b32 %r1, [test_bitcast_2xi32_to_4xhalf_param_0];
+; CHECK-NOI32X2-NEXT: st.param.v2.b32 [func_retval0], {%r1, 5};
+; CHECK-NOI32X2-NEXT: ret;
+;
+; CHECK-I32X2-LABEL: test_bitcast_2xi32_to_4xhalf(
+; CHECK-I32X2: {
+; CHECK-I32X2-NEXT: .reg .b32 %r<2>;
+; CHECK-I32X2-EMPTY:
+; CHECK-I32X2-NEXT: // %bb.0:
+; CHECK-I32X2-NEXT: ld.param::func.b32 %r1, [test_bitcast_2xi32_to_4xhalf_param_0];
+; CHECK-I32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r1, 5};
+; CHECK-I32X2-NEXT: ret;
%ins.0 = insertelement <2 x i32> poison, i32 %a, i32 0
%ins.1 = insertelement <2 x i32> %ins.0, i32 5, i32 1
%r = bitcast <2 x i32> %ins.1 to <4 x half>
@@ -1428,9 +1561,9 @@ define <2 x i32> @test_shufflevector(<2 x i32> %a) #0 {
; CHECK-I32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param.b64 %rd1, [test_shufflevector_param_0];
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_shufflevector_param_0];
; CHECK-I32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
-; CHECK-I32X2-NEXT: st.param.v2.b32 [func_retval0], {%r2, %r1};
+; CHECK-I32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r2, %r1};
; CHECK-I32X2-NEXT: ret;
%s = shufflevector <2 x i32> %a, <2 x i32> poison, <2 x i32> <i32 1, i32 0>
ret <2 x i32> %s
@@ -1453,11 +1586,11 @@ define <2 x i32> @test_shufflevector_2(<2 x i32> %a, <2 x i32> %b) #0 {
; CHECK-I32X2-NEXT: .reg .b64 %rd<3>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param.b64 %rd2, [test_shufflevector_2_param_1];
-; CHECK-I32X2-NEXT: ld.param.b64 %rd1, [test_shufflevector_2_param_0];
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd2, [test_shufflevector_2_param_1];
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_shufflevector_2_param_0];
; CHECK-I32X2-NEXT: mov.b64 {_, %r1}, %rd2;
; CHECK-I32X2-NEXT: mov.b64 {_, %r2}, %rd1;
-; CHECK-I32X2-NEXT: st.param.v2.b32 [func_retval0], {%r2, %r1};
+; CHECK-I32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r2, %r1};
; CHECK-I32X2-NEXT: ret;
%s = shufflevector <2 x i32> %a, <2 x i32> %b, <2 x i32> <i32 1, i32 3>
ret <2 x i32> %s
@@ -1481,65 +1614,107 @@ define <2 x i32> @test_insertelement(<2 x i32> %a, i32 %x) #0 {
; CHECK-I32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param.b32 %r1, [test_insertelement_param_1];
-; CHECK-I32X2-NEXT: ld.param.b64 %rd1, [test_insertelement_param_0];
+; CHECK-I32X2-NEXT: ld.param::func.b32 %r1, [test_insertelement_param_1];
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_insertelement_param_0];
; CHECK-I32X2-NEXT: mov.b64 {%r2, _}, %rd1;
-; CHECK-I32X2-NEXT: st.param.v2.b32 [func_retval0], {%r2, %r1};
+; CHECK-I32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r2, %r1};
; CHECK-I32X2-NEXT: ret;
%i = insertelement <2 x i32> %a, i32 %x, i64 1
ret <2 x i32> %i
}
define <2 x i32> @test_fptosi_2xhalf_to_2xi32(<2 x half> %a) #0 {
-; CHECK-LABEL: test_fptosi_2xhalf_to_2xi32(
-; CHECK: {
-; CHECK-NEXT: .reg .b16 %rs<3>;
-; CHECK-NEXT: .reg .b32 %r<4>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [test_fptosi_2xhalf_to_2xi32_param_0];
-; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r1;
-; CHECK-NEXT: cvt.rzi.s32.f16 %r2, %rs2;
-; CHECK-NEXT: cvt.rzi.s32.f16 %r3, %rs1;
-; CHECK-NEXT: st.param.v2.b32 [func_retval0], {%r3, %r2};
-; CHECK-NEXT: ret;
+; CHECK-NOI32X2-LABEL: test_fptosi_2xhalf_to_2xi32(
+; CHECK-NOI32X2: {
+; CHECK-NOI32X2-NEXT: .reg .b16 %rs<3>;
+; CHECK-NOI32X2-NEXT: .reg .b32 %r<4>;
+; CHECK-NOI32X2-EMPTY:
+; CHECK-NOI32X2-NEXT: // %bb.0:
+; CHECK-NOI32X2-NEXT: ld.param.b32 %r1, [test_fptosi_2xhalf_to_2xi32_param_0];
+; CHECK-NOI32X2-NEXT: mov.b32 {%rs1, %rs2}, %r1;
+; CHECK-NOI32X2-NEXT: cvt.rzi.s32.f16 %r2, %rs2;
+; CHECK-NOI32X2-NEXT: cvt.rzi.s32.f16 %r3, %rs1;
+; CHECK-NOI32X2-NEXT: st.param.v2.b32 [func_retval0], {%r3, %r2};
+; CHECK-NOI32X2-NEXT: ret;
+;
+; CHECK-I32X2-LABEL: test_fptosi_2xhalf_to_2xi32(
+; CHECK-I32X2: {
+; CHECK-I32X2-NEXT: .reg .b16 %rs<3>;
+; CHECK-I32X2-NEXT: .reg .b32 %r<4>;
+; CHECK-I32X2-EMPTY:
+; CHECK-I32X2-NEXT: // %bb.0:
+; CHECK-I32X2-NEXT: ld.param::func.b32 %r1, [test_fptosi_2xhalf_to_2xi32_param_0];
+; CHECK-I32X2-NEXT: mov.b32 {%rs1, %rs2}, %r1;
+; CHECK-I32X2-NEXT: cvt.rzi.s32.f16 %r2, %rs2;
+; CHECK-I32X2-NEXT: cvt.rzi.s32.f16 %r3, %rs1;
+; CHECK-I32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r3, %r2};
+; CHECK-I32X2-NEXT: ret;
%r = fptosi <2 x half> %a to <2 x i32>
ret <2 x i32> %r
}
define <2 x i32> @test_fptoui_2xhalf_to_2xi32(<2 x half> %a) #0 {
-; CHECK-LABEL: test_fptoui_2xhalf_to_2xi32(
-; CHECK: {
-; CHECK-NEXT: .reg .b16 %rs<3>;
-; CHECK-NEXT: .reg .b32 %r<4>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [test_fptoui_2xhalf_to_2xi32_param_0];
-; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r1;
-; CHECK-NEXT: cvt.rzi.u32.f16 %r2, %rs2;
-; CHECK-NEXT: cvt.rzi.u32.f16 %r3, %rs1;
-; CHECK-NEXT: st.param.v2.b32 [func_retval0], {%r3, %r2};
-; CHECK-NEXT: ret;
+; CHECK-NOI32X2-LABEL: test_fptoui_2xhalf_to_2xi32(
+; CHECK-NOI32X2: {
+; CHECK-NOI32X2-NEXT: .reg .b16 %rs<3>;
+; CHECK-NOI32X2-NEXT: .reg .b32 %r<4>;
+; CHECK-NOI32X2-EMPTY:
+; CHECK-NOI32X2-NEXT: // %bb.0:
+; CHECK-NOI32X2-NEXT: ld.param.b32 %r1, [test_fptoui_2xhalf_to_2xi32_param_0];
+; CHECK-NOI32X2-NEXT: mov.b32 {%rs1, %rs2}, %r1;
+; CHECK-NOI32X2-NEXT: cvt.rzi.u32.f16 %r2, %rs2;
+; CHECK-NOI32X2-NEXT: cvt.rzi.u32.f16 %r3, %rs1;
+; CHECK-NOI32X2-NEXT: st.param.v2.b32 [func_retval0], {%r3, %r2};
+; CHECK-NOI32X2-NEXT: ret;
+;
+; CHECK-I32X2-LABEL: test_fptoui_2xhalf_to_2xi32(
+; CHECK-I32X2: {
+; CHECK-I32X2-NEXT: .reg .b16 %rs<3>;
+; CHECK-I32X2-NEXT: .reg .b32 %r<4>;
+; CHECK-I32X2-EMPTY:
+; CHECK-I32X2-NEXT: // %bb.0:
+; CHECK-I32X2-NEXT: ld.param::func.b32 %r1, [test_fptoui_2xhalf_to_2xi32_param_0];
+; CHECK-I32X2-NEXT: mov.b32 {%rs1, %rs2}, %r1;
+; CHECK-I32X2-NEXT: cvt.rzi.u32.f16 %r2, %rs2;
+; CHECK-I32X2-NEXT: cvt.rzi.u32.f16 %r3, %rs1;
+; CHECK-I32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r3, %r2};
+; CHECK-I32X2-NEXT: ret;
%r = fptoui <2 x half> %a to <2 x i32>
ret <2 x i32> %r
}
define void @test_srem_v2i32(ptr %a, ptr %b, ptr %c) {
-; CHECK-LABEL: test_srem_v2i32(
-; CHECK: {
-; CHECK-NEXT: .reg .b32 %r<7>;
-; CHECK-NEXT: .reg .b64 %rd<4>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b64 %rd3, [test_srem_v2i32_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [test_srem_v2i32_param_1];
-; CHECK-NEXT: ld.param.b64 %rd1, [test_srem_v2i32_param_0];
-; CHECK-NEXT: ld.v2.b32 {%r1, %r2}, [%rd1];
-; CHECK-NEXT: ld.v2.b32 {%r3, %r4}, [%rd2];
-; CHECK-NEXT: rem.s32 %r5, %r2, %r4;
-; CHECK-NEXT: rem.s32 %r6, %r1, %r3;
-; CHECK-NEXT: st.v2.b32 [%rd3], {%r6, %r5};
-; CHECK-NEXT: ret;
+; CHECK-NOI32X2-LABEL: test_srem_v2i32(
+; CHECK-NOI32X2: {
+; CHECK-NOI32X2-NEXT: .reg .b32 %r<7>;
+; CHECK-NOI32X2-NEXT: .reg .b64 %rd<4>;
+; CHECK-NOI32X2-EMPTY:
+; CHECK-NOI32X2-NEXT: // %bb.0: // %entry
+; CHECK-NOI32X2-NEXT: ld.param.b64 %rd3, [test_srem_v2i32_param_2];
+; CHECK-NOI32X2-NEXT: ld.param.b64 %rd2, [test_srem_v2i32_param_1];
+; CHECK-NOI32X2-NEXT: ld.param.b64 %rd1, [test_srem_v2i32_param_0];
+; CHECK-NOI32X2-NEXT: ld.v2.b32 {%r1, %r2}, [%rd1];
+; CHECK-NOI32X2-NEXT: ld.v2.b32 {%r3, %r4}, [%rd2];
+; CHECK-NOI32X2-NEXT: rem.s32 %r5, %r2, %r4;
+; CHECK-NOI32X2-NEXT: rem.s32 %r6, %r1, %r3;
+; CHECK-NOI32X2-NEXT: st.v2.b32 [%rd3], {%r6, %r5};
+; CHECK-NOI32X2-NEXT: ret;
+;
+; CHECK-I32X2-LABEL: test_srem_v2i32(
+; CHECK-I32X2: {
+; CHECK-I32X2-NEXT: .reg .b32 %r<7>;
+; CHECK-I32X2-NEXT: .reg .b64 %rd<4>;
+; CHECK-I32X2-EMPTY:
+; CHECK-I32X2-NEXT: // %bb.0: // %entry
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd3, [test_srem_v2i32_param_2];
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd2, [test_srem_v2i32_param_1];
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_srem_v2i32_param_0];
+; CHECK-I32X2-NEXT: ld.v2.b32 {%r1, %r2}, [%rd1];
+; CHECK-I32X2-NEXT: ld.v2.b32 {%r3, %r4}, [%rd2];
+; CHECK-I32X2-NEXT: rem.s32 %r5, %r2, %r4;
+; CHECK-I32X2-NEXT: rem.s32 %r6, %r1, %r3;
+; CHECK-I32X2-NEXT: st.v2.b32 [%rd3], {%r6, %r5};
+; CHECK-I32X2-NEXT: ret;
entry:
%t57 = load <2 x i32>, ptr %a, align 8
%t59 = load <2 x i32>, ptr %b, align 8
@@ -1583,9 +1758,9 @@ define void @test_srem_v3i32(ptr %a, ptr %b, ptr %c) {
; CHECK-I32X2-NEXT: .reg .b64 %rd<4>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0: // %entry
-; CHECK-I32X2-NEXT: ld.param.b64 %rd3, [test_srem_v3i32_param_2];
-; CHECK-I32X2-NEXT: ld.param.b64 %rd2, [test_srem_v3i32_param_1];
-; CHECK-I32X2-NEXT: ld.param.b64 %rd1, [test_srem_v3i32_param_0];
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd3, [test_srem_v3i32_param_2];
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd2, [test_srem_v3i32_param_1];
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_srem_v3i32_param_0];
; CHECK-I32X2-NEXT: ld.v2.b32 {%r1, %r2}, [%rd1];
; CHECK-I32X2-NEXT: ld.b32 %r3, [%rd1+8];
; CHECK-I32X2-NEXT: ld.v2.b32 {%r4, %r5}, [%rd2];
@@ -1634,9 +1809,9 @@ define void @test_sext_v2i1_to_v2i32(ptr %a, ptr %b, ptr %c) {
; CHECK-I32X2-NEXT: .reg .b64 %rd<13>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0: // %entry
-; CHECK-I32X2-NEXT: ld.param.b64 %rd3, [test_sext_v2i1_to_v2i32_param_2];
-; CHECK-I32X2-NEXT: ld.param.b64 %rd2, [test_sext_v2i1_to_v2i32_param_1];
-; CHECK-I32X2-NEXT: ld.param.b64 %rd1, [test_sext_v2i1_to_v2i32_param_0];
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd3, [test_sext_v2i1_to_v2i32_param_2];
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd2, [test_sext_v2i1_to_v2i32_param_1];
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_sext_v2i1_to_v2i32_param_0];
; CHECK-I32X2-NEXT: ld.b32 %rd4, [%rd1];
; CHECK-I32X2-NEXT: ld.b32 %rd5, [%rd1+4];
; CHECK-I32X2-NEXT: shl.b64 %rd6, %rd5, 32;
@@ -1665,20 +1840,35 @@ entry:
}
define <2 x i32> @test_sext_v2i8_to_v2i32 (<2 x i8> %a) {
-; CHECK-LABEL: test_sext_v2i8_to_v2i32(
-; CHECK: {
-; CHECK-NEXT: .reg .b16 %rs<3>;
-; CHECK-NEXT: .reg .b32 %r<6>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.v2.b8 {%rs1, %rs2}, [test_sext_v2i8_to_v2i32_param_0];
-; CHECK-NEXT: mov.b32 %r1, {%rs1, %rs2};
-; CHECK-NEXT: cvt.u32.u16 %r2, %rs2;
-; CHECK-NEXT: cvt.s32.s8 %r3, %r2;
-; CHECK-NEXT: cvt.u32.u16 %r4, %rs1;
-; CHECK-NEXT: cvt.s32.s8 %r5, %r4;
-; CHECK-NEXT: st.param.v2.b32 [func_retval0], {%r5, %r3};
-; CHECK-NEXT: ret;
+; CHECK-NOI32X2-LABEL: test_sext_v2i8_to_v2i32(
+; CHECK-NOI32X2: {
+; CHECK-NOI32X2-NEXT: .reg .b16 %rs<3>;
+; CHECK-NOI32X2-NEXT: .reg .b32 %r<6>;
+; CHECK-NOI32X2-EMPTY:
+; CHECK-NOI32X2-NEXT: // %bb.0:
+; CHECK-NOI32X2-NEXT: ld.param.v2.b8 {%rs1, %rs2}, [test_sext_v2i8_to_v2i32_param_0];
+; CHECK-NOI32X2-NEXT: mov.b32 %r1, {%rs1, %rs2};
+; CHECK-NOI32X2-NEXT: cvt.u32.u16 %r2, %rs2;
+; CHECK-NOI32X2-NEXT: cvt.s32.s8 %r3, %r2;
+; CHECK-NOI32X2-NEXT: cvt.u32.u16 %r4, %rs1;
+; CHECK-NOI32X2-NEXT: cvt.s32.s8 %r5, %r4;
+; CHECK-NOI32X2-NEXT: st.param.v2.b32 [func_retval0], {%r5, %r3};
+; CHECK-NOI32X2-NEXT: ret;
+;
+; CHECK-I32X2-LABEL: test_sext_v2i8_to_v2i32(
+; CHECK-I32X2: {
+; CHECK-I32X2-NEXT: .reg .b16 %rs<3>;
+; CHECK-I32X2-NEXT: .reg .b32 %r<6>;
+; CHECK-I32X2-EMPTY:
+; CHECK-I32X2-NEXT: // %bb.0:
+; CHECK-I32X2-NEXT: ld.param::func.v2.b8 {%rs1, %rs2}, [test_sext_v2i8_to_v2i32_param_0];
+; CHECK-I32X2-NEXT: mov.b32 %r1, {%rs1, %rs2};
+; CHECK-I32X2-NEXT: cvt.u32.u16 %r2, %rs2;
+; CHECK-I32X2-NEXT: cvt.s32.s8 %r3, %r2;
+; CHECK-I32X2-NEXT: cvt.u32.u16 %r4, %rs1;
+; CHECK-I32X2-NEXT: cvt.s32.s8 %r5, %r4;
+; CHECK-I32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r5, %r3};
+; CHECK-I32X2-NEXT: ret;
%r = sext <2 x i8> %a to <2 x i32>
ret <2 x i32> %r
}
@@ -1703,11 +1893,11 @@ define <2 x i32> @test_sext_v2i16_to_v2i32 (<2 x i16> %a) {
; CHECK-I32X2-NEXT: .reg .b32 %r<4>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param.b32 %r1, [test_sext_v2i16_to_v2i32_param_0];
+; CHECK-I32X2-NEXT: ld.param::func.b32 %r1, [test_sext_v2i16_to_v2i32_param_0];
; CHECK-I32X2-NEXT: cvt.s32.s16 %r2, %r1;
; CHECK-I32X2-NEXT: mov.b32 {_, %rs1}, %r1;
; CHECK-I32X2-NEXT: cvt.s32.s16 %r3, %rs1;
-; CHECK-I32X2-NEXT: st.param.v2.b32 [func_retval0], {%r2, %r3};
+; CHECK-I32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r2, %r3};
; CHECK-I32X2-NEXT: ret;
%r = sext <2 x i16> %a to <2 x i32>
ret <2 x i32> %r
@@ -1731,11 +1921,11 @@ define <2 x float> @test_uitofp_v2i32(<2 x i32> %a) {
; CHECK-I32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param.b64 %rd1, [test_uitofp_v2i32_param_0];
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_uitofp_v2i32_param_0];
; CHECK-I32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
; CHECK-I32X2-NEXT: cvt.rn.f32.u32 %r3, %r2;
; CHECK-I32X2-NEXT: cvt.rn.f32.u32 %r4, %r1;
-; CHECK-I32X2-NEXT: st.param.v2.b32 [func_retval0], {%r4, %r3};
+; CHECK-I32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r4, %r3};
; CHECK-I32X2-NEXT: ret;
%r = uitofp <2 x i32> %a to <2 x float>
ret <2 x float> %r
@@ -1759,14 +1949,16 @@ define <2 x float> @test_sitofp_v2i32(<2 x i32> %a) {
; CHECK-I32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param.b64 %rd1, [test_sitofp_v2i32_param_0];
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_sitofp_v2i32_param_0];
; CHECK-I32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
; CHECK-I32X2-NEXT: cvt.rn.f32.s32 %r3, %r2;
; CHECK-I32X2-NEXT: cvt.rn.f32.s32 %r4, %r1;
-; CHECK-I32X2-NEXT: st.param.v2.b32 [func_retval0], {%r4, %r3};
+; CHECK-I32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r4, %r3};
; CHECK-I32X2-NEXT: ret;
%r = sitofp <2 x i32> %a to <2 x float>
ret <2 x float> %r
}
attributes #0 = { nounwind }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK: {{.*}}
diff --git a/llvm/test/CodeGen/NVPTX/ldg-invariant-256.ll b/llvm/test/CodeGen/NVPTX/ldg-invariant-256.ll
index d219493d2b31b..ad36120403bd7 100644
--- a/llvm/test/CodeGen/NVPTX/ldg-invariant-256.ll
+++ b/llvm/test/CodeGen/NVPTX/ldg-invariant-256.ll
@@ -15,7 +15,7 @@ define i8 @ld_global_v32i8(ptr addrspace(1) %ptr) {
; SM90-NEXT: .reg .b64 %rd<2>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [ld_global_v32i8_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd1, [ld_global_v32i8_param_0];
; SM90-NEXT: ld.global.nc.v4.b32 {%r1, %r2, %r3, %r4}, [%rd1+16];
; SM90-NEXT: prmt.b32 %r5, %r4, 0, 0x7770U;
; SM90-NEXT: cvt.u16.u32 %rs1, %r5;
@@ -42,7 +42,7 @@ define i8 @ld_global_v32i8(ptr addrspace(1) %ptr) {
; SM90-NEXT: add.s16 %rs14, %rs11, %rs12;
; SM90-NEXT: add.s16 %rs15, %rs13, %rs14;
; SM90-NEXT: cvt.u32.u16 %r17, %rs15;
-; SM90-NEXT: st.param.b32 [func_retval0], %r17;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r17;
; SM90-NEXT: ret;
;
; SM100-LABEL: ld_global_v32i8(
@@ -52,7 +52,7 @@ define i8 @ld_global_v32i8(ptr addrspace(1) %ptr) {
; SM100-NEXT: .reg .b64 %rd<2>;
; SM100-EMPTY:
; SM100-NEXT: // %bb.0:
-; SM100-NEXT: ld.param.b64 %rd1, [ld_global_v32i8_param_0];
+; SM100-NEXT: ld.param::func.b64 %rd1, [ld_global_v32i8_param_0];
; SM100-NEXT: ld.global.nc.v8.b32 {%r1, %r2, %r3, %r4, %r5, %r6, %r7, %r8}, [%rd1];
; SM100-NEXT: prmt.b32 %r9, %r8, 0, 0x7770U;
; SM100-NEXT: cvt.u16.u32 %rs1, %r9;
@@ -78,7 +78,7 @@ define i8 @ld_global_v32i8(ptr addrspace(1) %ptr) {
; SM100-NEXT: add.s16 %rs14, %rs11, %rs12;
; SM100-NEXT: add.s16 %rs15, %rs13, %rs14;
; SM100-NEXT: cvt.u32.u16 %r17, %rs15;
-; SM100-NEXT: st.param.b32 [func_retval0], %r17;
+; SM100-NEXT: st.param::func.b32 [func_retval0], %r17;
; SM100-NEXT: ret;
%a = load <32 x i8>, ptr addrspace(1) %ptr, !invariant.load !0
%v1 = extractelement <32 x i8> %a, i32 0
@@ -107,7 +107,7 @@ define i16 @ld_global_v16i16(ptr addrspace(1) %ptr) {
; SM90-NEXT: .reg .b64 %rd<2>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [ld_global_v16i16_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd1, [ld_global_v16i16_param_0];
; SM90-NEXT: ld.global.nc.v4.b32 {%r1, %r2, %r3, %r4}, [%rd1+16];
; SM90-NEXT: mov.b32 {%rs1, _}, %r4;
; SM90-NEXT: mov.b32 {%rs2, _}, %r3;
@@ -126,7 +126,7 @@ define i16 @ld_global_v16i16(ptr addrspace(1) %ptr) {
; SM90-NEXT: add.s16 %rs14, %rs11, %rs12;
; SM90-NEXT: add.s16 %rs15, %rs13, %rs14;
; SM90-NEXT: cvt.u32.u16 %r9, %rs15;
-; SM90-NEXT: st.param.b32 [func_retval0], %r9;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r9;
; SM90-NEXT: ret;
;
; SM100-LABEL: ld_global_v16i16(
@@ -136,7 +136,7 @@ define i16 @ld_global_v16i16(ptr addrspace(1) %ptr) {
; SM100-NEXT: .reg .b64 %rd<2>;
; SM100-EMPTY:
; SM100-NEXT: // %bb.0:
-; SM100-NEXT: ld.param.b64 %rd1, [ld_global_v16i16_param_0];
+; SM100-NEXT: ld.param::func.b64 %rd1, [ld_global_v16i16_param_0];
; SM100-NEXT: ld.global.nc.v8.b32 {%r1, %r2, %r3, %r4, %r5, %r6, %r7, %r8}, [%rd1];
; SM100-NEXT: mov.b32 {%rs1, _}, %r8;
; SM100-NEXT: mov.b32 {%rs2, _}, %r7;
@@ -154,7 +154,7 @@ define i16 @ld_global_v16i16(ptr addrspace(1) %ptr) {
; SM100-NEXT: add.s16 %rs14, %rs11, %rs12;
; SM100-NEXT: add.s16 %rs15, %rs13, %rs14;
; SM100-NEXT: cvt.u32.u16 %r9, %rs15;
-; SM100-NEXT: st.param.b32 [func_retval0], %r9;
+; SM100-NEXT: st.param::func.b32 [func_retval0], %r9;
; SM100-NEXT: ret;
%a = load <16 x i16>, ptr addrspace(1) %ptr, !invariant.load !0
%v1 = extractelement <16 x i16> %a, i32 0
@@ -183,7 +183,7 @@ define half @ld_global_v16f16(ptr addrspace(1) %ptr) {
; SM90-NEXT: .reg .b64 %rd<2>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [ld_global_v16f16_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd1, [ld_global_v16f16_param_0];
; SM90-NEXT: ld.global.nc.v4.b32 {%r1, %r2, %r3, %r4}, [%rd1+16];
; SM90-NEXT: mov.b32 {%rs1, _}, %r4;
; SM90-NEXT: mov.b32 {%rs2, _}, %r3;
@@ -201,7 +201,7 @@ define half @ld_global_v16f16(ptr addrspace(1) %ptr) {
; SM90-NEXT: add.rn.f16 %rs13, %rs9, %rs10;
; SM90-NEXT: add.rn.f16 %rs14, %rs11, %rs12;
; SM90-NEXT: add.rn.f16 %rs15, %rs13, %rs14;
-; SM90-NEXT: st.param.b16 [func_retval0], %rs15;
+; SM90-NEXT: st.param::func.b16 [func_retval0], %rs15;
; SM90-NEXT: ret;
;
; SM100-LABEL: ld_global_v16f16(
@@ -211,7 +211,7 @@ define half @ld_global_v16f16(ptr addrspace(1) %ptr) {
; SM100-NEXT: .reg .b64 %rd<2>;
; SM100-EMPTY:
; SM100-NEXT: // %bb.0:
-; SM100-NEXT: ld.param.b64 %rd1, [ld_global_v16f16_param_0];
+; SM100-NEXT: ld.param::func.b64 %rd1, [ld_global_v16f16_param_0];
; SM100-NEXT: ld.global.nc.v8.b32 {%r1, %r2, %r3, %r4, %r5, %r6, %r7, %r8}, [%rd1];
; SM100-NEXT: mov.b32 {%rs1, _}, %r8;
; SM100-NEXT: mov.b32 {%rs2, _}, %r7;
@@ -228,7 +228,7 @@ define half @ld_global_v16f16(ptr addrspace(1) %ptr) {
; SM100-NEXT: add.rn.f16 %rs13, %rs9, %rs10;
; SM100-NEXT: add.rn.f16 %rs14, %rs11, %rs12;
; SM100-NEXT: add.rn.f16 %rs15, %rs13, %rs14;
-; SM100-NEXT: st.param.b16 [func_retval0], %rs15;
+; SM100-NEXT: st.param::func.b16 [func_retval0], %rs15;
; SM100-NEXT: ret;
%a = load <16 x half>, ptr addrspace(1) %ptr, !invariant.load !0
%v1 = extractelement <16 x half> %a, i32 0
@@ -257,7 +257,7 @@ define bfloat @ld_global_v16bf16(ptr addrspace(1) %ptr) {
; SM90-NEXT: .reg .b64 %rd<2>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [ld_global_v16bf16_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd1, [ld_global_v16bf16_param_0];
; SM90-NEXT: ld.global.nc.v4.b32 {%r1, %r2, %r3, %r4}, [%rd1+16];
; SM90-NEXT: mov.b32 {%rs1, _}, %r4;
; SM90-NEXT: mov.b32 {%rs2, _}, %r3;
@@ -275,7 +275,7 @@ define bfloat @ld_global_v16bf16(ptr addrspace(1) %ptr) {
; SM90-NEXT: add.rn.bf16 %rs13, %rs9, %rs10;
; SM90-NEXT: add.rn.bf16 %rs14, %rs11, %rs12;
; SM90-NEXT: add.rn.bf16 %rs15, %rs13, %rs14;
-; SM90-NEXT: st.param.b16 [func_retval0], %rs15;
+; SM90-NEXT: st.param::func.b16 [func_retval0], %rs15;
; SM90-NEXT: ret;
;
; SM100-LABEL: ld_global_v16bf16(
@@ -285,7 +285,7 @@ define bfloat @ld_global_v16bf16(ptr addrspace(1) %ptr) {
; SM100-NEXT: .reg .b64 %rd<2>;
; SM100-EMPTY:
; SM100-NEXT: // %bb.0:
-; SM100-NEXT: ld.param.b64 %rd1, [ld_global_v16bf16_param_0];
+; SM100-NEXT: ld.param::func.b64 %rd1, [ld_global_v16bf16_param_0];
; SM100-NEXT: ld.global.nc.v8.b32 {%r1, %r2, %r3, %r4, %r5, %r6, %r7, %r8}, [%rd1];
; SM100-NEXT: mov.b32 {%rs1, _}, %r8;
; SM100-NEXT: mov.b32 {%rs2, _}, %r7;
@@ -302,7 +302,7 @@ define bfloat @ld_global_v16bf16(ptr addrspace(1) %ptr) {
; SM100-NEXT: add.rn.bf16 %rs13, %rs9, %rs10;
; SM100-NEXT: add.rn.bf16 %rs14, %rs11, %rs12;
; SM100-NEXT: add.rn.bf16 %rs15, %rs13, %rs14;
-; SM100-NEXT: st.param.b16 [func_retval0], %rs15;
+; SM100-NEXT: st.param::func.b16 [func_retval0], %rs15;
; SM100-NEXT: ret;
%a = load <16 x bfloat>, ptr addrspace(1) %ptr, !invariant.load !0
%v1 = extractelement <16 x bfloat> %a, i32 0
@@ -330,7 +330,7 @@ define i32 @ld_global_v8i32(ptr addrspace(1) %ptr) {
; SM90-NEXT: .reg .b64 %rd<2>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [ld_global_v8i32_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd1, [ld_global_v8i32_param_0];
; SM90-NEXT: ld.global.nc.v4.b32 {%r1, %r2, %r3, %r4}, [%rd1+16];
; SM90-NEXT: ld.global.nc.v4.b32 {%r5, %r6, %r7, %r8}, [%rd1];
; SM90-NEXT: add.s32 %r9, %r5, %r6;
@@ -340,7 +340,7 @@ define i32 @ld_global_v8i32(ptr addrspace(1) %ptr) {
; SM90-NEXT: add.s32 %r13, %r9, %r10;
; SM90-NEXT: add.s32 %r14, %r11, %r12;
; SM90-NEXT: add.s32 %r15, %r13, %r14;
-; SM90-NEXT: st.param.b32 [func_retval0], %r15;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r15;
; SM90-NEXT: ret;
;
; SM100-LABEL: ld_global_v8i32(
@@ -349,7 +349,7 @@ define i32 @ld_global_v8i32(ptr addrspace(1) %ptr) {
; SM100-NEXT: .reg .b64 %rd<2>;
; SM100-EMPTY:
; SM100-NEXT: // %bb.0:
-; SM100-NEXT: ld.param.b64 %rd1, [ld_global_v8i32_param_0];
+; SM100-NEXT: ld.param::func.b64 %rd1, [ld_global_v8i32_param_0];
; SM100-NEXT: ld.global.nc.v8.b32 {%r1, %r2, %r3, %r4, %r5, %r6, %r7, %r8}, [%rd1];
; SM100-NEXT: add.s32 %r9, %r1, %r2;
; SM100-NEXT: add.s32 %r10, %r3, %r4;
@@ -358,7 +358,7 @@ define i32 @ld_global_v8i32(ptr addrspace(1) %ptr) {
; SM100-NEXT: add.s32 %r13, %r9, %r10;
; SM100-NEXT: add.s32 %r14, %r11, %r12;
; SM100-NEXT: add.s32 %r15, %r13, %r14;
-; SM100-NEXT: st.param.b32 [func_retval0], %r15;
+; SM100-NEXT: st.param::func.b32 [func_retval0], %r15;
; SM100-NEXT: ret;
%a = load <8 x i32>, ptr addrspace(1) %ptr, !invariant.load !0
%v1 = extractelement <8 x i32> %a, i32 0
@@ -387,7 +387,7 @@ define float @ld_global_v8f32(ptr addrspace(1) %ptr) {
; SM90-NEXT: .reg .b64 %rd<2>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [ld_global_v8f32_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd1, [ld_global_v8f32_param_0];
; SM90-NEXT: ld.global.nc.v4.b32 {%r1, %r2, %r3, %r4}, [%rd1+16];
; SM90-NEXT: ld.global.nc.v4.b32 {%r5, %r6, %r7, %r8}, [%rd1];
; SM90-NEXT: add.rn.f32 %r9, %r5, %r6;
@@ -397,7 +397,7 @@ define float @ld_global_v8f32(ptr addrspace(1) %ptr) {
; SM90-NEXT: add.rn.f32 %r13, %r9, %r10;
; SM90-NEXT: add.rn.f32 %r14, %r11, %r12;
; SM90-NEXT: add.rn.f32 %r15, %r13, %r14;
-; SM90-NEXT: st.param.b32 [func_retval0], %r15;
+; SM90-NEXT: st.param::func.b32 [func_retval0], %r15;
; SM90-NEXT: ret;
;
; SM100-LABEL: ld_global_v8f32(
@@ -406,7 +406,7 @@ define float @ld_global_v8f32(ptr addrspace(1) %ptr) {
; SM100-NEXT: .reg .b64 %rd<2>;
; SM100-EMPTY:
; SM100-NEXT: // %bb.0:
-; SM100-NEXT: ld.param.b64 %rd1, [ld_global_v8f32_param_0];
+; SM100-NEXT: ld.param::func.b64 %rd1, [ld_global_v8f32_param_0];
; SM100-NEXT: ld.global.nc.v8.b32 {%r1, %r2, %r3, %r4, %r5, %r6, %r7, %r8}, [%rd1];
; SM100-NEXT: add.rn.f32 %r9, %r1, %r2;
; SM100-NEXT: add.rn.f32 %r10, %r3, %r4;
@@ -415,7 +415,7 @@ define float @ld_global_v8f32(ptr addrspace(1) %ptr) {
; SM100-NEXT: add.rn.f32 %r13, %r9, %r10;
; SM100-NEXT: add.rn.f32 %r14, %r11, %r12;
; SM100-NEXT: add.rn.f32 %r15, %r13, %r14;
-; SM100-NEXT: st.param.b32 [func_retval0], %r15;
+; SM100-NEXT: st.param::func.b32 [func_retval0], %r15;
; SM100-NEXT: ret;
%a = load <8 x float>, ptr addrspace(1) %ptr, !invariant.load !0
%v1 = extractelement <8 x float> %a, i32 0
@@ -443,13 +443,13 @@ define i64 @ld_global_v4i64(ptr addrspace(1) %ptr) {
; SM90-NEXT: .reg .b64 %rd<9>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [ld_global_v4i64_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd1, [ld_global_v4i64_param_0];
; SM90-NEXT: ld.global.nc.v2.b64 {%rd2, %rd3}, [%rd1+16];
; SM90-NEXT: ld.global.nc.v2.b64 {%rd4, %rd5}, [%rd1];
; SM90-NEXT: add.s64 %rd6, %rd4, %rd5;
; SM90-NEXT: add.s64 %rd7, %rd2, %rd3;
; SM90-NEXT: add.s64 %rd8, %rd6, %rd7;
-; SM90-NEXT: st.param.b64 [func_retval0], %rd8;
+; SM90-NEXT: st.param::func.b64 [func_retval0], %rd8;
; SM90-NEXT: ret;
;
; SM100-LABEL: ld_global_v4i64(
@@ -457,12 +457,12 @@ define i64 @ld_global_v4i64(ptr addrspace(1) %ptr) {
; SM100-NEXT: .reg .b64 %rd<9>;
; SM100-EMPTY:
; SM100-NEXT: // %bb.0:
-; SM100-NEXT: ld.param.b64 %rd1, [ld_global_v4i64_param_0];
+; SM100-NEXT: ld.param::func.b64 %rd1, [ld_global_v4i64_param_0];
; SM100-NEXT: ld.global.nc.v4.b64 {%rd2, %rd3, %rd4, %rd5}, [%rd1];
; SM100-NEXT: add.s64 %rd6, %rd2, %rd3;
; SM100-NEXT: add.s64 %rd7, %rd4, %rd5;
; SM100-NEXT: add.s64 %rd8, %rd6, %rd7;
-; SM100-NEXT: st.param.b64 [func_retval0], %rd8;
+; SM100-NEXT: st.param::func.b64 [func_retval0], %rd8;
; SM100-NEXT: ret;
%a = load <4 x i64>, ptr addrspace(1) %ptr, !invariant.load !0
%v1 = extractelement <4 x i64> %a, i32 0
@@ -481,13 +481,13 @@ define double @ld_global_v4f64(ptr addrspace(1) %ptr) {
; SM90-NEXT: .reg .b64 %rd<9>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [ld_global_v4f64_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd1, [ld_global_v4f64_param_0];
; SM90-NEXT: ld.global.nc.v2.b64 {%rd2, %rd3}, [%rd1+16];
; SM90-NEXT: ld.global.nc.v2.b64 {%rd4, %rd5}, [%rd1];
; SM90-NEXT: add.rn.f64 %rd6, %rd4, %rd5;
; SM90-NEXT: add.rn.f64 %rd7, %rd2, %rd3;
; SM90-NEXT: add.rn.f64 %rd8, %rd6, %rd7;
-; SM90-NEXT: st.param.b64 [func_retval0], %rd8;
+; SM90-NEXT: st.param::func.b64 [func_retval0], %rd8;
; SM90-NEXT: ret;
;
; SM100-LABEL: ld_global_v4f64(
@@ -495,12 +495,12 @@ define double @ld_global_v4f64(ptr addrspace(1) %ptr) {
; SM100-NEXT: .reg .b64 %rd<9>;
; SM100-EMPTY:
; SM100-NEXT: // %bb.0:
-; SM100-NEXT: ld.param.b64 %rd1, [ld_global_v4f64_param_0];
+; SM100-NEXT: ld.param::func.b64 %rd1, [ld_global_v4f64_param_0];
; SM100-NEXT: ld.global.nc.v4.b64 {%rd2, %rd3, %rd4, %rd5}, [%rd1];
; SM100-NEXT: add.rn.f64 %rd6, %rd2, %rd3;
; SM100-NEXT: add.rn.f64 %rd7, %rd4, %rd5;
; SM100-NEXT: add.rn.f64 %rd8, %rd6, %rd7;
-; SM100-NEXT: st.param.b64 [func_retval0], %rd8;
+; SM100-NEXT: st.param::func.b64 [func_retval0], %rd8;
; SM100-NEXT: ret;
%a = load <4 x double>, ptr addrspace(1) %ptr, !invariant.load !0
%v1 = extractelement <4 x double> %a, i32 0
diff --git a/llvm/test/CodeGen/NVPTX/load-store-256-addressing-invariant.ll b/llvm/test/CodeGen/NVPTX/load-store-256-addressing-invariant.ll
index 57852451c0c72..0c161c5a793f3 100644
--- a/llvm/test/CodeGen/NVPTX/load-store-256-addressing-invariant.ll
+++ b/llvm/test/CodeGen/NVPTX/load-store-256-addressing-invariant.ll
@@ -270,9 +270,9 @@ define void @areg_64_i8(ptr addrspace(1) %in, ptr addrspace(1) %out) {
; PTX-NEXT: .reg .b64 %rd<3>;
; PTX-EMPTY:
; PTX-NEXT: // %bb.0:
-; PTX-NEXT: ld.param.b64 %rd1, [areg_64_i8_param_0];
+; PTX-NEXT: ld.param::func.b64 %rd1, [areg_64_i8_param_0];
; PTX-NEXT: ld.global.nc.v8.b32 {%r1, %r2, %r3, %r4, %r5, %r6, %r7, %r8}, [%rd1];
-; PTX-NEXT: ld.param.b64 %rd2, [areg_64_i8_param_1];
+; PTX-NEXT: ld.param::func.b64 %rd2, [areg_64_i8_param_1];
; PTX-NEXT: st.global.v8.b32 [%rd2], {%r1, %r2, %r3, %r4, %r5, %r6, %r7, %r8};
; PTX-NEXT: ret;
%load = load <32 x i8>, ptr addrspace(1) %in, !invariant.load !0
@@ -286,9 +286,9 @@ define void @areg_64_i16(ptr addrspace(1) %in, ptr addrspace(1) %out) {
; PTX-NEXT: .reg .b64 %rd<3>;
; PTX-EMPTY:
; PTX-NEXT: // %bb.0:
-; PTX-NEXT: ld.param.b64 %rd1, [areg_64_i16_param_0];
+; PTX-NEXT: ld.param::func.b64 %rd1, [areg_64_i16_param_0];
; PTX-NEXT: ld.global.nc.v8.b32 {%r1, %r2, %r3, %r4, %r5, %r6, %r7, %r8}, [%rd1];
-; PTX-NEXT: ld.param.b64 %rd2, [areg_64_i16_param_1];
+; PTX-NEXT: ld.param::func.b64 %rd2, [areg_64_i16_param_1];
; PTX-NEXT: st.global.v8.b32 [%rd2], {%r1, %r2, %r3, %r4, %r5, %r6, %r7, %r8};
; PTX-NEXT: ret;
%load = load <16 x i16>, ptr addrspace(1) %in, !invariant.load !0
@@ -302,9 +302,9 @@ define void @areg_64_half(ptr addrspace(1) %in, ptr addrspace(1) %out) {
; PTX-NEXT: .reg .b64 %rd<3>;
; PTX-EMPTY:
; PTX-NEXT: // %bb.0:
-; PTX-NEXT: ld.param.b64 %rd1, [areg_64_half_param_0];
+; PTX-NEXT: ld.param::func.b64 %rd1, [areg_64_half_param_0];
; PTX-NEXT: ld.global.nc.v8.b32 {%r1, %r2, %r3, %r4, %r5, %r6, %r7, %r8}, [%rd1];
-; PTX-NEXT: ld.param.b64 %rd2, [areg_64_half_param_1];
+; PTX-NEXT: ld.param::func.b64 %rd2, [areg_64_half_param_1];
; PTX-NEXT: st.global.v8.b32 [%rd2], {%r1, %r2, %r3, %r4, %r5, %r6, %r7, %r8};
; PTX-NEXT: ret;
%load = load <16 x half>, ptr addrspace(1) %in, !invariant.load !0
@@ -318,9 +318,9 @@ define void @areg_64_bfloat(ptr addrspace(1) %in, ptr addrspace(1) %out) {
; PTX-NEXT: .reg .b64 %rd<3>;
; PTX-EMPTY:
; PTX-NEXT: // %bb.0:
-; PTX-NEXT: ld.param.b64 %rd1, [areg_64_bfloat_param_0];
+; PTX-NEXT: ld.param::func.b64 %rd1, [areg_64_bfloat_param_0];
; PTX-NEXT: ld.global.nc.v8.b32 {%r1, %r2, %r3, %r4, %r5, %r6, %r7, %r8}, [%rd1];
-; PTX-NEXT: ld.param.b64 %rd2, [areg_64_bfloat_param_1];
+; PTX-NEXT: ld.param::func.b64 %rd2, [areg_64_bfloat_param_1];
; PTX-NEXT: st.global.v8.b32 [%rd2], {%r1, %r2, %r3, %r4, %r5, %r6, %r7, %r8};
; PTX-NEXT: ret;
%load = load <16 x bfloat>, ptr addrspace(1) %in, !invariant.load !0
@@ -334,9 +334,9 @@ define void @areg_64_i32(ptr addrspace(1) %in, ptr addrspace(1) %out) {
; PTX-NEXT: .reg .b64 %rd<7>;
; PTX-EMPTY:
; PTX-NEXT: // %bb.0:
-; PTX-NEXT: ld.param.b64 %rd1, [areg_64_i32_param_0];
+; PTX-NEXT: ld.param::func.b64 %rd1, [areg_64_i32_param_0];
; PTX-NEXT: ld.global.nc.v4.b64 {%rd2, %rd3, %rd4, %rd5}, [%rd1];
-; PTX-NEXT: ld.param.b64 %rd6, [areg_64_i32_param_1];
+; PTX-NEXT: ld.param::func.b64 %rd6, [areg_64_i32_param_1];
; PTX-NEXT: st.global.v4.b64 [%rd6], {%rd2, %rd3, %rd4, %rd5};
; PTX-NEXT: ret;
%load = load <8 x i32>, ptr addrspace(1) %in, !invariant.load !0
@@ -350,9 +350,9 @@ define void @areg_64_i64(ptr addrspace(1) %in, ptr addrspace(1) %out) {
; PTX-NEXT: .reg .b64 %rd<7>;
; PTX-EMPTY:
; PTX-NEXT: // %bb.0:
-; PTX-NEXT: ld.param.b64 %rd1, [areg_64_i64_param_0];
+; PTX-NEXT: ld.param::func.b64 %rd1, [areg_64_i64_param_0];
; PTX-NEXT: ld.global.nc.v4.b64 {%rd2, %rd3, %rd4, %rd5}, [%rd1];
-; PTX-NEXT: ld.param.b64 %rd6, [areg_64_i64_param_1];
+; PTX-NEXT: ld.param::func.b64 %rd6, [areg_64_i64_param_1];
; PTX-NEXT: st.global.v4.b64 [%rd6], {%rd2, %rd3, %rd4, %rd5};
; PTX-NEXT: ret;
%load = load <4 x i64>, ptr addrspace(1) %in, !invariant.load !0
@@ -366,9 +366,9 @@ define void @areg_64_float(ptr addrspace(1) %in, ptr addrspace(1) %out) {
; PTX-NEXT: .reg .b64 %rd<7>;
; PTX-EMPTY:
; PTX-NEXT: // %bb.0:
-; PTX-NEXT: ld.param.b64 %rd1, [areg_64_float_param_0];
+; PTX-NEXT: ld.param::func.b64 %rd1, [areg_64_float_param_0];
; PTX-NEXT: ld.global.nc.v4.b64 {%rd2, %rd3, %rd4, %rd5}, [%rd1];
-; PTX-NEXT: ld.param.b64 %rd6, [areg_64_float_param_1];
+; PTX-NEXT: ld.param::func.b64 %rd6, [areg_64_float_param_1];
; PTX-NEXT: st.global.v4.b64 [%rd6], {%rd2, %rd3, %rd4, %rd5};
; PTX-NEXT: ret;
%load = load <8 x float>, ptr addrspace(1) %in, !invariant.load !0
@@ -382,9 +382,9 @@ define void @areg_64_double(ptr addrspace(1) %in, ptr addrspace(1) %out) {
; PTX-NEXT: .reg .b64 %rd<7>;
; PTX-EMPTY:
; PTX-NEXT: // %bb.0:
-; PTX-NEXT: ld.param.b64 %rd1, [areg_64_double_param_0];
+; PTX-NEXT: ld.param::func.b64 %rd1, [areg_64_double_param_0];
; PTX-NEXT: ld.global.nc.v4.b64 {%rd2, %rd3, %rd4, %rd5}, [%rd1];
-; PTX-NEXT: ld.param.b64 %rd6, [areg_64_double_param_1];
+; PTX-NEXT: ld.param::func.b64 %rd6, [areg_64_double_param_1];
; PTX-NEXT: st.global.v4.b64 [%rd6], {%rd2, %rd3, %rd4, %rd5};
; PTX-NEXT: ret;
%load = load <4 x double>, ptr addrspace(1) %in, !invariant.load !0
@@ -399,8 +399,8 @@ define void @ari_64_i8(ptr addrspace(1) %in, ptr addrspace(1) %out) {
; PTX-NEXT: .reg .b64 %rd<3>;
; PTX-EMPTY:
; PTX-NEXT: // %bb.0:
-; PTX-NEXT: ld.param.b64 %rd1, [ari_64_i8_param_0];
-; PTX-NEXT: ld.param.b64 %rd2, [ari_64_i8_param_1];
+; PTX-NEXT: ld.param::func.b64 %rd1, [ari_64_i8_param_0];
+; PTX-NEXT: ld.param::func.b64 %rd2, [ari_64_i8_param_1];
; PTX-NEXT: ld.global.nc.v8.b32 {%r1, %r2, %r3, %r4, %r5, %r6, %r7, %r8}, [%rd1+32];
; PTX-NEXT: st.global.v8.b32 [%rd2+32], {%r1, %r2, %r3, %r4, %r5, %r6, %r7, %r8};
; PTX-NEXT: ret;
@@ -418,8 +418,8 @@ define void @ari_64_i16(ptr addrspace(1) %in, ptr addrspace(1) %out) {
; PTX-NEXT: .reg .b64 %rd<3>;
; PTX-EMPTY:
; PTX-NEXT: // %bb.0:
-; PTX-NEXT: ld.param.b64 %rd1, [ari_64_i16_param_0];
-; PTX-NEXT: ld.param.b64 %rd2, [ari_64_i16_param_1];
+; PTX-NEXT: ld.param::func.b64 %rd1, [ari_64_i16_param_0];
+; PTX-NEXT: ld.param::func.b64 %rd2, [ari_64_i16_param_1];
; PTX-NEXT: ld.global.nc.v8.b32 {%r1, %r2, %r3, %r4, %r5, %r6, %r7, %r8}, [%rd1+32];
; PTX-NEXT: st.global.v8.b32 [%rd2+32], {%r1, %r2, %r3, %r4, %r5, %r6, %r7, %r8};
; PTX-NEXT: ret;
@@ -437,8 +437,8 @@ define void @ari_64_half(ptr addrspace(1) %in, ptr addrspace(1) %out) {
; PTX-NEXT: .reg .b64 %rd<3>;
; PTX-EMPTY:
; PTX-NEXT: // %bb.0:
-; PTX-NEXT: ld.param.b64 %rd1, [ari_64_half_param_0];
-; PTX-NEXT: ld.param.b64 %rd2, [ari_64_half_param_1];
+; PTX-NEXT: ld.param::func.b64 %rd1, [ari_64_half_param_0];
+; PTX-NEXT: ld.param::func.b64 %rd2, [ari_64_half_param_1];
; PTX-NEXT: ld.global.nc.v8.b32 {%r1, %r2, %r3, %r4, %r5, %r6, %r7, %r8}, [%rd1+32];
; PTX-NEXT: st.global.v8.b32 [%rd2+32], {%r1, %r2, %r3, %r4, %r5, %r6, %r7, %r8};
; PTX-NEXT: ret;
@@ -456,8 +456,8 @@ define void @ari_64_bfloat(ptr addrspace(1) %in, ptr addrspace(1) %out) {
; PTX-NEXT: .reg .b64 %rd<3>;
; PTX-EMPTY:
; PTX-NEXT: // %bb.0:
-; PTX-NEXT: ld.param.b64 %rd1, [ari_64_bfloat_param_0];
-; PTX-NEXT: ld.param.b64 %rd2, [ari_64_bfloat_param_1];
+; PTX-NEXT: ld.param::func.b64 %rd1, [ari_64_bfloat_param_0];
+; PTX-NEXT: ld.param::func.b64 %rd2, [ari_64_bfloat_param_1];
; PTX-NEXT: ld.global.nc.v8.b32 {%r1, %r2, %r3, %r4, %r5, %r6, %r7, %r8}, [%rd1+32];
; PTX-NEXT: st.global.v8.b32 [%rd2+32], {%r1, %r2, %r3, %r4, %r5, %r6, %r7, %r8};
; PTX-NEXT: ret;
@@ -474,8 +474,8 @@ define void @ari_64_i32(ptr addrspace(1) %in, ptr addrspace(1) %out) {
; PTX-NEXT: .reg .b64 %rd<7>;
; PTX-EMPTY:
; PTX-NEXT: // %bb.0:
-; PTX-NEXT: ld.param.b64 %rd1, [ari_64_i32_param_0];
-; PTX-NEXT: ld.param.b64 %rd2, [ari_64_i32_param_1];
+; PTX-NEXT: ld.param::func.b64 %rd1, [ari_64_i32_param_0];
+; PTX-NEXT: ld.param::func.b64 %rd2, [ari_64_i32_param_1];
; PTX-NEXT: ld.global.nc.v4.b64 {%rd3, %rd4, %rd5, %rd6}, [%rd1+32];
; PTX-NEXT: st.global.v4.b64 [%rd2+32], {%rd3, %rd4, %rd5, %rd6};
; PTX-NEXT: ret;
@@ -492,8 +492,8 @@ define void @ari_64_i64(ptr addrspace(1) %in, ptr addrspace(1) %out) {
; PTX-NEXT: .reg .b64 %rd<7>;
; PTX-EMPTY:
; PTX-NEXT: // %bb.0:
-; PTX-NEXT: ld.param.b64 %rd1, [ari_64_i64_param_0];
-; PTX-NEXT: ld.param.b64 %rd2, [ari_64_i64_param_1];
+; PTX-NEXT: ld.param::func.b64 %rd1, [ari_64_i64_param_0];
+; PTX-NEXT: ld.param::func.b64 %rd2, [ari_64_i64_param_1];
; PTX-NEXT: ld.global.nc.v4.b64 {%rd3, %rd4, %rd5, %rd6}, [%rd1+32];
; PTX-NEXT: st.global.v4.b64 [%rd2+32], {%rd3, %rd4, %rd5, %rd6};
; PTX-NEXT: ret;
@@ -510,8 +510,8 @@ define void @ari_64_float(ptr addrspace(1) %in, ptr addrspace(1) %out) {
; PTX-NEXT: .reg .b64 %rd<7>;
; PTX-EMPTY:
; PTX-NEXT: // %bb.0:
-; PTX-NEXT: ld.param.b64 %rd1, [ari_64_float_param_0];
-; PTX-NEXT: ld.param.b64 %rd2, [ari_64_float_param_1];
+; PTX-NEXT: ld.param::func.b64 %rd1, [ari_64_float_param_0];
+; PTX-NEXT: ld.param::func.b64 %rd2, [ari_64_float_param_1];
; PTX-NEXT: ld.global.nc.v4.b64 {%rd3, %rd4, %rd5, %rd6}, [%rd1+32];
; PTX-NEXT: st.global.v4.b64 [%rd2+32], {%rd3, %rd4, %rd5, %rd6};
; PTX-NEXT: ret;
@@ -528,8 +528,8 @@ define void @ari_64_double(ptr addrspace(1) %in, ptr addrspace(1) %out) {
; PTX-NEXT: .reg .b64 %rd<7>;
; PTX-EMPTY:
; PTX-NEXT: // %bb.0:
-; PTX-NEXT: ld.param.b64 %rd1, [ari_64_double_param_0];
-; PTX-NEXT: ld.param.b64 %rd2, [ari_64_double_param_1];
+; PTX-NEXT: ld.param::func.b64 %rd1, [ari_64_double_param_0];
+; PTX-NEXT: ld.param::func.b64 %rd2, [ari_64_double_param_1];
; PTX-NEXT: ld.global.nc.v4.b64 {%rd3, %rd4, %rd5, %rd6}, [%rd1+32];
; PTX-NEXT: st.global.v4.b64 [%rd2+32], {%rd3, %rd4, %rd5, %rd6};
; PTX-NEXT: ret;
diff --git a/llvm/test/CodeGen/NVPTX/load-store-256-addressing.ll b/llvm/test/CodeGen/NVPTX/load-store-256-addressing.ll
index 21604dfbf0013..2b9d65829bde1 100644
--- a/llvm/test/CodeGen/NVPTX/load-store-256-addressing.ll
+++ b/llvm/test/CodeGen/NVPTX/load-store-256-addressing.ll
@@ -266,9 +266,9 @@ define void @areg_64_i8(ptr addrspace(1) %in, ptr addrspace(1) %out) {
; PTX-NEXT: .reg .b64 %rd<3>;
; PTX-EMPTY:
; PTX-NEXT: // %bb.0:
-; PTX-NEXT: ld.param.b64 %rd1, [areg_64_i8_param_0];
+; PTX-NEXT: ld.param::func.b64 %rd1, [areg_64_i8_param_0];
; PTX-NEXT: ld.global.v8.b32 {%r1, %r2, %r3, %r4, %r5, %r6, %r7, %r8}, [%rd1];
-; PTX-NEXT: ld.param.b64 %rd2, [areg_64_i8_param_1];
+; PTX-NEXT: ld.param::func.b64 %rd2, [areg_64_i8_param_1];
; PTX-NEXT: st.global.v8.b32 [%rd2], {%r1, %r2, %r3, %r4, %r5, %r6, %r7, %r8};
; PTX-NEXT: ret;
%load = load <32 x i8>, ptr addrspace(1) %in
@@ -282,9 +282,9 @@ define void @areg_64_i16(ptr addrspace(1) %in, ptr addrspace(1) %out) {
; PTX-NEXT: .reg .b64 %rd<3>;
; PTX-EMPTY:
; PTX-NEXT: // %bb.0:
-; PTX-NEXT: ld.param.b64 %rd1, [areg_64_i16_param_0];
+; PTX-NEXT: ld.param::func.b64 %rd1, [areg_64_i16_param_0];
; PTX-NEXT: ld.global.v8.b32 {%r1, %r2, %r3, %r4, %r5, %r6, %r7, %r8}, [%rd1];
-; PTX-NEXT: ld.param.b64 %rd2, [areg_64_i16_param_1];
+; PTX-NEXT: ld.param::func.b64 %rd2, [areg_64_i16_param_1];
; PTX-NEXT: st.global.v8.b32 [%rd2], {%r1, %r2, %r3, %r4, %r5, %r6, %r7, %r8};
; PTX-NEXT: ret;
%load = load <16 x i16>, ptr addrspace(1) %in
@@ -298,9 +298,9 @@ define void @areg_64_half(ptr addrspace(1) %in, ptr addrspace(1) %out) {
; PTX-NEXT: .reg .b64 %rd<3>;
; PTX-EMPTY:
; PTX-NEXT: // %bb.0:
-; PTX-NEXT: ld.param.b64 %rd1, [areg_64_half_param_0];
+; PTX-NEXT: ld.param::func.b64 %rd1, [areg_64_half_param_0];
; PTX-NEXT: ld.global.v8.b32 {%r1, %r2, %r3, %r4, %r5, %r6, %r7, %r8}, [%rd1];
-; PTX-NEXT: ld.param.b64 %rd2, [areg_64_half_param_1];
+; PTX-NEXT: ld.param::func.b64 %rd2, [areg_64_half_param_1];
; PTX-NEXT: st.global.v8.b32 [%rd2], {%r1, %r2, %r3, %r4, %r5, %r6, %r7, %r8};
; PTX-NEXT: ret;
%load = load <16 x half>, ptr addrspace(1) %in
@@ -314,9 +314,9 @@ define void @areg_64_bfloat(ptr addrspace(1) %in, ptr addrspace(1) %out) {
; PTX-NEXT: .reg .b64 %rd<3>;
; PTX-EMPTY:
; PTX-NEXT: // %bb.0:
-; PTX-NEXT: ld.param.b64 %rd1, [areg_64_bfloat_param_0];
+; PTX-NEXT: ld.param::func.b64 %rd1, [areg_64_bfloat_param_0];
; PTX-NEXT: ld.global.v8.b32 {%r1, %r2, %r3, %r4, %r5, %r6, %r7, %r8}, [%rd1];
-; PTX-NEXT: ld.param.b64 %rd2, [areg_64_bfloat_param_1];
+; PTX-NEXT: ld.param::func.b64 %rd2, [areg_64_bfloat_param_1];
; PTX-NEXT: st.global.v8.b32 [%rd2], {%r1, %r2, %r3, %r4, %r5, %r6, %r7, %r8};
; PTX-NEXT: ret;
%load = load <16 x bfloat>, ptr addrspace(1) %in
@@ -330,9 +330,9 @@ define void @areg_64_i32(ptr addrspace(1) %in, ptr addrspace(1) %out) {
; PTX-NEXT: .reg .b64 %rd<7>;
; PTX-EMPTY:
; PTX-NEXT: // %bb.0:
-; PTX-NEXT: ld.param.b64 %rd1, [areg_64_i32_param_0];
+; PTX-NEXT: ld.param::func.b64 %rd1, [areg_64_i32_param_0];
; PTX-NEXT: ld.global.v4.b64 {%rd2, %rd3, %rd4, %rd5}, [%rd1];
-; PTX-NEXT: ld.param.b64 %rd6, [areg_64_i32_param_1];
+; PTX-NEXT: ld.param::func.b64 %rd6, [areg_64_i32_param_1];
; PTX-NEXT: st.global.v4.b64 [%rd6], {%rd2, %rd3, %rd4, %rd5};
; PTX-NEXT: ret;
%load = load <8 x i32>, ptr addrspace(1) %in
@@ -346,9 +346,9 @@ define void @areg_64_i64(ptr addrspace(1) %in, ptr addrspace(1) %out) {
; PTX-NEXT: .reg .b64 %rd<7>;
; PTX-EMPTY:
; PTX-NEXT: // %bb.0:
-; PTX-NEXT: ld.param.b64 %rd1, [areg_64_i64_param_0];
+; PTX-NEXT: ld.param::func.b64 %rd1, [areg_64_i64_param_0];
; PTX-NEXT: ld.global.v4.b64 {%rd2, %rd3, %rd4, %rd5}, [%rd1];
-; PTX-NEXT: ld.param.b64 %rd6, [areg_64_i64_param_1];
+; PTX-NEXT: ld.param::func.b64 %rd6, [areg_64_i64_param_1];
; PTX-NEXT: st.global.v4.b64 [%rd6], {%rd2, %rd3, %rd4, %rd5};
; PTX-NEXT: ret;
%load = load <4 x i64>, ptr addrspace(1) %in
@@ -362,9 +362,9 @@ define void @areg_64_float(ptr addrspace(1) %in, ptr addrspace(1) %out) {
; PTX-NEXT: .reg .b64 %rd<7>;
; PTX-EMPTY:
; PTX-NEXT: // %bb.0:
-; PTX-NEXT: ld.param.b64 %rd1, [areg_64_float_param_0];
+; PTX-NEXT: ld.param::func.b64 %rd1, [areg_64_float_param_0];
; PTX-NEXT: ld.global.v4.b64 {%rd2, %rd3, %rd4, %rd5}, [%rd1];
-; PTX-NEXT: ld.param.b64 %rd6, [areg_64_float_param_1];
+; PTX-NEXT: ld.param::func.b64 %rd6, [areg_64_float_param_1];
; PTX-NEXT: st.global.v4.b64 [%rd6], {%rd2, %rd3, %rd4, %rd5};
; PTX-NEXT: ret;
%load = load <8 x float>, ptr addrspace(1) %in
@@ -378,9 +378,9 @@ define void @areg_64_double(ptr addrspace(1) %in, ptr addrspace(1) %out) {
; PTX-NEXT: .reg .b64 %rd<7>;
; PTX-EMPTY:
; PTX-NEXT: // %bb.0:
-; PTX-NEXT: ld.param.b64 %rd1, [areg_64_double_param_0];
+; PTX-NEXT: ld.param::func.b64 %rd1, [areg_64_double_param_0];
; PTX-NEXT: ld.global.v4.b64 {%rd2, %rd3, %rd4, %rd5}, [%rd1];
-; PTX-NEXT: ld.param.b64 %rd6, [areg_64_double_param_1];
+; PTX-NEXT: ld.param::func.b64 %rd6, [areg_64_double_param_1];
; PTX-NEXT: st.global.v4.b64 [%rd6], {%rd2, %rd3, %rd4, %rd5};
; PTX-NEXT: ret;
%load = load <4 x double>, ptr addrspace(1) %in
@@ -395,8 +395,8 @@ define void @ari_64_i8(ptr addrspace(1) %in, ptr addrspace(1) %out) {
; PTX-NEXT: .reg .b64 %rd<3>;
; PTX-EMPTY:
; PTX-NEXT: // %bb.0:
-; PTX-NEXT: ld.param.b64 %rd1, [ari_64_i8_param_0];
-; PTX-NEXT: ld.param.b64 %rd2, [ari_64_i8_param_1];
+; PTX-NEXT: ld.param::func.b64 %rd1, [ari_64_i8_param_0];
+; PTX-NEXT: ld.param::func.b64 %rd2, [ari_64_i8_param_1];
; PTX-NEXT: ld.global.v8.b32 {%r1, %r2, %r3, %r4, %r5, %r6, %r7, %r8}, [%rd1+32];
; PTX-NEXT: st.global.v8.b32 [%rd2+32], {%r1, %r2, %r3, %r4, %r5, %r6, %r7, %r8};
; PTX-NEXT: ret;
@@ -414,8 +414,8 @@ define void @ari_64_i16(ptr addrspace(1) %in, ptr addrspace(1) %out) {
; PTX-NEXT: .reg .b64 %rd<3>;
; PTX-EMPTY:
; PTX-NEXT: // %bb.0:
-; PTX-NEXT: ld.param.b64 %rd1, [ari_64_i16_param_0];
-; PTX-NEXT: ld.param.b64 %rd2, [ari_64_i16_param_1];
+; PTX-NEXT: ld.param::func.b64 %rd1, [ari_64_i16_param_0];
+; PTX-NEXT: ld.param::func.b64 %rd2, [ari_64_i16_param_1];
; PTX-NEXT: ld.global.v8.b32 {%r1, %r2, %r3, %r4, %r5, %r6, %r7, %r8}, [%rd1+32];
; PTX-NEXT: st.global.v8.b32 [%rd2+32], {%r1, %r2, %r3, %r4, %r5, %r6, %r7, %r8};
; PTX-NEXT: ret;
@@ -433,8 +433,8 @@ define void @ari_64_half(ptr addrspace(1) %in, ptr addrspace(1) %out) {
; PTX-NEXT: .reg .b64 %rd<3>;
; PTX-EMPTY:
; PTX-NEXT: // %bb.0:
-; PTX-NEXT: ld.param.b64 %rd1, [ari_64_half_param_0];
-; PTX-NEXT: ld.param.b64 %rd2, [ari_64_half_param_1];
+; PTX-NEXT: ld.param::func.b64 %rd1, [ari_64_half_param_0];
+; PTX-NEXT: ld.param::func.b64 %rd2, [ari_64_half_param_1];
; PTX-NEXT: ld.global.v8.b32 {%r1, %r2, %r3, %r4, %r5, %r6, %r7, %r8}, [%rd1+32];
; PTX-NEXT: st.global.v8.b32 [%rd2+32], {%r1, %r2, %r3, %r4, %r5, %r6, %r7, %r8};
; PTX-NEXT: ret;
@@ -452,8 +452,8 @@ define void @ari_64_bfloat(ptr addrspace(1) %in, ptr addrspace(1) %out) {
; PTX-NEXT: .reg .b64 %rd<3>;
; PTX-EMPTY:
; PTX-NEXT: // %bb.0:
-; PTX-NEXT: ld.param.b64 %rd1, [ari_64_bfloat_param_0];
-; PTX-NEXT: ld.param.b64 %rd2, [ari_64_bfloat_param_1];
+; PTX-NEXT: ld.param::func.b64 %rd1, [ari_64_bfloat_param_0];
+; PTX-NEXT: ld.param::func.b64 %rd2, [ari_64_bfloat_param_1];
; PTX-NEXT: ld.global.v8.b32 {%r1, %r2, %r3, %r4, %r5, %r6, %r7, %r8}, [%rd1+32];
; PTX-NEXT: st.global.v8.b32 [%rd2+32], {%r1, %r2, %r3, %r4, %r5, %r6, %r7, %r8};
; PTX-NEXT: ret;
@@ -470,8 +470,8 @@ define void @ari_64_i32(ptr addrspace(1) %in, ptr addrspace(1) %out) {
; PTX-NEXT: .reg .b64 %rd<7>;
; PTX-EMPTY:
; PTX-NEXT: // %bb.0:
-; PTX-NEXT: ld.param.b64 %rd1, [ari_64_i32_param_0];
-; PTX-NEXT: ld.param.b64 %rd2, [ari_64_i32_param_1];
+; PTX-NEXT: ld.param::func.b64 %rd1, [ari_64_i32_param_0];
+; PTX-NEXT: ld.param::func.b64 %rd2, [ari_64_i32_param_1];
; PTX-NEXT: ld.global.v4.b64 {%rd3, %rd4, %rd5, %rd6}, [%rd1+32];
; PTX-NEXT: st.global.v4.b64 [%rd2+32], {%rd3, %rd4, %rd5, %rd6};
; PTX-NEXT: ret;
@@ -488,8 +488,8 @@ define void @ari_64_i64(ptr addrspace(1) %in, ptr addrspace(1) %out) {
; PTX-NEXT: .reg .b64 %rd<7>;
; PTX-EMPTY:
; PTX-NEXT: // %bb.0:
-; PTX-NEXT: ld.param.b64 %rd1, [ari_64_i64_param_0];
-; PTX-NEXT: ld.param.b64 %rd2, [ari_64_i64_param_1];
+; PTX-NEXT: ld.param::func.b64 %rd1, [ari_64_i64_param_0];
+; PTX-NEXT: ld.param::func.b64 %rd2, [ari_64_i64_param_1];
; PTX-NEXT: ld.global.v4.b64 {%rd3, %rd4, %rd5, %rd6}, [%rd1+32];
; PTX-NEXT: st.global.v4.b64 [%rd2+32], {%rd3, %rd4, %rd5, %rd6};
; PTX-NEXT: ret;
@@ -506,8 +506,8 @@ define void @ari_64_float(ptr addrspace(1) %in, ptr addrspace(1) %out) {
; PTX-NEXT: .reg .b64 %rd<7>;
; PTX-EMPTY:
; PTX-NEXT: // %bb.0:
-; PTX-NEXT: ld.param.b64 %rd1, [ari_64_float_param_0];
-; PTX-NEXT: ld.param.b64 %rd2, [ari_64_float_param_1];
+; PTX-NEXT: ld.param::func.b64 %rd1, [ari_64_float_param_0];
+; PTX-NEXT: ld.param::func.b64 %rd2, [ari_64_float_param_1];
; PTX-NEXT: ld.global.v4.b64 {%rd3, %rd4, %rd5, %rd6}, [%rd1+32];
; PTX-NEXT: st.global.v4.b64 [%rd2+32], {%rd3, %rd4, %rd5, %rd6};
; PTX-NEXT: ret;
@@ -524,8 +524,8 @@ define void @ari_64_double(ptr addrspace(1) %in, ptr addrspace(1) %out) {
; PTX-NEXT: .reg .b64 %rd<7>;
; PTX-EMPTY:
; PTX-NEXT: // %bb.0:
-; PTX-NEXT: ld.param.b64 %rd1, [ari_64_double_param_0];
-; PTX-NEXT: ld.param.b64 %rd2, [ari_64_double_param_1];
+; PTX-NEXT: ld.param::func.b64 %rd1, [ari_64_double_param_0];
+; PTX-NEXT: ld.param::func.b64 %rd2, [ari_64_double_param_1];
; PTX-NEXT: ld.global.v4.b64 {%rd3, %rd4, %rd5, %rd6}, [%rd1+32];
; PTX-NEXT: st.global.v4.b64 [%rd2+32], {%rd3, %rd4, %rd5, %rd6};
; PTX-NEXT: ret;
diff --git a/llvm/test/CodeGen/NVPTX/load-store-vectors-256.ll b/llvm/test/CodeGen/NVPTX/load-store-vectors-256.ll
index b5319935f0f9d..3a2a5a0f2914b 100644
--- a/llvm/test/CodeGen/NVPTX/load-store-vectors-256.ll
+++ b/llvm/test/CodeGen/NVPTX/load-store-vectors-256.ll
@@ -30,10 +30,10 @@ define void @generic_32xi8(ptr %a, ptr %b) {
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [generic_32xi8_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [generic_32xi8_param_0];
; CHECK-NEXT: ld.v4.b32 {%r1, %r2, %r3, %r4}, [%rd1];
; CHECK-NEXT: ld.v4.b32 {%r5, %r6, %r7, %r8}, [%rd1+16];
-; CHECK-NEXT: ld.param.b64 %rd2, [generic_32xi8_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [generic_32xi8_param_1];
; CHECK-NEXT: st.v4.b32 [%rd2+16], {%r5, %r6, %r7, %r8};
; CHECK-NEXT: st.v4.b32 [%rd2], {%r1, %r2, %r3, %r4};
; CHECK-NEXT: ret;
@@ -49,10 +49,10 @@ define void @generic_16xi16(ptr %a, ptr %b) {
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [generic_16xi16_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [generic_16xi16_param_0];
; CHECK-NEXT: ld.v4.b32 {%r1, %r2, %r3, %r4}, [%rd1];
; CHECK-NEXT: ld.v4.b32 {%r5, %r6, %r7, %r8}, [%rd1+16];
-; CHECK-NEXT: ld.param.b64 %rd2, [generic_16xi16_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [generic_16xi16_param_1];
; CHECK-NEXT: st.v4.b32 [%rd2+16], {%r5, %r6, %r7, %r8};
; CHECK-NEXT: st.v4.b32 [%rd2], {%r1, %r2, %r3, %r4};
; CHECK-NEXT: ret;
@@ -68,10 +68,10 @@ define void @generic_16xhalf(ptr %a, ptr %b) {
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [generic_16xhalf_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [generic_16xhalf_param_0];
; CHECK-NEXT: ld.v4.b32 {%r1, %r2, %r3, %r4}, [%rd1];
; CHECK-NEXT: ld.v4.b32 {%r5, %r6, %r7, %r8}, [%rd1+16];
-; CHECK-NEXT: ld.param.b64 %rd2, [generic_16xhalf_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [generic_16xhalf_param_1];
; CHECK-NEXT: st.v4.b32 [%rd2+16], {%r5, %r6, %r7, %r8};
; CHECK-NEXT: st.v4.b32 [%rd2], {%r1, %r2, %r3, %r4};
; CHECK-NEXT: ret;
@@ -87,10 +87,10 @@ define void @generic_16xbfloat(ptr %a, ptr %b) {
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [generic_16xbfloat_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [generic_16xbfloat_param_0];
; CHECK-NEXT: ld.v4.b32 {%r1, %r2, %r3, %r4}, [%rd1];
; CHECK-NEXT: ld.v4.b32 {%r5, %r6, %r7, %r8}, [%rd1+16];
-; CHECK-NEXT: ld.param.b64 %rd2, [generic_16xbfloat_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [generic_16xbfloat_param_1];
; CHECK-NEXT: st.v4.b32 [%rd2+16], {%r5, %r6, %r7, %r8};
; CHECK-NEXT: st.v4.b32 [%rd2], {%r1, %r2, %r3, %r4};
; CHECK-NEXT: ret;
@@ -106,10 +106,10 @@ define void @generic_8xi32(ptr %a, ptr %b) {
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [generic_8xi32_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd1, [generic_8xi32_param_0];
; SM90-NEXT: ld.v4.b32 {%r1, %r2, %r3, %r4}, [%rd1];
; SM90-NEXT: ld.v4.b32 {%r5, %r6, %r7, %r8}, [%rd1+16];
-; SM90-NEXT: ld.param.b64 %rd2, [generic_8xi32_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd2, [generic_8xi32_param_1];
; SM90-NEXT: st.v4.b32 [%rd2+16], {%r5, %r6, %r7, %r8};
; SM90-NEXT: st.v4.b32 [%rd2], {%r1, %r2, %r3, %r4};
; SM90-NEXT: ret;
@@ -119,10 +119,10 @@ define void @generic_8xi32(ptr %a, ptr %b) {
; SM100-NEXT: .reg .b64 %rd<7>;
; SM100-EMPTY:
; SM100-NEXT: // %bb.0:
-; SM100-NEXT: ld.param.b64 %rd1, [generic_8xi32_param_0];
+; SM100-NEXT: ld.param::func.b64 %rd1, [generic_8xi32_param_0];
; SM100-NEXT: ld.v2.b64 {%rd2, %rd3}, [%rd1];
; SM100-NEXT: ld.v2.b64 {%rd4, %rd5}, [%rd1+16];
-; SM100-NEXT: ld.param.b64 %rd6, [generic_8xi32_param_1];
+; SM100-NEXT: ld.param::func.b64 %rd6, [generic_8xi32_param_1];
; SM100-NEXT: st.v2.b64 [%rd6+16], {%rd4, %rd5};
; SM100-NEXT: st.v2.b64 [%rd6], {%rd2, %rd3};
; SM100-NEXT: ret;
@@ -137,10 +137,10 @@ define void @generic_4xi64(ptr %a, ptr %b) {
; CHECK-NEXT: .reg .b64 %rd<7>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [generic_4xi64_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [generic_4xi64_param_0];
; CHECK-NEXT: ld.v2.b64 {%rd2, %rd3}, [%rd1];
; CHECK-NEXT: ld.v2.b64 {%rd4, %rd5}, [%rd1+16];
-; CHECK-NEXT: ld.param.b64 %rd6, [generic_4xi64_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd6, [generic_4xi64_param_1];
; CHECK-NEXT: st.v2.b64 [%rd6+16], {%rd4, %rd5};
; CHECK-NEXT: st.v2.b64 [%rd6], {%rd2, %rd3};
; CHECK-NEXT: ret;
@@ -156,10 +156,10 @@ define void @generic_8xfloat(ptr %a, ptr %b) {
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [generic_8xfloat_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd1, [generic_8xfloat_param_0];
; SM90-NEXT: ld.v4.b32 {%r1, %r2, %r3, %r4}, [%rd1];
; SM90-NEXT: ld.v4.b32 {%r5, %r6, %r7, %r8}, [%rd1+16];
-; SM90-NEXT: ld.param.b64 %rd2, [generic_8xfloat_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd2, [generic_8xfloat_param_1];
; SM90-NEXT: st.v4.b32 [%rd2+16], {%r5, %r6, %r7, %r8};
; SM90-NEXT: st.v4.b32 [%rd2], {%r1, %r2, %r3, %r4};
; SM90-NEXT: ret;
@@ -169,10 +169,10 @@ define void @generic_8xfloat(ptr %a, ptr %b) {
; SM100-NEXT: .reg .b64 %rd<7>;
; SM100-EMPTY:
; SM100-NEXT: // %bb.0:
-; SM100-NEXT: ld.param.b64 %rd1, [generic_8xfloat_param_0];
+; SM100-NEXT: ld.param::func.b64 %rd1, [generic_8xfloat_param_0];
; SM100-NEXT: ld.v2.b64 {%rd2, %rd3}, [%rd1];
; SM100-NEXT: ld.v2.b64 {%rd4, %rd5}, [%rd1+16];
-; SM100-NEXT: ld.param.b64 %rd6, [generic_8xfloat_param_1];
+; SM100-NEXT: ld.param::func.b64 %rd6, [generic_8xfloat_param_1];
; SM100-NEXT: st.v2.b64 [%rd6+16], {%rd4, %rd5};
; SM100-NEXT: st.v2.b64 [%rd6], {%rd2, %rd3};
; SM100-NEXT: ret;
@@ -187,10 +187,10 @@ define void @generic_4xdouble(ptr %a, ptr %b) {
; CHECK-NEXT: .reg .b64 %rd<7>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [generic_4xdouble_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [generic_4xdouble_param_0];
; CHECK-NEXT: ld.v2.b64 {%rd2, %rd3}, [%rd1];
; CHECK-NEXT: ld.v2.b64 {%rd4, %rd5}, [%rd1+16];
-; CHECK-NEXT: ld.param.b64 %rd6, [generic_4xdouble_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd6, [generic_4xdouble_param_1];
; CHECK-NEXT: st.v2.b64 [%rd6+16], {%rd4, %rd5};
; CHECK-NEXT: st.v2.b64 [%rd6], {%rd2, %rd3};
; CHECK-NEXT: ret;
@@ -208,10 +208,10 @@ define void @generic_volatile_32xi8(ptr %a, ptr %b) {
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [generic_volatile_32xi8_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [generic_volatile_32xi8_param_0];
; CHECK-NEXT: ld.volatile.v4.b32 {%r1, %r2, %r3, %r4}, [%rd1];
; CHECK-NEXT: ld.volatile.v4.b32 {%r5, %r6, %r7, %r8}, [%rd1+16];
-; CHECK-NEXT: ld.param.b64 %rd2, [generic_volatile_32xi8_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [generic_volatile_32xi8_param_1];
; CHECK-NEXT: st.volatile.v4.b32 [%rd2+16], {%r5, %r6, %r7, %r8};
; CHECK-NEXT: st.volatile.v4.b32 [%rd2], {%r1, %r2, %r3, %r4};
; CHECK-NEXT: ret;
@@ -227,10 +227,10 @@ define void @generic_volatile_16xi16(ptr %a, ptr %b) {
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [generic_volatile_16xi16_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [generic_volatile_16xi16_param_0];
; CHECK-NEXT: ld.volatile.v4.b32 {%r1, %r2, %r3, %r4}, [%rd1];
; CHECK-NEXT: ld.volatile.v4.b32 {%r5, %r6, %r7, %r8}, [%rd1+16];
-; CHECK-NEXT: ld.param.b64 %rd2, [generic_volatile_16xi16_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [generic_volatile_16xi16_param_1];
; CHECK-NEXT: st.volatile.v4.b32 [%rd2+16], {%r5, %r6, %r7, %r8};
; CHECK-NEXT: st.volatile.v4.b32 [%rd2], {%r1, %r2, %r3, %r4};
; CHECK-NEXT: ret;
@@ -246,10 +246,10 @@ define void @generic_volatile_16xhalf(ptr %a, ptr %b) {
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [generic_volatile_16xhalf_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [generic_volatile_16xhalf_param_0];
; CHECK-NEXT: ld.volatile.v4.b32 {%r1, %r2, %r3, %r4}, [%rd1];
; CHECK-NEXT: ld.volatile.v4.b32 {%r5, %r6, %r7, %r8}, [%rd1+16];
-; CHECK-NEXT: ld.param.b64 %rd2, [generic_volatile_16xhalf_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [generic_volatile_16xhalf_param_1];
; CHECK-NEXT: st.volatile.v4.b32 [%rd2+16], {%r5, %r6, %r7, %r8};
; CHECK-NEXT: st.volatile.v4.b32 [%rd2], {%r1, %r2, %r3, %r4};
; CHECK-NEXT: ret;
@@ -265,10 +265,10 @@ define void @generic_volatile_16xbfloat(ptr %a, ptr %b) {
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [generic_volatile_16xbfloat_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [generic_volatile_16xbfloat_param_0];
; CHECK-NEXT: ld.volatile.v4.b32 {%r1, %r2, %r3, %r4}, [%rd1];
; CHECK-NEXT: ld.volatile.v4.b32 {%r5, %r6, %r7, %r8}, [%rd1+16];
-; CHECK-NEXT: ld.param.b64 %rd2, [generic_volatile_16xbfloat_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [generic_volatile_16xbfloat_param_1];
; CHECK-NEXT: st.volatile.v4.b32 [%rd2+16], {%r5, %r6, %r7, %r8};
; CHECK-NEXT: st.volatile.v4.b32 [%rd2], {%r1, %r2, %r3, %r4};
; CHECK-NEXT: ret;
@@ -284,10 +284,10 @@ define void @generic_volatile_8xi32(ptr %a, ptr %b) {
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [generic_volatile_8xi32_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd1, [generic_volatile_8xi32_param_0];
; SM90-NEXT: ld.volatile.v4.b32 {%r1, %r2, %r3, %r4}, [%rd1];
; SM90-NEXT: ld.volatile.v4.b32 {%r5, %r6, %r7, %r8}, [%rd1+16];
-; SM90-NEXT: ld.param.b64 %rd2, [generic_volatile_8xi32_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd2, [generic_volatile_8xi32_param_1];
; SM90-NEXT: st.volatile.v4.b32 [%rd2+16], {%r5, %r6, %r7, %r8};
; SM90-NEXT: st.volatile.v4.b32 [%rd2], {%r1, %r2, %r3, %r4};
; SM90-NEXT: ret;
@@ -297,10 +297,10 @@ define void @generic_volatile_8xi32(ptr %a, ptr %b) {
; SM100-NEXT: .reg .b64 %rd<7>;
; SM100-EMPTY:
; SM100-NEXT: // %bb.0:
-; SM100-NEXT: ld.param.b64 %rd1, [generic_volatile_8xi32_param_0];
+; SM100-NEXT: ld.param::func.b64 %rd1, [generic_volatile_8xi32_param_0];
; SM100-NEXT: ld.volatile.v2.b64 {%rd2, %rd3}, [%rd1];
; SM100-NEXT: ld.volatile.v2.b64 {%rd4, %rd5}, [%rd1+16];
-; SM100-NEXT: ld.param.b64 %rd6, [generic_volatile_8xi32_param_1];
+; SM100-NEXT: ld.param::func.b64 %rd6, [generic_volatile_8xi32_param_1];
; SM100-NEXT: st.volatile.v2.b64 [%rd6+16], {%rd4, %rd5};
; SM100-NEXT: st.volatile.v2.b64 [%rd6], {%rd2, %rd3};
; SM100-NEXT: ret;
@@ -315,10 +315,10 @@ define void @generic_volatile_4xi64(ptr %a, ptr %b) {
; CHECK-NEXT: .reg .b64 %rd<7>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [generic_volatile_4xi64_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [generic_volatile_4xi64_param_0];
; CHECK-NEXT: ld.volatile.v2.b64 {%rd2, %rd3}, [%rd1];
; CHECK-NEXT: ld.volatile.v2.b64 {%rd4, %rd5}, [%rd1+16];
-; CHECK-NEXT: ld.param.b64 %rd6, [generic_volatile_4xi64_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd6, [generic_volatile_4xi64_param_1];
; CHECK-NEXT: st.volatile.v2.b64 [%rd6+16], {%rd4, %rd5};
; CHECK-NEXT: st.volatile.v2.b64 [%rd6], {%rd2, %rd3};
; CHECK-NEXT: ret;
@@ -334,10 +334,10 @@ define void @generic_volatile_8xfloat(ptr %a, ptr %b) {
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [generic_volatile_8xfloat_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd1, [generic_volatile_8xfloat_param_0];
; SM90-NEXT: ld.volatile.v4.b32 {%r1, %r2, %r3, %r4}, [%rd1];
; SM90-NEXT: ld.volatile.v4.b32 {%r5, %r6, %r7, %r8}, [%rd1+16];
-; SM90-NEXT: ld.param.b64 %rd2, [generic_volatile_8xfloat_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd2, [generic_volatile_8xfloat_param_1];
; SM90-NEXT: st.volatile.v4.b32 [%rd2+16], {%r5, %r6, %r7, %r8};
; SM90-NEXT: st.volatile.v4.b32 [%rd2], {%r1, %r2, %r3, %r4};
; SM90-NEXT: ret;
@@ -347,10 +347,10 @@ define void @generic_volatile_8xfloat(ptr %a, ptr %b) {
; SM100-NEXT: .reg .b64 %rd<7>;
; SM100-EMPTY:
; SM100-NEXT: // %bb.0:
-; SM100-NEXT: ld.param.b64 %rd1, [generic_volatile_8xfloat_param_0];
+; SM100-NEXT: ld.param::func.b64 %rd1, [generic_volatile_8xfloat_param_0];
; SM100-NEXT: ld.volatile.v2.b64 {%rd2, %rd3}, [%rd1];
; SM100-NEXT: ld.volatile.v2.b64 {%rd4, %rd5}, [%rd1+16];
-; SM100-NEXT: ld.param.b64 %rd6, [generic_volatile_8xfloat_param_1];
+; SM100-NEXT: ld.param::func.b64 %rd6, [generic_volatile_8xfloat_param_1];
; SM100-NEXT: st.volatile.v2.b64 [%rd6+16], {%rd4, %rd5};
; SM100-NEXT: st.volatile.v2.b64 [%rd6], {%rd2, %rd3};
; SM100-NEXT: ret;
@@ -365,10 +365,10 @@ define void @generic_volatile_4xdouble(ptr %a, ptr %b) {
; CHECK-NEXT: .reg .b64 %rd<7>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [generic_volatile_4xdouble_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [generic_volatile_4xdouble_param_0];
; CHECK-NEXT: ld.volatile.v2.b64 {%rd2, %rd3}, [%rd1];
; CHECK-NEXT: ld.volatile.v2.b64 {%rd4, %rd5}, [%rd1+16];
-; CHECK-NEXT: ld.param.b64 %rd6, [generic_volatile_4xdouble_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd6, [generic_volatile_4xdouble_param_1];
; CHECK-NEXT: st.volatile.v2.b64 [%rd6+16], {%rd4, %rd5};
; CHECK-NEXT: st.volatile.v2.b64 [%rd6], {%rd2, %rd3};
; CHECK-NEXT: ret;
@@ -388,10 +388,10 @@ define void @global_32xi8(ptr addrspace(1) %a, ptr addrspace(1) %b) {
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [global_32xi8_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd1, [global_32xi8_param_0];
; SM90-NEXT: ld.global.v4.b32 {%r1, %r2, %r3, %r4}, [%rd1];
; SM90-NEXT: ld.global.v4.b32 {%r5, %r6, %r7, %r8}, [%rd1+16];
-; SM90-NEXT: ld.param.b64 %rd2, [global_32xi8_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd2, [global_32xi8_param_1];
; SM90-NEXT: st.global.v4.b32 [%rd2+16], {%r5, %r6, %r7, %r8};
; SM90-NEXT: st.global.v4.b32 [%rd2], {%r1, %r2, %r3, %r4};
; SM90-NEXT: ret;
@@ -402,9 +402,9 @@ define void @global_32xi8(ptr addrspace(1) %a, ptr addrspace(1) %b) {
; SM100-NEXT: .reg .b64 %rd<3>;
; SM100-EMPTY:
; SM100-NEXT: // %bb.0:
-; SM100-NEXT: ld.param.b64 %rd1, [global_32xi8_param_0];
+; SM100-NEXT: ld.param::func.b64 %rd1, [global_32xi8_param_0];
; SM100-NEXT: ld.global.v8.b32 {%r1, %r2, %r3, %r4, %r5, %r6, %r7, %r8}, [%rd1];
-; SM100-NEXT: ld.param.b64 %rd2, [global_32xi8_param_1];
+; SM100-NEXT: ld.param::func.b64 %rd2, [global_32xi8_param_1];
; SM100-NEXT: st.global.v8.b32 [%rd2], {%r1, %r2, %r3, %r4, %r5, %r6, %r7, %r8};
; SM100-NEXT: ret;
%a.load = load <32 x i8>, ptr addrspace(1) %a
@@ -419,10 +419,10 @@ define void @global_16xi16(ptr addrspace(1) %a, ptr addrspace(1) %b) {
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [global_16xi16_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd1, [global_16xi16_param_0];
; SM90-NEXT: ld.global.v4.b32 {%r1, %r2, %r3, %r4}, [%rd1];
; SM90-NEXT: ld.global.v4.b32 {%r5, %r6, %r7, %r8}, [%rd1+16];
-; SM90-NEXT: ld.param.b64 %rd2, [global_16xi16_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd2, [global_16xi16_param_1];
; SM90-NEXT: st.global.v4.b32 [%rd2+16], {%r5, %r6, %r7, %r8};
; SM90-NEXT: st.global.v4.b32 [%rd2], {%r1, %r2, %r3, %r4};
; SM90-NEXT: ret;
@@ -433,9 +433,9 @@ define void @global_16xi16(ptr addrspace(1) %a, ptr addrspace(1) %b) {
; SM100-NEXT: .reg .b64 %rd<3>;
; SM100-EMPTY:
; SM100-NEXT: // %bb.0:
-; SM100-NEXT: ld.param.b64 %rd1, [global_16xi16_param_0];
+; SM100-NEXT: ld.param::func.b64 %rd1, [global_16xi16_param_0];
; SM100-NEXT: ld.global.v8.b32 {%r1, %r2, %r3, %r4, %r5, %r6, %r7, %r8}, [%rd1];
-; SM100-NEXT: ld.param.b64 %rd2, [global_16xi16_param_1];
+; SM100-NEXT: ld.param::func.b64 %rd2, [global_16xi16_param_1];
; SM100-NEXT: st.global.v8.b32 [%rd2], {%r1, %r2, %r3, %r4, %r5, %r6, %r7, %r8};
; SM100-NEXT: ret;
%a.load = load <16 x i16>, ptr addrspace(1) %a
@@ -450,10 +450,10 @@ define void @global_16xhalf(ptr addrspace(1) %a, ptr addrspace(1) %b) {
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [global_16xhalf_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd1, [global_16xhalf_param_0];
; SM90-NEXT: ld.global.v4.b32 {%r1, %r2, %r3, %r4}, [%rd1];
; SM90-NEXT: ld.global.v4.b32 {%r5, %r6, %r7, %r8}, [%rd1+16];
-; SM90-NEXT: ld.param.b64 %rd2, [global_16xhalf_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd2, [global_16xhalf_param_1];
; SM90-NEXT: st.global.v4.b32 [%rd2+16], {%r5, %r6, %r7, %r8};
; SM90-NEXT: st.global.v4.b32 [%rd2], {%r1, %r2, %r3, %r4};
; SM90-NEXT: ret;
@@ -464,9 +464,9 @@ define void @global_16xhalf(ptr addrspace(1) %a, ptr addrspace(1) %b) {
; SM100-NEXT: .reg .b64 %rd<3>;
; SM100-EMPTY:
; SM100-NEXT: // %bb.0:
-; SM100-NEXT: ld.param.b64 %rd1, [global_16xhalf_param_0];
+; SM100-NEXT: ld.param::func.b64 %rd1, [global_16xhalf_param_0];
; SM100-NEXT: ld.global.v8.b32 {%r1, %r2, %r3, %r4, %r5, %r6, %r7, %r8}, [%rd1];
-; SM100-NEXT: ld.param.b64 %rd2, [global_16xhalf_param_1];
+; SM100-NEXT: ld.param::func.b64 %rd2, [global_16xhalf_param_1];
; SM100-NEXT: st.global.v8.b32 [%rd2], {%r1, %r2, %r3, %r4, %r5, %r6, %r7, %r8};
; SM100-NEXT: ret;
%a.load = load <16 x half>, ptr addrspace(1) %a
@@ -481,10 +481,10 @@ define void @global_16xbfloat(ptr addrspace(1) %a, ptr addrspace(1) %b) {
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [global_16xbfloat_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd1, [global_16xbfloat_param_0];
; SM90-NEXT: ld.global.v4.b32 {%r1, %r2, %r3, %r4}, [%rd1];
; SM90-NEXT: ld.global.v4.b32 {%r5, %r6, %r7, %r8}, [%rd1+16];
-; SM90-NEXT: ld.param.b64 %rd2, [global_16xbfloat_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd2, [global_16xbfloat_param_1];
; SM90-NEXT: st.global.v4.b32 [%rd2+16], {%r5, %r6, %r7, %r8};
; SM90-NEXT: st.global.v4.b32 [%rd2], {%r1, %r2, %r3, %r4};
; SM90-NEXT: ret;
@@ -495,9 +495,9 @@ define void @global_16xbfloat(ptr addrspace(1) %a, ptr addrspace(1) %b) {
; SM100-NEXT: .reg .b64 %rd<3>;
; SM100-EMPTY:
; SM100-NEXT: // %bb.0:
-; SM100-NEXT: ld.param.b64 %rd1, [global_16xbfloat_param_0];
+; SM100-NEXT: ld.param::func.b64 %rd1, [global_16xbfloat_param_0];
; SM100-NEXT: ld.global.v8.b32 {%r1, %r2, %r3, %r4, %r5, %r6, %r7, %r8}, [%rd1];
-; SM100-NEXT: ld.param.b64 %rd2, [global_16xbfloat_param_1];
+; SM100-NEXT: ld.param::func.b64 %rd2, [global_16xbfloat_param_1];
; SM100-NEXT: st.global.v8.b32 [%rd2], {%r1, %r2, %r3, %r4, %r5, %r6, %r7, %r8};
; SM100-NEXT: ret;
%a.load = load <16 x bfloat>, ptr addrspace(1) %a
@@ -512,10 +512,10 @@ define void @global_8xi32(ptr addrspace(1) %a, ptr addrspace(1) %b) {
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [global_8xi32_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd1, [global_8xi32_param_0];
; SM90-NEXT: ld.global.v4.b32 {%r1, %r2, %r3, %r4}, [%rd1];
; SM90-NEXT: ld.global.v4.b32 {%r5, %r6, %r7, %r8}, [%rd1+16];
-; SM90-NEXT: ld.param.b64 %rd2, [global_8xi32_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd2, [global_8xi32_param_1];
; SM90-NEXT: st.global.v4.b32 [%rd2+16], {%r5, %r6, %r7, %r8};
; SM90-NEXT: st.global.v4.b32 [%rd2], {%r1, %r2, %r3, %r4};
; SM90-NEXT: ret;
@@ -525,9 +525,9 @@ define void @global_8xi32(ptr addrspace(1) %a, ptr addrspace(1) %b) {
; SM100-NEXT: .reg .b64 %rd<7>;
; SM100-EMPTY:
; SM100-NEXT: // %bb.0:
-; SM100-NEXT: ld.param.b64 %rd1, [global_8xi32_param_0];
+; SM100-NEXT: ld.param::func.b64 %rd1, [global_8xi32_param_0];
; SM100-NEXT: ld.global.v4.b64 {%rd2, %rd3, %rd4, %rd5}, [%rd1];
-; SM100-NEXT: ld.param.b64 %rd6, [global_8xi32_param_1];
+; SM100-NEXT: ld.param::func.b64 %rd6, [global_8xi32_param_1];
; SM100-NEXT: st.global.v4.b64 [%rd6], {%rd2, %rd3, %rd4, %rd5};
; SM100-NEXT: ret;
%a.load = load <8 x i32>, ptr addrspace(1) %a
@@ -541,10 +541,10 @@ define void @global_4xi64(ptr addrspace(1) %a, ptr addrspace(1) %b) {
; SM90-NEXT: .reg .b64 %rd<7>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [global_4xi64_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd1, [global_4xi64_param_0];
; SM90-NEXT: ld.global.v2.b64 {%rd2, %rd3}, [%rd1];
; SM90-NEXT: ld.global.v2.b64 {%rd4, %rd5}, [%rd1+16];
-; SM90-NEXT: ld.param.b64 %rd6, [global_4xi64_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd6, [global_4xi64_param_1];
; SM90-NEXT: st.global.v2.b64 [%rd6+16], {%rd4, %rd5};
; SM90-NEXT: st.global.v2.b64 [%rd6], {%rd2, %rd3};
; SM90-NEXT: ret;
@@ -554,9 +554,9 @@ define void @global_4xi64(ptr addrspace(1) %a, ptr addrspace(1) %b) {
; SM100-NEXT: .reg .b64 %rd<7>;
; SM100-EMPTY:
; SM100-NEXT: // %bb.0:
-; SM100-NEXT: ld.param.b64 %rd1, [global_4xi64_param_0];
+; SM100-NEXT: ld.param::func.b64 %rd1, [global_4xi64_param_0];
; SM100-NEXT: ld.global.v4.b64 {%rd2, %rd3, %rd4, %rd5}, [%rd1];
-; SM100-NEXT: ld.param.b64 %rd6, [global_4xi64_param_1];
+; SM100-NEXT: ld.param::func.b64 %rd6, [global_4xi64_param_1];
; SM100-NEXT: st.global.v4.b64 [%rd6], {%rd2, %rd3, %rd4, %rd5};
; SM100-NEXT: ret;
%a.load = load <4 x i64>, ptr addrspace(1) %a
@@ -571,10 +571,10 @@ define void @global_8xfloat(ptr addrspace(1) %a, ptr addrspace(1) %b) {
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [global_8xfloat_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd1, [global_8xfloat_param_0];
; SM90-NEXT: ld.global.v4.b32 {%r1, %r2, %r3, %r4}, [%rd1];
; SM90-NEXT: ld.global.v4.b32 {%r5, %r6, %r7, %r8}, [%rd1+16];
-; SM90-NEXT: ld.param.b64 %rd2, [global_8xfloat_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd2, [global_8xfloat_param_1];
; SM90-NEXT: st.global.v4.b32 [%rd2+16], {%r5, %r6, %r7, %r8};
; SM90-NEXT: st.global.v4.b32 [%rd2], {%r1, %r2, %r3, %r4};
; SM90-NEXT: ret;
@@ -584,9 +584,9 @@ define void @global_8xfloat(ptr addrspace(1) %a, ptr addrspace(1) %b) {
; SM100-NEXT: .reg .b64 %rd<7>;
; SM100-EMPTY:
; SM100-NEXT: // %bb.0:
-; SM100-NEXT: ld.param.b64 %rd1, [global_8xfloat_param_0];
+; SM100-NEXT: ld.param::func.b64 %rd1, [global_8xfloat_param_0];
; SM100-NEXT: ld.global.v4.b64 {%rd2, %rd3, %rd4, %rd5}, [%rd1];
-; SM100-NEXT: ld.param.b64 %rd6, [global_8xfloat_param_1];
+; SM100-NEXT: ld.param::func.b64 %rd6, [global_8xfloat_param_1];
; SM100-NEXT: st.global.v4.b64 [%rd6], {%rd2, %rd3, %rd4, %rd5};
; SM100-NEXT: ret;
%a.load = load <8 x float>, ptr addrspace(1) %a
@@ -600,10 +600,10 @@ define void @global_4xdouble(ptr addrspace(1) %a, ptr addrspace(1) %b) {
; SM90-NEXT: .reg .b64 %rd<7>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [global_4xdouble_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd1, [global_4xdouble_param_0];
; SM90-NEXT: ld.global.v2.b64 {%rd2, %rd3}, [%rd1];
; SM90-NEXT: ld.global.v2.b64 {%rd4, %rd5}, [%rd1+16];
-; SM90-NEXT: ld.param.b64 %rd6, [global_4xdouble_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd6, [global_4xdouble_param_1];
; SM90-NEXT: st.global.v2.b64 [%rd6+16], {%rd4, %rd5};
; SM90-NEXT: st.global.v2.b64 [%rd6], {%rd2, %rd3};
; SM90-NEXT: ret;
@@ -613,9 +613,9 @@ define void @global_4xdouble(ptr addrspace(1) %a, ptr addrspace(1) %b) {
; SM100-NEXT: .reg .b64 %rd<7>;
; SM100-EMPTY:
; SM100-NEXT: // %bb.0:
-; SM100-NEXT: ld.param.b64 %rd1, [global_4xdouble_param_0];
+; SM100-NEXT: ld.param::func.b64 %rd1, [global_4xdouble_param_0];
; SM100-NEXT: ld.global.v4.b64 {%rd2, %rd3, %rd4, %rd5}, [%rd1];
-; SM100-NEXT: ld.param.b64 %rd6, [global_4xdouble_param_1];
+; SM100-NEXT: ld.param::func.b64 %rd6, [global_4xdouble_param_1];
; SM100-NEXT: st.global.v4.b64 [%rd6], {%rd2, %rd3, %rd4, %rd5};
; SM100-NEXT: ret;
%a.load = load <4 x double>, ptr addrspace(1) %a
@@ -632,10 +632,10 @@ define void @global_volatile_32xi8(ptr addrspace(1) %a, ptr addrspace(1) %b) {
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [global_volatile_32xi8_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd1, [global_volatile_32xi8_param_0];
; SM90-NEXT: ld.volatile.global.v4.b32 {%r1, %r2, %r3, %r4}, [%rd1];
; SM90-NEXT: ld.volatile.global.v4.b32 {%r5, %r6, %r7, %r8}, [%rd1+16];
-; SM90-NEXT: ld.param.b64 %rd2, [global_volatile_32xi8_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd2, [global_volatile_32xi8_param_1];
; SM90-NEXT: st.volatile.global.v4.b32 [%rd2+16], {%r5, %r6, %r7, %r8};
; SM90-NEXT: st.volatile.global.v4.b32 [%rd2], {%r1, %r2, %r3, %r4};
; SM90-NEXT: ret;
@@ -646,9 +646,9 @@ define void @global_volatile_32xi8(ptr addrspace(1) %a, ptr addrspace(1) %b) {
; SM100-NEXT: .reg .b64 %rd<3>;
; SM100-EMPTY:
; SM100-NEXT: // %bb.0:
-; SM100-NEXT: ld.param.b64 %rd1, [global_volatile_32xi8_param_0];
+; SM100-NEXT: ld.param::func.b64 %rd1, [global_volatile_32xi8_param_0];
; SM100-NEXT: ld.volatile.global.v8.b32 {%r1, %r2, %r3, %r4, %r5, %r6, %r7, %r8}, [%rd1];
-; SM100-NEXT: ld.param.b64 %rd2, [global_volatile_32xi8_param_1];
+; SM100-NEXT: ld.param::func.b64 %rd2, [global_volatile_32xi8_param_1];
; SM100-NEXT: st.volatile.global.v8.b32 [%rd2], {%r1, %r2, %r3, %r4, %r5, %r6, %r7, %r8};
; SM100-NEXT: ret;
%a.load = load volatile <32 x i8>, ptr addrspace(1) %a
@@ -663,10 +663,10 @@ define void @global_volatile_16xi16(ptr addrspace(1) %a, ptr addrspace(1) %b) {
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [global_volatile_16xi16_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd1, [global_volatile_16xi16_param_0];
; SM90-NEXT: ld.volatile.global.v4.b32 {%r1, %r2, %r3, %r4}, [%rd1];
; SM90-NEXT: ld.volatile.global.v4.b32 {%r5, %r6, %r7, %r8}, [%rd1+16];
-; SM90-NEXT: ld.param.b64 %rd2, [global_volatile_16xi16_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd2, [global_volatile_16xi16_param_1];
; SM90-NEXT: st.volatile.global.v4.b32 [%rd2+16], {%r5, %r6, %r7, %r8};
; SM90-NEXT: st.volatile.global.v4.b32 [%rd2], {%r1, %r2, %r3, %r4};
; SM90-NEXT: ret;
@@ -677,9 +677,9 @@ define void @global_volatile_16xi16(ptr addrspace(1) %a, ptr addrspace(1) %b) {
; SM100-NEXT: .reg .b64 %rd<3>;
; SM100-EMPTY:
; SM100-NEXT: // %bb.0:
-; SM100-NEXT: ld.param.b64 %rd1, [global_volatile_16xi16_param_0];
+; SM100-NEXT: ld.param::func.b64 %rd1, [global_volatile_16xi16_param_0];
; SM100-NEXT: ld.volatile.global.v8.b32 {%r1, %r2, %r3, %r4, %r5, %r6, %r7, %r8}, [%rd1];
-; SM100-NEXT: ld.param.b64 %rd2, [global_volatile_16xi16_param_1];
+; SM100-NEXT: ld.param::func.b64 %rd2, [global_volatile_16xi16_param_1];
; SM100-NEXT: st.volatile.global.v8.b32 [%rd2], {%r1, %r2, %r3, %r4, %r5, %r6, %r7, %r8};
; SM100-NEXT: ret;
%a.load = load volatile <16 x i16>, ptr addrspace(1) %a
@@ -694,10 +694,10 @@ define void @global_volatile_16xhalf(ptr addrspace(1) %a, ptr addrspace(1) %b) {
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [global_volatile_16xhalf_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd1, [global_volatile_16xhalf_param_0];
; SM90-NEXT: ld.volatile.global.v4.b32 {%r1, %r2, %r3, %r4}, [%rd1];
; SM90-NEXT: ld.volatile.global.v4.b32 {%r5, %r6, %r7, %r8}, [%rd1+16];
-; SM90-NEXT: ld.param.b64 %rd2, [global_volatile_16xhalf_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd2, [global_volatile_16xhalf_param_1];
; SM90-NEXT: st.volatile.global.v4.b32 [%rd2+16], {%r5, %r6, %r7, %r8};
; SM90-NEXT: st.volatile.global.v4.b32 [%rd2], {%r1, %r2, %r3, %r4};
; SM90-NEXT: ret;
@@ -708,9 +708,9 @@ define void @global_volatile_16xhalf(ptr addrspace(1) %a, ptr addrspace(1) %b) {
; SM100-NEXT: .reg .b64 %rd<3>;
; SM100-EMPTY:
; SM100-NEXT: // %bb.0:
-; SM100-NEXT: ld.param.b64 %rd1, [global_volatile_16xhalf_param_0];
+; SM100-NEXT: ld.param::func.b64 %rd1, [global_volatile_16xhalf_param_0];
; SM100-NEXT: ld.volatile.global.v8.b32 {%r1, %r2, %r3, %r4, %r5, %r6, %r7, %r8}, [%rd1];
-; SM100-NEXT: ld.param.b64 %rd2, [global_volatile_16xhalf_param_1];
+; SM100-NEXT: ld.param::func.b64 %rd2, [global_volatile_16xhalf_param_1];
; SM100-NEXT: st.volatile.global.v8.b32 [%rd2], {%r1, %r2, %r3, %r4, %r5, %r6, %r7, %r8};
; SM100-NEXT: ret;
%a.load = load volatile <16 x half>, ptr addrspace(1) %a
@@ -725,10 +725,10 @@ define void @global_volatile_16xbfloat(ptr addrspace(1) %a, ptr addrspace(1) %b)
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [global_volatile_16xbfloat_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd1, [global_volatile_16xbfloat_param_0];
; SM90-NEXT: ld.volatile.global.v4.b32 {%r1, %r2, %r3, %r4}, [%rd1];
; SM90-NEXT: ld.volatile.global.v4.b32 {%r5, %r6, %r7, %r8}, [%rd1+16];
-; SM90-NEXT: ld.param.b64 %rd2, [global_volatile_16xbfloat_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd2, [global_volatile_16xbfloat_param_1];
; SM90-NEXT: st.volatile.global.v4.b32 [%rd2+16], {%r5, %r6, %r7, %r8};
; SM90-NEXT: st.volatile.global.v4.b32 [%rd2], {%r1, %r2, %r3, %r4};
; SM90-NEXT: ret;
@@ -739,9 +739,9 @@ define void @global_volatile_16xbfloat(ptr addrspace(1) %a, ptr addrspace(1) %b)
; SM100-NEXT: .reg .b64 %rd<3>;
; SM100-EMPTY:
; SM100-NEXT: // %bb.0:
-; SM100-NEXT: ld.param.b64 %rd1, [global_volatile_16xbfloat_param_0];
+; SM100-NEXT: ld.param::func.b64 %rd1, [global_volatile_16xbfloat_param_0];
; SM100-NEXT: ld.volatile.global.v8.b32 {%r1, %r2, %r3, %r4, %r5, %r6, %r7, %r8}, [%rd1];
-; SM100-NEXT: ld.param.b64 %rd2, [global_volatile_16xbfloat_param_1];
+; SM100-NEXT: ld.param::func.b64 %rd2, [global_volatile_16xbfloat_param_1];
; SM100-NEXT: st.volatile.global.v8.b32 [%rd2], {%r1, %r2, %r3, %r4, %r5, %r6, %r7, %r8};
; SM100-NEXT: ret;
%a.load = load volatile <16 x bfloat>, ptr addrspace(1) %a
@@ -756,10 +756,10 @@ define void @global_volatile_8xi32(ptr addrspace(1) %a, ptr addrspace(1) %b) {
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [global_volatile_8xi32_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd1, [global_volatile_8xi32_param_0];
; SM90-NEXT: ld.volatile.global.v4.b32 {%r1, %r2, %r3, %r4}, [%rd1];
; SM90-NEXT: ld.volatile.global.v4.b32 {%r5, %r6, %r7, %r8}, [%rd1+16];
-; SM90-NEXT: ld.param.b64 %rd2, [global_volatile_8xi32_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd2, [global_volatile_8xi32_param_1];
; SM90-NEXT: st.volatile.global.v4.b32 [%rd2+16], {%r5, %r6, %r7, %r8};
; SM90-NEXT: st.volatile.global.v4.b32 [%rd2], {%r1, %r2, %r3, %r4};
; SM90-NEXT: ret;
@@ -769,9 +769,9 @@ define void @global_volatile_8xi32(ptr addrspace(1) %a, ptr addrspace(1) %b) {
; SM100-NEXT: .reg .b64 %rd<7>;
; SM100-EMPTY:
; SM100-NEXT: // %bb.0:
-; SM100-NEXT: ld.param.b64 %rd1, [global_volatile_8xi32_param_0];
+; SM100-NEXT: ld.param::func.b64 %rd1, [global_volatile_8xi32_param_0];
; SM100-NEXT: ld.volatile.global.v4.b64 {%rd2, %rd3, %rd4, %rd5}, [%rd1];
-; SM100-NEXT: ld.param.b64 %rd6, [global_volatile_8xi32_param_1];
+; SM100-NEXT: ld.param::func.b64 %rd6, [global_volatile_8xi32_param_1];
; SM100-NEXT: st.volatile.global.v4.b64 [%rd6], {%rd2, %rd3, %rd4, %rd5};
; SM100-NEXT: ret;
%a.load = load volatile <8 x i32>, ptr addrspace(1) %a
@@ -785,10 +785,10 @@ define void @global_volatile_4xi64(ptr addrspace(1) %a, ptr addrspace(1) %b) {
; SM90-NEXT: .reg .b64 %rd<7>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [global_volatile_4xi64_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd1, [global_volatile_4xi64_param_0];
; SM90-NEXT: ld.volatile.global.v2.b64 {%rd2, %rd3}, [%rd1];
; SM90-NEXT: ld.volatile.global.v2.b64 {%rd4, %rd5}, [%rd1+16];
-; SM90-NEXT: ld.param.b64 %rd6, [global_volatile_4xi64_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd6, [global_volatile_4xi64_param_1];
; SM90-NEXT: st.volatile.global.v2.b64 [%rd6+16], {%rd4, %rd5};
; SM90-NEXT: st.volatile.global.v2.b64 [%rd6], {%rd2, %rd3};
; SM90-NEXT: ret;
@@ -798,9 +798,9 @@ define void @global_volatile_4xi64(ptr addrspace(1) %a, ptr addrspace(1) %b) {
; SM100-NEXT: .reg .b64 %rd<7>;
; SM100-EMPTY:
; SM100-NEXT: // %bb.0:
-; SM100-NEXT: ld.param.b64 %rd1, [global_volatile_4xi64_param_0];
+; SM100-NEXT: ld.param::func.b64 %rd1, [global_volatile_4xi64_param_0];
; SM100-NEXT: ld.volatile.global.v4.b64 {%rd2, %rd3, %rd4, %rd5}, [%rd1];
-; SM100-NEXT: ld.param.b64 %rd6, [global_volatile_4xi64_param_1];
+; SM100-NEXT: ld.param::func.b64 %rd6, [global_volatile_4xi64_param_1];
; SM100-NEXT: st.volatile.global.v4.b64 [%rd6], {%rd2, %rd3, %rd4, %rd5};
; SM100-NEXT: ret;
%a.load = load volatile <4 x i64>, ptr addrspace(1) %a
@@ -815,10 +815,10 @@ define void @global_volatile_8xfloat(ptr addrspace(1) %a, ptr addrspace(1) %b) {
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [global_volatile_8xfloat_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd1, [global_volatile_8xfloat_param_0];
; SM90-NEXT: ld.volatile.global.v4.b32 {%r1, %r2, %r3, %r4}, [%rd1];
; SM90-NEXT: ld.volatile.global.v4.b32 {%r5, %r6, %r7, %r8}, [%rd1+16];
-; SM90-NEXT: ld.param.b64 %rd2, [global_volatile_8xfloat_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd2, [global_volatile_8xfloat_param_1];
; SM90-NEXT: st.volatile.global.v4.b32 [%rd2+16], {%r5, %r6, %r7, %r8};
; SM90-NEXT: st.volatile.global.v4.b32 [%rd2], {%r1, %r2, %r3, %r4};
; SM90-NEXT: ret;
@@ -828,9 +828,9 @@ define void @global_volatile_8xfloat(ptr addrspace(1) %a, ptr addrspace(1) %b) {
; SM100-NEXT: .reg .b64 %rd<7>;
; SM100-EMPTY:
; SM100-NEXT: // %bb.0:
-; SM100-NEXT: ld.param.b64 %rd1, [global_volatile_8xfloat_param_0];
+; SM100-NEXT: ld.param::func.b64 %rd1, [global_volatile_8xfloat_param_0];
; SM100-NEXT: ld.volatile.global.v4.b64 {%rd2, %rd3, %rd4, %rd5}, [%rd1];
-; SM100-NEXT: ld.param.b64 %rd6, [global_volatile_8xfloat_param_1];
+; SM100-NEXT: ld.param::func.b64 %rd6, [global_volatile_8xfloat_param_1];
; SM100-NEXT: st.volatile.global.v4.b64 [%rd6], {%rd2, %rd3, %rd4, %rd5};
; SM100-NEXT: ret;
%a.load = load volatile <8 x float>, ptr addrspace(1) %a
@@ -844,10 +844,10 @@ define void @global_volatile_4xdouble(ptr addrspace(1) %a, ptr addrspace(1) %b)
; SM90-NEXT: .reg .b64 %rd<7>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [global_volatile_4xdouble_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd1, [global_volatile_4xdouble_param_0];
; SM90-NEXT: ld.volatile.global.v2.b64 {%rd2, %rd3}, [%rd1];
; SM90-NEXT: ld.volatile.global.v2.b64 {%rd4, %rd5}, [%rd1+16];
-; SM90-NEXT: ld.param.b64 %rd6, [global_volatile_4xdouble_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd6, [global_volatile_4xdouble_param_1];
; SM90-NEXT: st.volatile.global.v2.b64 [%rd6+16], {%rd4, %rd5};
; SM90-NEXT: st.volatile.global.v2.b64 [%rd6], {%rd2, %rd3};
; SM90-NEXT: ret;
@@ -857,9 +857,9 @@ define void @global_volatile_4xdouble(ptr addrspace(1) %a, ptr addrspace(1) %b)
; SM100-NEXT: .reg .b64 %rd<7>;
; SM100-EMPTY:
; SM100-NEXT: // %bb.0:
-; SM100-NEXT: ld.param.b64 %rd1, [global_volatile_4xdouble_param_0];
+; SM100-NEXT: ld.param::func.b64 %rd1, [global_volatile_4xdouble_param_0];
; SM100-NEXT: ld.volatile.global.v4.b64 {%rd2, %rd3, %rd4, %rd5}, [%rd1];
-; SM100-NEXT: ld.param.b64 %rd6, [global_volatile_4xdouble_param_1];
+; SM100-NEXT: ld.param::func.b64 %rd6, [global_volatile_4xdouble_param_1];
; SM100-NEXT: st.volatile.global.v4.b64 [%rd6], {%rd2, %rd3, %rd4, %rd5};
; SM100-NEXT: ret;
%a.load = load volatile <4 x double>, ptr addrspace(1) %a
@@ -878,10 +878,10 @@ define void @shared_32xi8(ptr addrspace(3) %a, ptr addrspace(3) %b) {
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [shared_32xi8_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [shared_32xi8_param_0];
; CHECK-NEXT: ld.shared.v4.b32 {%r1, %r2, %r3, %r4}, [%rd1];
; CHECK-NEXT: ld.shared.v4.b32 {%r5, %r6, %r7, %r8}, [%rd1+16];
-; CHECK-NEXT: ld.param.b64 %rd2, [shared_32xi8_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [shared_32xi8_param_1];
; CHECK-NEXT: st.shared.v4.b32 [%rd2+16], {%r5, %r6, %r7, %r8};
; CHECK-NEXT: st.shared.v4.b32 [%rd2], {%r1, %r2, %r3, %r4};
; CHECK-NEXT: ret;
@@ -897,10 +897,10 @@ define void @shared_16xi16(ptr addrspace(3) %a, ptr addrspace(3) %b) {
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [shared_16xi16_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [shared_16xi16_param_0];
; CHECK-NEXT: ld.shared.v4.b32 {%r1, %r2, %r3, %r4}, [%rd1];
; CHECK-NEXT: ld.shared.v4.b32 {%r5, %r6, %r7, %r8}, [%rd1+16];
-; CHECK-NEXT: ld.param.b64 %rd2, [shared_16xi16_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [shared_16xi16_param_1];
; CHECK-NEXT: st.shared.v4.b32 [%rd2+16], {%r5, %r6, %r7, %r8};
; CHECK-NEXT: st.shared.v4.b32 [%rd2], {%r1, %r2, %r3, %r4};
; CHECK-NEXT: ret;
@@ -916,10 +916,10 @@ define void @shared_16xhalf(ptr addrspace(3) %a, ptr addrspace(3) %b) {
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [shared_16xhalf_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [shared_16xhalf_param_0];
; CHECK-NEXT: ld.shared.v4.b32 {%r1, %r2, %r3, %r4}, [%rd1];
; CHECK-NEXT: ld.shared.v4.b32 {%r5, %r6, %r7, %r8}, [%rd1+16];
-; CHECK-NEXT: ld.param.b64 %rd2, [shared_16xhalf_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [shared_16xhalf_param_1];
; CHECK-NEXT: st.shared.v4.b32 [%rd2+16], {%r5, %r6, %r7, %r8};
; CHECK-NEXT: st.shared.v4.b32 [%rd2], {%r1, %r2, %r3, %r4};
; CHECK-NEXT: ret;
@@ -935,10 +935,10 @@ define void @shared_16xbfloat(ptr addrspace(3) %a, ptr addrspace(3) %b) {
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [shared_16xbfloat_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [shared_16xbfloat_param_0];
; CHECK-NEXT: ld.shared.v4.b32 {%r1, %r2, %r3, %r4}, [%rd1];
; CHECK-NEXT: ld.shared.v4.b32 {%r5, %r6, %r7, %r8}, [%rd1+16];
-; CHECK-NEXT: ld.param.b64 %rd2, [shared_16xbfloat_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [shared_16xbfloat_param_1];
; CHECK-NEXT: st.shared.v4.b32 [%rd2+16], {%r5, %r6, %r7, %r8};
; CHECK-NEXT: st.shared.v4.b32 [%rd2], {%r1, %r2, %r3, %r4};
; CHECK-NEXT: ret;
@@ -954,10 +954,10 @@ define void @shared_8xi32(ptr addrspace(3) %a, ptr addrspace(3) %b) {
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [shared_8xi32_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd1, [shared_8xi32_param_0];
; SM90-NEXT: ld.shared.v4.b32 {%r1, %r2, %r3, %r4}, [%rd1];
; SM90-NEXT: ld.shared.v4.b32 {%r5, %r6, %r7, %r8}, [%rd1+16];
-; SM90-NEXT: ld.param.b64 %rd2, [shared_8xi32_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd2, [shared_8xi32_param_1];
; SM90-NEXT: st.shared.v4.b32 [%rd2+16], {%r5, %r6, %r7, %r8};
; SM90-NEXT: st.shared.v4.b32 [%rd2], {%r1, %r2, %r3, %r4};
; SM90-NEXT: ret;
@@ -967,10 +967,10 @@ define void @shared_8xi32(ptr addrspace(3) %a, ptr addrspace(3) %b) {
; SM100-NEXT: .reg .b64 %rd<7>;
; SM100-EMPTY:
; SM100-NEXT: // %bb.0:
-; SM100-NEXT: ld.param.b64 %rd1, [shared_8xi32_param_0];
+; SM100-NEXT: ld.param::func.b64 %rd1, [shared_8xi32_param_0];
; SM100-NEXT: ld.shared.v2.b64 {%rd2, %rd3}, [%rd1];
; SM100-NEXT: ld.shared.v2.b64 {%rd4, %rd5}, [%rd1+16];
-; SM100-NEXT: ld.param.b64 %rd6, [shared_8xi32_param_1];
+; SM100-NEXT: ld.param::func.b64 %rd6, [shared_8xi32_param_1];
; SM100-NEXT: st.shared.v2.b64 [%rd6+16], {%rd4, %rd5};
; SM100-NEXT: st.shared.v2.b64 [%rd6], {%rd2, %rd3};
; SM100-NEXT: ret;
@@ -985,10 +985,10 @@ define void @shared_4xi64(ptr addrspace(3) %a, ptr addrspace(3) %b) {
; CHECK-NEXT: .reg .b64 %rd<7>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [shared_4xi64_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [shared_4xi64_param_0];
; CHECK-NEXT: ld.shared.v2.b64 {%rd2, %rd3}, [%rd1];
; CHECK-NEXT: ld.shared.v2.b64 {%rd4, %rd5}, [%rd1+16];
-; CHECK-NEXT: ld.param.b64 %rd6, [shared_4xi64_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd6, [shared_4xi64_param_1];
; CHECK-NEXT: st.shared.v2.b64 [%rd6+16], {%rd4, %rd5};
; CHECK-NEXT: st.shared.v2.b64 [%rd6], {%rd2, %rd3};
; CHECK-NEXT: ret;
@@ -1004,10 +1004,10 @@ define void @shared_8xfloat(ptr addrspace(3) %a, ptr addrspace(3) %b) {
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [shared_8xfloat_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd1, [shared_8xfloat_param_0];
; SM90-NEXT: ld.shared.v4.b32 {%r1, %r2, %r3, %r4}, [%rd1];
; SM90-NEXT: ld.shared.v4.b32 {%r5, %r6, %r7, %r8}, [%rd1+16];
-; SM90-NEXT: ld.param.b64 %rd2, [shared_8xfloat_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd2, [shared_8xfloat_param_1];
; SM90-NEXT: st.shared.v4.b32 [%rd2+16], {%r5, %r6, %r7, %r8};
; SM90-NEXT: st.shared.v4.b32 [%rd2], {%r1, %r2, %r3, %r4};
; SM90-NEXT: ret;
@@ -1017,10 +1017,10 @@ define void @shared_8xfloat(ptr addrspace(3) %a, ptr addrspace(3) %b) {
; SM100-NEXT: .reg .b64 %rd<7>;
; SM100-EMPTY:
; SM100-NEXT: // %bb.0:
-; SM100-NEXT: ld.param.b64 %rd1, [shared_8xfloat_param_0];
+; SM100-NEXT: ld.param::func.b64 %rd1, [shared_8xfloat_param_0];
; SM100-NEXT: ld.shared.v2.b64 {%rd2, %rd3}, [%rd1];
; SM100-NEXT: ld.shared.v2.b64 {%rd4, %rd5}, [%rd1+16];
-; SM100-NEXT: ld.param.b64 %rd6, [shared_8xfloat_param_1];
+; SM100-NEXT: ld.param::func.b64 %rd6, [shared_8xfloat_param_1];
; SM100-NEXT: st.shared.v2.b64 [%rd6+16], {%rd4, %rd5};
; SM100-NEXT: st.shared.v2.b64 [%rd6], {%rd2, %rd3};
; SM100-NEXT: ret;
@@ -1035,10 +1035,10 @@ define void @shared_4xdouble(ptr addrspace(3) %a, ptr addrspace(3) %b) {
; CHECK-NEXT: .reg .b64 %rd<7>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [shared_4xdouble_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [shared_4xdouble_param_0];
; CHECK-NEXT: ld.shared.v2.b64 {%rd2, %rd3}, [%rd1];
; CHECK-NEXT: ld.shared.v2.b64 {%rd4, %rd5}, [%rd1+16];
-; CHECK-NEXT: ld.param.b64 %rd6, [shared_4xdouble_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd6, [shared_4xdouble_param_1];
; CHECK-NEXT: st.shared.v2.b64 [%rd6+16], {%rd4, %rd5};
; CHECK-NEXT: st.shared.v2.b64 [%rd6], {%rd2, %rd3};
; CHECK-NEXT: ret;
@@ -1056,10 +1056,10 @@ define void @shared_volatile_32xi8(ptr addrspace(3) %a, ptr addrspace(3) %b) {
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [shared_volatile_32xi8_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [shared_volatile_32xi8_param_0];
; CHECK-NEXT: ld.volatile.shared.v4.b32 {%r1, %r2, %r3, %r4}, [%rd1];
; CHECK-NEXT: ld.volatile.shared.v4.b32 {%r5, %r6, %r7, %r8}, [%rd1+16];
-; CHECK-NEXT: ld.param.b64 %rd2, [shared_volatile_32xi8_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [shared_volatile_32xi8_param_1];
; CHECK-NEXT: st.volatile.shared.v4.b32 [%rd2+16], {%r5, %r6, %r7, %r8};
; CHECK-NEXT: st.volatile.shared.v4.b32 [%rd2], {%r1, %r2, %r3, %r4};
; CHECK-NEXT: ret;
@@ -1075,10 +1075,10 @@ define void @shared_volatile_16xi16(ptr addrspace(3) %a, ptr addrspace(3) %b) {
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [shared_volatile_16xi16_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [shared_volatile_16xi16_param_0];
; CHECK-NEXT: ld.volatile.shared.v4.b32 {%r1, %r2, %r3, %r4}, [%rd1];
; CHECK-NEXT: ld.volatile.shared.v4.b32 {%r5, %r6, %r7, %r8}, [%rd1+16];
-; CHECK-NEXT: ld.param.b64 %rd2, [shared_volatile_16xi16_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [shared_volatile_16xi16_param_1];
; CHECK-NEXT: st.volatile.shared.v4.b32 [%rd2+16], {%r5, %r6, %r7, %r8};
; CHECK-NEXT: st.volatile.shared.v4.b32 [%rd2], {%r1, %r2, %r3, %r4};
; CHECK-NEXT: ret;
@@ -1094,10 +1094,10 @@ define void @shared_volatile_16xhalf(ptr addrspace(3) %a, ptr addrspace(3) %b) {
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [shared_volatile_16xhalf_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [shared_volatile_16xhalf_param_0];
; CHECK-NEXT: ld.volatile.shared.v4.b32 {%r1, %r2, %r3, %r4}, [%rd1];
; CHECK-NEXT: ld.volatile.shared.v4.b32 {%r5, %r6, %r7, %r8}, [%rd1+16];
-; CHECK-NEXT: ld.param.b64 %rd2, [shared_volatile_16xhalf_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [shared_volatile_16xhalf_param_1];
; CHECK-NEXT: st.volatile.shared.v4.b32 [%rd2+16], {%r5, %r6, %r7, %r8};
; CHECK-NEXT: st.volatile.shared.v4.b32 [%rd2], {%r1, %r2, %r3, %r4};
; CHECK-NEXT: ret;
@@ -1113,10 +1113,10 @@ define void @shared_volatile_16xbfloat(ptr addrspace(3) %a, ptr addrspace(3) %b)
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [shared_volatile_16xbfloat_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [shared_volatile_16xbfloat_param_0];
; CHECK-NEXT: ld.volatile.shared.v4.b32 {%r1, %r2, %r3, %r4}, [%rd1];
; CHECK-NEXT: ld.volatile.shared.v4.b32 {%r5, %r6, %r7, %r8}, [%rd1+16];
-; CHECK-NEXT: ld.param.b64 %rd2, [shared_volatile_16xbfloat_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [shared_volatile_16xbfloat_param_1];
; CHECK-NEXT: st.volatile.shared.v4.b32 [%rd2+16], {%r5, %r6, %r7, %r8};
; CHECK-NEXT: st.volatile.shared.v4.b32 [%rd2], {%r1, %r2, %r3, %r4};
; CHECK-NEXT: ret;
@@ -1132,10 +1132,10 @@ define void @shared_volatile_8xi32(ptr addrspace(3) %a, ptr addrspace(3) %b) {
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [shared_volatile_8xi32_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd1, [shared_volatile_8xi32_param_0];
; SM90-NEXT: ld.volatile.shared.v4.b32 {%r1, %r2, %r3, %r4}, [%rd1];
; SM90-NEXT: ld.volatile.shared.v4.b32 {%r5, %r6, %r7, %r8}, [%rd1+16];
-; SM90-NEXT: ld.param.b64 %rd2, [shared_volatile_8xi32_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd2, [shared_volatile_8xi32_param_1];
; SM90-NEXT: st.volatile.shared.v4.b32 [%rd2+16], {%r5, %r6, %r7, %r8};
; SM90-NEXT: st.volatile.shared.v4.b32 [%rd2], {%r1, %r2, %r3, %r4};
; SM90-NEXT: ret;
@@ -1145,10 +1145,10 @@ define void @shared_volatile_8xi32(ptr addrspace(3) %a, ptr addrspace(3) %b) {
; SM100-NEXT: .reg .b64 %rd<7>;
; SM100-EMPTY:
; SM100-NEXT: // %bb.0:
-; SM100-NEXT: ld.param.b64 %rd1, [shared_volatile_8xi32_param_0];
+; SM100-NEXT: ld.param::func.b64 %rd1, [shared_volatile_8xi32_param_0];
; SM100-NEXT: ld.volatile.shared.v2.b64 {%rd2, %rd3}, [%rd1];
; SM100-NEXT: ld.volatile.shared.v2.b64 {%rd4, %rd5}, [%rd1+16];
-; SM100-NEXT: ld.param.b64 %rd6, [shared_volatile_8xi32_param_1];
+; SM100-NEXT: ld.param::func.b64 %rd6, [shared_volatile_8xi32_param_1];
; SM100-NEXT: st.volatile.shared.v2.b64 [%rd6+16], {%rd4, %rd5};
; SM100-NEXT: st.volatile.shared.v2.b64 [%rd6], {%rd2, %rd3};
; SM100-NEXT: ret;
@@ -1163,10 +1163,10 @@ define void @shared_volatile_4xi64(ptr addrspace(3) %a, ptr addrspace(3) %b) {
; CHECK-NEXT: .reg .b64 %rd<7>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [shared_volatile_4xi64_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [shared_volatile_4xi64_param_0];
; CHECK-NEXT: ld.volatile.shared.v2.b64 {%rd2, %rd3}, [%rd1];
; CHECK-NEXT: ld.volatile.shared.v2.b64 {%rd4, %rd5}, [%rd1+16];
-; CHECK-NEXT: ld.param.b64 %rd6, [shared_volatile_4xi64_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd6, [shared_volatile_4xi64_param_1];
; CHECK-NEXT: st.volatile.shared.v2.b64 [%rd6+16], {%rd4, %rd5};
; CHECK-NEXT: st.volatile.shared.v2.b64 [%rd6], {%rd2, %rd3};
; CHECK-NEXT: ret;
@@ -1182,10 +1182,10 @@ define void @shared_volatile_8xfloat(ptr addrspace(3) %a, ptr addrspace(3) %b) {
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [shared_volatile_8xfloat_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd1, [shared_volatile_8xfloat_param_0];
; SM90-NEXT: ld.volatile.shared.v4.b32 {%r1, %r2, %r3, %r4}, [%rd1];
; SM90-NEXT: ld.volatile.shared.v4.b32 {%r5, %r6, %r7, %r8}, [%rd1+16];
-; SM90-NEXT: ld.param.b64 %rd2, [shared_volatile_8xfloat_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd2, [shared_volatile_8xfloat_param_1];
; SM90-NEXT: st.volatile.shared.v4.b32 [%rd2+16], {%r5, %r6, %r7, %r8};
; SM90-NEXT: st.volatile.shared.v4.b32 [%rd2], {%r1, %r2, %r3, %r4};
; SM90-NEXT: ret;
@@ -1195,10 +1195,10 @@ define void @shared_volatile_8xfloat(ptr addrspace(3) %a, ptr addrspace(3) %b) {
; SM100-NEXT: .reg .b64 %rd<7>;
; SM100-EMPTY:
; SM100-NEXT: // %bb.0:
-; SM100-NEXT: ld.param.b64 %rd1, [shared_volatile_8xfloat_param_0];
+; SM100-NEXT: ld.param::func.b64 %rd1, [shared_volatile_8xfloat_param_0];
; SM100-NEXT: ld.volatile.shared.v2.b64 {%rd2, %rd3}, [%rd1];
; SM100-NEXT: ld.volatile.shared.v2.b64 {%rd4, %rd5}, [%rd1+16];
-; SM100-NEXT: ld.param.b64 %rd6, [shared_volatile_8xfloat_param_1];
+; SM100-NEXT: ld.param::func.b64 %rd6, [shared_volatile_8xfloat_param_1];
; SM100-NEXT: st.volatile.shared.v2.b64 [%rd6+16], {%rd4, %rd5};
; SM100-NEXT: st.volatile.shared.v2.b64 [%rd6], {%rd2, %rd3};
; SM100-NEXT: ret;
@@ -1213,10 +1213,10 @@ define void @shared_volatile_4xdouble(ptr addrspace(3) %a, ptr addrspace(3) %b)
; CHECK-NEXT: .reg .b64 %rd<7>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [shared_volatile_4xdouble_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [shared_volatile_4xdouble_param_0];
; CHECK-NEXT: ld.volatile.shared.v2.b64 {%rd2, %rd3}, [%rd1];
; CHECK-NEXT: ld.volatile.shared.v2.b64 {%rd4, %rd5}, [%rd1+16];
-; CHECK-NEXT: ld.param.b64 %rd6, [shared_volatile_4xdouble_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd6, [shared_volatile_4xdouble_param_1];
; CHECK-NEXT: st.volatile.shared.v2.b64 [%rd6+16], {%rd4, %rd5};
; CHECK-NEXT: st.volatile.shared.v2.b64 [%rd6], {%rd2, %rd3};
; CHECK-NEXT: ret;
@@ -1236,10 +1236,10 @@ define void @local_32xi8(ptr addrspace(5) %a, ptr addrspace(5) %b) {
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [local_32xi8_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [local_32xi8_param_0];
; CHECK-NEXT: ld.local.v4.b32 {%r1, %r2, %r3, %r4}, [%rd1];
; CHECK-NEXT: ld.local.v4.b32 {%r5, %r6, %r7, %r8}, [%rd1+16];
-; CHECK-NEXT: ld.param.b64 %rd2, [local_32xi8_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [local_32xi8_param_1];
; CHECK-NEXT: st.local.v4.b32 [%rd2+16], {%r5, %r6, %r7, %r8};
; CHECK-NEXT: st.local.v4.b32 [%rd2], {%r1, %r2, %r3, %r4};
; CHECK-NEXT: ret;
@@ -1255,10 +1255,10 @@ define void @local_16xi16(ptr addrspace(5) %a, ptr addrspace(5) %b) {
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [local_16xi16_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [local_16xi16_param_0];
; CHECK-NEXT: ld.local.v4.b32 {%r1, %r2, %r3, %r4}, [%rd1];
; CHECK-NEXT: ld.local.v4.b32 {%r5, %r6, %r7, %r8}, [%rd1+16];
-; CHECK-NEXT: ld.param.b64 %rd2, [local_16xi16_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [local_16xi16_param_1];
; CHECK-NEXT: st.local.v4.b32 [%rd2+16], {%r5, %r6, %r7, %r8};
; CHECK-NEXT: st.local.v4.b32 [%rd2], {%r1, %r2, %r3, %r4};
; CHECK-NEXT: ret;
@@ -1274,10 +1274,10 @@ define void @local_16xhalf(ptr addrspace(5) %a, ptr addrspace(5) %b) {
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [local_16xhalf_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [local_16xhalf_param_0];
; CHECK-NEXT: ld.local.v4.b32 {%r1, %r2, %r3, %r4}, [%rd1];
; CHECK-NEXT: ld.local.v4.b32 {%r5, %r6, %r7, %r8}, [%rd1+16];
-; CHECK-NEXT: ld.param.b64 %rd2, [local_16xhalf_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [local_16xhalf_param_1];
; CHECK-NEXT: st.local.v4.b32 [%rd2+16], {%r5, %r6, %r7, %r8};
; CHECK-NEXT: st.local.v4.b32 [%rd2], {%r1, %r2, %r3, %r4};
; CHECK-NEXT: ret;
@@ -1293,10 +1293,10 @@ define void @local_16xbfloat(ptr addrspace(5) %a, ptr addrspace(5) %b) {
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [local_16xbfloat_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [local_16xbfloat_param_0];
; CHECK-NEXT: ld.local.v4.b32 {%r1, %r2, %r3, %r4}, [%rd1];
; CHECK-NEXT: ld.local.v4.b32 {%r5, %r6, %r7, %r8}, [%rd1+16];
-; CHECK-NEXT: ld.param.b64 %rd2, [local_16xbfloat_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [local_16xbfloat_param_1];
; CHECK-NEXT: st.local.v4.b32 [%rd2+16], {%r5, %r6, %r7, %r8};
; CHECK-NEXT: st.local.v4.b32 [%rd2], {%r1, %r2, %r3, %r4};
; CHECK-NEXT: ret;
@@ -1312,10 +1312,10 @@ define void @local_8xi32(ptr addrspace(5) %a, ptr addrspace(5) %b) {
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [local_8xi32_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd1, [local_8xi32_param_0];
; SM90-NEXT: ld.local.v4.b32 {%r1, %r2, %r3, %r4}, [%rd1];
; SM90-NEXT: ld.local.v4.b32 {%r5, %r6, %r7, %r8}, [%rd1+16];
-; SM90-NEXT: ld.param.b64 %rd2, [local_8xi32_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd2, [local_8xi32_param_1];
; SM90-NEXT: st.local.v4.b32 [%rd2+16], {%r5, %r6, %r7, %r8};
; SM90-NEXT: st.local.v4.b32 [%rd2], {%r1, %r2, %r3, %r4};
; SM90-NEXT: ret;
@@ -1325,10 +1325,10 @@ define void @local_8xi32(ptr addrspace(5) %a, ptr addrspace(5) %b) {
; SM100-NEXT: .reg .b64 %rd<7>;
; SM100-EMPTY:
; SM100-NEXT: // %bb.0:
-; SM100-NEXT: ld.param.b64 %rd1, [local_8xi32_param_0];
+; SM100-NEXT: ld.param::func.b64 %rd1, [local_8xi32_param_0];
; SM100-NEXT: ld.local.v2.b64 {%rd2, %rd3}, [%rd1];
; SM100-NEXT: ld.local.v2.b64 {%rd4, %rd5}, [%rd1+16];
-; SM100-NEXT: ld.param.b64 %rd6, [local_8xi32_param_1];
+; SM100-NEXT: ld.param::func.b64 %rd6, [local_8xi32_param_1];
; SM100-NEXT: st.local.v2.b64 [%rd6+16], {%rd4, %rd5};
; SM100-NEXT: st.local.v2.b64 [%rd6], {%rd2, %rd3};
; SM100-NEXT: ret;
@@ -1343,10 +1343,10 @@ define void @local_4xi64(ptr addrspace(5) %a, ptr addrspace(5) %b) {
; CHECK-NEXT: .reg .b64 %rd<7>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [local_4xi64_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [local_4xi64_param_0];
; CHECK-NEXT: ld.local.v2.b64 {%rd2, %rd3}, [%rd1];
; CHECK-NEXT: ld.local.v2.b64 {%rd4, %rd5}, [%rd1+16];
-; CHECK-NEXT: ld.param.b64 %rd6, [local_4xi64_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd6, [local_4xi64_param_1];
; CHECK-NEXT: st.local.v2.b64 [%rd6+16], {%rd4, %rd5};
; CHECK-NEXT: st.local.v2.b64 [%rd6], {%rd2, %rd3};
; CHECK-NEXT: ret;
@@ -1362,10 +1362,10 @@ define void @local_8xfloat(ptr addrspace(5) %a, ptr addrspace(5) %b) {
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [local_8xfloat_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd1, [local_8xfloat_param_0];
; SM90-NEXT: ld.local.v4.b32 {%r1, %r2, %r3, %r4}, [%rd1];
; SM90-NEXT: ld.local.v4.b32 {%r5, %r6, %r7, %r8}, [%rd1+16];
-; SM90-NEXT: ld.param.b64 %rd2, [local_8xfloat_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd2, [local_8xfloat_param_1];
; SM90-NEXT: st.local.v4.b32 [%rd2+16], {%r5, %r6, %r7, %r8};
; SM90-NEXT: st.local.v4.b32 [%rd2], {%r1, %r2, %r3, %r4};
; SM90-NEXT: ret;
@@ -1375,10 +1375,10 @@ define void @local_8xfloat(ptr addrspace(5) %a, ptr addrspace(5) %b) {
; SM100-NEXT: .reg .b64 %rd<7>;
; SM100-EMPTY:
; SM100-NEXT: // %bb.0:
-; SM100-NEXT: ld.param.b64 %rd1, [local_8xfloat_param_0];
+; SM100-NEXT: ld.param::func.b64 %rd1, [local_8xfloat_param_0];
; SM100-NEXT: ld.local.v2.b64 {%rd2, %rd3}, [%rd1];
; SM100-NEXT: ld.local.v2.b64 {%rd4, %rd5}, [%rd1+16];
-; SM100-NEXT: ld.param.b64 %rd6, [local_8xfloat_param_1];
+; SM100-NEXT: ld.param::func.b64 %rd6, [local_8xfloat_param_1];
; SM100-NEXT: st.local.v2.b64 [%rd6+16], {%rd4, %rd5};
; SM100-NEXT: st.local.v2.b64 [%rd6], {%rd2, %rd3};
; SM100-NEXT: ret;
@@ -1393,10 +1393,10 @@ define void @local_4xdouble(ptr addrspace(5) %a, ptr addrspace(5) %b) {
; CHECK-NEXT: .reg .b64 %rd<7>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [local_4xdouble_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [local_4xdouble_param_0];
; CHECK-NEXT: ld.local.v2.b64 {%rd2, %rd3}, [%rd1];
; CHECK-NEXT: ld.local.v2.b64 {%rd4, %rd5}, [%rd1+16];
-; CHECK-NEXT: ld.param.b64 %rd6, [local_4xdouble_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd6, [local_4xdouble_param_1];
; CHECK-NEXT: st.local.v2.b64 [%rd6+16], {%rd4, %rd5};
; CHECK-NEXT: st.local.v2.b64 [%rd6], {%rd2, %rd3};
; CHECK-NEXT: ret;
@@ -1414,10 +1414,10 @@ define void @local_volatile_32xi8(ptr addrspace(5) %a, ptr addrspace(5) %b) {
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [local_volatile_32xi8_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [local_volatile_32xi8_param_0];
; CHECK-NEXT: ld.local.v4.b32 {%r1, %r2, %r3, %r4}, [%rd1];
; CHECK-NEXT: ld.local.v4.b32 {%r5, %r6, %r7, %r8}, [%rd1+16];
-; CHECK-NEXT: ld.param.b64 %rd2, [local_volatile_32xi8_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [local_volatile_32xi8_param_1];
; CHECK-NEXT: st.local.v4.b32 [%rd2+16], {%r5, %r6, %r7, %r8};
; CHECK-NEXT: st.local.v4.b32 [%rd2], {%r1, %r2, %r3, %r4};
; CHECK-NEXT: ret;
@@ -1433,10 +1433,10 @@ define void @local_volatile_16xi16(ptr addrspace(5) %a, ptr addrspace(5) %b) {
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [local_volatile_16xi16_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [local_volatile_16xi16_param_0];
; CHECK-NEXT: ld.local.v4.b32 {%r1, %r2, %r3, %r4}, [%rd1];
; CHECK-NEXT: ld.local.v4.b32 {%r5, %r6, %r7, %r8}, [%rd1+16];
-; CHECK-NEXT: ld.param.b64 %rd2, [local_volatile_16xi16_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [local_volatile_16xi16_param_1];
; CHECK-NEXT: st.local.v4.b32 [%rd2+16], {%r5, %r6, %r7, %r8};
; CHECK-NEXT: st.local.v4.b32 [%rd2], {%r1, %r2, %r3, %r4};
; CHECK-NEXT: ret;
@@ -1452,10 +1452,10 @@ define void @local_volatile_16xhalf(ptr addrspace(5) %a, ptr addrspace(5) %b) {
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [local_volatile_16xhalf_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [local_volatile_16xhalf_param_0];
; CHECK-NEXT: ld.local.v4.b32 {%r1, %r2, %r3, %r4}, [%rd1];
; CHECK-NEXT: ld.local.v4.b32 {%r5, %r6, %r7, %r8}, [%rd1+16];
-; CHECK-NEXT: ld.param.b64 %rd2, [local_volatile_16xhalf_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [local_volatile_16xhalf_param_1];
; CHECK-NEXT: st.local.v4.b32 [%rd2+16], {%r5, %r6, %r7, %r8};
; CHECK-NEXT: st.local.v4.b32 [%rd2], {%r1, %r2, %r3, %r4};
; CHECK-NEXT: ret;
@@ -1471,10 +1471,10 @@ define void @local_volatile_16xbfloat(ptr addrspace(5) %a, ptr addrspace(5) %b)
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [local_volatile_16xbfloat_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [local_volatile_16xbfloat_param_0];
; CHECK-NEXT: ld.local.v4.b32 {%r1, %r2, %r3, %r4}, [%rd1];
; CHECK-NEXT: ld.local.v4.b32 {%r5, %r6, %r7, %r8}, [%rd1+16];
-; CHECK-NEXT: ld.param.b64 %rd2, [local_volatile_16xbfloat_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [local_volatile_16xbfloat_param_1];
; CHECK-NEXT: st.local.v4.b32 [%rd2+16], {%r5, %r6, %r7, %r8};
; CHECK-NEXT: st.local.v4.b32 [%rd2], {%r1, %r2, %r3, %r4};
; CHECK-NEXT: ret;
@@ -1490,10 +1490,10 @@ define void @local_volatile_8xi32(ptr addrspace(5) %a, ptr addrspace(5) %b) {
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [local_volatile_8xi32_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd1, [local_volatile_8xi32_param_0];
; SM90-NEXT: ld.local.v4.b32 {%r1, %r2, %r3, %r4}, [%rd1];
; SM90-NEXT: ld.local.v4.b32 {%r5, %r6, %r7, %r8}, [%rd1+16];
-; SM90-NEXT: ld.param.b64 %rd2, [local_volatile_8xi32_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd2, [local_volatile_8xi32_param_1];
; SM90-NEXT: st.local.v4.b32 [%rd2+16], {%r5, %r6, %r7, %r8};
; SM90-NEXT: st.local.v4.b32 [%rd2], {%r1, %r2, %r3, %r4};
; SM90-NEXT: ret;
@@ -1503,10 +1503,10 @@ define void @local_volatile_8xi32(ptr addrspace(5) %a, ptr addrspace(5) %b) {
; SM100-NEXT: .reg .b64 %rd<7>;
; SM100-EMPTY:
; SM100-NEXT: // %bb.0:
-; SM100-NEXT: ld.param.b64 %rd1, [local_volatile_8xi32_param_0];
+; SM100-NEXT: ld.param::func.b64 %rd1, [local_volatile_8xi32_param_0];
; SM100-NEXT: ld.local.v2.b64 {%rd2, %rd3}, [%rd1];
; SM100-NEXT: ld.local.v2.b64 {%rd4, %rd5}, [%rd1+16];
-; SM100-NEXT: ld.param.b64 %rd6, [local_volatile_8xi32_param_1];
+; SM100-NEXT: ld.param::func.b64 %rd6, [local_volatile_8xi32_param_1];
; SM100-NEXT: st.local.v2.b64 [%rd6+16], {%rd4, %rd5};
; SM100-NEXT: st.local.v2.b64 [%rd6], {%rd2, %rd3};
; SM100-NEXT: ret;
@@ -1521,10 +1521,10 @@ define void @local_volatile_4xi64(ptr addrspace(5) %a, ptr addrspace(5) %b) {
; CHECK-NEXT: .reg .b64 %rd<7>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [local_volatile_4xi64_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [local_volatile_4xi64_param_0];
; CHECK-NEXT: ld.local.v2.b64 {%rd2, %rd3}, [%rd1];
; CHECK-NEXT: ld.local.v2.b64 {%rd4, %rd5}, [%rd1+16];
-; CHECK-NEXT: ld.param.b64 %rd6, [local_volatile_4xi64_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd6, [local_volatile_4xi64_param_1];
; CHECK-NEXT: st.local.v2.b64 [%rd6+16], {%rd4, %rd5};
; CHECK-NEXT: st.local.v2.b64 [%rd6], {%rd2, %rd3};
; CHECK-NEXT: ret;
@@ -1540,10 +1540,10 @@ define void @local_volatile_8xfloat(ptr addrspace(5) %a, ptr addrspace(5) %b) {
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [local_volatile_8xfloat_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd1, [local_volatile_8xfloat_param_0];
; SM90-NEXT: ld.local.v4.b32 {%r1, %r2, %r3, %r4}, [%rd1];
; SM90-NEXT: ld.local.v4.b32 {%r5, %r6, %r7, %r8}, [%rd1+16];
-; SM90-NEXT: ld.param.b64 %rd2, [local_volatile_8xfloat_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd2, [local_volatile_8xfloat_param_1];
; SM90-NEXT: st.local.v4.b32 [%rd2+16], {%r5, %r6, %r7, %r8};
; SM90-NEXT: st.local.v4.b32 [%rd2], {%r1, %r2, %r3, %r4};
; SM90-NEXT: ret;
@@ -1553,10 +1553,10 @@ define void @local_volatile_8xfloat(ptr addrspace(5) %a, ptr addrspace(5) %b) {
; SM100-NEXT: .reg .b64 %rd<7>;
; SM100-EMPTY:
; SM100-NEXT: // %bb.0:
-; SM100-NEXT: ld.param.b64 %rd1, [local_volatile_8xfloat_param_0];
+; SM100-NEXT: ld.param::func.b64 %rd1, [local_volatile_8xfloat_param_0];
; SM100-NEXT: ld.local.v2.b64 {%rd2, %rd3}, [%rd1];
; SM100-NEXT: ld.local.v2.b64 {%rd4, %rd5}, [%rd1+16];
-; SM100-NEXT: ld.param.b64 %rd6, [local_volatile_8xfloat_param_1];
+; SM100-NEXT: ld.param::func.b64 %rd6, [local_volatile_8xfloat_param_1];
; SM100-NEXT: st.local.v2.b64 [%rd6+16], {%rd4, %rd5};
; SM100-NEXT: st.local.v2.b64 [%rd6], {%rd2, %rd3};
; SM100-NEXT: ret;
@@ -1571,10 +1571,10 @@ define void @local_volatile_4xdouble(ptr addrspace(5) %a, ptr addrspace(5) %b) {
; CHECK-NEXT: .reg .b64 %rd<7>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [local_volatile_4xdouble_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [local_volatile_4xdouble_param_0];
; CHECK-NEXT: ld.local.v2.b64 {%rd2, %rd3}, [%rd1];
; CHECK-NEXT: ld.local.v2.b64 {%rd4, %rd5}, [%rd1+16];
-; CHECK-NEXT: ld.param.b64 %rd6, [local_volatile_4xdouble_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd6, [local_volatile_4xdouble_param_1];
; CHECK-NEXT: st.local.v2.b64 [%rd6+16], {%rd4, %rd5};
; CHECK-NEXT: st.local.v2.b64 [%rd6], {%rd2, %rd3};
; CHECK-NEXT: ret;
@@ -1589,10 +1589,10 @@ define void @test_i256_global(ptr addrspace(1) %a, ptr addrspace(1) %b) {
; SM90-NEXT: .reg .b64 %rd<7>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [test_i256_global_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd1, [test_i256_global_param_0];
; SM90-NEXT: ld.global.v2.b64 {%rd2, %rd3}, [%rd1];
; SM90-NEXT: ld.global.v2.b64 {%rd4, %rd5}, [%rd1+16];
-; SM90-NEXT: ld.param.b64 %rd6, [test_i256_global_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd6, [test_i256_global_param_1];
; SM90-NEXT: st.global.v2.b64 [%rd6+16], {%rd4, %rd5};
; SM90-NEXT: st.global.v2.b64 [%rd6], {%rd2, %rd3};
; SM90-NEXT: ret;
@@ -1602,9 +1602,9 @@ define void @test_i256_global(ptr addrspace(1) %a, ptr addrspace(1) %b) {
; SM100-NEXT: .reg .b64 %rd<7>;
; SM100-EMPTY:
; SM100-NEXT: // %bb.0:
-; SM100-NEXT: ld.param.b64 %rd1, [test_i256_global_param_0];
+; SM100-NEXT: ld.param::func.b64 %rd1, [test_i256_global_param_0];
; SM100-NEXT: ld.global.v4.b64 {%rd2, %rd3, %rd4, %rd5}, [%rd1];
-; SM100-NEXT: ld.param.b64 %rd6, [test_i256_global_param_1];
+; SM100-NEXT: ld.param::func.b64 %rd6, [test_i256_global_param_1];
; SM100-NEXT: st.global.v4.b64 [%rd6], {%rd2, %rd3, %rd4, %rd5};
; SM100-NEXT: ret;
%a.load = load i256, ptr addrspace(1) %a, align 32
@@ -1619,10 +1619,10 @@ define void @test_i256_global_unaligned(ptr addrspace(1) %a, ptr addrspace(1) %b
; CHECK-NEXT: .reg .b64 %rd<7>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [test_i256_global_unaligned_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_i256_global_unaligned_param_0];
; CHECK-NEXT: ld.global.v2.b64 {%rd2, %rd3}, [%rd1];
; CHECK-NEXT: ld.global.v2.b64 {%rd4, %rd5}, [%rd1+16];
-; CHECK-NEXT: ld.param.b64 %rd6, [test_i256_global_unaligned_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd6, [test_i256_global_unaligned_param_1];
; CHECK-NEXT: st.global.v2.b64 [%rd6+16], {%rd4, %rd5};
; CHECK-NEXT: st.global.v2.b64 [%rd6], {%rd2, %rd3};
; CHECK-NEXT: ret;
@@ -1637,10 +1637,10 @@ define void @test_i256_generic(ptr %a, ptr %b) {
; CHECK-NEXT: .reg .b64 %rd<7>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [test_i256_generic_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_i256_generic_param_0];
; CHECK-NEXT: ld.v2.b64 {%rd2, %rd3}, [%rd1];
; CHECK-NEXT: ld.v2.b64 {%rd4, %rd5}, [%rd1+16];
-; CHECK-NEXT: ld.param.b64 %rd6, [test_i256_generic_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd6, [test_i256_generic_param_1];
; CHECK-NEXT: st.v2.b64 [%rd6+16], {%rd4, %rd5};
; CHECK-NEXT: st.v2.b64 [%rd6], {%rd2, %rd3};
; CHECK-NEXT: ret;
@@ -1655,10 +1655,10 @@ define void @test_i256_global_volatile(ptr addrspace(1) %a, ptr addrspace(1) %b)
; SM90-NEXT: .reg .b64 %rd<7>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [test_i256_global_volatile_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd1, [test_i256_global_volatile_param_0];
; SM90-NEXT: ld.volatile.global.v2.b64 {%rd2, %rd3}, [%rd1];
; SM90-NEXT: ld.volatile.global.v2.b64 {%rd4, %rd5}, [%rd1+16];
-; SM90-NEXT: ld.param.b64 %rd6, [test_i256_global_volatile_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd6, [test_i256_global_volatile_param_1];
; SM90-NEXT: st.volatile.global.v2.b64 [%rd6+16], {%rd4, %rd5};
; SM90-NEXT: st.volatile.global.v2.b64 [%rd6], {%rd2, %rd3};
; SM90-NEXT: ret;
@@ -1668,9 +1668,9 @@ define void @test_i256_global_volatile(ptr addrspace(1) %a, ptr addrspace(1) %b)
; SM100-NEXT: .reg .b64 %rd<7>;
; SM100-EMPTY:
; SM100-NEXT: // %bb.0:
-; SM100-NEXT: ld.param.b64 %rd1, [test_i256_global_volatile_param_0];
+; SM100-NEXT: ld.param::func.b64 %rd1, [test_i256_global_volatile_param_0];
; SM100-NEXT: ld.volatile.global.v4.b64 {%rd2, %rd3, %rd4, %rd5}, [%rd1];
-; SM100-NEXT: ld.param.b64 %rd6, [test_i256_global_volatile_param_1];
+; SM100-NEXT: ld.param::func.b64 %rd6, [test_i256_global_volatile_param_1];
; SM100-NEXT: st.volatile.global.v4.b64 [%rd6], {%rd2, %rd3, %rd4, %rd5};
; SM100-NEXT: ret;
%a.load = load volatile i256, ptr addrspace(1) %a, align 32
diff --git a/llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-multiple-users.ll b/llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-multiple-users.ll
index e3ca9b1d5ae74..935ba83486eed 100644
--- a/llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-multiple-users.ll
+++ b/llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-multiple-users.ll
@@ -13,8 +13,8 @@ define i32 @test_multiple_users(i32 %a, i32 %b) {
; CHECK-NEXT: .reg .b32 %r<6>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b32 %r3, [test_multiple_users_param_1];
-; CHECK-NEXT: ld.param.b32 %r2, [test_multiple_users_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r3, [test_multiple_users_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r2, [test_multiple_users_param_0];
; CHECK-NEXT: setp.eq.b32 %p1, %r2, %r3;
; CHECK-NEXT: mov.b32 %r5, 0;
; CHECK-NEXT: @%p1 bra $L__BB0_2;
@@ -28,7 +28,7 @@ define i32 @test_multiple_users(i32 %a, i32 %b) {
; CHECK-NEXT: mov.b32 %r5, 0;
; CHECK-NEXT: $L__BB0_4: // %merge2
; CHECK-NEXT: add.s32 %r4, %r5, %r1;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r4;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r4;
; CHECK-NEXT: ret;
entry:
%cmp1 = icmp eq i32 %a, %b
diff --git a/llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-vector-float.ll b/llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-vector-float.ll
index 32099625143f1..da59cf14c74d5 100644
--- a/llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-vector-float.ll
+++ b/llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-vector-float.ll
@@ -12,7 +12,7 @@ define i32 @test_float_f16x2_eq(i32 %arg) {
; CHECK-NEXT: .reg .b32 %r<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b32 %r1, [test_float_f16x2_eq_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_float_f16x2_eq_param_0];
; CHECK-NEXT: mov.b32 %r2, 0;
; CHECK-NEXT: setp.eq.f16x2 %p2|%p3, %r1, %r2;
; CHECK-NEXT: and.pred %p1, %p2, %p3;
@@ -25,7 +25,7 @@ define i32 @test_float_f16x2_eq(i32 %arg) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r2, 0;
; CHECK-NEXT: $L__BB0_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r2;
; CHECK-NEXT: ret;
entry:
%a = bitcast i32 %arg to <2 x half>
@@ -58,7 +58,7 @@ define i32 @test_float_bf16x2_eq(i32 %arg) {
; CHECK-NEXT: .reg .b32 %r<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b32 %r1, [test_float_bf16x2_eq_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_float_bf16x2_eq_param_0];
; CHECK-NEXT: mov.b32 %r2, 0;
; CHECK-NEXT: setp.eq.bf16x2 %p2|%p3, %r1, %r2;
; CHECK-NEXT: and.pred %p1, %p2, %p3;
@@ -71,7 +71,7 @@ define i32 @test_float_bf16x2_eq(i32 %arg) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r2, 0;
; CHECK-NEXT: $L__BB1_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r2;
; CHECK-NEXT: ret;
entry:
%a = bitcast i32 %arg to <2 x bfloat>
diff --git a/llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion.ll b/llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion.ll
index f07b0d908d8b9..50626fdeb5d83 100644
--- a/llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion.ll
+++ b/llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion.ll
@@ -12,8 +12,8 @@ define i32 @test_int16_eq(i16 %a, i16 %b) {
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_int16_eq_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_int16_eq_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs2, [test_int16_eq_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_int16_eq_param_0];
; CHECK-NEXT: setp.eq.b16 %p1, %rs1, %rs2;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB0_2;
@@ -24,7 +24,7 @@ define i32 @test_int16_eq(i16 %a, i16 %b) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB0_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
entry:
%cmp = icmp eq i16 %a, %b
@@ -54,8 +54,8 @@ define i32 @test_int16_ne(i16 %a, i16 %b) {
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_int16_ne_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_int16_ne_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs2, [test_int16_ne_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_int16_ne_param_0];
; CHECK-NEXT: setp.ne.b16 %p1, %rs1, %rs2;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB1_2;
@@ -66,7 +66,7 @@ define i32 @test_int16_ne(i16 %a, i16 %b) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB1_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
entry:
%cmp = icmp ne i16 %a, %b
@@ -96,8 +96,8 @@ define i32 @test_int16_slt(i16 %a, i16 %b) {
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_int16_slt_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_int16_slt_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs2, [test_int16_slt_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_int16_slt_param_0];
; CHECK-NEXT: setp.lt.s16 %p1, %rs1, %rs2;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB2_2;
@@ -108,7 +108,7 @@ define i32 @test_int16_slt(i16 %a, i16 %b) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB2_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
entry:
%cmp = icmp slt i16 %a, %b
@@ -138,8 +138,8 @@ define i32 @test_int16_sle(i16 %a, i16 %b) {
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_int16_sle_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_int16_sle_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs2, [test_int16_sle_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_int16_sle_param_0];
; CHECK-NEXT: setp.le.s16 %p1, %rs1, %rs2;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB3_2;
@@ -150,7 +150,7 @@ define i32 @test_int16_sle(i16 %a, i16 %b) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB3_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
entry:
%cmp = icmp sle i16 %a, %b
@@ -180,8 +180,8 @@ define i32 @test_int16_sgt(i16 %a, i16 %b) {
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_int16_sgt_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_int16_sgt_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs2, [test_int16_sgt_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_int16_sgt_param_0];
; CHECK-NEXT: setp.gt.s16 %p1, %rs1, %rs2;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB4_2;
@@ -192,7 +192,7 @@ define i32 @test_int16_sgt(i16 %a, i16 %b) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB4_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
entry:
%cmp = icmp sgt i16 %a, %b
@@ -222,8 +222,8 @@ define i32 @test_int16_sge(i16 %a, i16 %b) {
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_int16_sge_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_int16_sge_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs2, [test_int16_sge_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_int16_sge_param_0];
; CHECK-NEXT: setp.ge.s16 %p1, %rs1, %rs2;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB5_2;
@@ -234,7 +234,7 @@ define i32 @test_int16_sge(i16 %a, i16 %b) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB5_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
entry:
%cmp = icmp sge i16 %a, %b
@@ -264,8 +264,8 @@ define i32 @test_int16_ult(i16 %a, i16 %b) {
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_int16_ult_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_int16_ult_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs2, [test_int16_ult_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_int16_ult_param_0];
; CHECK-NEXT: setp.lt.u16 %p1, %rs1, %rs2;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB6_2;
@@ -276,7 +276,7 @@ define i32 @test_int16_ult(i16 %a, i16 %b) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB6_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
entry:
%cmp = icmp ult i16 %a, %b
@@ -306,8 +306,8 @@ define i32 @test_int16_ule(i16 %a, i16 %b) {
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_int16_ule_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_int16_ule_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs2, [test_int16_ule_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_int16_ule_param_0];
; CHECK-NEXT: setp.le.u16 %p1, %rs1, %rs2;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB7_2;
@@ -318,7 +318,7 @@ define i32 @test_int16_ule(i16 %a, i16 %b) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB7_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
entry:
%cmp = icmp ule i16 %a, %b
@@ -348,8 +348,8 @@ define i32 @test_int16_ugt(i16 %a, i16 %b) {
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_int16_ugt_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_int16_ugt_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs2, [test_int16_ugt_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_int16_ugt_param_0];
; CHECK-NEXT: setp.gt.u16 %p1, %rs1, %rs2;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB8_2;
@@ -360,7 +360,7 @@ define i32 @test_int16_ugt(i16 %a, i16 %b) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB8_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
entry:
%cmp = icmp ugt i16 %a, %b
@@ -390,8 +390,8 @@ define i32 @test_int16_uge(i16 %a, i16 %b) {
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_int16_uge_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_int16_uge_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs2, [test_int16_uge_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_int16_uge_param_0];
; CHECK-NEXT: setp.ge.u16 %p1, %rs1, %rs2;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB9_2;
@@ -402,7 +402,7 @@ define i32 @test_int16_uge(i16 %a, i16 %b) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB9_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
entry:
%cmp = icmp uge i16 %a, %b
@@ -431,8 +431,8 @@ define i32 @test_int32_eq(i32 %a, i32 %b) {
; CHECK-NEXT: .reg .b32 %r<4>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b32 %r2, [test_int32_eq_param_1];
-; CHECK-NEXT: ld.param.b32 %r1, [test_int32_eq_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r2, [test_int32_eq_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_int32_eq_param_0];
; CHECK-NEXT: setp.eq.b32 %p1, %r1, %r2;
; CHECK-NEXT: mov.b32 %r3, 0;
; CHECK-NEXT: @%p1 bra $L__BB10_2;
@@ -443,7 +443,7 @@ define i32 @test_int32_eq(i32 %a, i32 %b) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r3, 0;
; CHECK-NEXT: $L__BB10_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r3;
; CHECK-NEXT: ret;
entry:
%cmp = icmp eq i32 %a, %b
@@ -472,8 +472,8 @@ define i32 @test_int32_ne(i32 %a, i32 %b) {
; CHECK-NEXT: .reg .b32 %r<4>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b32 %r2, [test_int32_ne_param_1];
-; CHECK-NEXT: ld.param.b32 %r1, [test_int32_ne_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r2, [test_int32_ne_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_int32_ne_param_0];
; CHECK-NEXT: setp.ne.b32 %p1, %r1, %r2;
; CHECK-NEXT: mov.b32 %r3, 0;
; CHECK-NEXT: @%p1 bra $L__BB11_2;
@@ -484,7 +484,7 @@ define i32 @test_int32_ne(i32 %a, i32 %b) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r3, 0;
; CHECK-NEXT: $L__BB11_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r3;
; CHECK-NEXT: ret;
entry:
%cmp = icmp ne i32 %a, %b
@@ -513,8 +513,8 @@ define i32 @test_int32_slt(i32 %a, i32 %b) {
; CHECK-NEXT: .reg .b32 %r<4>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b32 %r2, [test_int32_slt_param_1];
-; CHECK-NEXT: ld.param.b32 %r1, [test_int32_slt_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r2, [test_int32_slt_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_int32_slt_param_0];
; CHECK-NEXT: setp.lt.s32 %p1, %r1, %r2;
; CHECK-NEXT: mov.b32 %r3, 0;
; CHECK-NEXT: @%p1 bra $L__BB12_2;
@@ -525,7 +525,7 @@ define i32 @test_int32_slt(i32 %a, i32 %b) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r3, 0;
; CHECK-NEXT: $L__BB12_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r3;
; CHECK-NEXT: ret;
entry:
%cmp = icmp slt i32 %a, %b
@@ -554,8 +554,8 @@ define i32 @test_int32_sle(i32 %a, i32 %b) {
; CHECK-NEXT: .reg .b32 %r<4>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b32 %r2, [test_int32_sle_param_1];
-; CHECK-NEXT: ld.param.b32 %r1, [test_int32_sle_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r2, [test_int32_sle_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_int32_sle_param_0];
; CHECK-NEXT: setp.le.s32 %p1, %r1, %r2;
; CHECK-NEXT: mov.b32 %r3, 0;
; CHECK-NEXT: @%p1 bra $L__BB13_2;
@@ -566,7 +566,7 @@ define i32 @test_int32_sle(i32 %a, i32 %b) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r3, 0;
; CHECK-NEXT: $L__BB13_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r3;
; CHECK-NEXT: ret;
entry:
%cmp = icmp sle i32 %a, %b
@@ -595,8 +595,8 @@ define i32 @test_int32_sgt(i32 %a, i32 %b) {
; CHECK-NEXT: .reg .b32 %r<4>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b32 %r2, [test_int32_sgt_param_1];
-; CHECK-NEXT: ld.param.b32 %r1, [test_int32_sgt_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r2, [test_int32_sgt_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_int32_sgt_param_0];
; CHECK-NEXT: setp.gt.s32 %p1, %r1, %r2;
; CHECK-NEXT: mov.b32 %r3, 0;
; CHECK-NEXT: @%p1 bra $L__BB14_2;
@@ -607,7 +607,7 @@ define i32 @test_int32_sgt(i32 %a, i32 %b) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r3, 0;
; CHECK-NEXT: $L__BB14_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r3;
; CHECK-NEXT: ret;
entry:
%cmp = icmp sgt i32 %a, %b
@@ -636,8 +636,8 @@ define i32 @test_int32_sge(i32 %a, i32 %b) {
; CHECK-NEXT: .reg .b32 %r<4>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b32 %r2, [test_int32_sge_param_1];
-; CHECK-NEXT: ld.param.b32 %r1, [test_int32_sge_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r2, [test_int32_sge_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_int32_sge_param_0];
; CHECK-NEXT: setp.ge.s32 %p1, %r1, %r2;
; CHECK-NEXT: mov.b32 %r3, 0;
; CHECK-NEXT: @%p1 bra $L__BB15_2;
@@ -648,7 +648,7 @@ define i32 @test_int32_sge(i32 %a, i32 %b) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r3, 0;
; CHECK-NEXT: $L__BB15_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r3;
; CHECK-NEXT: ret;
entry:
%cmp = icmp sge i32 %a, %b
@@ -677,8 +677,8 @@ define i32 @test_int32_ult(i32 %a, i32 %b) {
; CHECK-NEXT: .reg .b32 %r<4>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b32 %r2, [test_int32_ult_param_1];
-; CHECK-NEXT: ld.param.b32 %r1, [test_int32_ult_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r2, [test_int32_ult_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_int32_ult_param_0];
; CHECK-NEXT: setp.lt.u32 %p1, %r1, %r2;
; CHECK-NEXT: mov.b32 %r3, 0;
; CHECK-NEXT: @%p1 bra $L__BB16_2;
@@ -689,7 +689,7 @@ define i32 @test_int32_ult(i32 %a, i32 %b) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r3, 0;
; CHECK-NEXT: $L__BB16_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r3;
; CHECK-NEXT: ret;
entry:
%cmp = icmp ult i32 %a, %b
@@ -718,8 +718,8 @@ define i32 @test_int32_ule(i32 %a, i32 %b) {
; CHECK-NEXT: .reg .b32 %r<4>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b32 %r2, [test_int32_ule_param_1];
-; CHECK-NEXT: ld.param.b32 %r1, [test_int32_ule_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r2, [test_int32_ule_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_int32_ule_param_0];
; CHECK-NEXT: setp.le.u32 %p1, %r1, %r2;
; CHECK-NEXT: mov.b32 %r3, 0;
; CHECK-NEXT: @%p1 bra $L__BB17_2;
@@ -730,7 +730,7 @@ define i32 @test_int32_ule(i32 %a, i32 %b) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r3, 0;
; CHECK-NEXT: $L__BB17_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r3;
; CHECK-NEXT: ret;
entry:
%cmp = icmp ule i32 %a, %b
@@ -759,8 +759,8 @@ define i32 @test_int32_ugt(i32 %a, i32 %b) {
; CHECK-NEXT: .reg .b32 %r<4>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b32 %r2, [test_int32_ugt_param_1];
-; CHECK-NEXT: ld.param.b32 %r1, [test_int32_ugt_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r2, [test_int32_ugt_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_int32_ugt_param_0];
; CHECK-NEXT: setp.gt.u32 %p1, %r1, %r2;
; CHECK-NEXT: mov.b32 %r3, 0;
; CHECK-NEXT: @%p1 bra $L__BB18_2;
@@ -771,7 +771,7 @@ define i32 @test_int32_ugt(i32 %a, i32 %b) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r3, 0;
; CHECK-NEXT: $L__BB18_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r3;
; CHECK-NEXT: ret;
entry:
%cmp = icmp ugt i32 %a, %b
@@ -800,8 +800,8 @@ define i32 @test_int32_uge(i32 %a, i32 %b) {
; CHECK-NEXT: .reg .b32 %r<4>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b32 %r2, [test_int32_uge_param_1];
-; CHECK-NEXT: ld.param.b32 %r1, [test_int32_uge_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r2, [test_int32_uge_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_int32_uge_param_0];
; CHECK-NEXT: setp.ge.u32 %p1, %r1, %r2;
; CHECK-NEXT: mov.b32 %r3, 0;
; CHECK-NEXT: @%p1 bra $L__BB19_2;
@@ -812,7 +812,7 @@ define i32 @test_int32_uge(i32 %a, i32 %b) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r3, 0;
; CHECK-NEXT: $L__BB19_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r3;
; CHECK-NEXT: ret;
entry:
%cmp = icmp uge i32 %a, %b
@@ -842,8 +842,8 @@ define i32 @test_int64_eq(i64 %a, i64 %b) {
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b64 %rd2, [test_int64_eq_param_1];
-; CHECK-NEXT: ld.param.b64 %rd1, [test_int64_eq_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [test_int64_eq_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_int64_eq_param_0];
; CHECK-NEXT: setp.eq.b64 %p1, %rd1, %rd2;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB20_2;
@@ -854,7 +854,7 @@ define i32 @test_int64_eq(i64 %a, i64 %b) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB20_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
entry:
%cmp = icmp eq i64 %a, %b
@@ -884,8 +884,8 @@ define i32 @test_int64_ne(i64 %a, i64 %b) {
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b64 %rd2, [test_int64_ne_param_1];
-; CHECK-NEXT: ld.param.b64 %rd1, [test_int64_ne_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [test_int64_ne_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_int64_ne_param_0];
; CHECK-NEXT: setp.ne.b64 %p1, %rd1, %rd2;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB21_2;
@@ -896,7 +896,7 @@ define i32 @test_int64_ne(i64 %a, i64 %b) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB21_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
entry:
%cmp = icmp ne i64 %a, %b
@@ -926,8 +926,8 @@ define i32 @test_int64_slt(i64 %a, i64 %b) {
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b64 %rd2, [test_int64_slt_param_1];
-; CHECK-NEXT: ld.param.b64 %rd1, [test_int64_slt_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [test_int64_slt_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_int64_slt_param_0];
; CHECK-NEXT: setp.lt.s64 %p1, %rd1, %rd2;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB22_2;
@@ -938,7 +938,7 @@ define i32 @test_int64_slt(i64 %a, i64 %b) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB22_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
entry:
%cmp = icmp slt i64 %a, %b
@@ -968,8 +968,8 @@ define i32 @test_int64_sle(i64 %a, i64 %b) {
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b64 %rd2, [test_int64_sle_param_1];
-; CHECK-NEXT: ld.param.b64 %rd1, [test_int64_sle_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [test_int64_sle_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_int64_sle_param_0];
; CHECK-NEXT: setp.le.s64 %p1, %rd1, %rd2;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB23_2;
@@ -980,7 +980,7 @@ define i32 @test_int64_sle(i64 %a, i64 %b) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB23_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
entry:
%cmp = icmp sle i64 %a, %b
@@ -1010,8 +1010,8 @@ define i32 @test_int64_sgt(i64 %a, i64 %b) {
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b64 %rd2, [test_int64_sgt_param_1];
-; CHECK-NEXT: ld.param.b64 %rd1, [test_int64_sgt_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [test_int64_sgt_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_int64_sgt_param_0];
; CHECK-NEXT: setp.gt.s64 %p1, %rd1, %rd2;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB24_2;
@@ -1022,7 +1022,7 @@ define i32 @test_int64_sgt(i64 %a, i64 %b) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB24_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
entry:
%cmp = icmp sgt i64 %a, %b
@@ -1052,8 +1052,8 @@ define i32 @test_int64_sge(i64 %a, i64 %b) {
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b64 %rd2, [test_int64_sge_param_1];
-; CHECK-NEXT: ld.param.b64 %rd1, [test_int64_sge_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [test_int64_sge_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_int64_sge_param_0];
; CHECK-NEXT: setp.ge.s64 %p1, %rd1, %rd2;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB25_2;
@@ -1064,7 +1064,7 @@ define i32 @test_int64_sge(i64 %a, i64 %b) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB25_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
entry:
%cmp = icmp sge i64 %a, %b
@@ -1094,8 +1094,8 @@ define i32 @test_int64_ult(i64 %a, i64 %b) {
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b64 %rd2, [test_int64_ult_param_1];
-; CHECK-NEXT: ld.param.b64 %rd1, [test_int64_ult_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [test_int64_ult_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_int64_ult_param_0];
; CHECK-NEXT: setp.lt.u64 %p1, %rd1, %rd2;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB26_2;
@@ -1106,7 +1106,7 @@ define i32 @test_int64_ult(i64 %a, i64 %b) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB26_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
entry:
%cmp = icmp ult i64 %a, %b
@@ -1136,8 +1136,8 @@ define i32 @test_int64_ule(i64 %a, i64 %b) {
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b64 %rd2, [test_int64_ule_param_1];
-; CHECK-NEXT: ld.param.b64 %rd1, [test_int64_ule_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [test_int64_ule_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_int64_ule_param_0];
; CHECK-NEXT: setp.le.u64 %p1, %rd1, %rd2;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB27_2;
@@ -1148,7 +1148,7 @@ define i32 @test_int64_ule(i64 %a, i64 %b) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB27_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
entry:
%cmp = icmp ule i64 %a, %b
@@ -1178,8 +1178,8 @@ define i32 @test_int64_ugt(i64 %a, i64 %b) {
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b64 %rd2, [test_int64_ugt_param_1];
-; CHECK-NEXT: ld.param.b64 %rd1, [test_int64_ugt_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [test_int64_ugt_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_int64_ugt_param_0];
; CHECK-NEXT: setp.gt.u64 %p1, %rd1, %rd2;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB28_2;
@@ -1190,7 +1190,7 @@ define i32 @test_int64_ugt(i64 %a, i64 %b) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB28_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
entry:
%cmp = icmp ugt i64 %a, %b
@@ -1220,8 +1220,8 @@ define i32 @test_int64_uge(i64 %a, i64 %b) {
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b64 %rd2, [test_int64_uge_param_1];
-; CHECK-NEXT: ld.param.b64 %rd1, [test_int64_uge_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [test_int64_uge_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_int64_uge_param_0];
; CHECK-NEXT: setp.ge.u64 %p1, %rd1, %rd2;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB29_2;
@@ -1232,7 +1232,7 @@ define i32 @test_int64_uge(i64 %a, i64 %b) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB29_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
entry:
%cmp = icmp uge i64 %a, %b
@@ -1262,8 +1262,8 @@ define i32 @test_bfloat16_eq(bfloat %a, bfloat %b) {
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_bfloat16_eq_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_bfloat16_eq_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs2, [test_bfloat16_eq_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_bfloat16_eq_param_0];
; CHECK-NEXT: setp.eq.bf16 %p1, %rs1, %rs2;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB30_2;
@@ -1274,7 +1274,7 @@ define i32 @test_bfloat16_eq(bfloat %a, bfloat %b) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB30_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
entry:
%cmp = fcmp oeq bfloat %a, %b
@@ -1304,8 +1304,8 @@ define i32 @test_bfloat16_ne(bfloat %a, bfloat %b) {
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_bfloat16_ne_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_bfloat16_ne_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs2, [test_bfloat16_ne_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_bfloat16_ne_param_0];
; CHECK-NEXT: setp.ne.bf16 %p1, %rs1, %rs2;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB31_2;
@@ -1316,7 +1316,7 @@ define i32 @test_bfloat16_ne(bfloat %a, bfloat %b) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB31_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
entry:
%cmp = fcmp one bfloat %a, %b
@@ -1346,8 +1346,8 @@ define i32 @test_bfloat16_oeq(bfloat %a, bfloat %b) {
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_bfloat16_oeq_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_bfloat16_oeq_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs2, [test_bfloat16_oeq_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_bfloat16_oeq_param_0];
; CHECK-NEXT: setp.eq.bf16 %p1, %rs1, %rs2;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB32_2;
@@ -1358,7 +1358,7 @@ define i32 @test_bfloat16_oeq(bfloat %a, bfloat %b) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB32_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
entry:
%cmp = fcmp oeq bfloat %a, %b
@@ -1388,8 +1388,8 @@ define i32 @test_bfloat16_one(bfloat %a, bfloat %b) {
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_bfloat16_one_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_bfloat16_one_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs2, [test_bfloat16_one_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_bfloat16_one_param_0];
; CHECK-NEXT: setp.ne.bf16 %p1, %rs1, %rs2;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB33_2;
@@ -1400,7 +1400,7 @@ define i32 @test_bfloat16_one(bfloat %a, bfloat %b) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB33_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
entry:
%cmp = fcmp one bfloat %a, %b
@@ -1430,8 +1430,8 @@ define i32 @test_bfloat16_ueq(bfloat %a, bfloat %b) {
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_bfloat16_ueq_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_bfloat16_ueq_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs2, [test_bfloat16_ueq_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_bfloat16_ueq_param_0];
; CHECK-NEXT: setp.equ.bf16 %p1, %rs1, %rs2;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB34_2;
@@ -1442,7 +1442,7 @@ define i32 @test_bfloat16_ueq(bfloat %a, bfloat %b) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB34_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
entry:
%cmp = fcmp ueq bfloat %a, %b
@@ -1472,8 +1472,8 @@ define i32 @test_bfloat16_une(bfloat %a, bfloat %b) {
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_bfloat16_une_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_bfloat16_une_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs2, [test_bfloat16_une_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_bfloat16_une_param_0];
; CHECK-NEXT: setp.neu.bf16 %p1, %rs1, %rs2;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB35_2;
@@ -1484,7 +1484,7 @@ define i32 @test_bfloat16_une(bfloat %a, bfloat %b) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB35_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
entry:
%cmp = fcmp une bfloat %a, %b
@@ -1514,8 +1514,8 @@ define i32 @test_bfloat16_olt(bfloat %a, bfloat %b) {
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_bfloat16_olt_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_bfloat16_olt_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs2, [test_bfloat16_olt_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_bfloat16_olt_param_0];
; CHECK-NEXT: setp.lt.bf16 %p1, %rs1, %rs2;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB36_2;
@@ -1526,7 +1526,7 @@ define i32 @test_bfloat16_olt(bfloat %a, bfloat %b) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB36_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
entry:
%cmp = fcmp olt bfloat %a, %b
@@ -1556,8 +1556,8 @@ define i32 @test_bfloat16_ole(bfloat %a, bfloat %b) {
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_bfloat16_ole_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_bfloat16_ole_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs2, [test_bfloat16_ole_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_bfloat16_ole_param_0];
; CHECK-NEXT: setp.le.bf16 %p1, %rs1, %rs2;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB37_2;
@@ -1568,7 +1568,7 @@ define i32 @test_bfloat16_ole(bfloat %a, bfloat %b) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB37_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
entry:
%cmp = fcmp ole bfloat %a, %b
@@ -1598,8 +1598,8 @@ define i32 @test_bfloat16_ogt(bfloat %a, bfloat %b) {
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_bfloat16_ogt_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_bfloat16_ogt_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs2, [test_bfloat16_ogt_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_bfloat16_ogt_param_0];
; CHECK-NEXT: setp.gt.bf16 %p1, %rs1, %rs2;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB38_2;
@@ -1610,7 +1610,7 @@ define i32 @test_bfloat16_ogt(bfloat %a, bfloat %b) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB38_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
entry:
%cmp = fcmp ogt bfloat %a, %b
@@ -1640,8 +1640,8 @@ define i32 @test_bfloat16_oge(bfloat %a, bfloat %b) {
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_bfloat16_oge_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_bfloat16_oge_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs2, [test_bfloat16_oge_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_bfloat16_oge_param_0];
; CHECK-NEXT: setp.ge.bf16 %p1, %rs1, %rs2;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB39_2;
@@ -1652,7 +1652,7 @@ define i32 @test_bfloat16_oge(bfloat %a, bfloat %b) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB39_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
entry:
%cmp = fcmp oge bfloat %a, %b
@@ -1682,8 +1682,8 @@ define i32 @test_bfloat16_ult(bfloat %a, bfloat %b) {
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_bfloat16_ult_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_bfloat16_ult_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs2, [test_bfloat16_ult_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_bfloat16_ult_param_0];
; CHECK-NEXT: setp.ltu.bf16 %p1, %rs1, %rs2;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB40_2;
@@ -1694,7 +1694,7 @@ define i32 @test_bfloat16_ult(bfloat %a, bfloat %b) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB40_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
entry:
%cmp = fcmp ult bfloat %a, %b
@@ -1724,8 +1724,8 @@ define i32 @test_bfloat16_ule(bfloat %a, bfloat %b) {
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_bfloat16_ule_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_bfloat16_ule_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs2, [test_bfloat16_ule_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_bfloat16_ule_param_0];
; CHECK-NEXT: setp.leu.bf16 %p1, %rs1, %rs2;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB41_2;
@@ -1736,7 +1736,7 @@ define i32 @test_bfloat16_ule(bfloat %a, bfloat %b) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB41_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
entry:
%cmp = fcmp ule bfloat %a, %b
@@ -1766,8 +1766,8 @@ define i32 @test_bfloat16_ugt(bfloat %a, bfloat %b) {
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_bfloat16_ugt_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_bfloat16_ugt_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs2, [test_bfloat16_ugt_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_bfloat16_ugt_param_0];
; CHECK-NEXT: setp.gtu.bf16 %p1, %rs1, %rs2;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB42_2;
@@ -1778,7 +1778,7 @@ define i32 @test_bfloat16_ugt(bfloat %a, bfloat %b) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB42_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
entry:
%cmp = fcmp ugt bfloat %a, %b
@@ -1808,8 +1808,8 @@ define i32 @test_bfloat16_uge(bfloat %a, bfloat %b) {
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_bfloat16_uge_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_bfloat16_uge_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs2, [test_bfloat16_uge_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_bfloat16_uge_param_0];
; CHECK-NEXT: setp.geu.bf16 %p1, %rs1, %rs2;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB43_2;
@@ -1820,7 +1820,7 @@ define i32 @test_bfloat16_uge(bfloat %a, bfloat %b) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB43_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
entry:
%cmp = fcmp uge bfloat %a, %b
@@ -1850,8 +1850,8 @@ define i32 @test_bfloat16_ord(bfloat %a, bfloat %b) {
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_bfloat16_ord_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_bfloat16_ord_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs2, [test_bfloat16_ord_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_bfloat16_ord_param_0];
; CHECK-NEXT: setp.num.bf16 %p1, %rs1, %rs2;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @!%p1 bra $L__BB44_1;
@@ -1860,7 +1860,7 @@ define i32 @test_bfloat16_ord(bfloat %a, bfloat %b) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB44_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
; CHECK-NEXT: $L__BB44_1: // %then
; CHECK-NEXT: mov.b32 %r1, 1;
@@ -1893,8 +1893,8 @@ define i32 @test_bfloat16_uno(bfloat %a, bfloat %b) {
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_bfloat16_uno_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_bfloat16_uno_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs2, [test_bfloat16_uno_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_bfloat16_uno_param_0];
; CHECK-NEXT: setp.nan.bf16 %p1, %rs1, %rs2;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB45_2;
@@ -1903,7 +1903,7 @@ define i32 @test_bfloat16_uno(bfloat %a, bfloat %b) {
; CHECK-NEXT: $L__BB45_2: // %merge1
; CHECK-NEXT: @%p1 bra $L__BB45_3;
; CHECK-NEXT: $L__BB45_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
; CHECK-NEXT: $L__BB45_3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
@@ -1936,8 +1936,8 @@ define i32 @test_float16_eq(half %a, half %b) {
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_float16_eq_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_float16_eq_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs2, [test_float16_eq_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_float16_eq_param_0];
; CHECK-NEXT: setp.eq.f16 %p1, %rs1, %rs2;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB46_2;
@@ -1948,7 +1948,7 @@ define i32 @test_float16_eq(half %a, half %b) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB46_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
entry:
%cmp = fcmp oeq half %a, %b
@@ -1978,8 +1978,8 @@ define i32 @test_float16_ne(half %a, half %b) {
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_float16_ne_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_float16_ne_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs2, [test_float16_ne_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_float16_ne_param_0];
; CHECK-NEXT: setp.ne.f16 %p1, %rs1, %rs2;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB47_2;
@@ -1990,7 +1990,7 @@ define i32 @test_float16_ne(half %a, half %b) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB47_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
entry:
%cmp = fcmp one half %a, %b
@@ -2020,8 +2020,8 @@ define i32 @test_float16_oeq(half %a, half %b) {
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_float16_oeq_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_float16_oeq_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs2, [test_float16_oeq_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_float16_oeq_param_0];
; CHECK-NEXT: setp.eq.f16 %p1, %rs1, %rs2;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB48_2;
@@ -2032,7 +2032,7 @@ define i32 @test_float16_oeq(half %a, half %b) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB48_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
entry:
%cmp = fcmp oeq half %a, %b
@@ -2062,8 +2062,8 @@ define i32 @test_float16_one(half %a, half %b) {
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_float16_one_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_float16_one_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs2, [test_float16_one_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_float16_one_param_0];
; CHECK-NEXT: setp.ne.f16 %p1, %rs1, %rs2;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB49_2;
@@ -2074,7 +2074,7 @@ define i32 @test_float16_one(half %a, half %b) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB49_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
entry:
%cmp = fcmp one half %a, %b
@@ -2104,8 +2104,8 @@ define i32 @test_float16_ueq(half %a, half %b) {
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_float16_ueq_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_float16_ueq_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs2, [test_float16_ueq_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_float16_ueq_param_0];
; CHECK-NEXT: setp.equ.f16 %p1, %rs1, %rs2;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB50_2;
@@ -2116,7 +2116,7 @@ define i32 @test_float16_ueq(half %a, half %b) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB50_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
entry:
%cmp = fcmp ueq half %a, %b
@@ -2146,8 +2146,8 @@ define i32 @test_float16_une(half %a, half %b) {
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_float16_une_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_float16_une_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs2, [test_float16_une_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_float16_une_param_0];
; CHECK-NEXT: setp.neu.f16 %p1, %rs1, %rs2;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB51_2;
@@ -2158,7 +2158,7 @@ define i32 @test_float16_une(half %a, half %b) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB51_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
entry:
%cmp = fcmp une half %a, %b
@@ -2188,8 +2188,8 @@ define i32 @test_float16_olt(half %a, half %b) {
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_float16_olt_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_float16_olt_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs2, [test_float16_olt_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_float16_olt_param_0];
; CHECK-NEXT: setp.lt.f16 %p1, %rs1, %rs2;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB52_2;
@@ -2200,7 +2200,7 @@ define i32 @test_float16_olt(half %a, half %b) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB52_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
entry:
%cmp = fcmp olt half %a, %b
@@ -2230,8 +2230,8 @@ define i32 @test_float16_ole(half %a, half %b) {
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_float16_ole_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_float16_ole_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs2, [test_float16_ole_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_float16_ole_param_0];
; CHECK-NEXT: setp.le.f16 %p1, %rs1, %rs2;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB53_2;
@@ -2242,7 +2242,7 @@ define i32 @test_float16_ole(half %a, half %b) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB53_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
entry:
%cmp = fcmp ole half %a, %b
@@ -2272,8 +2272,8 @@ define i32 @test_float16_ogt(half %a, half %b) {
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_float16_ogt_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_float16_ogt_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs2, [test_float16_ogt_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_float16_ogt_param_0];
; CHECK-NEXT: setp.gt.f16 %p1, %rs1, %rs2;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB54_2;
@@ -2284,7 +2284,7 @@ define i32 @test_float16_ogt(half %a, half %b) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB54_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
entry:
%cmp = fcmp ogt half %a, %b
@@ -2314,8 +2314,8 @@ define i32 @test_float16_oge(half %a, half %b) {
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_float16_oge_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_float16_oge_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs2, [test_float16_oge_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_float16_oge_param_0];
; CHECK-NEXT: setp.ge.f16 %p1, %rs1, %rs2;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB55_2;
@@ -2326,7 +2326,7 @@ define i32 @test_float16_oge(half %a, half %b) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB55_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
entry:
%cmp = fcmp oge half %a, %b
@@ -2356,8 +2356,8 @@ define i32 @test_float16_ult(half %a, half %b) {
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_float16_ult_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_float16_ult_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs2, [test_float16_ult_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_float16_ult_param_0];
; CHECK-NEXT: setp.ltu.f16 %p1, %rs1, %rs2;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB56_2;
@@ -2368,7 +2368,7 @@ define i32 @test_float16_ult(half %a, half %b) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB56_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
entry:
%cmp = fcmp ult half %a, %b
@@ -2398,8 +2398,8 @@ define i32 @test_float16_ule(half %a, half %b) {
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_float16_ule_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_float16_ule_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs2, [test_float16_ule_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_float16_ule_param_0];
; CHECK-NEXT: setp.leu.f16 %p1, %rs1, %rs2;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB57_2;
@@ -2410,7 +2410,7 @@ define i32 @test_float16_ule(half %a, half %b) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB57_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
entry:
%cmp = fcmp ule half %a, %b
@@ -2440,8 +2440,8 @@ define i32 @test_float16_ugt(half %a, half %b) {
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_float16_ugt_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_float16_ugt_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs2, [test_float16_ugt_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_float16_ugt_param_0];
; CHECK-NEXT: setp.gtu.f16 %p1, %rs1, %rs2;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB58_2;
@@ -2452,7 +2452,7 @@ define i32 @test_float16_ugt(half %a, half %b) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB58_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
entry:
%cmp = fcmp ugt half %a, %b
@@ -2482,8 +2482,8 @@ define i32 @test_float16_uge(half %a, half %b) {
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_float16_uge_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_float16_uge_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs2, [test_float16_uge_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_float16_uge_param_0];
; CHECK-NEXT: setp.geu.f16 %p1, %rs1, %rs2;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB59_2;
@@ -2494,7 +2494,7 @@ define i32 @test_float16_uge(half %a, half %b) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB59_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
entry:
%cmp = fcmp uge half %a, %b
@@ -2524,8 +2524,8 @@ define i32 @test_float16_ord(half %a, half %b) {
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_float16_ord_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_float16_ord_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs2, [test_float16_ord_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_float16_ord_param_0];
; CHECK-NEXT: setp.num.f16 %p1, %rs1, %rs2;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @!%p1 bra $L__BB60_1;
@@ -2534,7 +2534,7 @@ define i32 @test_float16_ord(half %a, half %b) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB60_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
; CHECK-NEXT: $L__BB60_1: // %then
; CHECK-NEXT: mov.b32 %r1, 1;
@@ -2567,8 +2567,8 @@ define i32 @test_float16_uno(half %a, half %b) {
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_float16_uno_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_float16_uno_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs2, [test_float16_uno_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_float16_uno_param_0];
; CHECK-NEXT: setp.nan.f16 %p1, %rs1, %rs2;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB61_2;
@@ -2577,7 +2577,7 @@ define i32 @test_float16_uno(half %a, half %b) {
; CHECK-NEXT: $L__BB61_2: // %merge1
; CHECK-NEXT: @%p1 bra $L__BB61_3;
; CHECK-NEXT: $L__BB61_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
; CHECK-NEXT: $L__BB61_3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
@@ -2609,7 +2609,7 @@ define i32 @test_float32_eq(float %arg) {
; CHECK-NEXT: .reg .b32 %r<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b32 %r1, [test_float32_eq_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_float32_eq_param_0];
; CHECK-NEXT: setp.eq.f32 %p1, %r1, 0f00000000;
; CHECK-NEXT: mov.b32 %r2, 0;
; CHECK-NEXT: @%p1 bra $L__BB62_2;
@@ -2620,7 +2620,7 @@ define i32 @test_float32_eq(float %arg) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r2, 0;
; CHECK-NEXT: $L__BB62_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r2;
; CHECK-NEXT: ret;
entry:
%cmp = fcmp oeq float %arg, 0.000000e+00
@@ -2649,7 +2649,7 @@ define i32 @test_float32_ne(float %arg) {
; CHECK-NEXT: .reg .b32 %r<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b32 %r1, [test_float32_ne_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_float32_ne_param_0];
; CHECK-NEXT: setp.ne.f32 %p1, %r1, 0f00000000;
; CHECK-NEXT: mov.b32 %r2, 0;
; CHECK-NEXT: @%p1 bra $L__BB63_2;
@@ -2660,7 +2660,7 @@ define i32 @test_float32_ne(float %arg) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r2, 0;
; CHECK-NEXT: $L__BB63_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r2;
; CHECK-NEXT: ret;
entry:
%cmp = fcmp one float %arg, 0.000000e+00
@@ -2689,7 +2689,7 @@ define i32 @test_float32_oeq(float %arg) {
; CHECK-NEXT: .reg .b32 %r<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b32 %r1, [test_float32_oeq_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_float32_oeq_param_0];
; CHECK-NEXT: setp.eq.f32 %p1, %r1, 0f00000000;
; CHECK-NEXT: mov.b32 %r2, 0;
; CHECK-NEXT: @%p1 bra $L__BB64_2;
@@ -2700,7 +2700,7 @@ define i32 @test_float32_oeq(float %arg) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r2, 0;
; CHECK-NEXT: $L__BB64_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r2;
; CHECK-NEXT: ret;
entry:
%cmp = fcmp oeq float %arg, 0.000000e+00
@@ -2729,7 +2729,7 @@ define i32 @test_float32_one(float %arg) {
; CHECK-NEXT: .reg .b32 %r<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b32 %r1, [test_float32_one_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_float32_one_param_0];
; CHECK-NEXT: setp.ne.f32 %p1, %r1, 0f00000000;
; CHECK-NEXT: mov.b32 %r2, 0;
; CHECK-NEXT: @%p1 bra $L__BB65_2;
@@ -2740,7 +2740,7 @@ define i32 @test_float32_one(float %arg) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r2, 0;
; CHECK-NEXT: $L__BB65_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r2;
; CHECK-NEXT: ret;
entry:
%cmp = fcmp one float %arg, 0.000000e+00
@@ -2769,7 +2769,7 @@ define i32 @test_float32_ueq(float %arg) {
; CHECK-NEXT: .reg .b32 %r<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b32 %r1, [test_float32_ueq_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_float32_ueq_param_0];
; CHECK-NEXT: setp.equ.f32 %p1, %r1, 0f00000000;
; CHECK-NEXT: mov.b32 %r2, 0;
; CHECK-NEXT: @%p1 bra $L__BB66_2;
@@ -2780,7 +2780,7 @@ define i32 @test_float32_ueq(float %arg) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r2, 0;
; CHECK-NEXT: $L__BB66_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r2;
; CHECK-NEXT: ret;
entry:
%cmp = fcmp ueq float %arg, 0.000000e+00
@@ -2809,7 +2809,7 @@ define i32 @test_float32_une(float %arg) {
; CHECK-NEXT: .reg .b32 %r<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b32 %r1, [test_float32_une_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_float32_une_param_0];
; CHECK-NEXT: setp.neu.f32 %p1, %r1, 0f00000000;
; CHECK-NEXT: mov.b32 %r2, 0;
; CHECK-NEXT: @%p1 bra $L__BB67_2;
@@ -2820,7 +2820,7 @@ define i32 @test_float32_une(float %arg) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r2, 0;
; CHECK-NEXT: $L__BB67_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r2;
; CHECK-NEXT: ret;
entry:
%cmp = fcmp une float %arg, 0.000000e+00
@@ -2849,7 +2849,7 @@ define i32 @test_float32_olt(float %arg) {
; CHECK-NEXT: .reg .b32 %r<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b32 %r1, [test_float32_olt_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_float32_olt_param_0];
; CHECK-NEXT: setp.lt.f32 %p1, %r1, 0f00000000;
; CHECK-NEXT: mov.b32 %r2, 0;
; CHECK-NEXT: @%p1 bra $L__BB68_2;
@@ -2860,7 +2860,7 @@ define i32 @test_float32_olt(float %arg) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r2, 0;
; CHECK-NEXT: $L__BB68_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r2;
; CHECK-NEXT: ret;
entry:
%cmp = fcmp olt float %arg, 0.000000e+00
@@ -2889,7 +2889,7 @@ define i32 @test_float32_ole(float %arg) {
; CHECK-NEXT: .reg .b32 %r<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b32 %r1, [test_float32_ole_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_float32_ole_param_0];
; CHECK-NEXT: setp.le.f32 %p1, %r1, 0f00000000;
; CHECK-NEXT: mov.b32 %r2, 0;
; CHECK-NEXT: @%p1 bra $L__BB69_2;
@@ -2900,7 +2900,7 @@ define i32 @test_float32_ole(float %arg) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r2, 0;
; CHECK-NEXT: $L__BB69_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r2;
; CHECK-NEXT: ret;
entry:
%cmp = fcmp ole float %arg, 0.000000e+00
@@ -2929,7 +2929,7 @@ define i32 @test_float32_ogt(float %arg) {
; CHECK-NEXT: .reg .b32 %r<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b32 %r1, [test_float32_ogt_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_float32_ogt_param_0];
; CHECK-NEXT: setp.gt.f32 %p1, %r1, 0f00000000;
; CHECK-NEXT: mov.b32 %r2, 0;
; CHECK-NEXT: @%p1 bra $L__BB70_2;
@@ -2940,7 +2940,7 @@ define i32 @test_float32_ogt(float %arg) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r2, 0;
; CHECK-NEXT: $L__BB70_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r2;
; CHECK-NEXT: ret;
entry:
%cmp = fcmp ogt float %arg, 0.000000e+00
@@ -2969,7 +2969,7 @@ define i32 @test_float32_oge(float %arg) {
; CHECK-NEXT: .reg .b32 %r<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b32 %r1, [test_float32_oge_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_float32_oge_param_0];
; CHECK-NEXT: setp.ge.f32 %p1, %r1, 0f00000000;
; CHECK-NEXT: mov.b32 %r2, 0;
; CHECK-NEXT: @%p1 bra $L__BB71_2;
@@ -2980,7 +2980,7 @@ define i32 @test_float32_oge(float %arg) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r2, 0;
; CHECK-NEXT: $L__BB71_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r2;
; CHECK-NEXT: ret;
entry:
%cmp = fcmp oge float %arg, 0.000000e+00
@@ -3009,7 +3009,7 @@ define i32 @test_float32_ult(float %arg) {
; CHECK-NEXT: .reg .b32 %r<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b32 %r1, [test_float32_ult_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_float32_ult_param_0];
; CHECK-NEXT: setp.ltu.f32 %p1, %r1, 0f00000000;
; CHECK-NEXT: mov.b32 %r2, 0;
; CHECK-NEXT: @%p1 bra $L__BB72_2;
@@ -3020,7 +3020,7 @@ define i32 @test_float32_ult(float %arg) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r2, 0;
; CHECK-NEXT: $L__BB72_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r2;
; CHECK-NEXT: ret;
entry:
%cmp = fcmp ult float %arg, 0.000000e+00
@@ -3049,7 +3049,7 @@ define i32 @test_float32_ule(float %arg) {
; CHECK-NEXT: .reg .b32 %r<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b32 %r1, [test_float32_ule_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_float32_ule_param_0];
; CHECK-NEXT: setp.leu.f32 %p1, %r1, 0f00000000;
; CHECK-NEXT: mov.b32 %r2, 0;
; CHECK-NEXT: @%p1 bra $L__BB73_2;
@@ -3060,7 +3060,7 @@ define i32 @test_float32_ule(float %arg) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r2, 0;
; CHECK-NEXT: $L__BB73_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r2;
; CHECK-NEXT: ret;
entry:
%cmp = fcmp ule float %arg, 0.000000e+00
@@ -3089,7 +3089,7 @@ define i32 @test_float32_ugt(float %arg) {
; CHECK-NEXT: .reg .b32 %r<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b32 %r1, [test_float32_ugt_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_float32_ugt_param_0];
; CHECK-NEXT: setp.gtu.f32 %p1, %r1, 0f00000000;
; CHECK-NEXT: mov.b32 %r2, 0;
; CHECK-NEXT: @%p1 bra $L__BB74_2;
@@ -3100,7 +3100,7 @@ define i32 @test_float32_ugt(float %arg) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r2, 0;
; CHECK-NEXT: $L__BB74_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r2;
; CHECK-NEXT: ret;
entry:
%cmp = fcmp ugt float %arg, 0.000000e+00
@@ -3129,7 +3129,7 @@ define i32 @test_float32_uge(float %arg) {
; CHECK-NEXT: .reg .b32 %r<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b32 %r1, [test_float32_uge_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_float32_uge_param_0];
; CHECK-NEXT: setp.geu.f32 %p1, %r1, 0f00000000;
; CHECK-NEXT: mov.b32 %r2, 0;
; CHECK-NEXT: @%p1 bra $L__BB75_2;
@@ -3140,7 +3140,7 @@ define i32 @test_float32_uge(float %arg) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r2, 0;
; CHECK-NEXT: $L__BB75_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r2;
; CHECK-NEXT: ret;
entry:
%cmp = fcmp uge float %arg, 0.000000e+00
@@ -3169,7 +3169,7 @@ define i32 @test_float32_ord(float %arg) {
; CHECK-NEXT: .reg .b32 %r<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b32 %r1, [test_float32_ord_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_float32_ord_param_0];
; CHECK-NEXT: setp.num.f32 %p1, %r1, %r1;
; CHECK-NEXT: mov.b32 %r2, 0;
; CHECK-NEXT: @!%p1 bra $L__BB76_1;
@@ -3178,7 +3178,7 @@ define i32 @test_float32_ord(float %arg) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r2, 0;
; CHECK-NEXT: $L__BB76_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r2;
; CHECK-NEXT: ret;
; CHECK-NEXT: $L__BB76_1: // %then
; CHECK-NEXT: mov.b32 %r2, 1;
@@ -3210,7 +3210,7 @@ define i32 @test_float32_uno(float %arg) {
; CHECK-NEXT: .reg .b32 %r<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b32 %r1, [test_float32_uno_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_float32_uno_param_0];
; CHECK-NEXT: setp.nan.f32 %p1, %r1, %r1;
; CHECK-NEXT: mov.b32 %r2, 0;
; CHECK-NEXT: @%p1 bra $L__BB77_2;
@@ -3219,7 +3219,7 @@ define i32 @test_float32_uno(float %arg) {
; CHECK-NEXT: $L__BB77_2: // %merge1
; CHECK-NEXT: @%p1 bra $L__BB77_3;
; CHECK-NEXT: $L__BB77_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r2;
; CHECK-NEXT: ret;
; CHECK-NEXT: $L__BB77_3: // %else
; CHECK-NEXT: mov.b32 %r2, 0;
@@ -3252,7 +3252,7 @@ define i32 @test_float64_eq(double %arg) {
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b64 %rd1, [test_float64_eq_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_float64_eq_param_0];
; CHECK-NEXT: setp.eq.f64 %p1, %rd1, 0d0000000000000000;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB78_2;
@@ -3263,7 +3263,7 @@ define i32 @test_float64_eq(double %arg) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB78_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
entry:
%cmp = fcmp oeq double %arg, 0.000000e+00
@@ -3293,7 +3293,7 @@ define i32 @test_float64_ne(double %arg) {
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b64 %rd1, [test_float64_ne_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_float64_ne_param_0];
; CHECK-NEXT: setp.ne.f64 %p1, %rd1, 0d0000000000000000;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB79_2;
@@ -3304,7 +3304,7 @@ define i32 @test_float64_ne(double %arg) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB79_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
entry:
%cmp = fcmp one double %arg, 0.000000e+00
@@ -3334,7 +3334,7 @@ define i32 @test_float64_oeq(double %arg) {
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b64 %rd1, [test_float64_oeq_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_float64_oeq_param_0];
; CHECK-NEXT: setp.eq.f64 %p1, %rd1, 0d0000000000000000;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB80_2;
@@ -3345,7 +3345,7 @@ define i32 @test_float64_oeq(double %arg) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB80_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
entry:
%cmp = fcmp oeq double %arg, 0.000000e+00
@@ -3375,7 +3375,7 @@ define i32 @test_float64_one(double %arg) {
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b64 %rd1, [test_float64_one_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_float64_one_param_0];
; CHECK-NEXT: setp.ne.f64 %p1, %rd1, 0d0000000000000000;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB81_2;
@@ -3386,7 +3386,7 @@ define i32 @test_float64_one(double %arg) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB81_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
entry:
%cmp = fcmp one double %arg, 0.000000e+00
@@ -3416,7 +3416,7 @@ define i32 @test_float64_ueq(double %arg) {
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b64 %rd1, [test_float64_ueq_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_float64_ueq_param_0];
; CHECK-NEXT: setp.equ.f64 %p1, %rd1, 0d0000000000000000;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB82_2;
@@ -3427,7 +3427,7 @@ define i32 @test_float64_ueq(double %arg) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB82_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
entry:
%cmp = fcmp ueq double %arg, 0.000000e+00
@@ -3457,7 +3457,7 @@ define i32 @test_float64_une(double %arg) {
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b64 %rd1, [test_float64_une_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_float64_une_param_0];
; CHECK-NEXT: setp.neu.f64 %p1, %rd1, 0d0000000000000000;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB83_2;
@@ -3468,7 +3468,7 @@ define i32 @test_float64_une(double %arg) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB83_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
entry:
%cmp = fcmp une double %arg, 0.000000e+00
@@ -3498,7 +3498,7 @@ define i32 @test_float64_olt(double %arg) {
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b64 %rd1, [test_float64_olt_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_float64_olt_param_0];
; CHECK-NEXT: setp.lt.f64 %p1, %rd1, 0d0000000000000000;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB84_2;
@@ -3509,7 +3509,7 @@ define i32 @test_float64_olt(double %arg) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB84_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
entry:
%cmp = fcmp olt double %arg, 0.000000e+00
@@ -3539,7 +3539,7 @@ define i32 @test_float64_ole(double %arg) {
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b64 %rd1, [test_float64_ole_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_float64_ole_param_0];
; CHECK-NEXT: setp.le.f64 %p1, %rd1, 0d0000000000000000;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB85_2;
@@ -3550,7 +3550,7 @@ define i32 @test_float64_ole(double %arg) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB85_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
entry:
%cmp = fcmp ole double %arg, 0.000000e+00
@@ -3580,7 +3580,7 @@ define i32 @test_float64_ogt(double %arg) {
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b64 %rd1, [test_float64_ogt_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_float64_ogt_param_0];
; CHECK-NEXT: setp.gt.f64 %p1, %rd1, 0d0000000000000000;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB86_2;
@@ -3591,7 +3591,7 @@ define i32 @test_float64_ogt(double %arg) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB86_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
entry:
%cmp = fcmp ogt double %arg, 0.000000e+00
@@ -3621,7 +3621,7 @@ define i32 @test_float64_oge(double %arg) {
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b64 %rd1, [test_float64_oge_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_float64_oge_param_0];
; CHECK-NEXT: setp.ge.f64 %p1, %rd1, 0d0000000000000000;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB87_2;
@@ -3632,7 +3632,7 @@ define i32 @test_float64_oge(double %arg) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB87_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
entry:
%cmp = fcmp oge double %arg, 0.000000e+00
@@ -3662,7 +3662,7 @@ define i32 @test_float64_ult(double %arg) {
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b64 %rd1, [test_float64_ult_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_float64_ult_param_0];
; CHECK-NEXT: setp.ltu.f64 %p1, %rd1, 0d0000000000000000;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB88_2;
@@ -3673,7 +3673,7 @@ define i32 @test_float64_ult(double %arg) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB88_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
entry:
%cmp = fcmp ult double %arg, 0.000000e+00
@@ -3703,7 +3703,7 @@ define i32 @test_float64_ule(double %arg) {
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b64 %rd1, [test_float64_ule_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_float64_ule_param_0];
; CHECK-NEXT: setp.leu.f64 %p1, %rd1, 0d0000000000000000;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB89_2;
@@ -3714,7 +3714,7 @@ define i32 @test_float64_ule(double %arg) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB89_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
entry:
%cmp = fcmp ule double %arg, 0.000000e+00
@@ -3744,7 +3744,7 @@ define i32 @test_float64_ugt(double %arg) {
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b64 %rd1, [test_float64_ugt_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_float64_ugt_param_0];
; CHECK-NEXT: setp.gtu.f64 %p1, %rd1, 0d0000000000000000;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB90_2;
@@ -3755,7 +3755,7 @@ define i32 @test_float64_ugt(double %arg) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB90_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
entry:
%cmp = fcmp ugt double %arg, 0.000000e+00
@@ -3785,7 +3785,7 @@ define i32 @test_float64_uge(double %arg) {
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b64 %rd1, [test_float64_uge_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_float64_uge_param_0];
; CHECK-NEXT: setp.geu.f64 %p1, %rd1, 0d0000000000000000;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB91_2;
@@ -3796,7 +3796,7 @@ define i32 @test_float64_uge(double %arg) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB91_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
entry:
%cmp = fcmp uge double %arg, 0.000000e+00
@@ -3826,7 +3826,7 @@ define i32 @test_float64_ord(double %arg) {
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b64 %rd1, [test_float64_ord_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_float64_ord_param_0];
; CHECK-NEXT: setp.num.f64 %p1, %rd1, %rd1;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @!%p1 bra $L__BB92_1;
@@ -3835,7 +3835,7 @@ define i32 @test_float64_ord(double %arg) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB92_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
; CHECK-NEXT: $L__BB92_1: // %then
; CHECK-NEXT: mov.b32 %r1, 1;
@@ -3868,7 +3868,7 @@ define i32 @test_float64_uno(double %arg) {
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b64 %rd1, [test_float64_uno_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_float64_uno_param_0];
; CHECK-NEXT: setp.nan.f64 %p1, %rd1, %rd1;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB93_2;
@@ -3877,7 +3877,7 @@ define i32 @test_float64_uno(double %arg) {
; CHECK-NEXT: $L__BB93_2: // %merge1
; CHECK-NEXT: @%p1 bra $L__BB93_3;
; CHECK-NEXT: $L__BB93_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
; CHECK-NEXT: $L__BB93_3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
diff --git a/llvm/test/CodeGen/NVPTX/machine-cse-predicate-no-inversion.ll b/llvm/test/CodeGen/NVPTX/machine-cse-predicate-no-inversion.ll
index ce8eac39c4644..299ef67dc934e 100644
--- a/llvm/test/CodeGen/NVPTX/machine-cse-predicate-no-inversion.ll
+++ b/llvm/test/CodeGen/NVPTX/machine-cse-predicate-no-inversion.ll
@@ -12,8 +12,8 @@ define i32 @test_int16_slt_vs_sgt(i16 %a, i16 %b) {
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_int16_slt_vs_sgt_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_int16_slt_vs_sgt_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs2, [test_int16_slt_vs_sgt_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_int16_slt_vs_sgt_param_0];
; CHECK-NEXT: setp.lt.s16 %p1, %rs1, %rs2;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB0_2;
@@ -25,7 +25,7 @@ define i32 @test_int16_slt_vs_sgt(i16 %a, i16 %b) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB0_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
entry:
%cmp = icmp slt i16 %a, %b
@@ -55,8 +55,8 @@ define i32 @test_int16_ult_vs_ugt(i16 %a, i16 %b) {
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_int16_ult_vs_ugt_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_int16_ult_vs_ugt_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs2, [test_int16_ult_vs_ugt_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_int16_ult_vs_ugt_param_0];
; CHECK-NEXT: setp.lt.u16 %p1, %rs1, %rs2;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB1_2;
@@ -68,7 +68,7 @@ define i32 @test_int16_ult_vs_ugt(i16 %a, i16 %b) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB1_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
entry:
%cmp = icmp ult i16 %a, %b
@@ -98,8 +98,8 @@ define i32 @test_int16_slt_vs_uge(i16 %a, i16 %b) {
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_int16_slt_vs_uge_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_int16_slt_vs_uge_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs2, [test_int16_slt_vs_uge_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_int16_slt_vs_uge_param_0];
; CHECK-NEXT: setp.lt.s16 %p1, %rs1, %rs2;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB2_2;
@@ -111,7 +111,7 @@ define i32 @test_int16_slt_vs_uge(i16 %a, i16 %b) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB2_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
entry:
%cmp = icmp slt i16 %a, %b
@@ -141,8 +141,8 @@ define i32 @test_int16_eq_vs_slt(i16 %a, i16 %b) {
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_int16_eq_vs_slt_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_int16_eq_vs_slt_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs2, [test_int16_eq_vs_slt_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_int16_eq_vs_slt_param_0];
; CHECK-NEXT: setp.eq.b16 %p1, %rs1, %rs2;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB3_2;
@@ -154,7 +154,7 @@ define i32 @test_int16_eq_vs_slt(i16 %a, i16 %b) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB3_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
entry:
%cmp = icmp eq i16 %a, %b
@@ -184,8 +184,8 @@ define i32 @test_int16_ult_vs_sge(i16 %a, i16 %b) {
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_int16_ult_vs_sge_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_int16_ult_vs_sge_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs2, [test_int16_ult_vs_sge_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_int16_ult_vs_sge_param_0];
; CHECK-NEXT: setp.lt.u16 %p1, %rs1, %rs2;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB4_2;
@@ -197,7 +197,7 @@ define i32 @test_int16_ult_vs_sge(i16 %a, i16 %b) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB4_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
entry:
%cmp = icmp ult i16 %a, %b
@@ -226,8 +226,8 @@ define i32 @test_int32_slt_vs_sgt(i32 %a, i32 %b) {
; CHECK-NEXT: .reg .b32 %r<4>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b32 %r2, [test_int32_slt_vs_sgt_param_1];
-; CHECK-NEXT: ld.param.b32 %r1, [test_int32_slt_vs_sgt_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r2, [test_int32_slt_vs_sgt_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_int32_slt_vs_sgt_param_0];
; CHECK-NEXT: setp.lt.s32 %p1, %r1, %r2;
; CHECK-NEXT: mov.b32 %r3, 0;
; CHECK-NEXT: @%p1 bra $L__BB5_2;
@@ -239,7 +239,7 @@ define i32 @test_int32_slt_vs_sgt(i32 %a, i32 %b) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r3, 0;
; CHECK-NEXT: $L__BB5_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r3;
; CHECK-NEXT: ret;
entry:
%cmp = icmp slt i32 %a, %b
@@ -268,8 +268,8 @@ define i32 @test_int32_ult_vs_ugt(i32 %a, i32 %b) {
; CHECK-NEXT: .reg .b32 %r<4>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b32 %r2, [test_int32_ult_vs_ugt_param_1];
-; CHECK-NEXT: ld.param.b32 %r1, [test_int32_ult_vs_ugt_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r2, [test_int32_ult_vs_ugt_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_int32_ult_vs_ugt_param_0];
; CHECK-NEXT: setp.lt.u32 %p1, %r1, %r2;
; CHECK-NEXT: mov.b32 %r3, 0;
; CHECK-NEXT: @%p1 bra $L__BB6_2;
@@ -281,7 +281,7 @@ define i32 @test_int32_ult_vs_ugt(i32 %a, i32 %b) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r3, 0;
; CHECK-NEXT: $L__BB6_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r3;
; CHECK-NEXT: ret;
entry:
%cmp = icmp ult i32 %a, %b
@@ -310,8 +310,8 @@ define i32 @test_int32_slt_vs_uge(i32 %a, i32 %b) {
; CHECK-NEXT: .reg .b32 %r<4>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b32 %r2, [test_int32_slt_vs_uge_param_1];
-; CHECK-NEXT: ld.param.b32 %r1, [test_int32_slt_vs_uge_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r2, [test_int32_slt_vs_uge_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_int32_slt_vs_uge_param_0];
; CHECK-NEXT: setp.lt.s32 %p1, %r1, %r2;
; CHECK-NEXT: mov.b32 %r3, 0;
; CHECK-NEXT: @%p1 bra $L__BB7_2;
@@ -323,7 +323,7 @@ define i32 @test_int32_slt_vs_uge(i32 %a, i32 %b) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r3, 0;
; CHECK-NEXT: $L__BB7_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r3;
; CHECK-NEXT: ret;
entry:
%cmp = icmp slt i32 %a, %b
@@ -352,8 +352,8 @@ define i32 @test_int32_eq_vs_slt(i32 %a, i32 %b) {
; CHECK-NEXT: .reg .b32 %r<4>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b32 %r2, [test_int32_eq_vs_slt_param_1];
-; CHECK-NEXT: ld.param.b32 %r1, [test_int32_eq_vs_slt_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r2, [test_int32_eq_vs_slt_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_int32_eq_vs_slt_param_0];
; CHECK-NEXT: setp.eq.b32 %p1, %r1, %r2;
; CHECK-NEXT: mov.b32 %r3, 0;
; CHECK-NEXT: @%p1 bra $L__BB8_2;
@@ -365,7 +365,7 @@ define i32 @test_int32_eq_vs_slt(i32 %a, i32 %b) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r3, 0;
; CHECK-NEXT: $L__BB8_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r3;
; CHECK-NEXT: ret;
entry:
%cmp = icmp eq i32 %a, %b
@@ -394,8 +394,8 @@ define i32 @test_int32_ult_vs_sge(i32 %a, i32 %b) {
; CHECK-NEXT: .reg .b32 %r<4>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b32 %r2, [test_int32_ult_vs_sge_param_1];
-; CHECK-NEXT: ld.param.b32 %r1, [test_int32_ult_vs_sge_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r2, [test_int32_ult_vs_sge_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_int32_ult_vs_sge_param_0];
; CHECK-NEXT: setp.lt.u32 %p1, %r1, %r2;
; CHECK-NEXT: mov.b32 %r3, 0;
; CHECK-NEXT: @%p1 bra $L__BB9_2;
@@ -407,7 +407,7 @@ define i32 @test_int32_ult_vs_sge(i32 %a, i32 %b) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r3, 0;
; CHECK-NEXT: $L__BB9_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r3;
; CHECK-NEXT: ret;
entry:
%cmp = icmp ult i32 %a, %b
@@ -437,8 +437,8 @@ define i32 @test_int64_slt_vs_sgt(i64 %a, i64 %b) {
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b64 %rd2, [test_int64_slt_vs_sgt_param_1];
-; CHECK-NEXT: ld.param.b64 %rd1, [test_int64_slt_vs_sgt_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [test_int64_slt_vs_sgt_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_int64_slt_vs_sgt_param_0];
; CHECK-NEXT: setp.lt.s64 %p1, %rd1, %rd2;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB10_2;
@@ -450,7 +450,7 @@ define i32 @test_int64_slt_vs_sgt(i64 %a, i64 %b) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB10_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
entry:
%cmp = icmp slt i64 %a, %b
@@ -480,8 +480,8 @@ define i32 @test_int64_ult_vs_ugt(i64 %a, i64 %b) {
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b64 %rd2, [test_int64_ult_vs_ugt_param_1];
-; CHECK-NEXT: ld.param.b64 %rd1, [test_int64_ult_vs_ugt_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [test_int64_ult_vs_ugt_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_int64_ult_vs_ugt_param_0];
; CHECK-NEXT: setp.lt.u64 %p1, %rd1, %rd2;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB11_2;
@@ -493,7 +493,7 @@ define i32 @test_int64_ult_vs_ugt(i64 %a, i64 %b) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB11_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
entry:
%cmp = icmp ult i64 %a, %b
@@ -523,8 +523,8 @@ define i32 @test_int64_slt_vs_uge(i64 %a, i64 %b) {
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b64 %rd2, [test_int64_slt_vs_uge_param_1];
-; CHECK-NEXT: ld.param.b64 %rd1, [test_int64_slt_vs_uge_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [test_int64_slt_vs_uge_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_int64_slt_vs_uge_param_0];
; CHECK-NEXT: setp.lt.s64 %p1, %rd1, %rd2;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB12_2;
@@ -536,7 +536,7 @@ define i32 @test_int64_slt_vs_uge(i64 %a, i64 %b) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB12_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
entry:
%cmp = icmp slt i64 %a, %b
@@ -566,8 +566,8 @@ define i32 @test_int64_eq_vs_slt(i64 %a, i64 %b) {
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b64 %rd2, [test_int64_eq_vs_slt_param_1];
-; CHECK-NEXT: ld.param.b64 %rd1, [test_int64_eq_vs_slt_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [test_int64_eq_vs_slt_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_int64_eq_vs_slt_param_0];
; CHECK-NEXT: setp.eq.b64 %p1, %rd1, %rd2;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB13_2;
@@ -579,7 +579,7 @@ define i32 @test_int64_eq_vs_slt(i64 %a, i64 %b) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB13_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
entry:
%cmp = icmp eq i64 %a, %b
@@ -609,8 +609,8 @@ define i32 @test_int64_ult_vs_sge(i64 %a, i64 %b) {
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b64 %rd2, [test_int64_ult_vs_sge_param_1];
-; CHECK-NEXT: ld.param.b64 %rd1, [test_int64_ult_vs_sge_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [test_int64_ult_vs_sge_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_int64_ult_vs_sge_param_0];
; CHECK-NEXT: setp.lt.u64 %p1, %rd1, %rd2;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB14_2;
@@ -622,7 +622,7 @@ define i32 @test_int64_ult_vs_sge(i64 %a, i64 %b) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB14_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
entry:
%cmp = icmp ult i64 %a, %b
@@ -652,8 +652,8 @@ define i32 @test_bfloat16_ueq_vs_une(bfloat %a, bfloat %b) {
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_bfloat16_ueq_vs_une_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_bfloat16_ueq_vs_une_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs2, [test_bfloat16_ueq_vs_une_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_bfloat16_ueq_vs_une_param_0];
; CHECK-NEXT: setp.equ.bf16 %p1, %rs1, %rs2;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB15_2;
@@ -665,7 +665,7 @@ define i32 @test_bfloat16_ueq_vs_une(bfloat %a, bfloat %b) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB15_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
entry:
%cmp = fcmp ueq bfloat %a, %b
@@ -695,8 +695,8 @@ define i32 @test_bfloat16_oeq_vs_one(bfloat %a, bfloat %b) {
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_bfloat16_oeq_vs_one_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_bfloat16_oeq_vs_one_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs2, [test_bfloat16_oeq_vs_one_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_bfloat16_oeq_vs_one_param_0];
; CHECK-NEXT: setp.eq.bf16 %p1, %rs1, %rs2;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB16_2;
@@ -708,7 +708,7 @@ define i32 @test_bfloat16_oeq_vs_one(bfloat %a, bfloat %b) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB16_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
entry:
%cmp = fcmp oeq bfloat %a, %b
@@ -738,8 +738,8 @@ define i32 @test_bfloat16_olt_vs_ogt(bfloat %a, bfloat %b) {
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_bfloat16_olt_vs_ogt_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_bfloat16_olt_vs_ogt_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs2, [test_bfloat16_olt_vs_ogt_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_bfloat16_olt_vs_ogt_param_0];
; CHECK-NEXT: setp.lt.bf16 %p1, %rs1, %rs2;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB17_2;
@@ -751,7 +751,7 @@ define i32 @test_bfloat16_olt_vs_ogt(bfloat %a, bfloat %b) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB17_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
entry:
%cmp = fcmp olt bfloat %a, %b
@@ -781,8 +781,8 @@ define i32 @test_bfloat16_ult_vs_ugt(bfloat %a, bfloat %b) {
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_bfloat16_ult_vs_ugt_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_bfloat16_ult_vs_ugt_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs2, [test_bfloat16_ult_vs_ugt_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_bfloat16_ult_vs_ugt_param_0];
; CHECK-NEXT: setp.ltu.bf16 %p1, %rs1, %rs2;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB18_2;
@@ -794,7 +794,7 @@ define i32 @test_bfloat16_ult_vs_ugt(bfloat %a, bfloat %b) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB18_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
entry:
%cmp = fcmp ult bfloat %a, %b
@@ -824,8 +824,8 @@ define i32 @test_bfloat16_oeq_vs_olt(bfloat %a, bfloat %b) {
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_bfloat16_oeq_vs_olt_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_bfloat16_oeq_vs_olt_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs2, [test_bfloat16_oeq_vs_olt_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_bfloat16_oeq_vs_olt_param_0];
; CHECK-NEXT: setp.eq.bf16 %p1, %rs1, %rs2;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB19_2;
@@ -837,7 +837,7 @@ define i32 @test_bfloat16_oeq_vs_olt(bfloat %a, bfloat %b) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB19_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
entry:
%cmp = fcmp oeq bfloat %a, %b
@@ -867,8 +867,8 @@ define i32 @test_float16_ueq_vs_une(half %a, half %b) {
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_float16_ueq_vs_une_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_float16_ueq_vs_une_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs2, [test_float16_ueq_vs_une_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_float16_ueq_vs_une_param_0];
; CHECK-NEXT: setp.equ.f16 %p1, %rs1, %rs2;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB20_2;
@@ -880,7 +880,7 @@ define i32 @test_float16_ueq_vs_une(half %a, half %b) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB20_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
entry:
%cmp = fcmp ueq half %a, %b
@@ -910,8 +910,8 @@ define i32 @test_float16_oeq_vs_one(half %a, half %b) {
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_float16_oeq_vs_one_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_float16_oeq_vs_one_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs2, [test_float16_oeq_vs_one_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_float16_oeq_vs_one_param_0];
; CHECK-NEXT: setp.eq.f16 %p1, %rs1, %rs2;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB21_2;
@@ -923,7 +923,7 @@ define i32 @test_float16_oeq_vs_one(half %a, half %b) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB21_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
entry:
%cmp = fcmp oeq half %a, %b
@@ -953,8 +953,8 @@ define i32 @test_float16_olt_vs_ogt(half %a, half %b) {
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_float16_olt_vs_ogt_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_float16_olt_vs_ogt_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs2, [test_float16_olt_vs_ogt_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_float16_olt_vs_ogt_param_0];
; CHECK-NEXT: setp.lt.f16 %p1, %rs1, %rs2;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB22_2;
@@ -966,7 +966,7 @@ define i32 @test_float16_olt_vs_ogt(half %a, half %b) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB22_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
entry:
%cmp = fcmp olt half %a, %b
@@ -996,8 +996,8 @@ define i32 @test_float16_ult_vs_ugt(half %a, half %b) {
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_float16_ult_vs_ugt_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_float16_ult_vs_ugt_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs2, [test_float16_ult_vs_ugt_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_float16_ult_vs_ugt_param_0];
; CHECK-NEXT: setp.ltu.f16 %p1, %rs1, %rs2;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB23_2;
@@ -1009,7 +1009,7 @@ define i32 @test_float16_ult_vs_ugt(half %a, half %b) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB23_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
entry:
%cmp = fcmp ult half %a, %b
@@ -1039,8 +1039,8 @@ define i32 @test_float16_oeq_vs_olt(half %a, half %b) {
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_float16_oeq_vs_olt_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_float16_oeq_vs_olt_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs2, [test_float16_oeq_vs_olt_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_float16_oeq_vs_olt_param_0];
; CHECK-NEXT: setp.eq.f16 %p1, %rs1, %rs2;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB24_2;
@@ -1052,7 +1052,7 @@ define i32 @test_float16_oeq_vs_olt(half %a, half %b) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB24_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
entry:
%cmp = fcmp oeq half %a, %b
@@ -1081,7 +1081,7 @@ define i32 @test_float32_ueq_vs_une(float %arg) {
; CHECK-NEXT: .reg .b32 %r<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b32 %r1, [test_float32_ueq_vs_une_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_float32_ueq_vs_une_param_0];
; CHECK-NEXT: setp.equ.f32 %p1, %r1, 0f00000000;
; CHECK-NEXT: mov.b32 %r2, 0;
; CHECK-NEXT: @%p1 bra $L__BB25_2;
@@ -1093,7 +1093,7 @@ define i32 @test_float32_ueq_vs_une(float %arg) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r2, 0;
; CHECK-NEXT: $L__BB25_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r2;
; CHECK-NEXT: ret;
entry:
%cmp = fcmp ueq float %arg, 0.000000e+00
@@ -1122,7 +1122,7 @@ define i32 @test_float32_oeq_vs_one(float %arg) {
; CHECK-NEXT: .reg .b32 %r<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b32 %r1, [test_float32_oeq_vs_one_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_float32_oeq_vs_one_param_0];
; CHECK-NEXT: setp.eq.f32 %p1, %r1, 0f00000000;
; CHECK-NEXT: mov.b32 %r2, 0;
; CHECK-NEXT: @%p1 bra $L__BB26_2;
@@ -1134,7 +1134,7 @@ define i32 @test_float32_oeq_vs_one(float %arg) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r2, 0;
; CHECK-NEXT: $L__BB26_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r2;
; CHECK-NEXT: ret;
entry:
%cmp = fcmp oeq float %arg, 0.000000e+00
@@ -1163,7 +1163,7 @@ define i32 @test_float32_olt_vs_ogt(float %arg) {
; CHECK-NEXT: .reg .b32 %r<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b32 %r1, [test_float32_olt_vs_ogt_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_float32_olt_vs_ogt_param_0];
; CHECK-NEXT: setp.lt.f32 %p1, %r1, 0f00000000;
; CHECK-NEXT: mov.b32 %r2, 0;
; CHECK-NEXT: @%p1 bra $L__BB27_2;
@@ -1175,7 +1175,7 @@ define i32 @test_float32_olt_vs_ogt(float %arg) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r2, 0;
; CHECK-NEXT: $L__BB27_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r2;
; CHECK-NEXT: ret;
entry:
%cmp = fcmp olt float %arg, 0.000000e+00
@@ -1204,7 +1204,7 @@ define i32 @test_float32_ult_vs_ugt(float %arg) {
; CHECK-NEXT: .reg .b32 %r<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b32 %r1, [test_float32_ult_vs_ugt_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_float32_ult_vs_ugt_param_0];
; CHECK-NEXT: setp.ltu.f32 %p1, %r1, 0f00000000;
; CHECK-NEXT: mov.b32 %r2, 0;
; CHECK-NEXT: @%p1 bra $L__BB28_2;
@@ -1216,7 +1216,7 @@ define i32 @test_float32_ult_vs_ugt(float %arg) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r2, 0;
; CHECK-NEXT: $L__BB28_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r2;
; CHECK-NEXT: ret;
entry:
%cmp = fcmp ult float %arg, 0.000000e+00
@@ -1245,7 +1245,7 @@ define i32 @test_float32_oeq_vs_olt(float %arg) {
; CHECK-NEXT: .reg .b32 %r<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b32 %r1, [test_float32_oeq_vs_olt_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_float32_oeq_vs_olt_param_0];
; CHECK-NEXT: setp.eq.f32 %p1, %r1, 0f00000000;
; CHECK-NEXT: mov.b32 %r2, 0;
; CHECK-NEXT: @%p1 bra $L__BB29_2;
@@ -1257,7 +1257,7 @@ define i32 @test_float32_oeq_vs_olt(float %arg) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r2, 0;
; CHECK-NEXT: $L__BB29_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r2;
; CHECK-NEXT: ret;
entry:
%cmp = fcmp oeq float %arg, 0.000000e+00
@@ -1287,7 +1287,7 @@ define i32 @test_float64_ueq_vs_une(double %arg) {
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b64 %rd1, [test_float64_ueq_vs_une_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_float64_ueq_vs_une_param_0];
; CHECK-NEXT: setp.equ.f64 %p1, %rd1, 0d0000000000000000;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB30_2;
@@ -1299,7 +1299,7 @@ define i32 @test_float64_ueq_vs_une(double %arg) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB30_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
entry:
%cmp = fcmp ueq double %arg, 0.000000e+00
@@ -1329,7 +1329,7 @@ define i32 @test_float64_oeq_vs_one(double %arg) {
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b64 %rd1, [test_float64_oeq_vs_one_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_float64_oeq_vs_one_param_0];
; CHECK-NEXT: setp.eq.f64 %p1, %rd1, 0d0000000000000000;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB31_2;
@@ -1341,7 +1341,7 @@ define i32 @test_float64_oeq_vs_one(double %arg) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB31_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
entry:
%cmp = fcmp oeq double %arg, 0.000000e+00
@@ -1371,7 +1371,7 @@ define i32 @test_float64_olt_vs_ogt(double %arg) {
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b64 %rd1, [test_float64_olt_vs_ogt_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_float64_olt_vs_ogt_param_0];
; CHECK-NEXT: setp.lt.f64 %p1, %rd1, 0d0000000000000000;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB32_2;
@@ -1383,7 +1383,7 @@ define i32 @test_float64_olt_vs_ogt(double %arg) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB32_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
entry:
%cmp = fcmp olt double %arg, 0.000000e+00
@@ -1413,7 +1413,7 @@ define i32 @test_float64_ult_vs_ugt(double %arg) {
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b64 %rd1, [test_float64_ult_vs_ugt_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_float64_ult_vs_ugt_param_0];
; CHECK-NEXT: setp.ltu.f64 %p1, %rd1, 0d0000000000000000;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB33_2;
@@ -1425,7 +1425,7 @@ define i32 @test_float64_ult_vs_ugt(double %arg) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB33_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
entry:
%cmp = fcmp ult double %arg, 0.000000e+00
@@ -1455,7 +1455,7 @@ define i32 @test_float64_oeq_vs_olt(double %arg) {
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b64 %rd1, [test_float64_oeq_vs_olt_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_float64_oeq_vs_olt_param_0];
; CHECK-NEXT: setp.eq.f64 %p1, %rd1, 0d0000000000000000;
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: @%p1 bra $L__BB34_2;
@@ -1467,7 +1467,7 @@ define i32 @test_float64_oeq_vs_olt(double %arg) {
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r1, 0;
; CHECK-NEXT: $L__BB34_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
entry:
%cmp = fcmp oeq double %arg, 0.000000e+00
diff --git a/llvm/test/CodeGen/NVPTX/masked-load-3xhalf.ll b/llvm/test/CodeGen/NVPTX/masked-load-3xhalf.ll
index 8f150e29d95b5..dc69b778232a4 100644
--- a/llvm/test/CodeGen/NVPTX/masked-load-3xhalf.ll
+++ b/llvm/test/CodeGen/NVPTX/masked-load-3xhalf.ll
@@ -13,7 +13,7 @@ define void @halfx3_extend_chain(ptr align 16 captures(none) %rd0) {
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [halfx3_extend_chain_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [halfx3_extend_chain_param_0];
; CHECK-NEXT: .pragma "used_bytes_mask 0xfff";
; CHECK-NEXT: ld.v4.b32 {%r1, %r2, %r3, %r4}, [%rd1];
; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r3;
@@ -58,7 +58,7 @@ define void @halfx3_no_align(ptr align 4 captures(none) %rd0) {
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [halfx3_no_align_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [halfx3_no_align_param_0];
; CHECK-NEXT: ld.b16 %rs1, [%rd1+4];
; CHECK-NEXT: ld.v2.b16 {%rs2, %rs3}, [%rd1];
; CHECK-NEXT: mov.b16 %rs4, 0x0000;
diff --git a/llvm/test/CodeGen/NVPTX/masked-load-vectors.ll b/llvm/test/CodeGen/NVPTX/masked-load-vectors.ll
index 3f72ffe71b622..7d97c45ffd827 100644
--- a/llvm/test/CodeGen/NVPTX/masked-load-vectors.ll
+++ b/llvm/test/CodeGen/NVPTX/masked-load-vectors.ll
@@ -17,12 +17,12 @@ define void @global_8xi32(ptr addrspace(1) %a, ptr addrspace(1) %b) {
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [global_8xi32_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd1, [global_8xi32_param_0];
; SM90-NEXT: .pragma "used_bytes_mask 0xf000";
; SM90-NEXT: ld.global.v4.b32 {%r1, %r2, %r3, %r4}, [%rd1+16];
; SM90-NEXT: .pragma "used_bytes_mask 0xf0f";
; SM90-NEXT: ld.global.v4.b32 {%r5, %r6, %r7, %r8}, [%rd1];
-; SM90-NEXT: ld.param.b64 %rd2, [global_8xi32_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd2, [global_8xi32_param_1];
; SM90-NEXT: st.global.b32 [%rd2], %r5;
; SM90-NEXT: st.global.b32 [%rd2+8], %r7;
; SM90-NEXT: st.global.b32 [%rd2+28], %r4;
@@ -34,10 +34,10 @@ define void @global_8xi32(ptr addrspace(1) %a, ptr addrspace(1) %b) {
; SM100-NEXT: .reg .b64 %rd<3>;
; SM100-EMPTY:
; SM100-NEXT: // %bb.0:
-; SM100-NEXT: ld.param.b64 %rd1, [global_8xi32_param_0];
+; SM100-NEXT: ld.param::func.b64 %rd1, [global_8xi32_param_0];
; SM100-NEXT: .pragma "used_bytes_mask 0xf0000f0f";
; SM100-NEXT: ld.global.v8.b32 {%r1, %r2, %r3, %r4, %r5, %r6, %r7, %r8}, [%rd1];
-; SM100-NEXT: ld.param.b64 %rd2, [global_8xi32_param_1];
+; SM100-NEXT: ld.param::func.b64 %rd2, [global_8xi32_param_1];
; SM100-NEXT: st.global.v8.b32 [%rd2], {%r1, _, %r3, _, _, _, _, %r8};
; SM100-NEXT: ret;
%a.load = tail call <8 x i32> @llvm.masked.load.v8i32.p1(ptr addrspace(1) align 32 %a, <8 x i1> <i1 true, i1 false, i1 true, i1 false, i1 false, i1 false, i1 false, i1 true>, <8 x i32> poison)
@@ -55,7 +55,7 @@ define void @global_16xi16(ptr addrspace(1) %a, ptr addrspace(1) %b) {
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [global_16xi16_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd1, [global_16xi16_param_0];
; SM90-NEXT: .pragma "used_bytes_mask 0xf000";
; SM90-NEXT: ld.global.v4.b32 {%r1, %r2, %r3, %r4}, [%rd1+16];
; SM90-NEXT: mov.b32 {%rs1, %rs2}, %r4;
@@ -63,7 +63,7 @@ define void @global_16xi16(ptr addrspace(1) %a, ptr addrspace(1) %b) {
; SM90-NEXT: ld.global.v4.b32 {%r5, %r6, %r7, %r8}, [%rd1];
; SM90-NEXT: mov.b32 {%rs3, %rs4}, %r7;
; SM90-NEXT: mov.b32 {%rs5, %rs6}, %r5;
-; SM90-NEXT: ld.param.b64 %rd2, [global_16xi16_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd2, [global_16xi16_param_1];
; SM90-NEXT: st.global.b16 [%rd2], %rs5;
; SM90-NEXT: st.global.b16 [%rd2+2], %rs6;
; SM90-NEXT: st.global.b16 [%rd2+8], %rs3;
@@ -79,13 +79,13 @@ define void @global_16xi16(ptr addrspace(1) %a, ptr addrspace(1) %b) {
; SM100-NEXT: .reg .b64 %rd<3>;
; SM100-EMPTY:
; SM100-NEXT: // %bb.0:
-; SM100-NEXT: ld.param.b64 %rd1, [global_16xi16_param_0];
+; SM100-NEXT: ld.param::func.b64 %rd1, [global_16xi16_param_0];
; SM100-NEXT: .pragma "used_bytes_mask 0xf0000f0f";
; SM100-NEXT: ld.global.v8.b32 {%r1, %r2, %r3, %r4, %r5, %r6, %r7, %r8}, [%rd1];
; SM100-NEXT: mov.b32 {%rs1, %rs2}, %r8;
; SM100-NEXT: mov.b32 {%rs3, %rs4}, %r3;
; SM100-NEXT: mov.b32 {%rs5, %rs6}, %r1;
-; SM100-NEXT: ld.param.b64 %rd2, [global_16xi16_param_1];
+; SM100-NEXT: ld.param::func.b64 %rd2, [global_16xi16_param_1];
; SM100-NEXT: st.global.b16 [%rd2], %rs5;
; SM100-NEXT: st.global.b16 [%rd2+2], %rs6;
; SM100-NEXT: st.global.b16 [%rd2+8], %rs3;
@@ -105,9 +105,9 @@ define void @global_8xi32_no_align(ptr addrspace(1) %a, ptr addrspace(1) %b) {
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [global_8xi32_no_align_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [global_8xi32_no_align_param_0];
; CHECK-NEXT: ld.global.b32 %r1, [%rd1];
-; CHECK-NEXT: ld.param.b64 %rd2, [global_8xi32_no_align_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [global_8xi32_no_align_param_1];
; CHECK-NEXT: ld.global.b32 %r2, [%rd1+8];
; CHECK-NEXT: ld.global.b32 %r3, [%rd1+28];
; CHECK-NEXT: st.global.b32 [%rd2], %r1;
@@ -127,12 +127,12 @@ define void @global_8xi32_invariant(ptr addrspace(1) %a, ptr addrspace(1) %b) {
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [global_8xi32_invariant_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd1, [global_8xi32_invariant_param_0];
; SM90-NEXT: .pragma "used_bytes_mask 0xf000";
; SM90-NEXT: ld.global.nc.v4.b32 {%r1, %r2, %r3, %r4}, [%rd1+16];
; SM90-NEXT: .pragma "used_bytes_mask 0xf0f";
; SM90-NEXT: ld.global.nc.v4.b32 {%r5, %r6, %r7, %r8}, [%rd1];
-; SM90-NEXT: ld.param.b64 %rd2, [global_8xi32_invariant_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd2, [global_8xi32_invariant_param_1];
; SM90-NEXT: st.global.b32 [%rd2], %r5;
; SM90-NEXT: st.global.b32 [%rd2+8], %r7;
; SM90-NEXT: st.global.b32 [%rd2+28], %r4;
@@ -144,10 +144,10 @@ define void @global_8xi32_invariant(ptr addrspace(1) %a, ptr addrspace(1) %b) {
; SM100-NEXT: .reg .b64 %rd<3>;
; SM100-EMPTY:
; SM100-NEXT: // %bb.0:
-; SM100-NEXT: ld.param.b64 %rd1, [global_8xi32_invariant_param_0];
+; SM100-NEXT: ld.param::func.b64 %rd1, [global_8xi32_invariant_param_0];
; SM100-NEXT: .pragma "used_bytes_mask 0xf0000f0f";
; SM100-NEXT: ld.global.nc.v8.b32 {%r1, %r2, %r3, %r4, %r5, %r6, %r7, %r8}, [%rd1];
-; SM100-NEXT: ld.param.b64 %rd2, [global_8xi32_invariant_param_1];
+; SM100-NEXT: ld.param::func.b64 %rd2, [global_8xi32_invariant_param_1];
; SM100-NEXT: st.global.v8.b32 [%rd2], {%r1, _, %r3, _, _, _, _, %r8};
; SM100-NEXT: ret;
%a.load = tail call <8 x i32> @llvm.masked.load.v8i32.p1(ptr addrspace(1) align 32 %a, <8 x i1> <i1 true, i1 false, i1 true, i1 false, i1 false, i1 false, i1 false, i1 true>, <8 x i32> poison), !invariant.load !0
@@ -163,10 +163,10 @@ define void @global_2xi16(ptr addrspace(1) %a, ptr addrspace(1) %b) {
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [global_2xi16_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [global_2xi16_param_0];
; CHECK-NEXT: .pragma "used_bytes_mask 0x3";
; CHECK-NEXT: ld.global.b32 %r1, [%rd1];
-; CHECK-NEXT: ld.param.b64 %rd2, [global_2xi16_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [global_2xi16_param_1];
; CHECK-NEXT: mov.b32 {%rs1, _}, %r1;
; CHECK-NEXT: st.global.b16 [%rd2], %rs1;
; CHECK-NEXT: ret;
@@ -183,10 +183,10 @@ define void @global_2xi16_invariant(ptr addrspace(1) %a, ptr addrspace(1) %b) {
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [global_2xi16_invariant_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [global_2xi16_invariant_param_0];
; CHECK-NEXT: .pragma "used_bytes_mask 0x3";
; CHECK-NEXT: ld.global.nc.b32 %r1, [%rd1];
-; CHECK-NEXT: ld.param.b64 %rd2, [global_2xi16_invariant_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [global_2xi16_invariant_param_1];
; CHECK-NEXT: mov.b32 {%rs1, _}, %r1;
; CHECK-NEXT: st.global.b16 [%rd2], %rs1;
; CHECK-NEXT: ret;
@@ -202,9 +202,9 @@ define void @global_2xi16_no_align(ptr addrspace(1) %a, ptr addrspace(1) %b) {
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [global_2xi16_no_align_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [global_2xi16_no_align_param_0];
; CHECK-NEXT: ld.global.b16 %rs1, [%rd1];
-; CHECK-NEXT: ld.param.b64 %rd2, [global_2xi16_no_align_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [global_2xi16_no_align_param_1];
; CHECK-NEXT: st.global.b16 [%rd2], %rs1;
; CHECK-NEXT: ret;
%a.load = tail call <2 x i16> @llvm.masked.load.v2i16.p1(ptr addrspace(1) align 2 %a, <2 x i1> <i1 true, i1 false>, <2 x i16> poison)
@@ -219,10 +219,10 @@ define void @global_4xi8(ptr addrspace(1) %a, ptr addrspace(1) %b) {
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [global_4xi8_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [global_4xi8_param_0];
; CHECK-NEXT: .pragma "used_bytes_mask 0x5";
; CHECK-NEXT: ld.global.b32 %r1, [%rd1];
-; CHECK-NEXT: ld.param.b64 %rd2, [global_4xi8_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [global_4xi8_param_1];
; CHECK-NEXT: st.global.b8 [%rd2], %r1;
; CHECK-NEXT: prmt.b32 %r2, %r1, 0, 0x7772U;
; CHECK-NEXT: st.global.b8 [%rd2+2], %r2;
@@ -239,10 +239,10 @@ define void @global_4xi8_invariant(ptr addrspace(1) %a, ptr addrspace(1) %b) {
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [global_4xi8_invariant_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [global_4xi8_invariant_param_0];
; CHECK-NEXT: .pragma "used_bytes_mask 0x5";
; CHECK-NEXT: ld.global.nc.b32 %r1, [%rd1];
-; CHECK-NEXT: ld.param.b64 %rd2, [global_4xi8_invariant_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [global_4xi8_invariant_param_1];
; CHECK-NEXT: st.global.b8 [%rd2], %r1;
; CHECK-NEXT: prmt.b32 %r2, %r1, 0, 0x7772U;
; CHECK-NEXT: st.global.b8 [%rd2+2], %r2;
@@ -259,9 +259,9 @@ define void @global_4xi8_no_align(ptr addrspace(1) %a, ptr addrspace(1) %b) {
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [global_4xi8_no_align_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [global_4xi8_no_align_param_0];
; CHECK-NEXT: ld.global.b8 %rs1, [%rd1];
-; CHECK-NEXT: ld.param.b64 %rd2, [global_4xi8_no_align_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [global_4xi8_no_align_param_1];
; CHECK-NEXT: ld.global.b8 %rs2, [%rd1+2];
; CHECK-NEXT: st.global.b8 [%rd2], %rs1;
; CHECK-NEXT: st.global.b8 [%rd2+2], %rs2;
@@ -279,10 +279,10 @@ define void @global_2xf32(ptr addrspace(1) %a, ptr addrspace(1) %b) {
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [global_2xf32_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd1, [global_2xf32_param_0];
; SM90-NEXT: .pragma "used_bytes_mask 0xf";
; SM90-NEXT: ld.global.v2.b32 {%r1, %r2}, [%rd1];
-; SM90-NEXT: ld.param.b64 %rd2, [global_2xf32_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd2, [global_2xf32_param_1];
; SM90-NEXT: st.global.b32 [%rd2], %r1;
; SM90-NEXT: ret;
;
@@ -292,10 +292,10 @@ define void @global_2xf32(ptr addrspace(1) %a, ptr addrspace(1) %b) {
; SM100-NEXT: .reg .b64 %rd<4>;
; SM100-EMPTY:
; SM100-NEXT: // %bb.0:
-; SM100-NEXT: ld.param.b64 %rd1, [global_2xf32_param_0];
+; SM100-NEXT: ld.param::func.b64 %rd1, [global_2xf32_param_0];
; SM100-NEXT: .pragma "used_bytes_mask 0xf";
; SM100-NEXT: ld.global.b64 %rd2, [%rd1];
-; SM100-NEXT: ld.param.b64 %rd3, [global_2xf32_param_1];
+; SM100-NEXT: ld.param::func.b64 %rd3, [global_2xf32_param_1];
; SM100-NEXT: mov.b64 {%r1, _}, %rd2;
; SM100-NEXT: st.global.b32 [%rd3], %r1;
; SM100-NEXT: ret;
@@ -311,10 +311,10 @@ define void @global_2xf32_invariant(ptr addrspace(1) %a, ptr addrspace(1) %b) {
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [global_2xf32_invariant_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd1, [global_2xf32_invariant_param_0];
; SM90-NEXT: .pragma "used_bytes_mask 0xf";
; SM90-NEXT: ld.global.nc.v2.b32 {%r1, %r2}, [%rd1];
-; SM90-NEXT: ld.param.b64 %rd2, [global_2xf32_invariant_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd2, [global_2xf32_invariant_param_1];
; SM90-NEXT: st.global.b32 [%rd2], %r1;
; SM90-NEXT: ret;
;
@@ -324,10 +324,10 @@ define void @global_2xf32_invariant(ptr addrspace(1) %a, ptr addrspace(1) %b) {
; SM100-NEXT: .reg .b64 %rd<4>;
; SM100-EMPTY:
; SM100-NEXT: // %bb.0:
-; SM100-NEXT: ld.param.b64 %rd1, [global_2xf32_invariant_param_0];
+; SM100-NEXT: ld.param::func.b64 %rd1, [global_2xf32_invariant_param_0];
; SM100-NEXT: .pragma "used_bytes_mask 0xf";
; SM100-NEXT: ld.global.nc.b64 %rd2, [%rd1];
-; SM100-NEXT: ld.param.b64 %rd3, [global_2xf32_invariant_param_1];
+; SM100-NEXT: ld.param::func.b64 %rd3, [global_2xf32_invariant_param_1];
; SM100-NEXT: mov.b64 {%r1, _}, %rd2;
; SM100-NEXT: st.global.b32 [%rd3], %r1;
; SM100-NEXT: ret;
@@ -343,9 +343,9 @@ define void @global_2xf32_no_align(ptr addrspace(1) %a, ptr addrspace(1) %b) {
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [global_2xf32_no_align_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [global_2xf32_no_align_param_0];
; CHECK-NEXT: ld.global.b32 %r1, [%rd1];
-; CHECK-NEXT: ld.param.b64 %rd2, [global_2xf32_no_align_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [global_2xf32_no_align_param_1];
; CHECK-NEXT: st.global.b32 [%rd2], %r1;
; CHECK-NEXT: ret;
%a.load = tail call <2 x float> @llvm.masked.load.v2f32.p1(ptr addrspace(1) align 4 %a, <2 x i1> <i1 true, i1 false>, <2 x float> poison)
diff --git a/llvm/test/CodeGen/NVPTX/masked-store-variable-mask.ll b/llvm/test/CodeGen/NVPTX/masked-store-variable-mask.ll
index bbe2dbb6447bb..db684ac344f3e 100644
--- a/llvm/test/CodeGen/NVPTX/masked-store-variable-mask.ll
+++ b/llvm/test/CodeGen/NVPTX/masked-store-variable-mask.ll
@@ -12,17 +12,17 @@ define void @global_variable_mask(ptr addrspace(1) %a, ptr addrspace(1) %b, <4 x
; CHECK-NEXT: .reg .b64 %rd<7>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [global_variable_mask_param_2+3];
-; CHECK-NEXT: ld.param.b8 %rs3, [global_variable_mask_param_2+2];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [global_variable_mask_param_2+3];
+; CHECK-NEXT: ld.param::func.b8 %rs3, [global_variable_mask_param_2+2];
; CHECK-NEXT: and.b16 %rs4, %rs3, 1;
-; CHECK-NEXT: ld.param.b8 %rs5, [global_variable_mask_param_2+1];
+; CHECK-NEXT: ld.param::func.b8 %rs5, [global_variable_mask_param_2+1];
; CHECK-NEXT: and.b16 %rs6, %rs5, 1;
; CHECK-NEXT: setp.ne.b16 %p2, %rs6, 0;
-; CHECK-NEXT: ld.param.b8 %rs7, [global_variable_mask_param_2];
+; CHECK-NEXT: ld.param::func.b8 %rs7, [global_variable_mask_param_2];
; CHECK-NEXT: and.b16 %rs8, %rs7, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs8, 0;
-; CHECK-NEXT: ld.param.b64 %rd5, [global_variable_mask_param_1];
-; CHECK-NEXT: ld.param.b64 %rd6, [global_variable_mask_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd5, [global_variable_mask_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd6, [global_variable_mask_param_0];
; CHECK-NEXT: ld.global.v4.b64 {%rd1, %rd2, %rd3, %rd4}, [%rd6];
; CHECK-NEXT: not.pred %p5, %p1;
; CHECK-NEXT: @%p5 bra $L__BB0_2;
diff --git a/llvm/test/CodeGen/NVPTX/masked-store-vectors-256.ll b/llvm/test/CodeGen/NVPTX/masked-store-vectors-256.ll
index 1701c94e187f0..94d26880948d5 100644
--- a/llvm/test/CodeGen/NVPTX/masked-store-vectors-256.ll
+++ b/llvm/test/CodeGen/NVPTX/masked-store-vectors-256.ll
@@ -25,10 +25,10 @@ define void @generic_8xi32(ptr %a, ptr %b) {
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [generic_8xi32_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [generic_8xi32_param_0];
; CHECK-NEXT: ld.v4.b32 {%r1, %r2, %r3, %r4}, [%rd1+16];
; CHECK-NEXT: ld.v4.b32 {%r5, %r6, %r7, %r8}, [%rd1];
-; CHECK-NEXT: ld.param.b64 %rd2, [generic_8xi32_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [generic_8xi32_param_1];
; CHECK-NEXT: st.b32 [%rd2], %r5;
; CHECK-NEXT: st.b32 [%rd2+8], %r7;
; CHECK-NEXT: st.b32 [%rd2+28], %r4;
@@ -44,10 +44,10 @@ define void @generic_4xi64(ptr %a, ptr %b) {
; CHECK-NEXT: .reg .b64 %rd<7>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [generic_4xi64_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [generic_4xi64_param_0];
; CHECK-NEXT: ld.v2.b64 {%rd2, %rd3}, [%rd1+16];
; CHECK-NEXT: ld.v2.b64 {%rd4, %rd5}, [%rd1];
-; CHECK-NEXT: ld.param.b64 %rd6, [generic_4xi64_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd6, [generic_4xi64_param_1];
; CHECK-NEXT: st.b64 [%rd6], %rd4;
; CHECK-NEXT: st.b64 [%rd6+16], %rd2;
; CHECK-NEXT: ret;
@@ -63,10 +63,10 @@ define void @generic_8xfloat(ptr %a, ptr %b) {
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [generic_8xfloat_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [generic_8xfloat_param_0];
; CHECK-NEXT: ld.v4.b32 {%r1, %r2, %r3, %r4}, [%rd1+16];
; CHECK-NEXT: ld.v4.b32 {%r5, %r6, %r7, %r8}, [%rd1];
-; CHECK-NEXT: ld.param.b64 %rd2, [generic_8xfloat_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [generic_8xfloat_param_1];
; CHECK-NEXT: st.b32 [%rd2], %r5;
; CHECK-NEXT: st.b32 [%rd2+8], %r7;
; CHECK-NEXT: st.b32 [%rd2+28], %r4;
@@ -82,10 +82,10 @@ define void @generic_4xdouble(ptr %a, ptr %b) {
; CHECK-NEXT: .reg .b64 %rd<7>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [generic_4xdouble_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [generic_4xdouble_param_0];
; CHECK-NEXT: ld.v2.b64 {%rd2, %rd3}, [%rd1+16];
; CHECK-NEXT: ld.v2.b64 {%rd4, %rd5}, [%rd1];
-; CHECK-NEXT: ld.param.b64 %rd6, [generic_4xdouble_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd6, [generic_4xdouble_param_1];
; CHECK-NEXT: st.b64 [%rd6], %rd4;
; CHECK-NEXT: st.b64 [%rd6+16], %rd2;
; CHECK-NEXT: ret;
@@ -103,10 +103,10 @@ define void @global_8xi32(ptr addrspace(1) %a, ptr addrspace(1) %b) {
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [global_8xi32_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd1, [global_8xi32_param_0];
; SM90-NEXT: ld.global.v4.b32 {%r1, %r2, %r3, %r4}, [%rd1+16];
; SM90-NEXT: ld.global.v4.b32 {%r5, %r6, %r7, %r8}, [%rd1];
-; SM90-NEXT: ld.param.b64 %rd2, [global_8xi32_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd2, [global_8xi32_param_1];
; SM90-NEXT: st.global.b32 [%rd2], %r5;
; SM90-NEXT: st.global.b32 [%rd2+8], %r7;
; SM90-NEXT: st.global.b32 [%rd2+28], %r4;
@@ -118,9 +118,9 @@ define void @global_8xi32(ptr addrspace(1) %a, ptr addrspace(1) %b) {
; SM100-NEXT: .reg .b64 %rd<3>;
; SM100-EMPTY:
; SM100-NEXT: // %bb.0:
-; SM100-NEXT: ld.param.b64 %rd1, [global_8xi32_param_0];
+; SM100-NEXT: ld.param::func.b64 %rd1, [global_8xi32_param_0];
; SM100-NEXT: ld.global.v8.b32 {%r1, %r2, %r3, %r4, %r5, %r6, %r7, %r8}, [%rd1];
-; SM100-NEXT: ld.param.b64 %rd2, [global_8xi32_param_1];
+; SM100-NEXT: ld.param::func.b64 %rd2, [global_8xi32_param_1];
; SM100-NEXT: st.global.v8.b32 [%rd2], {%r1, _, %r3, _, _, _, _, %r8};
; SM100-NEXT: ret;
%a.load = load <8 x i32>, ptr addrspace(1) %a
@@ -134,10 +134,10 @@ define void @global_4xi64(ptr addrspace(1) %a, ptr addrspace(1) %b) {
; SM90-NEXT: .reg .b64 %rd<7>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [global_4xi64_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd1, [global_4xi64_param_0];
; SM90-NEXT: ld.global.v2.b64 {%rd2, %rd3}, [%rd1+16];
; SM90-NEXT: ld.global.v2.b64 {%rd4, %rd5}, [%rd1];
-; SM90-NEXT: ld.param.b64 %rd6, [global_4xi64_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd6, [global_4xi64_param_1];
; SM90-NEXT: st.global.b64 [%rd6], %rd4;
; SM90-NEXT: st.global.b64 [%rd6+16], %rd2;
; SM90-NEXT: ret;
@@ -147,9 +147,9 @@ define void @global_4xi64(ptr addrspace(1) %a, ptr addrspace(1) %b) {
; SM100-NEXT: .reg .b64 %rd<7>;
; SM100-EMPTY:
; SM100-NEXT: // %bb.0:
-; SM100-NEXT: ld.param.b64 %rd1, [global_4xi64_param_0];
+; SM100-NEXT: ld.param::func.b64 %rd1, [global_4xi64_param_0];
; SM100-NEXT: ld.global.v4.b64 {%rd2, %rd3, %rd4, %rd5}, [%rd1];
-; SM100-NEXT: ld.param.b64 %rd6, [global_4xi64_param_1];
+; SM100-NEXT: ld.param::func.b64 %rd6, [global_4xi64_param_1];
; SM100-NEXT: st.global.v4.b64 [%rd6], {%rd2, _, %rd4, _};
; SM100-NEXT: ret;
%a.load = load <4 x i64>, ptr addrspace(1) %a
@@ -164,10 +164,10 @@ define void @global_8xfloat(ptr addrspace(1) %a, ptr addrspace(1) %b) {
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [global_8xfloat_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd1, [global_8xfloat_param_0];
; SM90-NEXT: ld.global.v4.b32 {%r1, %r2, %r3, %r4}, [%rd1+16];
; SM90-NEXT: ld.global.v4.b32 {%r5, %r6, %r7, %r8}, [%rd1];
-; SM90-NEXT: ld.param.b64 %rd2, [global_8xfloat_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd2, [global_8xfloat_param_1];
; SM90-NEXT: st.global.b32 [%rd2], %r5;
; SM90-NEXT: st.global.b32 [%rd2+8], %r7;
; SM90-NEXT: st.global.b32 [%rd2+28], %r4;
@@ -179,9 +179,9 @@ define void @global_8xfloat(ptr addrspace(1) %a, ptr addrspace(1) %b) {
; SM100-NEXT: .reg .b64 %rd<3>;
; SM100-EMPTY:
; SM100-NEXT: // %bb.0:
-; SM100-NEXT: ld.param.b64 %rd1, [global_8xfloat_param_0];
+; SM100-NEXT: ld.param::func.b64 %rd1, [global_8xfloat_param_0];
; SM100-NEXT: ld.global.v8.b32 {%r1, %r2, %r3, %r4, %r5, %r6, %r7, %r8}, [%rd1];
-; SM100-NEXT: ld.param.b64 %rd2, [global_8xfloat_param_1];
+; SM100-NEXT: ld.param::func.b64 %rd2, [global_8xfloat_param_1];
; SM100-NEXT: st.global.v8.b32 [%rd2], {%r1, _, %r3, _, _, _, _, %r8};
; SM100-NEXT: ret;
%a.load = load <8 x float>, ptr addrspace(1) %a
@@ -195,10 +195,10 @@ define void @global_4xdouble(ptr addrspace(1) %a, ptr addrspace(1) %b) {
; SM90-NEXT: .reg .b64 %rd<7>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [global_4xdouble_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd1, [global_4xdouble_param_0];
; SM90-NEXT: ld.global.v2.b64 {%rd2, %rd3}, [%rd1+16];
; SM90-NEXT: ld.global.v2.b64 {%rd4, %rd5}, [%rd1];
-; SM90-NEXT: ld.param.b64 %rd6, [global_4xdouble_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd6, [global_4xdouble_param_1];
; SM90-NEXT: st.global.b64 [%rd6], %rd4;
; SM90-NEXT: st.global.b64 [%rd6+16], %rd2;
; SM90-NEXT: ret;
@@ -208,9 +208,9 @@ define void @global_4xdouble(ptr addrspace(1) %a, ptr addrspace(1) %b) {
; SM100-NEXT: .reg .b64 %rd<7>;
; SM100-EMPTY:
; SM100-NEXT: // %bb.0:
-; SM100-NEXT: ld.param.b64 %rd1, [global_4xdouble_param_0];
+; SM100-NEXT: ld.param::func.b64 %rd1, [global_4xdouble_param_0];
; SM100-NEXT: ld.global.v4.b64 {%rd2, %rd3, %rd4, %rd5}, [%rd1];
-; SM100-NEXT: ld.param.b64 %rd6, [global_4xdouble_param_1];
+; SM100-NEXT: ld.param::func.b64 %rd6, [global_4xdouble_param_1];
; SM100-NEXT: st.global.v4.b64 [%rd6], {%rd2, _, %rd4, _};
; SM100-NEXT: ret;
%a.load = load <4 x double>, ptr addrspace(1) %a
@@ -226,10 +226,10 @@ define void @global_8xi32_all_mask_on(ptr addrspace(1) %a, ptr addrspace(1) %b)
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [global_8xi32_all_mask_on_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd1, [global_8xi32_all_mask_on_param_0];
; SM90-NEXT: ld.global.v4.b32 {%r1, %r2, %r3, %r4}, [%rd1];
; SM90-NEXT: ld.global.v4.b32 {%r5, %r6, %r7, %r8}, [%rd1+16];
-; SM90-NEXT: ld.param.b64 %rd2, [global_8xi32_all_mask_on_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd2, [global_8xi32_all_mask_on_param_1];
; SM90-NEXT: st.global.v4.b32 [%rd2+16], {%r5, %r6, %r7, %r8};
; SM90-NEXT: st.global.v4.b32 [%rd2], {%r1, %r2, %r3, %r4};
; SM90-NEXT: ret;
@@ -239,9 +239,9 @@ define void @global_8xi32_all_mask_on(ptr addrspace(1) %a, ptr addrspace(1) %b)
; SM100-NEXT: .reg .b64 %rd<7>;
; SM100-EMPTY:
; SM100-NEXT: // %bb.0:
-; SM100-NEXT: ld.param.b64 %rd1, [global_8xi32_all_mask_on_param_0];
+; SM100-NEXT: ld.param::func.b64 %rd1, [global_8xi32_all_mask_on_param_0];
; SM100-NEXT: ld.global.v4.b64 {%rd2, %rd3, %rd4, %rd5}, [%rd1];
-; SM100-NEXT: ld.param.b64 %rd6, [global_8xi32_all_mask_on_param_1];
+; SM100-NEXT: ld.param::func.b64 %rd6, [global_8xi32_all_mask_on_param_1];
; SM100-NEXT: st.global.v4.b64 [%rd6], {%rd2, %rd3, %rd4, %rd5};
; SM100-NEXT: ret;
%a.load = load <8 x i32>, ptr addrspace(1) %a
@@ -268,10 +268,10 @@ define void @vectorizerOutput(ptr addrspace(1) %in, ptr addrspace(1) %out) {
; SM90-NEXT: .reg .b64 %rd<3>;
; SM90-EMPTY:
; SM90-NEXT: // %bb.0:
-; SM90-NEXT: ld.param.b64 %rd1, [vectorizerOutput_param_0];
+; SM90-NEXT: ld.param::func.b64 %rd1, [vectorizerOutput_param_0];
; SM90-NEXT: ld.global.v4.b32 {%r1, %r2, %r3, %r4}, [%rd1+16];
; SM90-NEXT: ld.global.v4.b32 {%r5, %r6, %r7, %r8}, [%rd1];
-; SM90-NEXT: ld.param.b64 %rd2, [vectorizerOutput_param_1];
+; SM90-NEXT: ld.param::func.b64 %rd2, [vectorizerOutput_param_1];
; SM90-NEXT: st.global.b32 [%rd2], %r5;
; SM90-NEXT: st.global.b32 [%rd2+4], %r6;
; SM90-NEXT: st.global.b32 [%rd2+12], %r8;
@@ -284,9 +284,9 @@ define void @vectorizerOutput(ptr addrspace(1) %in, ptr addrspace(1) %out) {
; SM100-NEXT: .reg .b64 %rd<3>;
; SM100-EMPTY:
; SM100-NEXT: // %bb.0:
-; SM100-NEXT: ld.param.b64 %rd1, [vectorizerOutput_param_0];
+; SM100-NEXT: ld.param::func.b64 %rd1, [vectorizerOutput_param_0];
; SM100-NEXT: ld.global.v8.b32 {%r1, %r2, %r3, %r4, %r5, %r6, %r7, %r8}, [%rd1];
-; SM100-NEXT: ld.param.b64 %rd2, [vectorizerOutput_param_1];
+; SM100-NEXT: ld.param::func.b64 %rd2, [vectorizerOutput_param_1];
; SM100-NEXT: st.global.v8.b32 [%rd2], {%r1, %r2, _, %r4, %r5, _, _, _};
; SM100-NEXT: ret;
%1 = load <8 x i32>, ptr addrspace(1) %in, align 32
diff --git a/llvm/test/CodeGen/NVPTX/mbarrier_arr_relaxed.ll b/llvm/test/CodeGen/NVPTX/mbarrier_arr_relaxed.ll
index 09e75232e490c..26e931822693c 100644
--- a/llvm/test/CodeGen/NVPTX/mbarrier_arr_relaxed.ll
+++ b/llvm/test/CodeGen/NVPTX/mbarrier_arr_relaxed.ll
@@ -12,8 +12,8 @@ define void @test_mbarrier_arrive_relaxed_scope_cta_space_cta(ptr addrspace(3) %
; CHECK-PTX64-NEXT: .reg .b64 %rd<6>;
; CHECK-PTX64-EMPTY:
; CHECK-PTX64-NEXT: // %bb.0:
-; CHECK-PTX64-NEXT: ld.param.b64 %rd1, [test_mbarrier_arrive_relaxed_scope_cta_space_cta_param_0];
-; CHECK-PTX64-NEXT: ld.param.b32 %r1, [test_mbarrier_arrive_relaxed_scope_cta_space_cta_param_1];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd1, [test_mbarrier_arrive_relaxed_scope_cta_space_cta_param_0];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r1, [test_mbarrier_arrive_relaxed_scope_cta_space_cta_param_1];
; CHECK-PTX64-NEXT: mbarrier.arrive.relaxed.cta.shared.b64 %rd2, [%rd1], %r1;
; CHECK-PTX64-NEXT: mbarrier.arrive.expect_tx.relaxed.cta.shared.b64 %rd3, [%rd1], %r1;
; CHECK-PTX64-NEXT: mbarrier.arrive_drop.relaxed.cta.shared.b64 %rd4, [%rd1], %r1;
@@ -26,8 +26,8 @@ define void @test_mbarrier_arrive_relaxed_scope_cta_space_cta(ptr addrspace(3) %
; CHECK-PTX-SHARED32-NEXT: .reg .b64 %rd<5>;
; CHECK-PTX-SHARED32-EMPTY:
; CHECK-PTX-SHARED32-NEXT: // %bb.0:
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r1, [test_mbarrier_arrive_relaxed_scope_cta_space_cta_param_0];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r2, [test_mbarrier_arrive_relaxed_scope_cta_space_cta_param_1];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r1, [test_mbarrier_arrive_relaxed_scope_cta_space_cta_param_0];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r2, [test_mbarrier_arrive_relaxed_scope_cta_space_cta_param_1];
; CHECK-PTX-SHARED32-NEXT: mbarrier.arrive.relaxed.cta.shared.b64 %rd1, [%r1], %r2;
; CHECK-PTX-SHARED32-NEXT: mbarrier.arrive.expect_tx.relaxed.cta.shared.b64 %rd2, [%r1], %r2;
; CHECK-PTX-SHARED32-NEXT: mbarrier.arrive_drop.relaxed.cta.shared.b64 %rd3, [%r1], %r2;
@@ -47,8 +47,8 @@ define void @test_mbarrier_arrive_relaxed_scope_cluster_space_cta(ptr addrspace(
; CHECK-PTX64-NEXT: .reg .b64 %rd<6>;
; CHECK-PTX64-EMPTY:
; CHECK-PTX64-NEXT: // %bb.0:
-; CHECK-PTX64-NEXT: ld.param.b64 %rd1, [test_mbarrier_arrive_relaxed_scope_cluster_space_cta_param_0];
-; CHECK-PTX64-NEXT: ld.param.b32 %r1, [test_mbarrier_arrive_relaxed_scope_cluster_space_cta_param_1];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd1, [test_mbarrier_arrive_relaxed_scope_cluster_space_cta_param_0];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r1, [test_mbarrier_arrive_relaxed_scope_cluster_space_cta_param_1];
; CHECK-PTX64-NEXT: mbarrier.arrive.relaxed.cluster.shared.b64 %rd2, [%rd1], %r1;
; CHECK-PTX64-NEXT: mbarrier.arrive.expect_tx.relaxed.cluster.shared.b64 %rd3, [%rd1], %r1;
; CHECK-PTX64-NEXT: mbarrier.arrive_drop.relaxed.cluster.shared.b64 %rd4, [%rd1], %r1;
@@ -61,8 +61,8 @@ define void @test_mbarrier_arrive_relaxed_scope_cluster_space_cta(ptr addrspace(
; CHECK-PTX-SHARED32-NEXT: .reg .b64 %rd<5>;
; CHECK-PTX-SHARED32-EMPTY:
; CHECK-PTX-SHARED32-NEXT: // %bb.0:
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r1, [test_mbarrier_arrive_relaxed_scope_cluster_space_cta_param_0];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r2, [test_mbarrier_arrive_relaxed_scope_cluster_space_cta_param_1];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r1, [test_mbarrier_arrive_relaxed_scope_cluster_space_cta_param_0];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r2, [test_mbarrier_arrive_relaxed_scope_cluster_space_cta_param_1];
; CHECK-PTX-SHARED32-NEXT: mbarrier.arrive.relaxed.cluster.shared.b64 %rd1, [%r1], %r2;
; CHECK-PTX-SHARED32-NEXT: mbarrier.arrive.expect_tx.relaxed.cluster.shared.b64 %rd2, [%r1], %r2;
; CHECK-PTX-SHARED32-NEXT: mbarrier.arrive_drop.relaxed.cluster.shared.b64 %rd3, [%r1], %r2;
@@ -83,8 +83,8 @@ define void @test_mbarrier_arrive_relaxed_scope_cta_space_cluster(ptr addrspace(
; CHECK-PTX64-NEXT: .reg .b64 %rd<2>;
; CHECK-PTX64-EMPTY:
; CHECK-PTX64-NEXT: // %bb.0:
-; CHECK-PTX64-NEXT: ld.param.b64 %rd1, [test_mbarrier_arrive_relaxed_scope_cta_space_cluster_param_0];
-; CHECK-PTX64-NEXT: ld.param.b32 %r1, [test_mbarrier_arrive_relaxed_scope_cta_space_cluster_param_1];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd1, [test_mbarrier_arrive_relaxed_scope_cta_space_cluster_param_0];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r1, [test_mbarrier_arrive_relaxed_scope_cta_space_cluster_param_1];
; CHECK-PTX64-NEXT: mbarrier.arrive.relaxed.cta.shared::cluster.b64 _, [%rd1], %r1;
; CHECK-PTX64-NEXT: mbarrier.arrive.expect_tx.relaxed.cta.shared::cluster.b64 _, [%rd1], %r1;
; CHECK-PTX64-NEXT: mbarrier.arrive_drop.relaxed.cta.shared::cluster.b64 _, [%rd1], %r1;
@@ -96,8 +96,8 @@ define void @test_mbarrier_arrive_relaxed_scope_cta_space_cluster(ptr addrspace(
; CHECK-PTX-SHARED32-NEXT: .reg .b32 %r<3>;
; CHECK-PTX-SHARED32-EMPTY:
; CHECK-PTX-SHARED32-NEXT: // %bb.0:
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r1, [test_mbarrier_arrive_relaxed_scope_cta_space_cluster_param_0];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r2, [test_mbarrier_arrive_relaxed_scope_cta_space_cluster_param_1];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r1, [test_mbarrier_arrive_relaxed_scope_cta_space_cluster_param_0];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r2, [test_mbarrier_arrive_relaxed_scope_cta_space_cluster_param_1];
; CHECK-PTX-SHARED32-NEXT: mbarrier.arrive.relaxed.cta.shared::cluster.b64 _, [%r1], %r2;
; CHECK-PTX-SHARED32-NEXT: mbarrier.arrive.expect_tx.relaxed.cta.shared::cluster.b64 _, [%r1], %r2;
; CHECK-PTX-SHARED32-NEXT: mbarrier.arrive_drop.relaxed.cta.shared::cluster.b64 _, [%r1], %r2;
@@ -117,8 +117,8 @@ define void @test_mbarrier_arrive_relaxed_scope_cluster_space_cluster(ptr addrsp
; CHECK-PTX64-NEXT: .reg .b64 %rd<2>;
; CHECK-PTX64-EMPTY:
; CHECK-PTX64-NEXT: // %bb.0:
-; CHECK-PTX64-NEXT: ld.param.b64 %rd1, [test_mbarrier_arrive_relaxed_scope_cluster_space_cluster_param_0];
-; CHECK-PTX64-NEXT: ld.param.b32 %r1, [test_mbarrier_arrive_relaxed_scope_cluster_space_cluster_param_1];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd1, [test_mbarrier_arrive_relaxed_scope_cluster_space_cluster_param_0];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r1, [test_mbarrier_arrive_relaxed_scope_cluster_space_cluster_param_1];
; CHECK-PTX64-NEXT: mbarrier.arrive.relaxed.cluster.shared::cluster.b64 _, [%rd1], %r1;
; CHECK-PTX64-NEXT: mbarrier.arrive.expect_tx.relaxed.cluster.shared::cluster.b64 _, [%rd1], %r1;
; CHECK-PTX64-NEXT: mbarrier.arrive_drop.relaxed.cluster.shared::cluster.b64 _, [%rd1], %r1;
@@ -130,8 +130,8 @@ define void @test_mbarrier_arrive_relaxed_scope_cluster_space_cluster(ptr addrsp
; CHECK-PTX-SHARED32-NEXT: .reg .b32 %r<3>;
; CHECK-PTX-SHARED32-EMPTY:
; CHECK-PTX-SHARED32-NEXT: // %bb.0:
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r1, [test_mbarrier_arrive_relaxed_scope_cluster_space_cluster_param_0];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r2, [test_mbarrier_arrive_relaxed_scope_cluster_space_cluster_param_1];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r1, [test_mbarrier_arrive_relaxed_scope_cluster_space_cluster_param_0];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r2, [test_mbarrier_arrive_relaxed_scope_cluster_space_cluster_param_1];
; CHECK-PTX-SHARED32-NEXT: mbarrier.arrive.relaxed.cluster.shared::cluster.b64 _, [%r1], %r2;
; CHECK-PTX-SHARED32-NEXT: mbarrier.arrive.expect_tx.relaxed.cluster.shared::cluster.b64 _, [%r1], %r2;
; CHECK-PTX-SHARED32-NEXT: mbarrier.arrive_drop.relaxed.cluster.shared::cluster.b64 _, [%r1], %r2;
diff --git a/llvm/test/CodeGen/NVPTX/mbarrier_wait_sm90_ptx86.ll b/llvm/test/CodeGen/NVPTX/mbarrier_wait_sm90_ptx86.ll
index 7c4c4d7cab1cd..1cbab2ca7d101 100644
--- a/llvm/test/CodeGen/NVPTX/mbarrier_wait_sm90_ptx86.ll
+++ b/llvm/test/CodeGen/NVPTX/mbarrier_wait_sm90_ptx86.ll
@@ -30,11 +30,11 @@ define void @mbar_test_wait(ptr addrspace(3) %mbar, i64 %state, i32 %parity) {
; CHECK-PTX64-NEXT: .reg .b64 %rd<3>;
; CHECK-PTX64-EMPTY:
; CHECK-PTX64-NEXT: // %bb.0:
-; CHECK-PTX64-NEXT: ld.param.b64 %rd1, [mbar_test_wait_param_0];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd2, [mbar_test_wait_param_1];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd1, [mbar_test_wait_param_0];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd2, [mbar_test_wait_param_1];
; CHECK-PTX64-NEXT: mbarrier.test_wait.relaxed.cta.shared.b64 %p1, [%rd1], %rd2;
; CHECK-PTX64-NEXT: mbarrier.test_wait.relaxed.cluster.shared.b64 %p2, [%rd1], %rd2;
-; CHECK-PTX64-NEXT: ld.param.b32 %r1, [mbar_test_wait_param_2];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r1, [mbar_test_wait_param_2];
; CHECK-PTX64-NEXT: mbarrier.test_wait.parity.relaxed.cta.shared.b64 %p3, [%rd1], %r1;
; CHECK-PTX64-NEXT: mbarrier.test_wait.parity.relaxed.cluster.shared.b64 %p4, [%rd1], %r1;
; CHECK-PTX64-NEXT: ret;
@@ -46,11 +46,11 @@ define void @mbar_test_wait(ptr addrspace(3) %mbar, i64 %state, i32 %parity) {
; CHECK-PTX-SHARED32-NEXT: .reg .b64 %rd<2>;
; CHECK-PTX-SHARED32-EMPTY:
; CHECK-PTX-SHARED32-NEXT: // %bb.0:
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r1, [mbar_test_wait_param_0];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd1, [mbar_test_wait_param_1];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r1, [mbar_test_wait_param_0];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd1, [mbar_test_wait_param_1];
; CHECK-PTX-SHARED32-NEXT: mbarrier.test_wait.relaxed.cta.shared.b64 %p1, [%r1], %rd1;
; CHECK-PTX-SHARED32-NEXT: mbarrier.test_wait.relaxed.cluster.shared.b64 %p2, [%r1], %rd1;
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r2, [mbar_test_wait_param_2];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r2, [mbar_test_wait_param_2];
; CHECK-PTX-SHARED32-NEXT: mbarrier.test_wait.parity.relaxed.cta.shared.b64 %p3, [%r1], %r2;
; CHECK-PTX-SHARED32-NEXT: mbarrier.test_wait.parity.relaxed.cluster.shared.b64 %p4, [%r1], %r2;
; CHECK-PTX-SHARED32-NEXT: ret;
@@ -71,11 +71,11 @@ define void @mbar_try_wait(ptr addrspace(3) %mbar, i64 %state, i32 %parity) {
; CHECK-PTX64-NEXT: .reg .b64 %rd<3>;
; CHECK-PTX64-EMPTY:
; CHECK-PTX64-NEXT: // %bb.0:
-; CHECK-PTX64-NEXT: ld.param.b64 %rd1, [mbar_try_wait_param_0];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd2, [mbar_try_wait_param_1];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd1, [mbar_try_wait_param_0];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd2, [mbar_try_wait_param_1];
; CHECK-PTX64-NEXT: mbarrier.try_wait.relaxed.cta.shared.b64 %p1, [%rd1], %rd2;
; CHECK-PTX64-NEXT: mbarrier.try_wait.relaxed.cluster.shared.b64 %p2, [%rd1], %rd2;
-; CHECK-PTX64-NEXT: ld.param.b32 %r1, [mbar_try_wait_param_2];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r1, [mbar_try_wait_param_2];
; CHECK-PTX64-NEXT: mbarrier.try_wait.parity.relaxed.cta.shared.b64 %p3, [%rd1], %r1;
; CHECK-PTX64-NEXT: mbarrier.try_wait.parity.relaxed.cluster.shared.b64 %p4, [%rd1], %r1;
; CHECK-PTX64-NEXT: ret;
@@ -87,11 +87,11 @@ define void @mbar_try_wait(ptr addrspace(3) %mbar, i64 %state, i32 %parity) {
; CHECK-PTX-SHARED32-NEXT: .reg .b64 %rd<2>;
; CHECK-PTX-SHARED32-EMPTY:
; CHECK-PTX-SHARED32-NEXT: // %bb.0:
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r1, [mbar_try_wait_param_0];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd1, [mbar_try_wait_param_1];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r1, [mbar_try_wait_param_0];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd1, [mbar_try_wait_param_1];
; CHECK-PTX-SHARED32-NEXT: mbarrier.try_wait.relaxed.cta.shared.b64 %p1, [%r1], %rd1;
; CHECK-PTX-SHARED32-NEXT: mbarrier.try_wait.relaxed.cluster.shared.b64 %p2, [%r1], %rd1;
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r2, [mbar_try_wait_param_2];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r2, [mbar_try_wait_param_2];
; CHECK-PTX-SHARED32-NEXT: mbarrier.try_wait.parity.relaxed.cta.shared.b64 %p3, [%r1], %r2;
; CHECK-PTX-SHARED32-NEXT: mbarrier.try_wait.parity.relaxed.cluster.shared.b64 %p4, [%r1], %r2;
; CHECK-PTX-SHARED32-NEXT: ret;
@@ -112,12 +112,12 @@ define void @mbar_try_wait_tl(ptr addrspace(3) %mbar, i64 %state, i32 %parity, i
; CHECK-PTX64-NEXT: .reg .b64 %rd<3>;
; CHECK-PTX64-EMPTY:
; CHECK-PTX64-NEXT: // %bb.0:
-; CHECK-PTX64-NEXT: ld.param.b64 %rd1, [mbar_try_wait_tl_param_0];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd2, [mbar_try_wait_tl_param_1];
-; CHECK-PTX64-NEXT: ld.param.b32 %r1, [mbar_try_wait_tl_param_3];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd1, [mbar_try_wait_tl_param_0];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd2, [mbar_try_wait_tl_param_1];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r1, [mbar_try_wait_tl_param_3];
; CHECK-PTX64-NEXT: mbarrier.try_wait.relaxed.cta.shared.b64 %p1, [%rd1], %rd2, %r1;
; CHECK-PTX64-NEXT: mbarrier.try_wait.relaxed.cluster.shared.b64 %p2, [%rd1], %rd2, %r1;
-; CHECK-PTX64-NEXT: ld.param.b32 %r2, [mbar_try_wait_tl_param_2];
+; CHECK-PTX64-NEXT: ld.param::func.b32 %r2, [mbar_try_wait_tl_param_2];
; CHECK-PTX64-NEXT: mbarrier.try_wait.parity.relaxed.cta.shared.b64 %p3, [%rd1], %r2, %r1;
; CHECK-PTX64-NEXT: mbarrier.try_wait.parity.relaxed.cluster.shared.b64 %p4, [%rd1], %r2, %r1;
; CHECK-PTX64-NEXT: ret;
@@ -129,12 +129,12 @@ define void @mbar_try_wait_tl(ptr addrspace(3) %mbar, i64 %state, i32 %parity, i
; CHECK-PTX-SHARED32-NEXT: .reg .b64 %rd<2>;
; CHECK-PTX-SHARED32-EMPTY:
; CHECK-PTX-SHARED32-NEXT: // %bb.0:
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r1, [mbar_try_wait_tl_param_0];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd1, [mbar_try_wait_tl_param_1];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r2, [mbar_try_wait_tl_param_3];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r1, [mbar_try_wait_tl_param_0];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd1, [mbar_try_wait_tl_param_1];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r2, [mbar_try_wait_tl_param_3];
; CHECK-PTX-SHARED32-NEXT: mbarrier.try_wait.relaxed.cta.shared.b64 %p1, [%r1], %rd1, %r2;
; CHECK-PTX-SHARED32-NEXT: mbarrier.try_wait.relaxed.cluster.shared.b64 %p2, [%r1], %rd1, %r2;
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r3, [mbar_try_wait_tl_param_2];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r3, [mbar_try_wait_tl_param_2];
; CHECK-PTX-SHARED32-NEXT: mbarrier.try_wait.parity.relaxed.cta.shared.b64 %p3, [%r1], %r3, %r2;
; CHECK-PTX-SHARED32-NEXT: mbarrier.try_wait.parity.relaxed.cluster.shared.b64 %p4, [%r1], %r3, %r2;
; CHECK-PTX-SHARED32-NEXT: ret;
diff --git a/llvm/test/CodeGen/NVPTX/mixed-precision-fp.ll b/llvm/test/CodeGen/NVPTX/mixed-precision-fp.ll
index 1d77763db3c30..5f82d2e77a468 100644
--- a/llvm/test/CodeGen/NVPTX/mixed-precision-fp.ll
+++ b/llvm/test/CodeGen/NVPTX/mixed-precision-fp.ll
@@ -13,8 +13,8 @@ define float @test_add_f32_f16_1(half %a, float %b) {
; CHECK-NEXT: .reg .b32 %r<10>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b16 %rs1, [test_add_f32_f16_1_param_0];
-; CHECK-NEXT: ld.param.b32 %r1, [test_add_f32_f16_1_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_add_f32_f16_1_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_add_f32_f16_1_param_1];
; CHECK-NEXT: add.rn.f32.f16 %r2, %rs1, %r1;
; CHECK-NEXT: add.rz.f32.f16 %r3, %rs1, %r2;
; CHECK-NEXT: add.rm.f32.f16 %r4, %rs1, %r3;
@@ -23,7 +23,7 @@ define float @test_add_f32_f16_1(half %a, float %b) {
; CHECK-NEXT: add.rz.sat.f32.f16 %r7, %rs1, %r6;
; CHECK-NEXT: add.rm.sat.f32.f16 %r8, %rs1, %r7;
; CHECK-NEXT: add.rp.sat.f32.f16 %r9, %rs1, %r8;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r9;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r9;
; CHECK-NEXT: ret;
%r0 = fpext half %a to float
@@ -48,10 +48,10 @@ define float @test_add_f32_f16_2(half %a, float %b) {
; CHECK-NOF32FTZ-NEXT: .reg .b32 %r<3>;
; CHECK-NOF32FTZ-EMPTY:
; CHECK-NOF32FTZ-NEXT: // %bb.0:
-; CHECK-NOF32FTZ-NEXT: ld.param.b16 %rs1, [test_add_f32_f16_2_param_0];
-; CHECK-NOF32FTZ-NEXT: ld.param.b32 %r1, [test_add_f32_f16_2_param_1];
+; CHECK-NOF32FTZ-NEXT: ld.param::func.b16 %rs1, [test_add_f32_f16_2_param_0];
+; CHECK-NOF32FTZ-NEXT: ld.param::func.b32 %r1, [test_add_f32_f16_2_param_1];
; CHECK-NOF32FTZ-NEXT: add.rn.f32.f16 %r2, %rs1, %r1;
-; CHECK-NOF32FTZ-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NOF32FTZ-NEXT: st.param::func.b32 [func_retval0], %r2;
; CHECK-NOF32FTZ-NEXT: ret;
;
; CHECK-F32FTZ-LABEL: test_add_f32_f16_2(
@@ -60,11 +60,11 @@ define float @test_add_f32_f16_2(half %a, float %b) {
; CHECK-F32FTZ-NEXT: .reg .b32 %r<4>;
; CHECK-F32FTZ-EMPTY:
; CHECK-F32FTZ-NEXT: // %bb.0:
-; CHECK-F32FTZ-NEXT: ld.param.b16 %rs1, [test_add_f32_f16_2_param_0];
+; CHECK-F32FTZ-NEXT: ld.param::func.b16 %rs1, [test_add_f32_f16_2_param_0];
; CHECK-F32FTZ-NEXT: cvt.ftz.f32.f16 %r1, %rs1;
-; CHECK-F32FTZ-NEXT: ld.param.b32 %r2, [test_add_f32_f16_2_param_1];
+; CHECK-F32FTZ-NEXT: ld.param::func.b32 %r2, [test_add_f32_f16_2_param_1];
; CHECK-F32FTZ-NEXT: add.rn.ftz.f32 %r3, %r1, %r2;
-; CHECK-F32FTZ-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-F32FTZ-NEXT: st.param::func.b32 [func_retval0], %r3;
; CHECK-F32FTZ-NEXT: ret;
%r0 = fpext half %a to float
%r1 = fadd float %r0, %b
@@ -79,8 +79,8 @@ define float @test_add_f32_bf16_1(bfloat %a, float %b) {
; CHECK-NEXT: .reg .b32 %r<10>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b16 %rs1, [test_add_f32_bf16_1_param_0];
-; CHECK-NEXT: ld.param.b32 %r1, [test_add_f32_bf16_1_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_add_f32_bf16_1_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_add_f32_bf16_1_param_1];
; CHECK-NEXT: add.rn.f32.bf16 %r2, %rs1, %r1;
; CHECK-NEXT: add.rz.f32.bf16 %r3, %rs1, %r2;
; CHECK-NEXT: add.rm.f32.bf16 %r4, %rs1, %r3;
@@ -89,7 +89,7 @@ define float @test_add_f32_bf16_1(bfloat %a, float %b) {
; CHECK-NEXT: add.rz.sat.f32.bf16 %r7, %rs1, %r6;
; CHECK-NEXT: add.rm.sat.f32.bf16 %r8, %rs1, %r7;
; CHECK-NEXT: add.rp.sat.f32.bf16 %r9, %rs1, %r8;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r9;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r9;
; CHECK-NEXT: ret;
%r0 = fpext bfloat %a to float
@@ -113,10 +113,10 @@ define float @test_add_f32_bf16_2(bfloat %a, float %b) {
; CHECK-NOF32FTZ-NEXT: .reg .b32 %r<3>;
; CHECK-NOF32FTZ-EMPTY:
; CHECK-NOF32FTZ-NEXT: // %bb.0:
-; CHECK-NOF32FTZ-NEXT: ld.param.b16 %rs1, [test_add_f32_bf16_2_param_0];
-; CHECK-NOF32FTZ-NEXT: ld.param.b32 %r1, [test_add_f32_bf16_2_param_1];
+; CHECK-NOF32FTZ-NEXT: ld.param::func.b16 %rs1, [test_add_f32_bf16_2_param_0];
+; CHECK-NOF32FTZ-NEXT: ld.param::func.b32 %r1, [test_add_f32_bf16_2_param_1];
; CHECK-NOF32FTZ-NEXT: add.rn.f32.bf16 %r2, %rs1, %r1;
-; CHECK-NOF32FTZ-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NOF32FTZ-NEXT: st.param::func.b32 [func_retval0], %r2;
; CHECK-NOF32FTZ-NEXT: ret;
;
; CHECK-F32FTZ-LABEL: test_add_f32_bf16_2(
@@ -125,11 +125,11 @@ define float @test_add_f32_bf16_2(bfloat %a, float %b) {
; CHECK-F32FTZ-NEXT: .reg .b32 %r<4>;
; CHECK-F32FTZ-EMPTY:
; CHECK-F32FTZ-NEXT: // %bb.0:
-; CHECK-F32FTZ-NEXT: ld.param.b16 %rs1, [test_add_f32_bf16_2_param_0];
+; CHECK-F32FTZ-NEXT: ld.param::func.b16 %rs1, [test_add_f32_bf16_2_param_0];
; CHECK-F32FTZ-NEXT: cvt.ftz.f32.bf16 %r1, %rs1;
-; CHECK-F32FTZ-NEXT: ld.param.b32 %r2, [test_add_f32_bf16_2_param_1];
+; CHECK-F32FTZ-NEXT: ld.param::func.b32 %r2, [test_add_f32_bf16_2_param_1];
; CHECK-F32FTZ-NEXT: add.rn.ftz.f32 %r3, %r1, %r2;
-; CHECK-F32FTZ-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-F32FTZ-NEXT: st.param::func.b32 [func_retval0], %r3;
; CHECK-F32FTZ-NEXT: ret;
%r0 = fpext bfloat %a to float
%r1 = fadd float %r0, %b
@@ -146,8 +146,8 @@ define float @test_sub_f32_f16_1(half %a, float %b) {
; CHECK-NEXT: .reg .b32 %r<9>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b16 %rs1, [test_sub_f32_f16_1_param_0];
-; CHECK-NEXT: ld.param.b32 %r1, [test_sub_f32_f16_1_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_sub_f32_f16_1_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_sub_f32_f16_1_param_1];
; CHECK-NEXT: sub.rn.f32.f16 %r2, %rs1, %r1;
; CHECK-NEXT: sub.rz.f32.f16 %r3, %rs1, %r2;
; CHECK-NEXT: sub.rm.f32.f16 %r4, %rs1, %r3;
@@ -155,7 +155,7 @@ define float @test_sub_f32_f16_1(half %a, float %b) {
; CHECK-NEXT: sub.rn.sat.f32.f16 %r6, %rs1, %r5;
; CHECK-NEXT: sub.rz.sat.f32.f16 %r7, %rs1, %r6;
; CHECK-NEXT: sub.rm.sat.f32.f16 %r8, %rs1, %r7;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r8;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r8;
; CHECK-NEXT: ret;
%r0 = fpext half %a to float
@@ -194,10 +194,10 @@ define float @test_sub_f32_f16_2(half %a, float %b) {
; CHECK-NOF32FTZ-NEXT: .reg .b32 %r<3>;
; CHECK-NOF32FTZ-EMPTY:
; CHECK-NOF32FTZ-NEXT: // %bb.0:
-; CHECK-NOF32FTZ-NEXT: ld.param.b16 %rs1, [test_sub_f32_f16_2_param_0];
-; CHECK-NOF32FTZ-NEXT: ld.param.b32 %r1, [test_sub_f32_f16_2_param_1];
+; CHECK-NOF32FTZ-NEXT: ld.param::func.b16 %rs1, [test_sub_f32_f16_2_param_0];
+; CHECK-NOF32FTZ-NEXT: ld.param::func.b32 %r1, [test_sub_f32_f16_2_param_1];
; CHECK-NOF32FTZ-NEXT: sub.rn.f32.f16 %r2, %rs1, %r1;
-; CHECK-NOF32FTZ-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NOF32FTZ-NEXT: st.param::func.b32 [func_retval0], %r2;
; CHECK-NOF32FTZ-NEXT: ret;
;
; CHECK-F32FTZ-LABEL: test_sub_f32_f16_2(
@@ -206,11 +206,11 @@ define float @test_sub_f32_f16_2(half %a, float %b) {
; CHECK-F32FTZ-NEXT: .reg .b32 %r<4>;
; CHECK-F32FTZ-EMPTY:
; CHECK-F32FTZ-NEXT: // %bb.0:
-; CHECK-F32FTZ-NEXT: ld.param.b16 %rs1, [test_sub_f32_f16_2_param_0];
+; CHECK-F32FTZ-NEXT: ld.param::func.b16 %rs1, [test_sub_f32_f16_2_param_0];
; CHECK-F32FTZ-NEXT: cvt.ftz.f32.f16 %r1, %rs1;
-; CHECK-F32FTZ-NEXT: ld.param.b32 %r2, [test_sub_f32_f16_2_param_1];
+; CHECK-F32FTZ-NEXT: ld.param::func.b32 %r2, [test_sub_f32_f16_2_param_1];
; CHECK-F32FTZ-NEXT: sub.rn.ftz.f32 %r3, %r1, %r2;
-; CHECK-F32FTZ-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-F32FTZ-NEXT: st.param::func.b32 [func_retval0], %r3;
; CHECK-F32FTZ-NEXT: ret;
%r0 = fpext half %a to float
%r1 = fsub float %r0, %b
@@ -225,8 +225,8 @@ define float @test_sub_f32_bf16_1(bfloat %a, float %b) {
; CHECK-NEXT: .reg .b32 %r<10>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b16 %rs1, [test_sub_f32_bf16_1_param_0];
-; CHECK-NEXT: ld.param.b32 %r1, [test_sub_f32_bf16_1_param_1];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_sub_f32_bf16_1_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_sub_f32_bf16_1_param_1];
; CHECK-NEXT: sub.rn.f32.bf16 %r2, %rs1, %r1;
; CHECK-NEXT: sub.rz.f32.bf16 %r3, %rs1, %r2;
; CHECK-NEXT: sub.rm.f32.bf16 %r4, %rs1, %r3;
@@ -235,7 +235,7 @@ define float @test_sub_f32_bf16_1(bfloat %a, float %b) {
; CHECK-NEXT: sub.rz.sat.f32.bf16 %r7, %rs1, %r6;
; CHECK-NEXT: sub.rm.sat.f32.bf16 %r8, %rs1, %r7;
; CHECK-NEXT: sub.rp.sat.f32.bf16 %r9, %rs1, %r8;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r9;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r9;
; CHECK-NEXT: ret;
%r0 = fpext bfloat %a to float
@@ -274,10 +274,10 @@ define float @test_sub_f32_bf16_2(bfloat %a, float %b) {
; CHECK-NOF32FTZ-NEXT: .reg .b32 %r<3>;
; CHECK-NOF32FTZ-EMPTY:
; CHECK-NOF32FTZ-NEXT: // %bb.0:
-; CHECK-NOF32FTZ-NEXT: ld.param.b16 %rs1, [test_sub_f32_bf16_2_param_0];
-; CHECK-NOF32FTZ-NEXT: ld.param.b32 %r1, [test_sub_f32_bf16_2_param_1];
+; CHECK-NOF32FTZ-NEXT: ld.param::func.b16 %rs1, [test_sub_f32_bf16_2_param_0];
+; CHECK-NOF32FTZ-NEXT: ld.param::func.b32 %r1, [test_sub_f32_bf16_2_param_1];
; CHECK-NOF32FTZ-NEXT: sub.rn.f32.bf16 %r2, %rs1, %r1;
-; CHECK-NOF32FTZ-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NOF32FTZ-NEXT: st.param::func.b32 [func_retval0], %r2;
; CHECK-NOF32FTZ-NEXT: ret;
;
; CHECK-F32FTZ-LABEL: test_sub_f32_bf16_2(
@@ -286,11 +286,11 @@ define float @test_sub_f32_bf16_2(bfloat %a, float %b) {
; CHECK-F32FTZ-NEXT: .reg .b32 %r<4>;
; CHECK-F32FTZ-EMPTY:
; CHECK-F32FTZ-NEXT: // %bb.0:
-; CHECK-F32FTZ-NEXT: ld.param.b16 %rs1, [test_sub_f32_bf16_2_param_0];
+; CHECK-F32FTZ-NEXT: ld.param::func.b16 %rs1, [test_sub_f32_bf16_2_param_0];
; CHECK-F32FTZ-NEXT: cvt.ftz.f32.bf16 %r1, %rs1;
-; CHECK-F32FTZ-NEXT: ld.param.b32 %r2, [test_sub_f32_bf16_2_param_1];
+; CHECK-F32FTZ-NEXT: ld.param::func.b32 %r2, [test_sub_f32_bf16_2_param_1];
; CHECK-F32FTZ-NEXT: sub.rn.ftz.f32 %r3, %r1, %r2;
-; CHECK-F32FTZ-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-F32FTZ-NEXT: st.param::func.b32 [func_retval0], %r3;
; CHECK-F32FTZ-NEXT: ret;
%r0 = fpext bfloat %a to float
%r1 = fsub float %r0, %b
@@ -307,9 +307,9 @@ define float @test_fma_f32_f16_1(half %a, half %b, float %c) {
; CHECK-NEXT: .reg .b32 %r<9>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b16 %rs1, [test_fma_f32_f16_1_param_0];
-; CHECK-NEXT: ld.param.b16 %rs2, [test_fma_f32_f16_1_param_1];
-; CHECK-NEXT: ld.param.b32 %r1, [test_fma_f32_f16_1_param_2];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_fma_f32_f16_1_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs2, [test_fma_f32_f16_1_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_fma_f32_f16_1_param_2];
; CHECK-NEXT: fma.rn.f32.f16 %r2, %rs1, %rs2, %r1;
; CHECK-NEXT: fma.rz.f32.f16 %r3, %rs1, %rs2, %r2;
; CHECK-NEXT: fma.rm.f32.f16 %r4, %rs1, %rs2, %r3;
@@ -317,7 +317,7 @@ define float @test_fma_f32_f16_1(half %a, half %b, float %c) {
; CHECK-NEXT: fma.rn.sat.f32.f16 %r6, %rs1, %rs2, %r5;
; CHECK-NEXT: fma.rz.sat.f32.f16 %r7, %rs1, %rs2, %r6;
; CHECK-NEXT: fma.rm.sat.f32.f16 %r8, %rs1, %rs2, %r7;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r8;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r8;
; CHECK-NEXT: ret;
%r0 = fpext half %a to float
%r1 = fpext half %b to float
@@ -343,11 +343,11 @@ define float @test_fma_f32_f16_2(half %a, half %b, float %c) {
; CHECK-NOF32FTZ-NEXT: .reg .b32 %r<3>;
; CHECK-NOF32FTZ-EMPTY:
; CHECK-NOF32FTZ-NEXT: // %bb.0:
-; CHECK-NOF32FTZ-NEXT: ld.param.b16 %rs1, [test_fma_f32_f16_2_param_0];
-; CHECK-NOF32FTZ-NEXT: ld.param.b16 %rs2, [test_fma_f32_f16_2_param_1];
-; CHECK-NOF32FTZ-NEXT: ld.param.b32 %r1, [test_fma_f32_f16_2_param_2];
+; CHECK-NOF32FTZ-NEXT: ld.param::func.b16 %rs1, [test_fma_f32_f16_2_param_0];
+; CHECK-NOF32FTZ-NEXT: ld.param::func.b16 %rs2, [test_fma_f32_f16_2_param_1];
+; CHECK-NOF32FTZ-NEXT: ld.param::func.b32 %r1, [test_fma_f32_f16_2_param_2];
; CHECK-NOF32FTZ-NEXT: fma.rn.f32.f16 %r2, %rs1, %rs2, %r1;
-; CHECK-NOF32FTZ-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NOF32FTZ-NEXT: st.param::func.b32 [func_retval0], %r2;
; CHECK-NOF32FTZ-NEXT: ret;
;
; CHECK-F32FTZ-LABEL: test_fma_f32_f16_2(
@@ -356,13 +356,13 @@ define float @test_fma_f32_f16_2(half %a, half %b, float %c) {
; CHECK-F32FTZ-NEXT: .reg .b32 %r<5>;
; CHECK-F32FTZ-EMPTY:
; CHECK-F32FTZ-NEXT: // %bb.0:
-; CHECK-F32FTZ-NEXT: ld.param.b16 %rs1, [test_fma_f32_f16_2_param_0];
+; CHECK-F32FTZ-NEXT: ld.param::func.b16 %rs1, [test_fma_f32_f16_2_param_0];
; CHECK-F32FTZ-NEXT: cvt.ftz.f32.f16 %r1, %rs1;
-; CHECK-F32FTZ-NEXT: ld.param.b16 %rs2, [test_fma_f32_f16_2_param_1];
+; CHECK-F32FTZ-NEXT: ld.param::func.b16 %rs2, [test_fma_f32_f16_2_param_1];
; CHECK-F32FTZ-NEXT: cvt.ftz.f32.f16 %r2, %rs2;
-; CHECK-F32FTZ-NEXT: ld.param.b32 %r3, [test_fma_f32_f16_2_param_2];
+; CHECK-F32FTZ-NEXT: ld.param::func.b32 %r3, [test_fma_f32_f16_2_param_2];
; CHECK-F32FTZ-NEXT: fma.rn.ftz.f32 %r4, %r1, %r2, %r3;
-; CHECK-F32FTZ-NEXT: st.param.b32 [func_retval0], %r4;
+; CHECK-F32FTZ-NEXT: st.param::func.b32 [func_retval0], %r4;
; CHECK-F32FTZ-NEXT: ret;
%r0 = fpext half %a to float
%r1 = fpext half %b to float
@@ -378,9 +378,9 @@ define float @test_fma_f32_bf16_1(bfloat %a, bfloat %b, float %c) {
; CHECK-NEXT: .reg .b32 %r<9>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b16 %rs1, [test_fma_f32_bf16_1_param_0];
-; CHECK-NEXT: ld.param.b16 %rs2, [test_fma_f32_bf16_1_param_1];
-; CHECK-NEXT: ld.param.b32 %r1, [test_fma_f32_bf16_1_param_2];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_fma_f32_bf16_1_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs2, [test_fma_f32_bf16_1_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_fma_f32_bf16_1_param_2];
; CHECK-NEXT: fma.rn.f32.bf16 %r2, %rs1, %rs2, %r1;
; CHECK-NEXT: fma.rz.f32.bf16 %r3, %rs1, %rs2, %r2;
; CHECK-NEXT: fma.rm.f32.bf16 %r4, %rs1, %rs2, %r3;
@@ -388,7 +388,7 @@ define float @test_fma_f32_bf16_1(bfloat %a, bfloat %b, float %c) {
; CHECK-NEXT: fma.rn.sat.f32.bf16 %r6, %rs1, %rs2, %r5;
; CHECK-NEXT: fma.rz.sat.f32.bf16 %r7, %rs1, %rs2, %r6;
; CHECK-NEXT: fma.rm.sat.f32.bf16 %r8, %rs1, %rs2, %r7;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r8;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r8;
; CHECK-NEXT: ret;
%r0 = fpext bfloat %a to float
%r1 = fpext bfloat %b to float
@@ -414,11 +414,11 @@ define float @test_fma_f32_bf16_2(bfloat %a, bfloat %b, float %c) {
; CHECK-NOF32FTZ-NEXT: .reg .b32 %r<3>;
; CHECK-NOF32FTZ-EMPTY:
; CHECK-NOF32FTZ-NEXT: // %bb.0:
-; CHECK-NOF32FTZ-NEXT: ld.param.b16 %rs1, [test_fma_f32_bf16_2_param_0];
-; CHECK-NOF32FTZ-NEXT: ld.param.b16 %rs2, [test_fma_f32_bf16_2_param_1];
-; CHECK-NOF32FTZ-NEXT: ld.param.b32 %r1, [test_fma_f32_bf16_2_param_2];
+; CHECK-NOF32FTZ-NEXT: ld.param::func.b16 %rs1, [test_fma_f32_bf16_2_param_0];
+; CHECK-NOF32FTZ-NEXT: ld.param::func.b16 %rs2, [test_fma_f32_bf16_2_param_1];
+; CHECK-NOF32FTZ-NEXT: ld.param::func.b32 %r1, [test_fma_f32_bf16_2_param_2];
; CHECK-NOF32FTZ-NEXT: fma.rn.f32.bf16 %r2, %rs1, %rs2, %r1;
-; CHECK-NOF32FTZ-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NOF32FTZ-NEXT: st.param::func.b32 [func_retval0], %r2;
; CHECK-NOF32FTZ-NEXT: ret;
;
; CHECK-F32FTZ-LABEL: test_fma_f32_bf16_2(
@@ -427,13 +427,13 @@ define float @test_fma_f32_bf16_2(bfloat %a, bfloat %b, float %c) {
; CHECK-F32FTZ-NEXT: .reg .b32 %r<5>;
; CHECK-F32FTZ-EMPTY:
; CHECK-F32FTZ-NEXT: // %bb.0:
-; CHECK-F32FTZ-NEXT: ld.param.b16 %rs1, [test_fma_f32_bf16_2_param_0];
+; CHECK-F32FTZ-NEXT: ld.param::func.b16 %rs1, [test_fma_f32_bf16_2_param_0];
; CHECK-F32FTZ-NEXT: cvt.ftz.f32.bf16 %r1, %rs1;
-; CHECK-F32FTZ-NEXT: ld.param.b16 %rs2, [test_fma_f32_bf16_2_param_1];
+; CHECK-F32FTZ-NEXT: ld.param::func.b16 %rs2, [test_fma_f32_bf16_2_param_1];
; CHECK-F32FTZ-NEXT: cvt.ftz.f32.bf16 %r2, %rs2;
-; CHECK-F32FTZ-NEXT: ld.param.b32 %r3, [test_fma_f32_bf16_2_param_2];
+; CHECK-F32FTZ-NEXT: ld.param::func.b32 %r3, [test_fma_f32_bf16_2_param_2];
; CHECK-F32FTZ-NEXT: fma.rn.ftz.f32 %r4, %r1, %r2, %r3;
-; CHECK-F32FTZ-NEXT: st.param.b32 [func_retval0], %r4;
+; CHECK-F32FTZ-NEXT: st.param::func.b32 [func_retval0], %r4;
; CHECK-F32FTZ-NEXT: ret;
%r0 = fpext bfloat %a to float
%r1 = fpext bfloat %b to float
diff --git a/llvm/test/CodeGen/NVPTX/no-f32x2.ll b/llvm/test/CodeGen/NVPTX/no-f32x2.ll
index b2b909166a0c6..fdf84e86fa4bd 100644
--- a/llvm/test/CodeGen/NVPTX/no-f32x2.ll
+++ b/llvm/test/CodeGen/NVPTX/no-f32x2.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc < %s -mcpu=sm_100 | FileCheck %s --check-prefix=F32X2
-; RUN: llc < %s -mcpu=sm_90 | FileCheck %s --check-prefix=NOF32X2
-; RUN: llc < %s -mcpu=sm_100 -nvptx-no-f32x2 | FileCheck %s --check-prefix=NOF32X2
+; RUN: llc < %s -mcpu=sm_100 -mattr=+ptx86 | FileCheck %s --check-prefix=F32X2
+; RUN: llc < %s -mcpu=sm_90 -mattr=+ptx86 | FileCheck %s --check-prefix=NOF32X2
+; RUN: llc < %s -mcpu=sm_100 -mattr=+ptx86 -nvptx-no-f32x2 | FileCheck %s --check-prefix=NOF32X2
target triple = "nvptx64-nvidia-cuda"
@@ -11,10 +11,10 @@ define <2 x float> @test(<2 x float> %a, <2 x float> %b) {
; F32X2-NEXT: .reg .b64 %rd<4>;
; F32X2-EMPTY:
; F32X2-NEXT: // %bb.0:
-; F32X2-NEXT: ld.param.b64 %rd1, [test_param_0];
-; F32X2-NEXT: ld.param.b64 %rd2, [test_param_1];
+; F32X2-NEXT: ld.param::func.b64 %rd1, [test_param_0];
+; F32X2-NEXT: ld.param::func.b64 %rd2, [test_param_1];
; F32X2-NEXT: add.rn.f32x2 %rd3, %rd1, %rd2;
-; F32X2-NEXT: st.param.b64 [func_retval0], %rd3;
+; F32X2-NEXT: st.param::func.b64 [func_retval0], %rd3;
; F32X2-NEXT: ret;
;
; NOF32X2-LABEL: test(
@@ -22,11 +22,11 @@ define <2 x float> @test(<2 x float> %a, <2 x float> %b) {
; NOF32X2-NEXT: .reg .b32 %r<7>;
; NOF32X2-EMPTY:
; NOF32X2-NEXT: // %bb.0:
-; NOF32X2-NEXT: ld.param.v2.b32 {%r1, %r2}, [test_param_0];
-; NOF32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_param_1];
+; NOF32X2-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [test_param_0];
+; NOF32X2-NEXT: ld.param::func.v2.b32 {%r3, %r4}, [test_param_1];
; NOF32X2-NEXT: add.rn.f32 %r5, %r2, %r4;
; NOF32X2-NEXT: add.rn.f32 %r6, %r1, %r3;
-; NOF32X2-NEXT: st.param.v2.b32 [func_retval0], {%r6, %r5};
+; NOF32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r6, %r5};
; NOF32X2-NEXT: ret;
%c = fadd <2 x float> %a, %b
ret <2 x float> %c
diff --git a/llvm/test/CodeGen/NVPTX/reduction-intrinsics.ll b/llvm/test/CodeGen/NVPTX/reduction-intrinsics.ll
index 87787ba2bf81c..d6f3f8c9ef14d 100644
--- a/llvm/test/CodeGen/NVPTX/reduction-intrinsics.ll
+++ b/llvm/test/CodeGen/NVPTX/reduction-intrinsics.ll
@@ -15,72 +15,131 @@ target triple = "nvptx64-nvidia-cuda"
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
define half @reduce_fadd_half(<8 x half> %in) {
-; CHECK-LABEL: reduce_fadd_half(
-; CHECK: {
-; CHECK-NEXT: .reg .b16 %rs<18>;
-; CHECK-NEXT: .reg .b32 %r<5>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fadd_half_param_0];
-; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r4;
-; CHECK-NEXT: mov.b32 {%rs3, %rs4}, %r3;
-; CHECK-NEXT: mov.b32 {%rs5, %rs6}, %r2;
-; CHECK-NEXT: mov.b32 {%rs7, %rs8}, %r1;
-; CHECK-NEXT: mov.b16 %rs9, 0x0000;
-; CHECK-NEXT: add.rn.f16 %rs10, %rs7, %rs9;
-; CHECK-NEXT: add.rn.f16 %rs11, %rs10, %rs8;
-; CHECK-NEXT: add.rn.f16 %rs12, %rs11, %rs5;
-; CHECK-NEXT: add.rn.f16 %rs13, %rs12, %rs6;
-; CHECK-NEXT: add.rn.f16 %rs14, %rs13, %rs3;
-; CHECK-NEXT: add.rn.f16 %rs15, %rs14, %rs4;
-; CHECK-NEXT: add.rn.f16 %rs16, %rs15, %rs1;
-; CHECK-NEXT: add.rn.f16 %rs17, %rs16, %rs2;
-; CHECK-NEXT: st.param.b16 [func_retval0], %rs17;
-; CHECK-NEXT: ret;
+; CHECK-SM80-LABEL: reduce_fadd_half(
+; CHECK-SM80: {
+; CHECK-SM80-NEXT: .reg .b16 %rs<18>;
+; CHECK-SM80-NEXT: .reg .b32 %r<5>;
+; CHECK-SM80-EMPTY:
+; CHECK-SM80-NEXT: // %bb.0:
+; CHECK-SM80-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fadd_half_param_0];
+; CHECK-SM80-NEXT: mov.b32 {%rs1, %rs2}, %r4;
+; CHECK-SM80-NEXT: mov.b32 {%rs3, %rs4}, %r3;
+; CHECK-SM80-NEXT: mov.b32 {%rs5, %rs6}, %r2;
+; CHECK-SM80-NEXT: mov.b32 {%rs7, %rs8}, %r1;
+; CHECK-SM80-NEXT: mov.b16 %rs9, 0x0000;
+; CHECK-SM80-NEXT: add.rn.f16 %rs10, %rs7, %rs9;
+; CHECK-SM80-NEXT: add.rn.f16 %rs11, %rs10, %rs8;
+; CHECK-SM80-NEXT: add.rn.f16 %rs12, %rs11, %rs5;
+; CHECK-SM80-NEXT: add.rn.f16 %rs13, %rs12, %rs6;
+; CHECK-SM80-NEXT: add.rn.f16 %rs14, %rs13, %rs3;
+; CHECK-SM80-NEXT: add.rn.f16 %rs15, %rs14, %rs4;
+; CHECK-SM80-NEXT: add.rn.f16 %rs16, %rs15, %rs1;
+; CHECK-SM80-NEXT: add.rn.f16 %rs17, %rs16, %rs2;
+; CHECK-SM80-NEXT: st.param.b16 [func_retval0], %rs17;
+; CHECK-SM80-NEXT: ret;
+;
+; CHECK-SM100-LABEL: reduce_fadd_half(
+; CHECK-SM100: {
+; CHECK-SM100-NEXT: .reg .b16 %rs<18>;
+; CHECK-SM100-NEXT: .reg .b32 %r<5>;
+; CHECK-SM100-EMPTY:
+; CHECK-SM100-NEXT: // %bb.0:
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fadd_half_param_0];
+; CHECK-SM100-NEXT: mov.b32 {%rs1, %rs2}, %r4;
+; CHECK-SM100-NEXT: mov.b32 {%rs3, %rs4}, %r3;
+; CHECK-SM100-NEXT: mov.b32 {%rs5, %rs6}, %r2;
+; CHECK-SM100-NEXT: mov.b32 {%rs7, %rs8}, %r1;
+; CHECK-SM100-NEXT: mov.b16 %rs9, 0x0000;
+; CHECK-SM100-NEXT: add.rn.f16 %rs10, %rs7, %rs9;
+; CHECK-SM100-NEXT: add.rn.f16 %rs11, %rs10, %rs8;
+; CHECK-SM100-NEXT: add.rn.f16 %rs12, %rs11, %rs5;
+; CHECK-SM100-NEXT: add.rn.f16 %rs13, %rs12, %rs6;
+; CHECK-SM100-NEXT: add.rn.f16 %rs14, %rs13, %rs3;
+; CHECK-SM100-NEXT: add.rn.f16 %rs15, %rs14, %rs4;
+; CHECK-SM100-NEXT: add.rn.f16 %rs16, %rs15, %rs1;
+; CHECK-SM100-NEXT: add.rn.f16 %rs17, %rs16, %rs2;
+; CHECK-SM100-NEXT: st.param::func.b16 [func_retval0], %rs17;
+; CHECK-SM100-NEXT: ret;
%res = call half @llvm.vector.reduce.fadd(half 0.0, <8 x half> %in)
ret half %res
}
define half @reduce_fadd_half_reassoc(<8 x half> %in) {
-; CHECK-LABEL: reduce_fadd_half_reassoc(
-; CHECK: {
-; CHECK-NEXT: .reg .b16 %rs<6>;
-; CHECK-NEXT: .reg .b32 %r<8>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fadd_half_reassoc_param_0];
-; CHECK-NEXT: add.rn.f16x2 %r5, %r2, %r4;
-; CHECK-NEXT: add.rn.f16x2 %r6, %r1, %r3;
-; CHECK-NEXT: add.rn.f16x2 %r7, %r6, %r5;
-; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r7;
-; CHECK-NEXT: add.rn.f16 %rs3, %rs1, %rs2;
-; CHECK-NEXT: mov.b16 %rs4, 0x0000;
-; CHECK-NEXT: add.rn.f16 %rs5, %rs3, %rs4;
-; CHECK-NEXT: st.param.b16 [func_retval0], %rs5;
-; CHECK-NEXT: ret;
+; CHECK-SM80-LABEL: reduce_fadd_half_reassoc(
+; CHECK-SM80: {
+; CHECK-SM80-NEXT: .reg .b16 %rs<6>;
+; CHECK-SM80-NEXT: .reg .b32 %r<8>;
+; CHECK-SM80-EMPTY:
+; CHECK-SM80-NEXT: // %bb.0:
+; CHECK-SM80-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fadd_half_reassoc_param_0];
+; CHECK-SM80-NEXT: add.rn.f16x2 %r5, %r2, %r4;
+; CHECK-SM80-NEXT: add.rn.f16x2 %r6, %r1, %r3;
+; CHECK-SM80-NEXT: add.rn.f16x2 %r7, %r6, %r5;
+; CHECK-SM80-NEXT: mov.b32 {%rs1, %rs2}, %r7;
+; CHECK-SM80-NEXT: add.rn.f16 %rs3, %rs1, %rs2;
+; CHECK-SM80-NEXT: mov.b16 %rs4, 0x0000;
+; CHECK-SM80-NEXT: add.rn.f16 %rs5, %rs3, %rs4;
+; CHECK-SM80-NEXT: st.param.b16 [func_retval0], %rs5;
+; CHECK-SM80-NEXT: ret;
+;
+; CHECK-SM100-LABEL: reduce_fadd_half_reassoc(
+; CHECK-SM100: {
+; CHECK-SM100-NEXT: .reg .b16 %rs<6>;
+; CHECK-SM100-NEXT: .reg .b32 %r<8>;
+; CHECK-SM100-EMPTY:
+; CHECK-SM100-NEXT: // %bb.0:
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fadd_half_reassoc_param_0];
+; CHECK-SM100-NEXT: add.rn.f16x2 %r5, %r2, %r4;
+; CHECK-SM100-NEXT: add.rn.f16x2 %r6, %r1, %r3;
+; CHECK-SM100-NEXT: add.rn.f16x2 %r7, %r6, %r5;
+; CHECK-SM100-NEXT: mov.b32 {%rs1, %rs2}, %r7;
+; CHECK-SM100-NEXT: add.rn.f16 %rs3, %rs1, %rs2;
+; CHECK-SM100-NEXT: mov.b16 %rs4, 0x0000;
+; CHECK-SM100-NEXT: add.rn.f16 %rs5, %rs3, %rs4;
+; CHECK-SM100-NEXT: st.param::func.b16 [func_retval0], %rs5;
+; CHECK-SM100-NEXT: ret;
%res = call reassoc half @llvm.vector.reduce.fadd(half 0.0, <8 x half> %in)
ret half %res
}
define half @reduce_fadd_half_reassoc_nonpow2(<7 x half> %in) {
-; CHECK-LABEL: reduce_fadd_half_reassoc_nonpow2(
-; CHECK: {
-; CHECK-NEXT: .reg .b16 %rs<16>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b16 %rs7, [reduce_fadd_half_reassoc_nonpow2_param_0+12];
-; CHECK-NEXT: ld.param.v2.b16 {%rs5, %rs6}, [reduce_fadd_half_reassoc_nonpow2_param_0+8];
-; CHECK-NEXT: ld.param.v4.b16 {%rs1, %rs2, %rs3, %rs4}, [reduce_fadd_half_reassoc_nonpow2_param_0];
-; CHECK-NEXT: mov.b16 %rs8, 0x0000;
-; CHECK-NEXT: add.rn.f16 %rs9, %rs1, %rs8;
-; CHECK-NEXT: add.rn.f16 %rs10, %rs9, %rs2;
-; CHECK-NEXT: add.rn.f16 %rs11, %rs10, %rs3;
-; CHECK-NEXT: add.rn.f16 %rs12, %rs11, %rs4;
-; CHECK-NEXT: add.rn.f16 %rs13, %rs12, %rs5;
-; CHECK-NEXT: add.rn.f16 %rs14, %rs13, %rs6;
-; CHECK-NEXT: add.rn.f16 %rs15, %rs14, %rs7;
-; CHECK-NEXT: st.param.b16 [func_retval0], %rs15;
-; CHECK-NEXT: ret;
+; CHECK-SM80-LABEL: reduce_fadd_half_reassoc_nonpow2(
+; CHECK-SM80: {
+; CHECK-SM80-NEXT: .reg .b16 %rs<16>;
+; CHECK-SM80-EMPTY:
+; CHECK-SM80-NEXT: // %bb.0:
+; CHECK-SM80-NEXT: ld.param.b16 %rs7, [reduce_fadd_half_reassoc_nonpow2_param_0+12];
+; CHECK-SM80-NEXT: ld.param.v2.b16 {%rs5, %rs6}, [reduce_fadd_half_reassoc_nonpow2_param_0+8];
+; CHECK-SM80-NEXT: ld.param.v4.b16 {%rs1, %rs2, %rs3, %rs4}, [reduce_fadd_half_reassoc_nonpow2_param_0];
+; CHECK-SM80-NEXT: mov.b16 %rs8, 0x0000;
+; CHECK-SM80-NEXT: add.rn.f16 %rs9, %rs1, %rs8;
+; CHECK-SM80-NEXT: add.rn.f16 %rs10, %rs9, %rs2;
+; CHECK-SM80-NEXT: add.rn.f16 %rs11, %rs10, %rs3;
+; CHECK-SM80-NEXT: add.rn.f16 %rs12, %rs11, %rs4;
+; CHECK-SM80-NEXT: add.rn.f16 %rs13, %rs12, %rs5;
+; CHECK-SM80-NEXT: add.rn.f16 %rs14, %rs13, %rs6;
+; CHECK-SM80-NEXT: add.rn.f16 %rs15, %rs14, %rs7;
+; CHECK-SM80-NEXT: st.param.b16 [func_retval0], %rs15;
+; CHECK-SM80-NEXT: ret;
+;
+; CHECK-SM100-LABEL: reduce_fadd_half_reassoc_nonpow2(
+; CHECK-SM100: {
+; CHECK-SM100-NEXT: .reg .b16 %rs<16>;
+; CHECK-SM100-EMPTY:
+; CHECK-SM100-NEXT: // %bb.0:
+; CHECK-SM100-NEXT: ld.param::func.b16 %rs7, [reduce_fadd_half_reassoc_nonpow2_param_0+12];
+; CHECK-SM100-NEXT: ld.param::func.v2.b16 {%rs5, %rs6}, [reduce_fadd_half_reassoc_nonpow2_param_0+8];
+; CHECK-SM100-NEXT: ld.param::func.v4.b16 {%rs1, %rs2, %rs3, %rs4}, [reduce_fadd_half_reassoc_nonpow2_param_0];
+; CHECK-SM100-NEXT: mov.b16 %rs8, 0x0000;
+; CHECK-SM100-NEXT: add.rn.f16 %rs9, %rs1, %rs8;
+; CHECK-SM100-NEXT: add.rn.f16 %rs10, %rs9, %rs2;
+; CHECK-SM100-NEXT: add.rn.f16 %rs11, %rs10, %rs3;
+; CHECK-SM100-NEXT: add.rn.f16 %rs12, %rs11, %rs4;
+; CHECK-SM100-NEXT: add.rn.f16 %rs13, %rs12, %rs5;
+; CHECK-SM100-NEXT: add.rn.f16 %rs14, %rs13, %rs6;
+; CHECK-SM100-NEXT: add.rn.f16 %rs15, %rs14, %rs7;
+; CHECK-SM100-NEXT: st.param::func.b16 [func_retval0], %rs15;
+; CHECK-SM100-NEXT: ret;
%res = call half @llvm.vector.reduce.fadd(half 0.0, <7 x half> %in)
ret half %res
}
@@ -110,10 +169,10 @@ define float @reduce_fadd_float(<8 x float> %in) {
; CHECK-SM100-NEXT: .reg .b64 %rd<5>;
; CHECK-SM100-EMPTY:
; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param.v2.b64 {%rd3, %rd4}, [reduce_fadd_float_param_0+16];
+; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd3, %rd4}, [reduce_fadd_float_param_0+16];
; CHECK-SM100-NEXT: mov.b64 {%r1, %r2}, %rd4;
; CHECK-SM100-NEXT: mov.b64 {%r3, %r4}, %rd3;
-; CHECK-SM100-NEXT: ld.param.v2.b64 {%rd1, %rd2}, [reduce_fadd_float_param_0];
+; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd1, %rd2}, [reduce_fadd_float_param_0];
; CHECK-SM100-NEXT: mov.b64 {%r5, %r6}, %rd2;
; CHECK-SM100-NEXT: mov.b64 {%r7, %r8}, %rd1;
; CHECK-SM100-NEXT: add.rn.f32 %r9, %r7, 0f00000000;
@@ -124,7 +183,7 @@ define float @reduce_fadd_float(<8 x float> %in) {
; CHECK-SM100-NEXT: add.rn.f32 %r14, %r13, %r4;
; CHECK-SM100-NEXT: add.rn.f32 %r15, %r14, %r1;
; CHECK-SM100-NEXT: add.rn.f32 %r16, %r15, %r2;
-; CHECK-SM100-NEXT: st.param.b32 [func_retval0], %r16;
+; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r16;
; CHECK-SM100-NEXT: ret;
%res = call float @llvm.vector.reduce.fadd(float 0.0, <8 x float> %in)
ret float %res
@@ -155,15 +214,15 @@ define float @reduce_fadd_float_reassoc(<8 x float> %in) {
; CHECK-SM100-NEXT: .reg .b64 %rd<8>;
; CHECK-SM100-EMPTY:
; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param.v2.b64 {%rd3, %rd4}, [reduce_fadd_float_reassoc_param_0+16];
-; CHECK-SM100-NEXT: ld.param.v2.b64 {%rd1, %rd2}, [reduce_fadd_float_reassoc_param_0];
+; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd3, %rd4}, [reduce_fadd_float_reassoc_param_0+16];
+; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd1, %rd2}, [reduce_fadd_float_reassoc_param_0];
; CHECK-SM100-NEXT: add.rn.f32x2 %rd5, %rd2, %rd4;
; CHECK-SM100-NEXT: add.rn.f32x2 %rd6, %rd1, %rd3;
; CHECK-SM100-NEXT: add.rn.f32x2 %rd7, %rd6, %rd5;
; CHECK-SM100-NEXT: mov.b64 {%r1, %r2}, %rd7;
; CHECK-SM100-NEXT: add.rn.f32 %r3, %r1, %r2;
; CHECK-SM100-NEXT: add.rn.f32 %r4, %r3, 0f00000000;
-; CHECK-SM100-NEXT: st.param.b32 [func_retval0], %r4;
+; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r4;
; CHECK-SM100-NEXT: ret;
%res = call reassoc float @llvm.vector.reduce.fadd(float 0.0, <8 x float> %in)
ret float %res
@@ -194,12 +253,12 @@ define float @reduce_fadd_float_reassoc_nonpow2(<7 x float> %in) {
; CHECK-SM100-NEXT: .reg .b64 %rd<8>;
; CHECK-SM100-EMPTY:
; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param.b64 %rd1, [reduce_fadd_float_reassoc_nonpow2_param_0+16];
+; CHECK-SM100-NEXT: ld.param::func.b64 %rd1, [reduce_fadd_float_reassoc_nonpow2_param_0+16];
; CHECK-SM100-NEXT: mov.b64 {%r5, %r6}, %rd1;
-; CHECK-SM100-NEXT: ld.param.v2.b64 {%rd2, %rd3}, [reduce_fadd_float_reassoc_nonpow2_param_0];
+; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd2, %rd3}, [reduce_fadd_float_reassoc_nonpow2_param_0];
; CHECK-SM100-NEXT: mov.b64 {%r3, %r4}, %rd3;
; CHECK-SM100-NEXT: mov.b64 {%r1, %r2}, %rd2;
-; CHECK-SM100-NEXT: ld.param.b32 %r7, [reduce_fadd_float_reassoc_nonpow2_param_0+24];
+; CHECK-SM100-NEXT: ld.param::func.b32 %r7, [reduce_fadd_float_reassoc_nonpow2_param_0+24];
; CHECK-SM100-NEXT: add.rn.f32x2 %rd4, %rd2, %rd1;
; CHECK-SM100-NEXT: mov.b32 %r8, 0f80000000;
; CHECK-SM100-NEXT: mov.b64 %rd5, {%r7, %r8};
@@ -208,78 +267,136 @@ define float @reduce_fadd_float_reassoc_nonpow2(<7 x float> %in) {
; CHECK-SM100-NEXT: mov.b64 {%r9, %r10}, %rd7;
; CHECK-SM100-NEXT: add.rn.f32 %r11, %r9, %r10;
; CHECK-SM100-NEXT: add.rn.f32 %r12, %r11, 0f00000000;
-; CHECK-SM100-NEXT: st.param.b32 [func_retval0], %r12;
+; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r12;
; CHECK-SM100-NEXT: ret;
%res = call reassoc float @llvm.vector.reduce.fadd(float 0.0, <7 x float> %in)
ret float %res
}
define half @reduce_fmul_half(<8 x half> %in) {
-; CHECK-LABEL: reduce_fmul_half(
-; CHECK: {
-; CHECK-NEXT: .reg .b16 %rs<16>;
-; CHECK-NEXT: .reg .b32 %r<5>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fmul_half_param_0];
-; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r4;
-; CHECK-NEXT: mov.b32 {%rs3, %rs4}, %r3;
-; CHECK-NEXT: mov.b32 {%rs5, %rs6}, %r2;
-; CHECK-NEXT: mov.b32 {%rs7, %rs8}, %r1;
-; CHECK-NEXT: mul.rn.f16 %rs9, %rs7, %rs8;
-; CHECK-NEXT: mul.rn.f16 %rs10, %rs9, %rs5;
-; CHECK-NEXT: mul.rn.f16 %rs11, %rs10, %rs6;
-; CHECK-NEXT: mul.rn.f16 %rs12, %rs11, %rs3;
-; CHECK-NEXT: mul.rn.f16 %rs13, %rs12, %rs4;
-; CHECK-NEXT: mul.rn.f16 %rs14, %rs13, %rs1;
-; CHECK-NEXT: mul.rn.f16 %rs15, %rs14, %rs2;
-; CHECK-NEXT: st.param.b16 [func_retval0], %rs15;
-; CHECK-NEXT: ret;
+; CHECK-SM80-LABEL: reduce_fmul_half(
+; CHECK-SM80: {
+; CHECK-SM80-NEXT: .reg .b16 %rs<16>;
+; CHECK-SM80-NEXT: .reg .b32 %r<5>;
+; CHECK-SM80-EMPTY:
+; CHECK-SM80-NEXT: // %bb.0:
+; CHECK-SM80-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fmul_half_param_0];
+; CHECK-SM80-NEXT: mov.b32 {%rs1, %rs2}, %r4;
+; CHECK-SM80-NEXT: mov.b32 {%rs3, %rs4}, %r3;
+; CHECK-SM80-NEXT: mov.b32 {%rs5, %rs6}, %r2;
+; CHECK-SM80-NEXT: mov.b32 {%rs7, %rs8}, %r1;
+; CHECK-SM80-NEXT: mul.rn.f16 %rs9, %rs7, %rs8;
+; CHECK-SM80-NEXT: mul.rn.f16 %rs10, %rs9, %rs5;
+; CHECK-SM80-NEXT: mul.rn.f16 %rs11, %rs10, %rs6;
+; CHECK-SM80-NEXT: mul.rn.f16 %rs12, %rs11, %rs3;
+; CHECK-SM80-NEXT: mul.rn.f16 %rs13, %rs12, %rs4;
+; CHECK-SM80-NEXT: mul.rn.f16 %rs14, %rs13, %rs1;
+; CHECK-SM80-NEXT: mul.rn.f16 %rs15, %rs14, %rs2;
+; CHECK-SM80-NEXT: st.param.b16 [func_retval0], %rs15;
+; CHECK-SM80-NEXT: ret;
+;
+; CHECK-SM100-LABEL: reduce_fmul_half(
+; CHECK-SM100: {
+; CHECK-SM100-NEXT: .reg .b16 %rs<16>;
+; CHECK-SM100-NEXT: .reg .b32 %r<5>;
+; CHECK-SM100-EMPTY:
+; CHECK-SM100-NEXT: // %bb.0:
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fmul_half_param_0];
+; CHECK-SM100-NEXT: mov.b32 {%rs1, %rs2}, %r4;
+; CHECK-SM100-NEXT: mov.b32 {%rs3, %rs4}, %r3;
+; CHECK-SM100-NEXT: mov.b32 {%rs5, %rs6}, %r2;
+; CHECK-SM100-NEXT: mov.b32 {%rs7, %rs8}, %r1;
+; CHECK-SM100-NEXT: mul.rn.f16 %rs9, %rs7, %rs8;
+; CHECK-SM100-NEXT: mul.rn.f16 %rs10, %rs9, %rs5;
+; CHECK-SM100-NEXT: mul.rn.f16 %rs11, %rs10, %rs6;
+; CHECK-SM100-NEXT: mul.rn.f16 %rs12, %rs11, %rs3;
+; CHECK-SM100-NEXT: mul.rn.f16 %rs13, %rs12, %rs4;
+; CHECK-SM100-NEXT: mul.rn.f16 %rs14, %rs13, %rs1;
+; CHECK-SM100-NEXT: mul.rn.f16 %rs15, %rs14, %rs2;
+; CHECK-SM100-NEXT: st.param::func.b16 [func_retval0], %rs15;
+; CHECK-SM100-NEXT: ret;
%res = call half @llvm.vector.reduce.fmul(half 1.0, <8 x half> %in)
ret half %res
}
define half @reduce_fmul_half_reassoc(<8 x half> %in) {
-; CHECK-LABEL: reduce_fmul_half_reassoc(
-; CHECK: {
-; CHECK-NEXT: .reg .b16 %rs<4>;
-; CHECK-NEXT: .reg .b32 %r<8>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fmul_half_reassoc_param_0];
-; CHECK-NEXT: mul.rn.f16x2 %r5, %r2, %r4;
-; CHECK-NEXT: mul.rn.f16x2 %r6, %r1, %r3;
-; CHECK-NEXT: mul.rn.f16x2 %r7, %r6, %r5;
-; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r7;
-; CHECK-NEXT: mul.rn.f16 %rs3, %rs1, %rs2;
-; CHECK-NEXT: st.param.b16 [func_retval0], %rs3;
-; CHECK-NEXT: ret;
+; CHECK-SM80-LABEL: reduce_fmul_half_reassoc(
+; CHECK-SM80: {
+; CHECK-SM80-NEXT: .reg .b16 %rs<4>;
+; CHECK-SM80-NEXT: .reg .b32 %r<8>;
+; CHECK-SM80-EMPTY:
+; CHECK-SM80-NEXT: // %bb.0:
+; CHECK-SM80-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fmul_half_reassoc_param_0];
+; CHECK-SM80-NEXT: mul.rn.f16x2 %r5, %r2, %r4;
+; CHECK-SM80-NEXT: mul.rn.f16x2 %r6, %r1, %r3;
+; CHECK-SM80-NEXT: mul.rn.f16x2 %r7, %r6, %r5;
+; CHECK-SM80-NEXT: mov.b32 {%rs1, %rs2}, %r7;
+; CHECK-SM80-NEXT: mul.rn.f16 %rs3, %rs1, %rs2;
+; CHECK-SM80-NEXT: st.param.b16 [func_retval0], %rs3;
+; CHECK-SM80-NEXT: ret;
+;
+; CHECK-SM100-LABEL: reduce_fmul_half_reassoc(
+; CHECK-SM100: {
+; CHECK-SM100-NEXT: .reg .b16 %rs<4>;
+; CHECK-SM100-NEXT: .reg .b32 %r<8>;
+; CHECK-SM100-EMPTY:
+; CHECK-SM100-NEXT: // %bb.0:
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fmul_half_reassoc_param_0];
+; CHECK-SM100-NEXT: mul.rn.f16x2 %r5, %r2, %r4;
+; CHECK-SM100-NEXT: mul.rn.f16x2 %r6, %r1, %r3;
+; CHECK-SM100-NEXT: mul.rn.f16x2 %r7, %r6, %r5;
+; CHECK-SM100-NEXT: mov.b32 {%rs1, %rs2}, %r7;
+; CHECK-SM100-NEXT: mul.rn.f16 %rs3, %rs1, %rs2;
+; CHECK-SM100-NEXT: st.param::func.b16 [func_retval0], %rs3;
+; CHECK-SM100-NEXT: ret;
%res = call reassoc half @llvm.vector.reduce.fmul(half 1.0, <8 x half> %in)
ret half %res
}
define half @reduce_fmul_half_reassoc_nonpow2(<7 x half> %in) {
-; CHECK-LABEL: reduce_fmul_half_reassoc_nonpow2(
-; CHECK: {
-; CHECK-NEXT: .reg .b16 %rs<12>;
-; CHECK-NEXT: .reg .b32 %r<8>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [reduce_fmul_half_reassoc_nonpow2_param_0+8];
-; CHECK-NEXT: mov.b32 {%rs5, %rs6}, %r1;
-; CHECK-NEXT: ld.param.v2.b32 {%r2, %r3}, [reduce_fmul_half_reassoc_nonpow2_param_0];
-; CHECK-NEXT: mov.b32 {%rs3, %rs4}, %r3;
-; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r2;
-; CHECK-NEXT: ld.param.b16 %rs7, [reduce_fmul_half_reassoc_nonpow2_param_0+12];
-; CHECK-NEXT: mul.rn.f16x2 %r4, %r2, %r1;
-; CHECK-NEXT: mov.b16 %rs8, 0x3C00;
-; CHECK-NEXT: mov.b32 %r5, {%rs7, %rs8};
-; CHECK-NEXT: mul.rn.f16x2 %r6, %r3, %r5;
-; CHECK-NEXT: mul.rn.f16x2 %r7, %r4, %r6;
-; CHECK-NEXT: mov.b32 {%rs9, %rs10}, %r7;
-; CHECK-NEXT: mul.rn.f16 %rs11, %rs9, %rs10;
-; CHECK-NEXT: st.param.b16 [func_retval0], %rs11;
-; CHECK-NEXT: ret;
+; CHECK-SM80-LABEL: reduce_fmul_half_reassoc_nonpow2(
+; CHECK-SM80: {
+; CHECK-SM80-NEXT: .reg .b16 %rs<12>;
+; CHECK-SM80-NEXT: .reg .b32 %r<8>;
+; CHECK-SM80-EMPTY:
+; CHECK-SM80-NEXT: // %bb.0:
+; CHECK-SM80-NEXT: ld.param.b32 %r1, [reduce_fmul_half_reassoc_nonpow2_param_0+8];
+; CHECK-SM80-NEXT: mov.b32 {%rs5, %rs6}, %r1;
+; CHECK-SM80-NEXT: ld.param.v2.b32 {%r2, %r3}, [reduce_fmul_half_reassoc_nonpow2_param_0];
+; CHECK-SM80-NEXT: mov.b32 {%rs3, %rs4}, %r3;
+; CHECK-SM80-NEXT: mov.b32 {%rs1, %rs2}, %r2;
+; CHECK-SM80-NEXT: ld.param.b16 %rs7, [reduce_fmul_half_reassoc_nonpow2_param_0+12];
+; CHECK-SM80-NEXT: mul.rn.f16x2 %r4, %r2, %r1;
+; CHECK-SM80-NEXT: mov.b16 %rs8, 0x3C00;
+; CHECK-SM80-NEXT: mov.b32 %r5, {%rs7, %rs8};
+; CHECK-SM80-NEXT: mul.rn.f16x2 %r6, %r3, %r5;
+; CHECK-SM80-NEXT: mul.rn.f16x2 %r7, %r4, %r6;
+; CHECK-SM80-NEXT: mov.b32 {%rs9, %rs10}, %r7;
+; CHECK-SM80-NEXT: mul.rn.f16 %rs11, %rs9, %rs10;
+; CHECK-SM80-NEXT: st.param.b16 [func_retval0], %rs11;
+; CHECK-SM80-NEXT: ret;
+;
+; CHECK-SM100-LABEL: reduce_fmul_half_reassoc_nonpow2(
+; CHECK-SM100: {
+; CHECK-SM100-NEXT: .reg .b16 %rs<12>;
+; CHECK-SM100-NEXT: .reg .b32 %r<8>;
+; CHECK-SM100-EMPTY:
+; CHECK-SM100-NEXT: // %bb.0:
+; CHECK-SM100-NEXT: ld.param::func.b32 %r1, [reduce_fmul_half_reassoc_nonpow2_param_0+8];
+; CHECK-SM100-NEXT: mov.b32 {%rs5, %rs6}, %r1;
+; CHECK-SM100-NEXT: ld.param::func.v2.b32 {%r2, %r3}, [reduce_fmul_half_reassoc_nonpow2_param_0];
+; CHECK-SM100-NEXT: mov.b32 {%rs3, %rs4}, %r3;
+; CHECK-SM100-NEXT: mov.b32 {%rs1, %rs2}, %r2;
+; CHECK-SM100-NEXT: ld.param::func.b16 %rs7, [reduce_fmul_half_reassoc_nonpow2_param_0+12];
+; CHECK-SM100-NEXT: mul.rn.f16x2 %r4, %r2, %r1;
+; CHECK-SM100-NEXT: mov.b16 %rs8, 0x3C00;
+; CHECK-SM100-NEXT: mov.b32 %r5, {%rs7, %rs8};
+; CHECK-SM100-NEXT: mul.rn.f16x2 %r6, %r3, %r5;
+; CHECK-SM100-NEXT: mul.rn.f16x2 %r7, %r4, %r6;
+; CHECK-SM100-NEXT: mov.b32 {%rs9, %rs10}, %r7;
+; CHECK-SM100-NEXT: mul.rn.f16 %rs11, %rs9, %rs10;
+; CHECK-SM100-NEXT: st.param::func.b16 [func_retval0], %rs11;
+; CHECK-SM100-NEXT: ret;
%res = call reassoc half @llvm.vector.reduce.fmul(half 1.0, <7 x half> %in)
ret half %res
}
@@ -308,10 +425,10 @@ define float @reduce_fmul_float(<8 x float> %in) {
; CHECK-SM100-NEXT: .reg .b64 %rd<5>;
; CHECK-SM100-EMPTY:
; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param.v2.b64 {%rd3, %rd4}, [reduce_fmul_float_param_0+16];
+; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd3, %rd4}, [reduce_fmul_float_param_0+16];
; CHECK-SM100-NEXT: mov.b64 {%r1, %r2}, %rd4;
; CHECK-SM100-NEXT: mov.b64 {%r3, %r4}, %rd3;
-; CHECK-SM100-NEXT: ld.param.v2.b64 {%rd1, %rd2}, [reduce_fmul_float_param_0];
+; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd1, %rd2}, [reduce_fmul_float_param_0];
; CHECK-SM100-NEXT: mov.b64 {%r5, %r6}, %rd2;
; CHECK-SM100-NEXT: mov.b64 {%r7, %r8}, %rd1;
; CHECK-SM100-NEXT: mul.rn.f32 %r9, %r7, %r8;
@@ -321,7 +438,7 @@ define float @reduce_fmul_float(<8 x float> %in) {
; CHECK-SM100-NEXT: mul.rn.f32 %r13, %r12, %r4;
; CHECK-SM100-NEXT: mul.rn.f32 %r14, %r13, %r1;
; CHECK-SM100-NEXT: mul.rn.f32 %r15, %r14, %r2;
-; CHECK-SM100-NEXT: st.param.b32 [func_retval0], %r15;
+; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r15;
; CHECK-SM100-NEXT: ret;
%res = call float @llvm.vector.reduce.fmul(float 1.0, <8 x float> %in)
ret float %res
@@ -351,14 +468,14 @@ define float @reduce_fmul_float_reassoc(<8 x float> %in) {
; CHECK-SM100-NEXT: .reg .b64 %rd<8>;
; CHECK-SM100-EMPTY:
; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param.v2.b64 {%rd3, %rd4}, [reduce_fmul_float_reassoc_param_0+16];
-; CHECK-SM100-NEXT: ld.param.v2.b64 {%rd1, %rd2}, [reduce_fmul_float_reassoc_param_0];
+; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd3, %rd4}, [reduce_fmul_float_reassoc_param_0+16];
+; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd1, %rd2}, [reduce_fmul_float_reassoc_param_0];
; CHECK-SM100-NEXT: mul.rn.f32x2 %rd5, %rd2, %rd4;
; CHECK-SM100-NEXT: mul.rn.f32x2 %rd6, %rd1, %rd3;
; CHECK-SM100-NEXT: mul.rn.f32x2 %rd7, %rd6, %rd5;
; CHECK-SM100-NEXT: mov.b64 {%r1, %r2}, %rd7;
; CHECK-SM100-NEXT: mul.rn.f32 %r3, %r1, %r2;
-; CHECK-SM100-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r3;
; CHECK-SM100-NEXT: ret;
%res = call reassoc float @llvm.vector.reduce.fmul(float 1.0, <8 x float> %in)
ret float %res
@@ -388,12 +505,12 @@ define float @reduce_fmul_float_reassoc_nonpow2(<7 x float> %in) {
; CHECK-SM100-NEXT: .reg .b64 %rd<8>;
; CHECK-SM100-EMPTY:
; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param.b64 %rd1, [reduce_fmul_float_reassoc_nonpow2_param_0+16];
+; CHECK-SM100-NEXT: ld.param::func.b64 %rd1, [reduce_fmul_float_reassoc_nonpow2_param_0+16];
; CHECK-SM100-NEXT: mov.b64 {%r5, %r6}, %rd1;
-; CHECK-SM100-NEXT: ld.param.v2.b64 {%rd2, %rd3}, [reduce_fmul_float_reassoc_nonpow2_param_0];
+; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd2, %rd3}, [reduce_fmul_float_reassoc_nonpow2_param_0];
; CHECK-SM100-NEXT: mov.b64 {%r3, %r4}, %rd3;
; CHECK-SM100-NEXT: mov.b64 {%r1, %r2}, %rd2;
-; CHECK-SM100-NEXT: ld.param.b32 %r7, [reduce_fmul_float_reassoc_nonpow2_param_0+24];
+; CHECK-SM100-NEXT: ld.param::func.b32 %r7, [reduce_fmul_float_reassoc_nonpow2_param_0+24];
; CHECK-SM100-NEXT: mul.rn.f32x2 %rd4, %rd2, %rd1;
; CHECK-SM100-NEXT: mov.b32 %r8, 0f3F800000;
; CHECK-SM100-NEXT: mov.b64 %rd5, {%r7, %r8};
@@ -401,117 +518,206 @@ define float @reduce_fmul_float_reassoc_nonpow2(<7 x float> %in) {
; CHECK-SM100-NEXT: mul.rn.f32x2 %rd7, %rd4, %rd6;
; CHECK-SM100-NEXT: mov.b64 {%r9, %r10}, %rd7;
; CHECK-SM100-NEXT: mul.rn.f32 %r11, %r9, %r10;
-; CHECK-SM100-NEXT: st.param.b32 [func_retval0], %r11;
+; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r11;
; CHECK-SM100-NEXT: ret;
%res = call reassoc float @llvm.vector.reduce.fmul(float 1.0, <7 x float> %in)
ret float %res
}
define half @reduce_fmax_half(<8 x half> %in) {
-; CHECK-LABEL: reduce_fmax_half(
-; CHECK: {
-; CHECK-NEXT: .reg .b16 %rs<4>;
-; CHECK-NEXT: .reg .b32 %r<8>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fmax_half_param_0];
-; CHECK-NEXT: max.f16x2 %r5, %r2, %r4;
-; CHECK-NEXT: max.f16x2 %r6, %r1, %r3;
-; CHECK-NEXT: max.f16x2 %r7, %r6, %r5;
-; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r7;
-; CHECK-NEXT: max.f16 %rs3, %rs1, %rs2;
-; CHECK-NEXT: st.param.b16 [func_retval0], %rs3;
-; CHECK-NEXT: ret;
+; CHECK-SM80-LABEL: reduce_fmax_half(
+; CHECK-SM80: {
+; CHECK-SM80-NEXT: .reg .b16 %rs<4>;
+; CHECK-SM80-NEXT: .reg .b32 %r<8>;
+; CHECK-SM80-EMPTY:
+; CHECK-SM80-NEXT: // %bb.0:
+; CHECK-SM80-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fmax_half_param_0];
+; CHECK-SM80-NEXT: max.f16x2 %r5, %r2, %r4;
+; CHECK-SM80-NEXT: max.f16x2 %r6, %r1, %r3;
+; CHECK-SM80-NEXT: max.f16x2 %r7, %r6, %r5;
+; CHECK-SM80-NEXT: mov.b32 {%rs1, %rs2}, %r7;
+; CHECK-SM80-NEXT: max.f16 %rs3, %rs1, %rs2;
+; CHECK-SM80-NEXT: st.param.b16 [func_retval0], %rs3;
+; CHECK-SM80-NEXT: ret;
+;
+; CHECK-SM100-LABEL: reduce_fmax_half(
+; CHECK-SM100: {
+; CHECK-SM100-NEXT: .reg .b16 %rs<4>;
+; CHECK-SM100-NEXT: .reg .b32 %r<8>;
+; CHECK-SM100-EMPTY:
+; CHECK-SM100-NEXT: // %bb.0:
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fmax_half_param_0];
+; CHECK-SM100-NEXT: max.f16x2 %r5, %r2, %r4;
+; CHECK-SM100-NEXT: max.f16x2 %r6, %r1, %r3;
+; CHECK-SM100-NEXT: max.f16x2 %r7, %r6, %r5;
+; CHECK-SM100-NEXT: mov.b32 {%rs1, %rs2}, %r7;
+; CHECK-SM100-NEXT: max.f16 %rs3, %rs1, %rs2;
+; CHECK-SM100-NEXT: st.param::func.b16 [func_retval0], %rs3;
+; CHECK-SM100-NEXT: ret;
%res = call half @llvm.vector.reduce.fmax(<8 x half> %in)
ret half %res
}
define half @reduce_fmax_half_reassoc(<8 x half> %in) {
-; CHECK-LABEL: reduce_fmax_half_reassoc(
-; CHECK: {
-; CHECK-NEXT: .reg .b16 %rs<4>;
-; CHECK-NEXT: .reg .b32 %r<8>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fmax_half_reassoc_param_0];
-; CHECK-NEXT: max.f16x2 %r5, %r2, %r4;
-; CHECK-NEXT: max.f16x2 %r6, %r1, %r3;
-; CHECK-NEXT: max.f16x2 %r7, %r6, %r5;
-; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r7;
-; CHECK-NEXT: max.f16 %rs3, %rs1, %rs2;
-; CHECK-NEXT: st.param.b16 [func_retval0], %rs3;
-; CHECK-NEXT: ret;
+; CHECK-SM80-LABEL: reduce_fmax_half_reassoc(
+; CHECK-SM80: {
+; CHECK-SM80-NEXT: .reg .b16 %rs<4>;
+; CHECK-SM80-NEXT: .reg .b32 %r<8>;
+; CHECK-SM80-EMPTY:
+; CHECK-SM80-NEXT: // %bb.0:
+; CHECK-SM80-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fmax_half_reassoc_param_0];
+; CHECK-SM80-NEXT: max.f16x2 %r5, %r2, %r4;
+; CHECK-SM80-NEXT: max.f16x2 %r6, %r1, %r3;
+; CHECK-SM80-NEXT: max.f16x2 %r7, %r6, %r5;
+; CHECK-SM80-NEXT: mov.b32 {%rs1, %rs2}, %r7;
+; CHECK-SM80-NEXT: max.f16 %rs3, %rs1, %rs2;
+; CHECK-SM80-NEXT: st.param.b16 [func_retval0], %rs3;
+; CHECK-SM80-NEXT: ret;
+;
+; CHECK-SM100-LABEL: reduce_fmax_half_reassoc(
+; CHECK-SM100: {
+; CHECK-SM100-NEXT: .reg .b16 %rs<4>;
+; CHECK-SM100-NEXT: .reg .b32 %r<8>;
+; CHECK-SM100-EMPTY:
+; CHECK-SM100-NEXT: // %bb.0:
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fmax_half_reassoc_param_0];
+; CHECK-SM100-NEXT: max.f16x2 %r5, %r2, %r4;
+; CHECK-SM100-NEXT: max.f16x2 %r6, %r1, %r3;
+; CHECK-SM100-NEXT: max.f16x2 %r7, %r6, %r5;
+; CHECK-SM100-NEXT: mov.b32 {%rs1, %rs2}, %r7;
+; CHECK-SM100-NEXT: max.f16 %rs3, %rs1, %rs2;
+; CHECK-SM100-NEXT: st.param::func.b16 [func_retval0], %rs3;
+; CHECK-SM100-NEXT: ret;
%res = call reassoc half @llvm.vector.reduce.fmax(<8 x half> %in)
ret half %res
}
define half @reduce_fmax_half_reassoc_nonpow2(<7 x half> %in) {
-; CHECK-LABEL: reduce_fmax_half_reassoc_nonpow2(
-; CHECK: {
-; CHECK-NEXT: .reg .b16 %rs<12>;
-; CHECK-NEXT: .reg .b32 %r<8>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [reduce_fmax_half_reassoc_nonpow2_param_0+8];
-; CHECK-NEXT: mov.b32 {%rs5, %rs6}, %r1;
-; CHECK-NEXT: ld.param.v2.b32 {%r2, %r3}, [reduce_fmax_half_reassoc_nonpow2_param_0];
-; CHECK-NEXT: mov.b32 {%rs3, %rs4}, %r3;
-; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r2;
-; CHECK-NEXT: ld.param.b16 %rs7, [reduce_fmax_half_reassoc_nonpow2_param_0+12];
-; CHECK-NEXT: max.f16x2 %r4, %r2, %r1;
-; CHECK-NEXT: mov.b16 %rs8, 0xFE00;
-; CHECK-NEXT: mov.b32 %r5, {%rs7, %rs8};
-; CHECK-NEXT: max.f16x2 %r6, %r3, %r5;
-; CHECK-NEXT: max.f16x2 %r7, %r4, %r6;
-; CHECK-NEXT: mov.b32 {%rs9, %rs10}, %r7;
-; CHECK-NEXT: max.f16 %rs11, %rs9, %rs10;
-; CHECK-NEXT: st.param.b16 [func_retval0], %rs11;
-; CHECK-NEXT: ret;
+; CHECK-SM80-LABEL: reduce_fmax_half_reassoc_nonpow2(
+; CHECK-SM80: {
+; CHECK-SM80-NEXT: .reg .b16 %rs<12>;
+; CHECK-SM80-NEXT: .reg .b32 %r<8>;
+; CHECK-SM80-EMPTY:
+; CHECK-SM80-NEXT: // %bb.0:
+; CHECK-SM80-NEXT: ld.param.b32 %r1, [reduce_fmax_half_reassoc_nonpow2_param_0+8];
+; CHECK-SM80-NEXT: mov.b32 {%rs5, %rs6}, %r1;
+; CHECK-SM80-NEXT: ld.param.v2.b32 {%r2, %r3}, [reduce_fmax_half_reassoc_nonpow2_param_0];
+; CHECK-SM80-NEXT: mov.b32 {%rs3, %rs4}, %r3;
+; CHECK-SM80-NEXT: mov.b32 {%rs1, %rs2}, %r2;
+; CHECK-SM80-NEXT: ld.param.b16 %rs7, [reduce_fmax_half_reassoc_nonpow2_param_0+12];
+; CHECK-SM80-NEXT: max.f16x2 %r4, %r2, %r1;
+; CHECK-SM80-NEXT: mov.b16 %rs8, 0xFE00;
+; CHECK-SM80-NEXT: mov.b32 %r5, {%rs7, %rs8};
+; CHECK-SM80-NEXT: max.f16x2 %r6, %r3, %r5;
+; CHECK-SM80-NEXT: max.f16x2 %r7, %r4, %r6;
+; CHECK-SM80-NEXT: mov.b32 {%rs9, %rs10}, %r7;
+; CHECK-SM80-NEXT: max.f16 %rs11, %rs9, %rs10;
+; CHECK-SM80-NEXT: st.param.b16 [func_retval0], %rs11;
+; CHECK-SM80-NEXT: ret;
+;
+; CHECK-SM100-LABEL: reduce_fmax_half_reassoc_nonpow2(
+; CHECK-SM100: {
+; CHECK-SM100-NEXT: .reg .b16 %rs<12>;
+; CHECK-SM100-NEXT: .reg .b32 %r<8>;
+; CHECK-SM100-EMPTY:
+; CHECK-SM100-NEXT: // %bb.0:
+; CHECK-SM100-NEXT: ld.param::func.b32 %r1, [reduce_fmax_half_reassoc_nonpow2_param_0+8];
+; CHECK-SM100-NEXT: mov.b32 {%rs5, %rs6}, %r1;
+; CHECK-SM100-NEXT: ld.param::func.v2.b32 {%r2, %r3}, [reduce_fmax_half_reassoc_nonpow2_param_0];
+; CHECK-SM100-NEXT: mov.b32 {%rs3, %rs4}, %r3;
+; CHECK-SM100-NEXT: mov.b32 {%rs1, %rs2}, %r2;
+; CHECK-SM100-NEXT: ld.param::func.b16 %rs7, [reduce_fmax_half_reassoc_nonpow2_param_0+12];
+; CHECK-SM100-NEXT: max.f16x2 %r4, %r2, %r1;
+; CHECK-SM100-NEXT: mov.b16 %rs8, 0xFE00;
+; CHECK-SM100-NEXT: mov.b32 %r5, {%rs7, %rs8};
+; CHECK-SM100-NEXT: max.f16x2 %r6, %r3, %r5;
+; CHECK-SM100-NEXT: max.f16x2 %r7, %r4, %r6;
+; CHECK-SM100-NEXT: mov.b32 {%rs9, %rs10}, %r7;
+; CHECK-SM100-NEXT: max.f16 %rs11, %rs9, %rs10;
+; CHECK-SM100-NEXT: st.param::func.b16 [func_retval0], %rs11;
+; CHECK-SM100-NEXT: ret;
%res = call reassoc half @llvm.vector.reduce.fmax(<7 x half> %in)
ret half %res
}
define half @reduce_fmax_half_nnan(<8 x half> %in) {
-; CHECK-LABEL: reduce_fmax_half_nnan(
-; CHECK: {
-; CHECK-NEXT: .reg .b16 %rs<4>;
-; CHECK-NEXT: .reg .b32 %r<8>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fmax_half_nnan_param_0];
-; CHECK-NEXT: max.f16x2 %r5, %r2, %r4;
-; CHECK-NEXT: max.f16x2 %r6, %r1, %r3;
-; CHECK-NEXT: max.f16x2 %r7, %r6, %r5;
-; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r7;
-; CHECK-NEXT: max.f16 %rs3, %rs1, %rs2;
-; CHECK-NEXT: st.param.b16 [func_retval0], %rs3;
-; CHECK-NEXT: ret;
+; CHECK-SM80-LABEL: reduce_fmax_half_nnan(
+; CHECK-SM80: {
+; CHECK-SM80-NEXT: .reg .b16 %rs<4>;
+; CHECK-SM80-NEXT: .reg .b32 %r<8>;
+; CHECK-SM80-EMPTY:
+; CHECK-SM80-NEXT: // %bb.0:
+; CHECK-SM80-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fmax_half_nnan_param_0];
+; CHECK-SM80-NEXT: max.f16x2 %r5, %r2, %r4;
+; CHECK-SM80-NEXT: max.f16x2 %r6, %r1, %r3;
+; CHECK-SM80-NEXT: max.f16x2 %r7, %r6, %r5;
+; CHECK-SM80-NEXT: mov.b32 {%rs1, %rs2}, %r7;
+; CHECK-SM80-NEXT: max.f16 %rs3, %rs1, %rs2;
+; CHECK-SM80-NEXT: st.param.b16 [func_retval0], %rs3;
+; CHECK-SM80-NEXT: ret;
+;
+; CHECK-SM100-LABEL: reduce_fmax_half_nnan(
+; CHECK-SM100: {
+; CHECK-SM100-NEXT: .reg .b16 %rs<4>;
+; CHECK-SM100-NEXT: .reg .b32 %r<8>;
+; CHECK-SM100-EMPTY:
+; CHECK-SM100-NEXT: // %bb.0:
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fmax_half_nnan_param_0];
+; CHECK-SM100-NEXT: max.f16x2 %r5, %r2, %r4;
+; CHECK-SM100-NEXT: max.f16x2 %r6, %r1, %r3;
+; CHECK-SM100-NEXT: max.f16x2 %r7, %r6, %r5;
+; CHECK-SM100-NEXT: mov.b32 {%rs1, %rs2}, %r7;
+; CHECK-SM100-NEXT: max.f16 %rs3, %rs1, %rs2;
+; CHECK-SM100-NEXT: st.param::func.b16 [func_retval0], %rs3;
+; CHECK-SM100-NEXT: ret;
%res = call nnan half @llvm.vector.reduce.fmax(<8 x half> %in)
ret half %res
}
define half @reduce_fmax_half_nnan_nonpow2(<7 x half> %in) {
-; CHECK-LABEL: reduce_fmax_half_nnan_nonpow2(
-; CHECK: {
-; CHECK-NEXT: .reg .b16 %rs<12>;
-; CHECK-NEXT: .reg .b32 %r<8>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [reduce_fmax_half_nnan_nonpow2_param_0+8];
-; CHECK-NEXT: mov.b32 {%rs5, %rs6}, %r1;
-; CHECK-NEXT: ld.param.v2.b32 {%r2, %r3}, [reduce_fmax_half_nnan_nonpow2_param_0];
-; CHECK-NEXT: mov.b32 {%rs3, %rs4}, %r3;
-; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r2;
-; CHECK-NEXT: ld.param.b16 %rs7, [reduce_fmax_half_nnan_nonpow2_param_0+12];
-; CHECK-NEXT: max.f16x2 %r4, %r2, %r1;
-; CHECK-NEXT: mov.b16 %rs8, 0xFC00;
-; CHECK-NEXT: mov.b32 %r5, {%rs7, %rs8};
-; CHECK-NEXT: max.f16x2 %r6, %r3, %r5;
-; CHECK-NEXT: max.f16x2 %r7, %r4, %r6;
-; CHECK-NEXT: mov.b32 {%rs9, %rs10}, %r7;
-; CHECK-NEXT: max.f16 %rs11, %rs9, %rs10;
-; CHECK-NEXT: st.param.b16 [func_retval0], %rs11;
-; CHECK-NEXT: ret;
+; CHECK-SM80-LABEL: reduce_fmax_half_nnan_nonpow2(
+; CHECK-SM80: {
+; CHECK-SM80-NEXT: .reg .b16 %rs<12>;
+; CHECK-SM80-NEXT: .reg .b32 %r<8>;
+; CHECK-SM80-EMPTY:
+; CHECK-SM80-NEXT: // %bb.0:
+; CHECK-SM80-NEXT: ld.param.b32 %r1, [reduce_fmax_half_nnan_nonpow2_param_0+8];
+; CHECK-SM80-NEXT: mov.b32 {%rs5, %rs6}, %r1;
+; CHECK-SM80-NEXT: ld.param.v2.b32 {%r2, %r3}, [reduce_fmax_half_nnan_nonpow2_param_0];
+; CHECK-SM80-NEXT: mov.b32 {%rs3, %rs4}, %r3;
+; CHECK-SM80-NEXT: mov.b32 {%rs1, %rs2}, %r2;
+; CHECK-SM80-NEXT: ld.param.b16 %rs7, [reduce_fmax_half_nnan_nonpow2_param_0+12];
+; CHECK-SM80-NEXT: max.f16x2 %r4, %r2, %r1;
+; CHECK-SM80-NEXT: mov.b16 %rs8, 0xFC00;
+; CHECK-SM80-NEXT: mov.b32 %r5, {%rs7, %rs8};
+; CHECK-SM80-NEXT: max.f16x2 %r6, %r3, %r5;
+; CHECK-SM80-NEXT: max.f16x2 %r7, %r4, %r6;
+; CHECK-SM80-NEXT: mov.b32 {%rs9, %rs10}, %r7;
+; CHECK-SM80-NEXT: max.f16 %rs11, %rs9, %rs10;
+; CHECK-SM80-NEXT: st.param.b16 [func_retval0], %rs11;
+; CHECK-SM80-NEXT: ret;
+;
+; CHECK-SM100-LABEL: reduce_fmax_half_nnan_nonpow2(
+; CHECK-SM100: {
+; CHECK-SM100-NEXT: .reg .b16 %rs<12>;
+; CHECK-SM100-NEXT: .reg .b32 %r<8>;
+; CHECK-SM100-EMPTY:
+; CHECK-SM100-NEXT: // %bb.0:
+; CHECK-SM100-NEXT: ld.param::func.b32 %r1, [reduce_fmax_half_nnan_nonpow2_param_0+8];
+; CHECK-SM100-NEXT: mov.b32 {%rs5, %rs6}, %r1;
+; CHECK-SM100-NEXT: ld.param::func.v2.b32 {%r2, %r3}, [reduce_fmax_half_nnan_nonpow2_param_0];
+; CHECK-SM100-NEXT: mov.b32 {%rs3, %rs4}, %r3;
+; CHECK-SM100-NEXT: mov.b32 {%rs1, %rs2}, %r2;
+; CHECK-SM100-NEXT: ld.param::func.b16 %rs7, [reduce_fmax_half_nnan_nonpow2_param_0+12];
+; CHECK-SM100-NEXT: max.f16x2 %r4, %r2, %r1;
+; CHECK-SM100-NEXT: mov.b16 %rs8, 0xFC00;
+; CHECK-SM100-NEXT: mov.b32 %r5, {%rs7, %rs8};
+; CHECK-SM100-NEXT: max.f16x2 %r6, %r3, %r5;
+; CHECK-SM100-NEXT: max.f16x2 %r7, %r4, %r6;
+; CHECK-SM100-NEXT: mov.b32 {%rs9, %rs10}, %r7;
+; CHECK-SM100-NEXT: max.f16 %rs11, %rs9, %rs10;
+; CHECK-SM100-NEXT: st.param::func.b16 [func_retval0], %rs11;
+; CHECK-SM100-NEXT: ret;
%res = call nnan half @llvm.vector.reduce.fmax(<7 x half> %in)
ret half %res
}
@@ -540,9 +746,9 @@ define float @reduce_fmax_float(<8 x float> %in) {
; CHECK-SM100-NEXT: .reg .b64 %rd<5>;
; CHECK-SM100-EMPTY:
; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param.v2.b64 {%rd3, %rd4}, [reduce_fmax_float_param_0+16];
+; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd3, %rd4}, [reduce_fmax_float_param_0+16];
; CHECK-SM100-NEXT: mov.b64 {%r1, %r2}, %rd4;
-; CHECK-SM100-NEXT: ld.param.v2.b64 {%rd1, %rd2}, [reduce_fmax_float_param_0];
+; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd1, %rd2}, [reduce_fmax_float_param_0];
; CHECK-SM100-NEXT: mov.b64 {%r3, %r4}, %rd1;
; CHECK-SM100-NEXT: mov.b64 {%r5, %r6}, %rd3;
; CHECK-SM100-NEXT: mov.b64 {%r7, %r8}, %rd2;
@@ -550,7 +756,7 @@ define float @reduce_fmax_float(<8 x float> %in) {
; CHECK-SM100-NEXT: max.f32 %r10, %r3, %r4, %r7;
; CHECK-SM100-NEXT: max.f32 %r11, %r10, %r9, %r1;
; CHECK-SM100-NEXT: max.f32 %r12, %r11, %r2;
-; CHECK-SM100-NEXT: st.param.b32 [func_retval0], %r12;
+; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r12;
; CHECK-SM100-NEXT: ret;
%res = call float @llvm.vector.reduce.fmax(<8 x float> %in)
ret float %res
@@ -580,9 +786,9 @@ define float @reduce_fmax_float_reassoc(<8 x float> %in) {
; CHECK-SM100-NEXT: .reg .b64 %rd<5>;
; CHECK-SM100-EMPTY:
; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param.v2.b64 {%rd3, %rd4}, [reduce_fmax_float_reassoc_param_0+16];
+; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd3, %rd4}, [reduce_fmax_float_reassoc_param_0+16];
; CHECK-SM100-NEXT: mov.b64 {%r1, %r2}, %rd4;
-; CHECK-SM100-NEXT: ld.param.v2.b64 {%rd1, %rd2}, [reduce_fmax_float_reassoc_param_0];
+; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd1, %rd2}, [reduce_fmax_float_reassoc_param_0];
; CHECK-SM100-NEXT: mov.b64 {%r3, %r4}, %rd1;
; CHECK-SM100-NEXT: mov.b64 {%r5, %r6}, %rd3;
; CHECK-SM100-NEXT: mov.b64 {%r7, %r8}, %rd2;
@@ -590,7 +796,7 @@ define float @reduce_fmax_float_reassoc(<8 x float> %in) {
; CHECK-SM100-NEXT: max.f32 %r10, %r3, %r4, %r7;
; CHECK-SM100-NEXT: max.f32 %r11, %r10, %r9, %r1;
; CHECK-SM100-NEXT: max.f32 %r12, %r11, %r2;
-; CHECK-SM100-NEXT: st.param.b32 [func_retval0], %r12;
+; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r12;
; CHECK-SM100-NEXT: ret;
%res = call reassoc float @llvm.vector.reduce.fmax(<8 x float> %in)
ret float %res
@@ -619,13 +825,13 @@ define float @reduce_fmax_float_reassoc_nonpow2(<7 x float> %in) {
; CHECK-SM100-NEXT: .reg .b32 %r<11>;
; CHECK-SM100-EMPTY:
; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param.b32 %r7, [reduce_fmax_float_reassoc_nonpow2_param_0+24];
-; CHECK-SM100-NEXT: ld.param.v2.b32 {%r5, %r6}, [reduce_fmax_float_reassoc_nonpow2_param_0+16];
-; CHECK-SM100-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fmax_float_reassoc_nonpow2_param_0];
+; CHECK-SM100-NEXT: ld.param::func.b32 %r7, [reduce_fmax_float_reassoc_nonpow2_param_0+24];
+; CHECK-SM100-NEXT: ld.param::func.v2.b32 {%r5, %r6}, [reduce_fmax_float_reassoc_nonpow2_param_0+16];
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fmax_float_reassoc_nonpow2_param_0];
; CHECK-SM100-NEXT: max.f32 %r8, %r4, %r5, %r6;
; CHECK-SM100-NEXT: max.f32 %r9, %r1, %r2, %r3;
; CHECK-SM100-NEXT: max.f32 %r10, %r9, %r8, %r7;
-; CHECK-SM100-NEXT: st.param.b32 [func_retval0], %r10;
+; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r10;
; CHECK-SM100-NEXT: ret;
%res = call reassoc float @llvm.vector.reduce.fmax(<7 x float> %in)
ret float %res
@@ -655,9 +861,9 @@ define float @reduce_fmax_float_nnan(<8 x float> %in) {
; CHECK-SM100-NEXT: .reg .b64 %rd<5>;
; CHECK-SM100-EMPTY:
; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param.v2.b64 {%rd3, %rd4}, [reduce_fmax_float_nnan_param_0+16];
+; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd3, %rd4}, [reduce_fmax_float_nnan_param_0+16];
; CHECK-SM100-NEXT: mov.b64 {%r1, %r2}, %rd4;
-; CHECK-SM100-NEXT: ld.param.v2.b64 {%rd1, %rd2}, [reduce_fmax_float_nnan_param_0];
+; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd1, %rd2}, [reduce_fmax_float_nnan_param_0];
; CHECK-SM100-NEXT: mov.b64 {%r3, %r4}, %rd1;
; CHECK-SM100-NEXT: mov.b64 {%r5, %r6}, %rd3;
; CHECK-SM100-NEXT: mov.b64 {%r7, %r8}, %rd2;
@@ -665,7 +871,7 @@ define float @reduce_fmax_float_nnan(<8 x float> %in) {
; CHECK-SM100-NEXT: max.f32 %r10, %r3, %r4, %r7;
; CHECK-SM100-NEXT: max.f32 %r11, %r10, %r9, %r1;
; CHECK-SM100-NEXT: max.f32 %r12, %r11, %r2;
-; CHECK-SM100-NEXT: st.param.b32 [func_retval0], %r12;
+; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r12;
; CHECK-SM100-NEXT: ret;
%res = call nnan float @llvm.vector.reduce.fmax(<8 x float> %in)
ret float %res
@@ -694,123 +900,212 @@ define float @reduce_fmax_float_nnan_nonpow2(<7 x float> %in) {
; CHECK-SM100-NEXT: .reg .b32 %r<11>;
; CHECK-SM100-EMPTY:
; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param.b32 %r7, [reduce_fmax_float_nnan_nonpow2_param_0+24];
-; CHECK-SM100-NEXT: ld.param.v2.b32 {%r5, %r6}, [reduce_fmax_float_nnan_nonpow2_param_0+16];
-; CHECK-SM100-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fmax_float_nnan_nonpow2_param_0];
+; CHECK-SM100-NEXT: ld.param::func.b32 %r7, [reduce_fmax_float_nnan_nonpow2_param_0+24];
+; CHECK-SM100-NEXT: ld.param::func.v2.b32 {%r5, %r6}, [reduce_fmax_float_nnan_nonpow2_param_0+16];
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fmax_float_nnan_nonpow2_param_0];
; CHECK-SM100-NEXT: max.f32 %r8, %r4, %r5, %r6;
; CHECK-SM100-NEXT: max.f32 %r9, %r1, %r2, %r3;
; CHECK-SM100-NEXT: max.f32 %r10, %r9, %r8, %r7;
-; CHECK-SM100-NEXT: st.param.b32 [func_retval0], %r10;
+; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r10;
; CHECK-SM100-NEXT: ret;
%res = call nnan float @llvm.vector.reduce.fmax(<7 x float> %in)
ret float %res
}
define half @reduce_fmin_half(<8 x half> %in) {
-; CHECK-LABEL: reduce_fmin_half(
-; CHECK: {
-; CHECK-NEXT: .reg .b16 %rs<4>;
-; CHECK-NEXT: .reg .b32 %r<8>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fmin_half_param_0];
-; CHECK-NEXT: min.f16x2 %r5, %r2, %r4;
-; CHECK-NEXT: min.f16x2 %r6, %r1, %r3;
-; CHECK-NEXT: min.f16x2 %r7, %r6, %r5;
-; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r7;
-; CHECK-NEXT: min.f16 %rs3, %rs1, %rs2;
-; CHECK-NEXT: st.param.b16 [func_retval0], %rs3;
-; CHECK-NEXT: ret;
+; CHECK-SM80-LABEL: reduce_fmin_half(
+; CHECK-SM80: {
+; CHECK-SM80-NEXT: .reg .b16 %rs<4>;
+; CHECK-SM80-NEXT: .reg .b32 %r<8>;
+; CHECK-SM80-EMPTY:
+; CHECK-SM80-NEXT: // %bb.0:
+; CHECK-SM80-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fmin_half_param_0];
+; CHECK-SM80-NEXT: min.f16x2 %r5, %r2, %r4;
+; CHECK-SM80-NEXT: min.f16x2 %r6, %r1, %r3;
+; CHECK-SM80-NEXT: min.f16x2 %r7, %r6, %r5;
+; CHECK-SM80-NEXT: mov.b32 {%rs1, %rs2}, %r7;
+; CHECK-SM80-NEXT: min.f16 %rs3, %rs1, %rs2;
+; CHECK-SM80-NEXT: st.param.b16 [func_retval0], %rs3;
+; CHECK-SM80-NEXT: ret;
+;
+; CHECK-SM100-LABEL: reduce_fmin_half(
+; CHECK-SM100: {
+; CHECK-SM100-NEXT: .reg .b16 %rs<4>;
+; CHECK-SM100-NEXT: .reg .b32 %r<8>;
+; CHECK-SM100-EMPTY:
+; CHECK-SM100-NEXT: // %bb.0:
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fmin_half_param_0];
+; CHECK-SM100-NEXT: min.f16x2 %r5, %r2, %r4;
+; CHECK-SM100-NEXT: min.f16x2 %r6, %r1, %r3;
+; CHECK-SM100-NEXT: min.f16x2 %r7, %r6, %r5;
+; CHECK-SM100-NEXT: mov.b32 {%rs1, %rs2}, %r7;
+; CHECK-SM100-NEXT: min.f16 %rs3, %rs1, %rs2;
+; CHECK-SM100-NEXT: st.param::func.b16 [func_retval0], %rs3;
+; CHECK-SM100-NEXT: ret;
%res = call half @llvm.vector.reduce.fmin(<8 x half> %in)
ret half %res
}
define half @reduce_fmin_half_reassoc(<8 x half> %in) {
-; CHECK-LABEL: reduce_fmin_half_reassoc(
-; CHECK: {
-; CHECK-NEXT: .reg .b16 %rs<4>;
-; CHECK-NEXT: .reg .b32 %r<8>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fmin_half_reassoc_param_0];
-; CHECK-NEXT: min.f16x2 %r5, %r2, %r4;
-; CHECK-NEXT: min.f16x2 %r6, %r1, %r3;
-; CHECK-NEXT: min.f16x2 %r7, %r6, %r5;
-; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r7;
-; CHECK-NEXT: min.f16 %rs3, %rs1, %rs2;
-; CHECK-NEXT: st.param.b16 [func_retval0], %rs3;
-; CHECK-NEXT: ret;
+; CHECK-SM80-LABEL: reduce_fmin_half_reassoc(
+; CHECK-SM80: {
+; CHECK-SM80-NEXT: .reg .b16 %rs<4>;
+; CHECK-SM80-NEXT: .reg .b32 %r<8>;
+; CHECK-SM80-EMPTY:
+; CHECK-SM80-NEXT: // %bb.0:
+; CHECK-SM80-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fmin_half_reassoc_param_0];
+; CHECK-SM80-NEXT: min.f16x2 %r5, %r2, %r4;
+; CHECK-SM80-NEXT: min.f16x2 %r6, %r1, %r3;
+; CHECK-SM80-NEXT: min.f16x2 %r7, %r6, %r5;
+; CHECK-SM80-NEXT: mov.b32 {%rs1, %rs2}, %r7;
+; CHECK-SM80-NEXT: min.f16 %rs3, %rs1, %rs2;
+; CHECK-SM80-NEXT: st.param.b16 [func_retval0], %rs3;
+; CHECK-SM80-NEXT: ret;
+;
+; CHECK-SM100-LABEL: reduce_fmin_half_reassoc(
+; CHECK-SM100: {
+; CHECK-SM100-NEXT: .reg .b16 %rs<4>;
+; CHECK-SM100-NEXT: .reg .b32 %r<8>;
+; CHECK-SM100-EMPTY:
+; CHECK-SM100-NEXT: // %bb.0:
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fmin_half_reassoc_param_0];
+; CHECK-SM100-NEXT: min.f16x2 %r5, %r2, %r4;
+; CHECK-SM100-NEXT: min.f16x2 %r6, %r1, %r3;
+; CHECK-SM100-NEXT: min.f16x2 %r7, %r6, %r5;
+; CHECK-SM100-NEXT: mov.b32 {%rs1, %rs2}, %r7;
+; CHECK-SM100-NEXT: min.f16 %rs3, %rs1, %rs2;
+; CHECK-SM100-NEXT: st.param::func.b16 [func_retval0], %rs3;
+; CHECK-SM100-NEXT: ret;
%res = call reassoc half @llvm.vector.reduce.fmin(<8 x half> %in)
ret half %res
}
define half @reduce_fmin_half_reassoc_nonpow2(<7 x half> %in) {
-; CHECK-LABEL: reduce_fmin_half_reassoc_nonpow2(
-; CHECK: {
-; CHECK-NEXT: .reg .b16 %rs<12>;
-; CHECK-NEXT: .reg .b32 %r<8>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [reduce_fmin_half_reassoc_nonpow2_param_0+8];
-; CHECK-NEXT: mov.b32 {%rs5, %rs6}, %r1;
-; CHECK-NEXT: ld.param.v2.b32 {%r2, %r3}, [reduce_fmin_half_reassoc_nonpow2_param_0];
-; CHECK-NEXT: mov.b32 {%rs3, %rs4}, %r3;
-; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r2;
-; CHECK-NEXT: ld.param.b16 %rs7, [reduce_fmin_half_reassoc_nonpow2_param_0+12];
-; CHECK-NEXT: min.f16x2 %r4, %r2, %r1;
-; CHECK-NEXT: mov.b16 %rs8, 0x7E00;
-; CHECK-NEXT: mov.b32 %r5, {%rs7, %rs8};
-; CHECK-NEXT: min.f16x2 %r6, %r3, %r5;
-; CHECK-NEXT: min.f16x2 %r7, %r4, %r6;
-; CHECK-NEXT: mov.b32 {%rs9, %rs10}, %r7;
-; CHECK-NEXT: min.f16 %rs11, %rs9, %rs10;
-; CHECK-NEXT: st.param.b16 [func_retval0], %rs11;
-; CHECK-NEXT: ret;
+; CHECK-SM80-LABEL: reduce_fmin_half_reassoc_nonpow2(
+; CHECK-SM80: {
+; CHECK-SM80-NEXT: .reg .b16 %rs<12>;
+; CHECK-SM80-NEXT: .reg .b32 %r<8>;
+; CHECK-SM80-EMPTY:
+; CHECK-SM80-NEXT: // %bb.0:
+; CHECK-SM80-NEXT: ld.param.b32 %r1, [reduce_fmin_half_reassoc_nonpow2_param_0+8];
+; CHECK-SM80-NEXT: mov.b32 {%rs5, %rs6}, %r1;
+; CHECK-SM80-NEXT: ld.param.v2.b32 {%r2, %r3}, [reduce_fmin_half_reassoc_nonpow2_param_0];
+; CHECK-SM80-NEXT: mov.b32 {%rs3, %rs4}, %r3;
+; CHECK-SM80-NEXT: mov.b32 {%rs1, %rs2}, %r2;
+; CHECK-SM80-NEXT: ld.param.b16 %rs7, [reduce_fmin_half_reassoc_nonpow2_param_0+12];
+; CHECK-SM80-NEXT: min.f16x2 %r4, %r2, %r1;
+; CHECK-SM80-NEXT: mov.b16 %rs8, 0x7E00;
+; CHECK-SM80-NEXT: mov.b32 %r5, {%rs7, %rs8};
+; CHECK-SM80-NEXT: min.f16x2 %r6, %r3, %r5;
+; CHECK-SM80-NEXT: min.f16x2 %r7, %r4, %r6;
+; CHECK-SM80-NEXT: mov.b32 {%rs9, %rs10}, %r7;
+; CHECK-SM80-NEXT: min.f16 %rs11, %rs9, %rs10;
+; CHECK-SM80-NEXT: st.param.b16 [func_retval0], %rs11;
+; CHECK-SM80-NEXT: ret;
+;
+; CHECK-SM100-LABEL: reduce_fmin_half_reassoc_nonpow2(
+; CHECK-SM100: {
+; CHECK-SM100-NEXT: .reg .b16 %rs<12>;
+; CHECK-SM100-NEXT: .reg .b32 %r<8>;
+; CHECK-SM100-EMPTY:
+; CHECK-SM100-NEXT: // %bb.0:
+; CHECK-SM100-NEXT: ld.param::func.b32 %r1, [reduce_fmin_half_reassoc_nonpow2_param_0+8];
+; CHECK-SM100-NEXT: mov.b32 {%rs5, %rs6}, %r1;
+; CHECK-SM100-NEXT: ld.param::func.v2.b32 {%r2, %r3}, [reduce_fmin_half_reassoc_nonpow2_param_0];
+; CHECK-SM100-NEXT: mov.b32 {%rs3, %rs4}, %r3;
+; CHECK-SM100-NEXT: mov.b32 {%rs1, %rs2}, %r2;
+; CHECK-SM100-NEXT: ld.param::func.b16 %rs7, [reduce_fmin_half_reassoc_nonpow2_param_0+12];
+; CHECK-SM100-NEXT: min.f16x2 %r4, %r2, %r1;
+; CHECK-SM100-NEXT: mov.b16 %rs8, 0x7E00;
+; CHECK-SM100-NEXT: mov.b32 %r5, {%rs7, %rs8};
+; CHECK-SM100-NEXT: min.f16x2 %r6, %r3, %r5;
+; CHECK-SM100-NEXT: min.f16x2 %r7, %r4, %r6;
+; CHECK-SM100-NEXT: mov.b32 {%rs9, %rs10}, %r7;
+; CHECK-SM100-NEXT: min.f16 %rs11, %rs9, %rs10;
+; CHECK-SM100-NEXT: st.param::func.b16 [func_retval0], %rs11;
+; CHECK-SM100-NEXT: ret;
%res = call reassoc half @llvm.vector.reduce.fmin(<7 x half> %in)
ret half %res
}
define half @reduce_fmin_half_nnan(<8 x half> %in) {
-; CHECK-LABEL: reduce_fmin_half_nnan(
-; CHECK: {
-; CHECK-NEXT: .reg .b16 %rs<4>;
-; CHECK-NEXT: .reg .b32 %r<8>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fmin_half_nnan_param_0];
-; CHECK-NEXT: min.f16x2 %r5, %r2, %r4;
-; CHECK-NEXT: min.f16x2 %r6, %r1, %r3;
-; CHECK-NEXT: min.f16x2 %r7, %r6, %r5;
-; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r7;
-; CHECK-NEXT: min.f16 %rs3, %rs1, %rs2;
-; CHECK-NEXT: st.param.b16 [func_retval0], %rs3;
-; CHECK-NEXT: ret;
+; CHECK-SM80-LABEL: reduce_fmin_half_nnan(
+; CHECK-SM80: {
+; CHECK-SM80-NEXT: .reg .b16 %rs<4>;
+; CHECK-SM80-NEXT: .reg .b32 %r<8>;
+; CHECK-SM80-EMPTY:
+; CHECK-SM80-NEXT: // %bb.0:
+; CHECK-SM80-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fmin_half_nnan_param_0];
+; CHECK-SM80-NEXT: min.f16x2 %r5, %r2, %r4;
+; CHECK-SM80-NEXT: min.f16x2 %r6, %r1, %r3;
+; CHECK-SM80-NEXT: min.f16x2 %r7, %r6, %r5;
+; CHECK-SM80-NEXT: mov.b32 {%rs1, %rs2}, %r7;
+; CHECK-SM80-NEXT: min.f16 %rs3, %rs1, %rs2;
+; CHECK-SM80-NEXT: st.param.b16 [func_retval0], %rs3;
+; CHECK-SM80-NEXT: ret;
+;
+; CHECK-SM100-LABEL: reduce_fmin_half_nnan(
+; CHECK-SM100: {
+; CHECK-SM100-NEXT: .reg .b16 %rs<4>;
+; CHECK-SM100-NEXT: .reg .b32 %r<8>;
+; CHECK-SM100-EMPTY:
+; CHECK-SM100-NEXT: // %bb.0:
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fmin_half_nnan_param_0];
+; CHECK-SM100-NEXT: min.f16x2 %r5, %r2, %r4;
+; CHECK-SM100-NEXT: min.f16x2 %r6, %r1, %r3;
+; CHECK-SM100-NEXT: min.f16x2 %r7, %r6, %r5;
+; CHECK-SM100-NEXT: mov.b32 {%rs1, %rs2}, %r7;
+; CHECK-SM100-NEXT: min.f16 %rs3, %rs1, %rs2;
+; CHECK-SM100-NEXT: st.param::func.b16 [func_retval0], %rs3;
+; CHECK-SM100-NEXT: ret;
%res = call nnan half @llvm.vector.reduce.fmin(<8 x half> %in)
ret half %res
}
define half @reduce_fmin_half_nnan_nonpow2(<7 x half> %in) {
-; CHECK-LABEL: reduce_fmin_half_nnan_nonpow2(
-; CHECK: {
-; CHECK-NEXT: .reg .b16 %rs<12>;
-; CHECK-NEXT: .reg .b32 %r<8>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [reduce_fmin_half_nnan_nonpow2_param_0+8];
-; CHECK-NEXT: mov.b32 {%rs5, %rs6}, %r1;
-; CHECK-NEXT: ld.param.v2.b32 {%r2, %r3}, [reduce_fmin_half_nnan_nonpow2_param_0];
-; CHECK-NEXT: mov.b32 {%rs3, %rs4}, %r3;
-; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r2;
-; CHECK-NEXT: ld.param.b16 %rs7, [reduce_fmin_half_nnan_nonpow2_param_0+12];
-; CHECK-NEXT: min.f16x2 %r4, %r2, %r1;
-; CHECK-NEXT: mov.b16 %rs8, 0x7C00;
-; CHECK-NEXT: mov.b32 %r5, {%rs7, %rs8};
-; CHECK-NEXT: min.f16x2 %r6, %r3, %r5;
-; CHECK-NEXT: min.f16x2 %r7, %r4, %r6;
-; CHECK-NEXT: mov.b32 {%rs9, %rs10}, %r7;
-; CHECK-NEXT: min.f16 %rs11, %rs9, %rs10;
-; CHECK-NEXT: st.param.b16 [func_retval0], %rs11;
-; CHECK-NEXT: ret;
+; CHECK-SM80-LABEL: reduce_fmin_half_nnan_nonpow2(
+; CHECK-SM80: {
+; CHECK-SM80-NEXT: .reg .b16 %rs<12>;
+; CHECK-SM80-NEXT: .reg .b32 %r<8>;
+; CHECK-SM80-EMPTY:
+; CHECK-SM80-NEXT: // %bb.0:
+; CHECK-SM80-NEXT: ld.param.b32 %r1, [reduce_fmin_half_nnan_nonpow2_param_0+8];
+; CHECK-SM80-NEXT: mov.b32 {%rs5, %rs6}, %r1;
+; CHECK-SM80-NEXT: ld.param.v2.b32 {%r2, %r3}, [reduce_fmin_half_nnan_nonpow2_param_0];
+; CHECK-SM80-NEXT: mov.b32 {%rs3, %rs4}, %r3;
+; CHECK-SM80-NEXT: mov.b32 {%rs1, %rs2}, %r2;
+; CHECK-SM80-NEXT: ld.param.b16 %rs7, [reduce_fmin_half_nnan_nonpow2_param_0+12];
+; CHECK-SM80-NEXT: min.f16x2 %r4, %r2, %r1;
+; CHECK-SM80-NEXT: mov.b16 %rs8, 0x7C00;
+; CHECK-SM80-NEXT: mov.b32 %r5, {%rs7, %rs8};
+; CHECK-SM80-NEXT: min.f16x2 %r6, %r3, %r5;
+; CHECK-SM80-NEXT: min.f16x2 %r7, %r4, %r6;
+; CHECK-SM80-NEXT: mov.b32 {%rs9, %rs10}, %r7;
+; CHECK-SM80-NEXT: min.f16 %rs11, %rs9, %rs10;
+; CHECK-SM80-NEXT: st.param.b16 [func_retval0], %rs11;
+; CHECK-SM80-NEXT: ret;
+;
+; CHECK-SM100-LABEL: reduce_fmin_half_nnan_nonpow2(
+; CHECK-SM100: {
+; CHECK-SM100-NEXT: .reg .b16 %rs<12>;
+; CHECK-SM100-NEXT: .reg .b32 %r<8>;
+; CHECK-SM100-EMPTY:
+; CHECK-SM100-NEXT: // %bb.0:
+; CHECK-SM100-NEXT: ld.param::func.b32 %r1, [reduce_fmin_half_nnan_nonpow2_param_0+8];
+; CHECK-SM100-NEXT: mov.b32 {%rs5, %rs6}, %r1;
+; CHECK-SM100-NEXT: ld.param::func.v2.b32 {%r2, %r3}, [reduce_fmin_half_nnan_nonpow2_param_0];
+; CHECK-SM100-NEXT: mov.b32 {%rs3, %rs4}, %r3;
+; CHECK-SM100-NEXT: mov.b32 {%rs1, %rs2}, %r2;
+; CHECK-SM100-NEXT: ld.param::func.b16 %rs7, [reduce_fmin_half_nnan_nonpow2_param_0+12];
+; CHECK-SM100-NEXT: min.f16x2 %r4, %r2, %r1;
+; CHECK-SM100-NEXT: mov.b16 %rs8, 0x7C00;
+; CHECK-SM100-NEXT: mov.b32 %r5, {%rs7, %rs8};
+; CHECK-SM100-NEXT: min.f16x2 %r6, %r3, %r5;
+; CHECK-SM100-NEXT: min.f16x2 %r7, %r4, %r6;
+; CHECK-SM100-NEXT: mov.b32 {%rs9, %rs10}, %r7;
+; CHECK-SM100-NEXT: min.f16 %rs11, %rs9, %rs10;
+; CHECK-SM100-NEXT: st.param::func.b16 [func_retval0], %rs11;
+; CHECK-SM100-NEXT: ret;
%res = call nnan half @llvm.vector.reduce.fmin(<7 x half> %in)
ret half %res
}
@@ -839,9 +1134,9 @@ define float @reduce_fmin_float(<8 x float> %in) {
; CHECK-SM100-NEXT: .reg .b64 %rd<5>;
; CHECK-SM100-EMPTY:
; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param.v2.b64 {%rd3, %rd4}, [reduce_fmin_float_param_0+16];
+; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd3, %rd4}, [reduce_fmin_float_param_0+16];
; CHECK-SM100-NEXT: mov.b64 {%r1, %r2}, %rd4;
-; CHECK-SM100-NEXT: ld.param.v2.b64 {%rd1, %rd2}, [reduce_fmin_float_param_0];
+; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd1, %rd2}, [reduce_fmin_float_param_0];
; CHECK-SM100-NEXT: mov.b64 {%r3, %r4}, %rd1;
; CHECK-SM100-NEXT: mov.b64 {%r5, %r6}, %rd3;
; CHECK-SM100-NEXT: mov.b64 {%r7, %r8}, %rd2;
@@ -849,7 +1144,7 @@ define float @reduce_fmin_float(<8 x float> %in) {
; CHECK-SM100-NEXT: min.f32 %r10, %r3, %r4, %r7;
; CHECK-SM100-NEXT: min.f32 %r11, %r10, %r9, %r1;
; CHECK-SM100-NEXT: min.f32 %r12, %r11, %r2;
-; CHECK-SM100-NEXT: st.param.b32 [func_retval0], %r12;
+; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r12;
; CHECK-SM100-NEXT: ret;
%res = call float @llvm.vector.reduce.fmin(<8 x float> %in)
ret float %res
@@ -879,9 +1174,9 @@ define float @reduce_fmin_float_reassoc(<8 x float> %in) {
; CHECK-SM100-NEXT: .reg .b64 %rd<5>;
; CHECK-SM100-EMPTY:
; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param.v2.b64 {%rd3, %rd4}, [reduce_fmin_float_reassoc_param_0+16];
+; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd3, %rd4}, [reduce_fmin_float_reassoc_param_0+16];
; CHECK-SM100-NEXT: mov.b64 {%r1, %r2}, %rd4;
-; CHECK-SM100-NEXT: ld.param.v2.b64 {%rd1, %rd2}, [reduce_fmin_float_reassoc_param_0];
+; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd1, %rd2}, [reduce_fmin_float_reassoc_param_0];
; CHECK-SM100-NEXT: mov.b64 {%r3, %r4}, %rd1;
; CHECK-SM100-NEXT: mov.b64 {%r5, %r6}, %rd3;
; CHECK-SM100-NEXT: mov.b64 {%r7, %r8}, %rd2;
@@ -889,7 +1184,7 @@ define float @reduce_fmin_float_reassoc(<8 x float> %in) {
; CHECK-SM100-NEXT: min.f32 %r10, %r3, %r4, %r7;
; CHECK-SM100-NEXT: min.f32 %r11, %r10, %r9, %r1;
; CHECK-SM100-NEXT: min.f32 %r12, %r11, %r2;
-; CHECK-SM100-NEXT: st.param.b32 [func_retval0], %r12;
+; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r12;
; CHECK-SM100-NEXT: ret;
%res = call reassoc float @llvm.vector.reduce.fmin(<8 x float> %in)
ret float %res
@@ -918,13 +1213,13 @@ define float @reduce_fmin_float_reassoc_nonpow2(<7 x float> %in) {
; CHECK-SM100-NEXT: .reg .b32 %r<11>;
; CHECK-SM100-EMPTY:
; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param.b32 %r7, [reduce_fmin_float_reassoc_nonpow2_param_0+24];
-; CHECK-SM100-NEXT: ld.param.v2.b32 {%r5, %r6}, [reduce_fmin_float_reassoc_nonpow2_param_0+16];
-; CHECK-SM100-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fmin_float_reassoc_nonpow2_param_0];
+; CHECK-SM100-NEXT: ld.param::func.b32 %r7, [reduce_fmin_float_reassoc_nonpow2_param_0+24];
+; CHECK-SM100-NEXT: ld.param::func.v2.b32 {%r5, %r6}, [reduce_fmin_float_reassoc_nonpow2_param_0+16];
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fmin_float_reassoc_nonpow2_param_0];
; CHECK-SM100-NEXT: min.f32 %r8, %r4, %r5, %r6;
; CHECK-SM100-NEXT: min.f32 %r9, %r1, %r2, %r3;
; CHECK-SM100-NEXT: min.f32 %r10, %r9, %r8, %r7;
-; CHECK-SM100-NEXT: st.param.b32 [func_retval0], %r10;
+; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r10;
; CHECK-SM100-NEXT: ret;
%res = call reassoc float @llvm.vector.reduce.fmin(<7 x float> %in)
ret float %res
@@ -954,9 +1249,9 @@ define float @reduce_fmin_float_nnan(<8 x float> %in) {
; CHECK-SM100-NEXT: .reg .b64 %rd<5>;
; CHECK-SM100-EMPTY:
; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param.v2.b64 {%rd3, %rd4}, [reduce_fmin_float_nnan_param_0+16];
+; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd3, %rd4}, [reduce_fmin_float_nnan_param_0+16];
; CHECK-SM100-NEXT: mov.b64 {%r1, %r2}, %rd4;
-; CHECK-SM100-NEXT: ld.param.v2.b64 {%rd1, %rd2}, [reduce_fmin_float_nnan_param_0];
+; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd1, %rd2}, [reduce_fmin_float_nnan_param_0];
; CHECK-SM100-NEXT: mov.b64 {%r3, %r4}, %rd1;
; CHECK-SM100-NEXT: mov.b64 {%r5, %r6}, %rd3;
; CHECK-SM100-NEXT: mov.b64 {%r7, %r8}, %rd2;
@@ -964,7 +1259,7 @@ define float @reduce_fmin_float_nnan(<8 x float> %in) {
; CHECK-SM100-NEXT: min.f32 %r10, %r3, %r4, %r7;
; CHECK-SM100-NEXT: min.f32 %r11, %r10, %r9, %r1;
; CHECK-SM100-NEXT: min.f32 %r12, %r11, %r2;
-; CHECK-SM100-NEXT: st.param.b32 [func_retval0], %r12;
+; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r12;
; CHECK-SM100-NEXT: ret;
%res = call nnan float @llvm.vector.reduce.fmin(<8 x float> %in)
ret float %res
@@ -993,78 +1288,130 @@ define float @reduce_fmin_float_nnan_nonpow2(<7 x float> %in) {
; CHECK-SM100-NEXT: .reg .b32 %r<11>;
; CHECK-SM100-EMPTY:
; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param.b32 %r7, [reduce_fmin_float_nnan_nonpow2_param_0+24];
-; CHECK-SM100-NEXT: ld.param.v2.b32 {%r5, %r6}, [reduce_fmin_float_nnan_nonpow2_param_0+16];
-; CHECK-SM100-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fmin_float_nnan_nonpow2_param_0];
+; CHECK-SM100-NEXT: ld.param::func.b32 %r7, [reduce_fmin_float_nnan_nonpow2_param_0+24];
+; CHECK-SM100-NEXT: ld.param::func.v2.b32 {%r5, %r6}, [reduce_fmin_float_nnan_nonpow2_param_0+16];
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fmin_float_nnan_nonpow2_param_0];
; CHECK-SM100-NEXT: min.f32 %r8, %r4, %r5, %r6;
; CHECK-SM100-NEXT: min.f32 %r9, %r1, %r2, %r3;
; CHECK-SM100-NEXT: min.f32 %r10, %r9, %r8, %r7;
-; CHECK-SM100-NEXT: st.param.b32 [func_retval0], %r10;
+; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r10;
; CHECK-SM100-NEXT: ret;
%res = call nnan float @llvm.vector.reduce.fmin(<7 x float> %in)
ret float %res
}
define half @reduce_fmaximum_half(<8 x half> %in) {
-; CHECK-LABEL: reduce_fmaximum_half(
-; CHECK: {
-; CHECK-NEXT: .reg .b16 %rs<4>;
-; CHECK-NEXT: .reg .b32 %r<8>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fmaximum_half_param_0];
-; CHECK-NEXT: max.NaN.f16x2 %r5, %r2, %r4;
-; CHECK-NEXT: max.NaN.f16x2 %r6, %r1, %r3;
-; CHECK-NEXT: max.NaN.f16x2 %r7, %r6, %r5;
-; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r7;
-; CHECK-NEXT: max.NaN.f16 %rs3, %rs1, %rs2;
-; CHECK-NEXT: st.param.b16 [func_retval0], %rs3;
-; CHECK-NEXT: ret;
+; CHECK-SM80-LABEL: reduce_fmaximum_half(
+; CHECK-SM80: {
+; CHECK-SM80-NEXT: .reg .b16 %rs<4>;
+; CHECK-SM80-NEXT: .reg .b32 %r<8>;
+; CHECK-SM80-EMPTY:
+; CHECK-SM80-NEXT: // %bb.0:
+; CHECK-SM80-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fmaximum_half_param_0];
+; CHECK-SM80-NEXT: max.NaN.f16x2 %r5, %r2, %r4;
+; CHECK-SM80-NEXT: max.NaN.f16x2 %r6, %r1, %r3;
+; CHECK-SM80-NEXT: max.NaN.f16x2 %r7, %r6, %r5;
+; CHECK-SM80-NEXT: mov.b32 {%rs1, %rs2}, %r7;
+; CHECK-SM80-NEXT: max.NaN.f16 %rs3, %rs1, %rs2;
+; CHECK-SM80-NEXT: st.param.b16 [func_retval0], %rs3;
+; CHECK-SM80-NEXT: ret;
+;
+; CHECK-SM100-LABEL: reduce_fmaximum_half(
+; CHECK-SM100: {
+; CHECK-SM100-NEXT: .reg .b16 %rs<4>;
+; CHECK-SM100-NEXT: .reg .b32 %r<8>;
+; CHECK-SM100-EMPTY:
+; CHECK-SM100-NEXT: // %bb.0:
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fmaximum_half_param_0];
+; CHECK-SM100-NEXT: max.NaN.f16x2 %r5, %r2, %r4;
+; CHECK-SM100-NEXT: max.NaN.f16x2 %r6, %r1, %r3;
+; CHECK-SM100-NEXT: max.NaN.f16x2 %r7, %r6, %r5;
+; CHECK-SM100-NEXT: mov.b32 {%rs1, %rs2}, %r7;
+; CHECK-SM100-NEXT: max.NaN.f16 %rs3, %rs1, %rs2;
+; CHECK-SM100-NEXT: st.param::func.b16 [func_retval0], %rs3;
+; CHECK-SM100-NEXT: ret;
%res = call half @llvm.vector.reduce.fmaximum(<8 x half> %in)
ret half %res
}
define half @reduce_fmaximum_half_reassoc(<8 x half> %in) {
-; CHECK-LABEL: reduce_fmaximum_half_reassoc(
-; CHECK: {
-; CHECK-NEXT: .reg .b16 %rs<4>;
-; CHECK-NEXT: .reg .b32 %r<8>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fmaximum_half_reassoc_param_0];
-; CHECK-NEXT: max.NaN.f16x2 %r5, %r2, %r4;
-; CHECK-NEXT: max.NaN.f16x2 %r6, %r1, %r3;
-; CHECK-NEXT: max.NaN.f16x2 %r7, %r6, %r5;
-; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r7;
-; CHECK-NEXT: max.NaN.f16 %rs3, %rs1, %rs2;
-; CHECK-NEXT: st.param.b16 [func_retval0], %rs3;
-; CHECK-NEXT: ret;
+; CHECK-SM80-LABEL: reduce_fmaximum_half_reassoc(
+; CHECK-SM80: {
+; CHECK-SM80-NEXT: .reg .b16 %rs<4>;
+; CHECK-SM80-NEXT: .reg .b32 %r<8>;
+; CHECK-SM80-EMPTY:
+; CHECK-SM80-NEXT: // %bb.0:
+; CHECK-SM80-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fmaximum_half_reassoc_param_0];
+; CHECK-SM80-NEXT: max.NaN.f16x2 %r5, %r2, %r4;
+; CHECK-SM80-NEXT: max.NaN.f16x2 %r6, %r1, %r3;
+; CHECK-SM80-NEXT: max.NaN.f16x2 %r7, %r6, %r5;
+; CHECK-SM80-NEXT: mov.b32 {%rs1, %rs2}, %r7;
+; CHECK-SM80-NEXT: max.NaN.f16 %rs3, %rs1, %rs2;
+; CHECK-SM80-NEXT: st.param.b16 [func_retval0], %rs3;
+; CHECK-SM80-NEXT: ret;
+;
+; CHECK-SM100-LABEL: reduce_fmaximum_half_reassoc(
+; CHECK-SM100: {
+; CHECK-SM100-NEXT: .reg .b16 %rs<4>;
+; CHECK-SM100-NEXT: .reg .b32 %r<8>;
+; CHECK-SM100-EMPTY:
+; CHECK-SM100-NEXT: // %bb.0:
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fmaximum_half_reassoc_param_0];
+; CHECK-SM100-NEXT: max.NaN.f16x2 %r5, %r2, %r4;
+; CHECK-SM100-NEXT: max.NaN.f16x2 %r6, %r1, %r3;
+; CHECK-SM100-NEXT: max.NaN.f16x2 %r7, %r6, %r5;
+; CHECK-SM100-NEXT: mov.b32 {%rs1, %rs2}, %r7;
+; CHECK-SM100-NEXT: max.NaN.f16 %rs3, %rs1, %rs2;
+; CHECK-SM100-NEXT: st.param::func.b16 [func_retval0], %rs3;
+; CHECK-SM100-NEXT: ret;
%res = call reassoc half @llvm.vector.reduce.fmaximum(<8 x half> %in)
ret half %res
}
define half @reduce_fmaximum_half_reassoc_nonpow2(<7 x half> %in) {
-; CHECK-LABEL: reduce_fmaximum_half_reassoc_nonpow2(
-; CHECK: {
-; CHECK-NEXT: .reg .b16 %rs<12>;
-; CHECK-NEXT: .reg .b32 %r<8>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [reduce_fmaximum_half_reassoc_nonpow2_param_0+8];
-; CHECK-NEXT: mov.b32 {%rs5, %rs6}, %r1;
-; CHECK-NEXT: ld.param.v2.b32 {%r2, %r3}, [reduce_fmaximum_half_reassoc_nonpow2_param_0];
-; CHECK-NEXT: mov.b32 {%rs3, %rs4}, %r3;
-; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r2;
-; CHECK-NEXT: ld.param.b16 %rs7, [reduce_fmaximum_half_reassoc_nonpow2_param_0+12];
-; CHECK-NEXT: max.NaN.f16x2 %r4, %r2, %r1;
-; CHECK-NEXT: mov.b16 %rs8, 0xFC00;
-; CHECK-NEXT: mov.b32 %r5, {%rs7, %rs8};
-; CHECK-NEXT: max.NaN.f16x2 %r6, %r3, %r5;
-; CHECK-NEXT: max.NaN.f16x2 %r7, %r4, %r6;
-; CHECK-NEXT: mov.b32 {%rs9, %rs10}, %r7;
-; CHECK-NEXT: max.NaN.f16 %rs11, %rs9, %rs10;
-; CHECK-NEXT: st.param.b16 [func_retval0], %rs11;
-; CHECK-NEXT: ret;
+; CHECK-SM80-LABEL: reduce_fmaximum_half_reassoc_nonpow2(
+; CHECK-SM80: {
+; CHECK-SM80-NEXT: .reg .b16 %rs<12>;
+; CHECK-SM80-NEXT: .reg .b32 %r<8>;
+; CHECK-SM80-EMPTY:
+; CHECK-SM80-NEXT: // %bb.0:
+; CHECK-SM80-NEXT: ld.param.b32 %r1, [reduce_fmaximum_half_reassoc_nonpow2_param_0+8];
+; CHECK-SM80-NEXT: mov.b32 {%rs5, %rs6}, %r1;
+; CHECK-SM80-NEXT: ld.param.v2.b32 {%r2, %r3}, [reduce_fmaximum_half_reassoc_nonpow2_param_0];
+; CHECK-SM80-NEXT: mov.b32 {%rs3, %rs4}, %r3;
+; CHECK-SM80-NEXT: mov.b32 {%rs1, %rs2}, %r2;
+; CHECK-SM80-NEXT: ld.param.b16 %rs7, [reduce_fmaximum_half_reassoc_nonpow2_param_0+12];
+; CHECK-SM80-NEXT: max.NaN.f16x2 %r4, %r2, %r1;
+; CHECK-SM80-NEXT: mov.b16 %rs8, 0xFC00;
+; CHECK-SM80-NEXT: mov.b32 %r5, {%rs7, %rs8};
+; CHECK-SM80-NEXT: max.NaN.f16x2 %r6, %r3, %r5;
+; CHECK-SM80-NEXT: max.NaN.f16x2 %r7, %r4, %r6;
+; CHECK-SM80-NEXT: mov.b32 {%rs9, %rs10}, %r7;
+; CHECK-SM80-NEXT: max.NaN.f16 %rs11, %rs9, %rs10;
+; CHECK-SM80-NEXT: st.param.b16 [func_retval0], %rs11;
+; CHECK-SM80-NEXT: ret;
+;
+; CHECK-SM100-LABEL: reduce_fmaximum_half_reassoc_nonpow2(
+; CHECK-SM100: {
+; CHECK-SM100-NEXT: .reg .b16 %rs<12>;
+; CHECK-SM100-NEXT: .reg .b32 %r<8>;
+; CHECK-SM100-EMPTY:
+; CHECK-SM100-NEXT: // %bb.0:
+; CHECK-SM100-NEXT: ld.param::func.b32 %r1, [reduce_fmaximum_half_reassoc_nonpow2_param_0+8];
+; CHECK-SM100-NEXT: mov.b32 {%rs5, %rs6}, %r1;
+; CHECK-SM100-NEXT: ld.param::func.v2.b32 {%r2, %r3}, [reduce_fmaximum_half_reassoc_nonpow2_param_0];
+; CHECK-SM100-NEXT: mov.b32 {%rs3, %rs4}, %r3;
+; CHECK-SM100-NEXT: mov.b32 {%rs1, %rs2}, %r2;
+; CHECK-SM100-NEXT: ld.param::func.b16 %rs7, [reduce_fmaximum_half_reassoc_nonpow2_param_0+12];
+; CHECK-SM100-NEXT: max.NaN.f16x2 %r4, %r2, %r1;
+; CHECK-SM100-NEXT: mov.b16 %rs8, 0xFC00;
+; CHECK-SM100-NEXT: mov.b32 %r5, {%rs7, %rs8};
+; CHECK-SM100-NEXT: max.NaN.f16x2 %r6, %r3, %r5;
+; CHECK-SM100-NEXT: max.NaN.f16x2 %r7, %r4, %r6;
+; CHECK-SM100-NEXT: mov.b32 {%rs9, %rs10}, %r7;
+; CHECK-SM100-NEXT: max.NaN.f16 %rs11, %rs9, %rs10;
+; CHECK-SM100-NEXT: st.param::func.b16 [func_retval0], %rs11;
+; CHECK-SM100-NEXT: ret;
%res = call reassoc half @llvm.vector.reduce.fmaximum(<7 x half> %in)
ret half %res
}
@@ -1093,9 +1440,9 @@ define float @reduce_fmaximum_float(<8 x float> %in) {
; CHECK-SM100-NEXT: .reg .b64 %rd<5>;
; CHECK-SM100-EMPTY:
; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param.v2.b64 {%rd3, %rd4}, [reduce_fmaximum_float_param_0+16];
+; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd3, %rd4}, [reduce_fmaximum_float_param_0+16];
; CHECK-SM100-NEXT: mov.b64 {%r1, %r2}, %rd4;
-; CHECK-SM100-NEXT: ld.param.v2.b64 {%rd1, %rd2}, [reduce_fmaximum_float_param_0];
+; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd1, %rd2}, [reduce_fmaximum_float_param_0];
; CHECK-SM100-NEXT: mov.b64 {%r3, %r4}, %rd1;
; CHECK-SM100-NEXT: mov.b64 {%r5, %r6}, %rd3;
; CHECK-SM100-NEXT: mov.b64 {%r7, %r8}, %rd2;
@@ -1103,7 +1450,7 @@ define float @reduce_fmaximum_float(<8 x float> %in) {
; CHECK-SM100-NEXT: max.NaN.f32 %r10, %r3, %r4, %r7;
; CHECK-SM100-NEXT: max.NaN.f32 %r11, %r10, %r9, %r1;
; CHECK-SM100-NEXT: max.NaN.f32 %r12, %r11, %r2;
-; CHECK-SM100-NEXT: st.param.b32 [func_retval0], %r12;
+; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r12;
; CHECK-SM100-NEXT: ret;
%res = call float @llvm.vector.reduce.fmaximum(<8 x float> %in)
ret float %res
@@ -1133,9 +1480,9 @@ define float @reduce_fmaximum_float_reassoc(<8 x float> %in) {
; CHECK-SM100-NEXT: .reg .b64 %rd<5>;
; CHECK-SM100-EMPTY:
; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param.v2.b64 {%rd3, %rd4}, [reduce_fmaximum_float_reassoc_param_0+16];
+; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd3, %rd4}, [reduce_fmaximum_float_reassoc_param_0+16];
; CHECK-SM100-NEXT: mov.b64 {%r1, %r2}, %rd4;
-; CHECK-SM100-NEXT: ld.param.v2.b64 {%rd1, %rd2}, [reduce_fmaximum_float_reassoc_param_0];
+; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd1, %rd2}, [reduce_fmaximum_float_reassoc_param_0];
; CHECK-SM100-NEXT: mov.b64 {%r3, %r4}, %rd1;
; CHECK-SM100-NEXT: mov.b64 {%r5, %r6}, %rd3;
; CHECK-SM100-NEXT: mov.b64 {%r7, %r8}, %rd2;
@@ -1143,7 +1490,7 @@ define float @reduce_fmaximum_float_reassoc(<8 x float> %in) {
; CHECK-SM100-NEXT: max.NaN.f32 %r10, %r3, %r4, %r7;
; CHECK-SM100-NEXT: max.NaN.f32 %r11, %r10, %r9, %r1;
; CHECK-SM100-NEXT: max.NaN.f32 %r12, %r11, %r2;
-; CHECK-SM100-NEXT: st.param.b32 [func_retval0], %r12;
+; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r12;
; CHECK-SM100-NEXT: ret;
%res = call reassoc float @llvm.vector.reduce.fmaximum(<8 x float> %in)
ret float %res
@@ -1172,78 +1519,130 @@ define float @reduce_fmaximum_float_reassoc_nonpow2(<7 x float> %in) {
; CHECK-SM100-NEXT: .reg .b32 %r<11>;
; CHECK-SM100-EMPTY:
; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param.b32 %r7, [reduce_fmaximum_float_reassoc_nonpow2_param_0+24];
-; CHECK-SM100-NEXT: ld.param.v2.b32 {%r5, %r6}, [reduce_fmaximum_float_reassoc_nonpow2_param_0+16];
-; CHECK-SM100-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fmaximum_float_reassoc_nonpow2_param_0];
+; CHECK-SM100-NEXT: ld.param::func.b32 %r7, [reduce_fmaximum_float_reassoc_nonpow2_param_0+24];
+; CHECK-SM100-NEXT: ld.param::func.v2.b32 {%r5, %r6}, [reduce_fmaximum_float_reassoc_nonpow2_param_0+16];
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fmaximum_float_reassoc_nonpow2_param_0];
; CHECK-SM100-NEXT: max.NaN.f32 %r8, %r4, %r5, %r6;
; CHECK-SM100-NEXT: max.NaN.f32 %r9, %r1, %r2, %r3;
; CHECK-SM100-NEXT: max.NaN.f32 %r10, %r9, %r8, %r7;
-; CHECK-SM100-NEXT: st.param.b32 [func_retval0], %r10;
+; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r10;
; CHECK-SM100-NEXT: ret;
%res = call reassoc float @llvm.vector.reduce.fmaximum(<7 x float> %in)
ret float %res
}
define half @reduce_fminimum_half(<8 x half> %in) {
-; CHECK-LABEL: reduce_fminimum_half(
-; CHECK: {
-; CHECK-NEXT: .reg .b16 %rs<4>;
-; CHECK-NEXT: .reg .b32 %r<8>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fminimum_half_param_0];
-; CHECK-NEXT: min.NaN.f16x2 %r5, %r2, %r4;
-; CHECK-NEXT: min.NaN.f16x2 %r6, %r1, %r3;
-; CHECK-NEXT: min.NaN.f16x2 %r7, %r6, %r5;
-; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r7;
-; CHECK-NEXT: min.NaN.f16 %rs3, %rs1, %rs2;
-; CHECK-NEXT: st.param.b16 [func_retval0], %rs3;
-; CHECK-NEXT: ret;
+; CHECK-SM80-LABEL: reduce_fminimum_half(
+; CHECK-SM80: {
+; CHECK-SM80-NEXT: .reg .b16 %rs<4>;
+; CHECK-SM80-NEXT: .reg .b32 %r<8>;
+; CHECK-SM80-EMPTY:
+; CHECK-SM80-NEXT: // %bb.0:
+; CHECK-SM80-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fminimum_half_param_0];
+; CHECK-SM80-NEXT: min.NaN.f16x2 %r5, %r2, %r4;
+; CHECK-SM80-NEXT: min.NaN.f16x2 %r6, %r1, %r3;
+; CHECK-SM80-NEXT: min.NaN.f16x2 %r7, %r6, %r5;
+; CHECK-SM80-NEXT: mov.b32 {%rs1, %rs2}, %r7;
+; CHECK-SM80-NEXT: min.NaN.f16 %rs3, %rs1, %rs2;
+; CHECK-SM80-NEXT: st.param.b16 [func_retval0], %rs3;
+; CHECK-SM80-NEXT: ret;
+;
+; CHECK-SM100-LABEL: reduce_fminimum_half(
+; CHECK-SM100: {
+; CHECK-SM100-NEXT: .reg .b16 %rs<4>;
+; CHECK-SM100-NEXT: .reg .b32 %r<8>;
+; CHECK-SM100-EMPTY:
+; CHECK-SM100-NEXT: // %bb.0:
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fminimum_half_param_0];
+; CHECK-SM100-NEXT: min.NaN.f16x2 %r5, %r2, %r4;
+; CHECK-SM100-NEXT: min.NaN.f16x2 %r6, %r1, %r3;
+; CHECK-SM100-NEXT: min.NaN.f16x2 %r7, %r6, %r5;
+; CHECK-SM100-NEXT: mov.b32 {%rs1, %rs2}, %r7;
+; CHECK-SM100-NEXT: min.NaN.f16 %rs3, %rs1, %rs2;
+; CHECK-SM100-NEXT: st.param::func.b16 [func_retval0], %rs3;
+; CHECK-SM100-NEXT: ret;
%res = call half @llvm.vector.reduce.fminimum(<8 x half> %in)
ret half %res
}
define half @reduce_fminimum_half_reassoc(<8 x half> %in) {
-; CHECK-LABEL: reduce_fminimum_half_reassoc(
-; CHECK: {
-; CHECK-NEXT: .reg .b16 %rs<4>;
-; CHECK-NEXT: .reg .b32 %r<8>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fminimum_half_reassoc_param_0];
-; CHECK-NEXT: min.NaN.f16x2 %r5, %r2, %r4;
-; CHECK-NEXT: min.NaN.f16x2 %r6, %r1, %r3;
-; CHECK-NEXT: min.NaN.f16x2 %r7, %r6, %r5;
-; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r7;
-; CHECK-NEXT: min.NaN.f16 %rs3, %rs1, %rs2;
-; CHECK-NEXT: st.param.b16 [func_retval0], %rs3;
-; CHECK-NEXT: ret;
+; CHECK-SM80-LABEL: reduce_fminimum_half_reassoc(
+; CHECK-SM80: {
+; CHECK-SM80-NEXT: .reg .b16 %rs<4>;
+; CHECK-SM80-NEXT: .reg .b32 %r<8>;
+; CHECK-SM80-EMPTY:
+; CHECK-SM80-NEXT: // %bb.0:
+; CHECK-SM80-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fminimum_half_reassoc_param_0];
+; CHECK-SM80-NEXT: min.NaN.f16x2 %r5, %r2, %r4;
+; CHECK-SM80-NEXT: min.NaN.f16x2 %r6, %r1, %r3;
+; CHECK-SM80-NEXT: min.NaN.f16x2 %r7, %r6, %r5;
+; CHECK-SM80-NEXT: mov.b32 {%rs1, %rs2}, %r7;
+; CHECK-SM80-NEXT: min.NaN.f16 %rs3, %rs1, %rs2;
+; CHECK-SM80-NEXT: st.param.b16 [func_retval0], %rs3;
+; CHECK-SM80-NEXT: ret;
+;
+; CHECK-SM100-LABEL: reduce_fminimum_half_reassoc(
+; CHECK-SM100: {
+; CHECK-SM100-NEXT: .reg .b16 %rs<4>;
+; CHECK-SM100-NEXT: .reg .b32 %r<8>;
+; CHECK-SM100-EMPTY:
+; CHECK-SM100-NEXT: // %bb.0:
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fminimum_half_reassoc_param_0];
+; CHECK-SM100-NEXT: min.NaN.f16x2 %r5, %r2, %r4;
+; CHECK-SM100-NEXT: min.NaN.f16x2 %r6, %r1, %r3;
+; CHECK-SM100-NEXT: min.NaN.f16x2 %r7, %r6, %r5;
+; CHECK-SM100-NEXT: mov.b32 {%rs1, %rs2}, %r7;
+; CHECK-SM100-NEXT: min.NaN.f16 %rs3, %rs1, %rs2;
+; CHECK-SM100-NEXT: st.param::func.b16 [func_retval0], %rs3;
+; CHECK-SM100-NEXT: ret;
%res = call reassoc half @llvm.vector.reduce.fminimum(<8 x half> %in)
ret half %res
}
define half @reduce_fminimum_half_reassoc_nonpow2(<7 x half> %in) {
-; CHECK-LABEL: reduce_fminimum_half_reassoc_nonpow2(
-; CHECK: {
-; CHECK-NEXT: .reg .b16 %rs<12>;
-; CHECK-NEXT: .reg .b32 %r<8>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [reduce_fminimum_half_reassoc_nonpow2_param_0+8];
-; CHECK-NEXT: mov.b32 {%rs5, %rs6}, %r1;
-; CHECK-NEXT: ld.param.v2.b32 {%r2, %r3}, [reduce_fminimum_half_reassoc_nonpow2_param_0];
-; CHECK-NEXT: mov.b32 {%rs3, %rs4}, %r3;
-; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r2;
-; CHECK-NEXT: ld.param.b16 %rs7, [reduce_fminimum_half_reassoc_nonpow2_param_0+12];
-; CHECK-NEXT: min.NaN.f16x2 %r4, %r2, %r1;
-; CHECK-NEXT: mov.b16 %rs8, 0x7C00;
-; CHECK-NEXT: mov.b32 %r5, {%rs7, %rs8};
-; CHECK-NEXT: min.NaN.f16x2 %r6, %r3, %r5;
-; CHECK-NEXT: min.NaN.f16x2 %r7, %r4, %r6;
-; CHECK-NEXT: mov.b32 {%rs9, %rs10}, %r7;
-; CHECK-NEXT: min.NaN.f16 %rs11, %rs9, %rs10;
-; CHECK-NEXT: st.param.b16 [func_retval0], %rs11;
-; CHECK-NEXT: ret;
+; CHECK-SM80-LABEL: reduce_fminimum_half_reassoc_nonpow2(
+; CHECK-SM80: {
+; CHECK-SM80-NEXT: .reg .b16 %rs<12>;
+; CHECK-SM80-NEXT: .reg .b32 %r<8>;
+; CHECK-SM80-EMPTY:
+; CHECK-SM80-NEXT: // %bb.0:
+; CHECK-SM80-NEXT: ld.param.b32 %r1, [reduce_fminimum_half_reassoc_nonpow2_param_0+8];
+; CHECK-SM80-NEXT: mov.b32 {%rs5, %rs6}, %r1;
+; CHECK-SM80-NEXT: ld.param.v2.b32 {%r2, %r3}, [reduce_fminimum_half_reassoc_nonpow2_param_0];
+; CHECK-SM80-NEXT: mov.b32 {%rs3, %rs4}, %r3;
+; CHECK-SM80-NEXT: mov.b32 {%rs1, %rs2}, %r2;
+; CHECK-SM80-NEXT: ld.param.b16 %rs7, [reduce_fminimum_half_reassoc_nonpow2_param_0+12];
+; CHECK-SM80-NEXT: min.NaN.f16x2 %r4, %r2, %r1;
+; CHECK-SM80-NEXT: mov.b16 %rs8, 0x7C00;
+; CHECK-SM80-NEXT: mov.b32 %r5, {%rs7, %rs8};
+; CHECK-SM80-NEXT: min.NaN.f16x2 %r6, %r3, %r5;
+; CHECK-SM80-NEXT: min.NaN.f16x2 %r7, %r4, %r6;
+; CHECK-SM80-NEXT: mov.b32 {%rs9, %rs10}, %r7;
+; CHECK-SM80-NEXT: min.NaN.f16 %rs11, %rs9, %rs10;
+; CHECK-SM80-NEXT: st.param.b16 [func_retval0], %rs11;
+; CHECK-SM80-NEXT: ret;
+;
+; CHECK-SM100-LABEL: reduce_fminimum_half_reassoc_nonpow2(
+; CHECK-SM100: {
+; CHECK-SM100-NEXT: .reg .b16 %rs<12>;
+; CHECK-SM100-NEXT: .reg .b32 %r<8>;
+; CHECK-SM100-EMPTY:
+; CHECK-SM100-NEXT: // %bb.0:
+; CHECK-SM100-NEXT: ld.param::func.b32 %r1, [reduce_fminimum_half_reassoc_nonpow2_param_0+8];
+; CHECK-SM100-NEXT: mov.b32 {%rs5, %rs6}, %r1;
+; CHECK-SM100-NEXT: ld.param::func.v2.b32 {%r2, %r3}, [reduce_fminimum_half_reassoc_nonpow2_param_0];
+; CHECK-SM100-NEXT: mov.b32 {%rs3, %rs4}, %r3;
+; CHECK-SM100-NEXT: mov.b32 {%rs1, %rs2}, %r2;
+; CHECK-SM100-NEXT: ld.param::func.b16 %rs7, [reduce_fminimum_half_reassoc_nonpow2_param_0+12];
+; CHECK-SM100-NEXT: min.NaN.f16x2 %r4, %r2, %r1;
+; CHECK-SM100-NEXT: mov.b16 %rs8, 0x7C00;
+; CHECK-SM100-NEXT: mov.b32 %r5, {%rs7, %rs8};
+; CHECK-SM100-NEXT: min.NaN.f16x2 %r6, %r3, %r5;
+; CHECK-SM100-NEXT: min.NaN.f16x2 %r7, %r4, %r6;
+; CHECK-SM100-NEXT: mov.b32 {%rs9, %rs10}, %r7;
+; CHECK-SM100-NEXT: min.NaN.f16 %rs11, %rs9, %rs10;
+; CHECK-SM100-NEXT: st.param::func.b16 [func_retval0], %rs11;
+; CHECK-SM100-NEXT: ret;
%res = call reassoc half @llvm.vector.reduce.fminimum(<7 x half> %in)
ret half %res
}
@@ -1272,9 +1671,9 @@ define float @reduce_fminimum_float(<8 x float> %in) {
; CHECK-SM100-NEXT: .reg .b64 %rd<5>;
; CHECK-SM100-EMPTY:
; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param.v2.b64 {%rd3, %rd4}, [reduce_fminimum_float_param_0+16];
+; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd3, %rd4}, [reduce_fminimum_float_param_0+16];
; CHECK-SM100-NEXT: mov.b64 {%r1, %r2}, %rd4;
-; CHECK-SM100-NEXT: ld.param.v2.b64 {%rd1, %rd2}, [reduce_fminimum_float_param_0];
+; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd1, %rd2}, [reduce_fminimum_float_param_0];
; CHECK-SM100-NEXT: mov.b64 {%r3, %r4}, %rd1;
; CHECK-SM100-NEXT: mov.b64 {%r5, %r6}, %rd3;
; CHECK-SM100-NEXT: mov.b64 {%r7, %r8}, %rd2;
@@ -1282,7 +1681,7 @@ define float @reduce_fminimum_float(<8 x float> %in) {
; CHECK-SM100-NEXT: min.NaN.f32 %r10, %r3, %r4, %r7;
; CHECK-SM100-NEXT: min.NaN.f32 %r11, %r10, %r9, %r1;
; CHECK-SM100-NEXT: min.NaN.f32 %r12, %r11, %r2;
-; CHECK-SM100-NEXT: st.param.b32 [func_retval0], %r12;
+; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r12;
; CHECK-SM100-NEXT: ret;
%res = call float @llvm.vector.reduce.fminimum(<8 x float> %in)
ret float %res
@@ -1312,9 +1711,9 @@ define float @reduce_fminimum_float_reassoc(<8 x float> %in) {
; CHECK-SM100-NEXT: .reg .b64 %rd<5>;
; CHECK-SM100-EMPTY:
; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param.v2.b64 {%rd3, %rd4}, [reduce_fminimum_float_reassoc_param_0+16];
+; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd3, %rd4}, [reduce_fminimum_float_reassoc_param_0+16];
; CHECK-SM100-NEXT: mov.b64 {%r1, %r2}, %rd4;
-; CHECK-SM100-NEXT: ld.param.v2.b64 {%rd1, %rd2}, [reduce_fminimum_float_reassoc_param_0];
+; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd1, %rd2}, [reduce_fminimum_float_reassoc_param_0];
; CHECK-SM100-NEXT: mov.b64 {%r3, %r4}, %rd1;
; CHECK-SM100-NEXT: mov.b64 {%r5, %r6}, %rd3;
; CHECK-SM100-NEXT: mov.b64 {%r7, %r8}, %rd2;
@@ -1322,7 +1721,7 @@ define float @reduce_fminimum_float_reassoc(<8 x float> %in) {
; CHECK-SM100-NEXT: min.NaN.f32 %r10, %r3, %r4, %r7;
; CHECK-SM100-NEXT: min.NaN.f32 %r11, %r10, %r9, %r1;
; CHECK-SM100-NEXT: min.NaN.f32 %r12, %r11, %r2;
-; CHECK-SM100-NEXT: st.param.b32 [func_retval0], %r12;
+; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r12;
; CHECK-SM100-NEXT: ret;
%res = call reassoc float @llvm.vector.reduce.fminimum(<8 x float> %in)
ret float %res
@@ -1351,13 +1750,13 @@ define float @reduce_fminimum_float_reassoc_nonpow2(<7 x float> %in) {
; CHECK-SM100-NEXT: .reg .b32 %r<11>;
; CHECK-SM100-EMPTY:
; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param.b32 %r7, [reduce_fminimum_float_reassoc_nonpow2_param_0+24];
-; CHECK-SM100-NEXT: ld.param.v2.b32 {%r5, %r6}, [reduce_fminimum_float_reassoc_nonpow2_param_0+16];
-; CHECK-SM100-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fminimum_float_reassoc_nonpow2_param_0];
+; CHECK-SM100-NEXT: ld.param::func.b32 %r7, [reduce_fminimum_float_reassoc_nonpow2_param_0+24];
+; CHECK-SM100-NEXT: ld.param::func.v2.b32 {%r5, %r6}, [reduce_fminimum_float_reassoc_nonpow2_param_0+16];
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fminimum_float_reassoc_nonpow2_param_0];
; CHECK-SM100-NEXT: min.NaN.f32 %r8, %r4, %r5, %r6;
; CHECK-SM100-NEXT: min.NaN.f32 %r9, %r1, %r2, %r3;
; CHECK-SM100-NEXT: min.NaN.f32 %r10, %r9, %r8, %r7;
-; CHECK-SM100-NEXT: st.param.b32 [func_retval0], %r10;
+; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r10;
; CHECK-SM100-NEXT: ret;
%res = call reassoc float @llvm.vector.reduce.fminimum(<7 x float> %in)
ret float %res
@@ -1392,14 +1791,14 @@ define i16 @reduce_add_i16(<8 x i16> %in) {
; CHECK-SM100-NEXT: .reg .b32 %r<9>;
; CHECK-SM100-EMPTY:
; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_add_i16_param_0];
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_add_i16_param_0];
; CHECK-SM100-NEXT: add.s16x2 %r5, %r2, %r4;
; CHECK-SM100-NEXT: add.s16x2 %r6, %r1, %r3;
; CHECK-SM100-NEXT: add.s16x2 %r7, %r6, %r5;
; CHECK-SM100-NEXT: mov.b32 {%rs1, %rs2}, %r7;
; CHECK-SM100-NEXT: add.s16 %rs3, %rs1, %rs2;
; CHECK-SM100-NEXT: cvt.u32.u16 %r8, %rs3;
-; CHECK-SM100-NEXT: st.param.b32 [func_retval0], %r8;
+; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r8;
; CHECK-SM100-NEXT: ret;
%res = call i16 @llvm.vector.reduce.add(<8 x i16> %in)
ret i16 %res
@@ -1431,12 +1830,12 @@ define i16 @reduce_add_i16_nonpow2(<7 x i16> %in) {
; CHECK-SM100-NEXT: .reg .b32 %r<9>;
; CHECK-SM100-EMPTY:
; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param.b32 %r1, [reduce_add_i16_nonpow2_param_0+8];
+; CHECK-SM100-NEXT: ld.param::func.b32 %r1, [reduce_add_i16_nonpow2_param_0+8];
; CHECK-SM100-NEXT: mov.b32 {%rs5, %rs6}, %r1;
-; CHECK-SM100-NEXT: ld.param.v2.b32 {%r2, %r3}, [reduce_add_i16_nonpow2_param_0];
+; CHECK-SM100-NEXT: ld.param::func.v2.b32 {%r2, %r3}, [reduce_add_i16_nonpow2_param_0];
; CHECK-SM100-NEXT: mov.b32 {%rs3, %rs4}, %r3;
; CHECK-SM100-NEXT: mov.b32 {%rs1, %rs2}, %r2;
-; CHECK-SM100-NEXT: ld.param.b16 %rs7, [reduce_add_i16_nonpow2_param_0+12];
+; CHECK-SM100-NEXT: ld.param::func.b16 %rs7, [reduce_add_i16_nonpow2_param_0+12];
; CHECK-SM100-NEXT: add.s16x2 %r4, %r2, %r1;
; CHECK-SM100-NEXT: mov.b16 %rs8, 0;
; CHECK-SM100-NEXT: mov.b32 %r5, {%rs7, %rs8};
@@ -1445,7 +1844,7 @@ define i16 @reduce_add_i16_nonpow2(<7 x i16> %in) {
; CHECK-SM100-NEXT: mov.b32 {%rs9, %rs10}, %r7;
; CHECK-SM100-NEXT: add.s16 %rs11, %rs9, %rs10;
; CHECK-SM100-NEXT: cvt.u32.u16 %r8, %rs11;
-; CHECK-SM100-NEXT: st.param.b32 [func_retval0], %r8;
+; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r8;
; CHECK-SM100-NEXT: ret;
%res = call i16 @llvm.vector.reduce.add(<7 x i16> %in)
ret i16 %res
@@ -1475,8 +1874,8 @@ define i32 @reduce_add_i32(<8 x i32> %in) {
; CHECK-SM100-NEXT: .reg .b64 %rd<5>;
; CHECK-SM100-EMPTY:
; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param.v2.b64 {%rd3, %rd4}, [reduce_add_i32_param_0+16];
-; CHECK-SM100-NEXT: ld.param.v2.b64 {%rd1, %rd2}, [reduce_add_i32_param_0];
+; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd3, %rd4}, [reduce_add_i32_param_0+16];
+; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd1, %rd2}, [reduce_add_i32_param_0];
; CHECK-SM100-NEXT: mov.b64 {%r1, %r2}, %rd4;
; CHECK-SM100-NEXT: mov.b64 {%r3, %r4}, %rd2;
; CHECK-SM100-NEXT: add.s32 %r5, %r4, %r2;
@@ -1488,78 +1887,136 @@ define i32 @reduce_add_i32(<8 x i32> %in) {
; CHECK-SM100-NEXT: add.s32 %r13, %r8, %r6;
; CHECK-SM100-NEXT: add.s32 %r14, %r13, %r12;
; CHECK-SM100-NEXT: add.s32 %r15, %r14, %r11;
-; CHECK-SM100-NEXT: st.param.b32 [func_retval0], %r15;
+; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r15;
; CHECK-SM100-NEXT: ret;
%res = call i32 @llvm.vector.reduce.add(<8 x i32> %in)
ret i32 %res
}
define i32 @reduce_add_i32_nonpow2(<7 x i32> %in) {
-; CHECK-LABEL: reduce_add_i32_nonpow2(
-; CHECK: {
-; CHECK-NEXT: .reg .b32 %r<14>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r7, [reduce_add_i32_nonpow2_param_0+24];
-; CHECK-NEXT: ld.param.v2.b32 {%r5, %r6}, [reduce_add_i32_nonpow2_param_0+16];
-; CHECK-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_add_i32_nonpow2_param_0];
-; CHECK-NEXT: add.s32 %r8, %r3, %r7;
-; CHECK-NEXT: add.s32 %r9, %r1, %r5;
-; CHECK-NEXT: add.s32 %r10, %r9, %r8;
-; CHECK-NEXT: add.s32 %r11, %r2, %r6;
-; CHECK-NEXT: add.s32 %r12, %r11, %r4;
-; CHECK-NEXT: add.s32 %r13, %r10, %r12;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r13;
-; CHECK-NEXT: ret;
+; CHECK-SM80-LABEL: reduce_add_i32_nonpow2(
+; CHECK-SM80: {
+; CHECK-SM80-NEXT: .reg .b32 %r<14>;
+; CHECK-SM80-EMPTY:
+; CHECK-SM80-NEXT: // %bb.0:
+; CHECK-SM80-NEXT: ld.param.b32 %r7, [reduce_add_i32_nonpow2_param_0+24];
+; CHECK-SM80-NEXT: ld.param.v2.b32 {%r5, %r6}, [reduce_add_i32_nonpow2_param_0+16];
+; CHECK-SM80-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_add_i32_nonpow2_param_0];
+; CHECK-SM80-NEXT: add.s32 %r8, %r3, %r7;
+; CHECK-SM80-NEXT: add.s32 %r9, %r1, %r5;
+; CHECK-SM80-NEXT: add.s32 %r10, %r9, %r8;
+; CHECK-SM80-NEXT: add.s32 %r11, %r2, %r6;
+; CHECK-SM80-NEXT: add.s32 %r12, %r11, %r4;
+; CHECK-SM80-NEXT: add.s32 %r13, %r10, %r12;
+; CHECK-SM80-NEXT: st.param.b32 [func_retval0], %r13;
+; CHECK-SM80-NEXT: ret;
+;
+; CHECK-SM100-LABEL: reduce_add_i32_nonpow2(
+; CHECK-SM100: {
+; CHECK-SM100-NEXT: .reg .b32 %r<14>;
+; CHECK-SM100-EMPTY:
+; CHECK-SM100-NEXT: // %bb.0:
+; CHECK-SM100-NEXT: ld.param::func.b32 %r7, [reduce_add_i32_nonpow2_param_0+24];
+; CHECK-SM100-NEXT: ld.param::func.v2.b32 {%r5, %r6}, [reduce_add_i32_nonpow2_param_0+16];
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_add_i32_nonpow2_param_0];
+; CHECK-SM100-NEXT: add.s32 %r8, %r3, %r7;
+; CHECK-SM100-NEXT: add.s32 %r9, %r1, %r5;
+; CHECK-SM100-NEXT: add.s32 %r10, %r9, %r8;
+; CHECK-SM100-NEXT: add.s32 %r11, %r2, %r6;
+; CHECK-SM100-NEXT: add.s32 %r12, %r11, %r4;
+; CHECK-SM100-NEXT: add.s32 %r13, %r10, %r12;
+; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r13;
+; CHECK-SM100-NEXT: ret;
%res = call i32 @llvm.vector.reduce.add(<7 x i32> %in)
ret i32 %res
}
define i16 @reduce_mul_i16(<8 x i16> %in) {
-; CHECK-LABEL: reduce_mul_i16(
-; CHECK: {
-; CHECK-NEXT: .reg .b16 %rs<16>;
-; CHECK-NEXT: .reg .b32 %r<6>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_mul_i16_param_0];
-; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r4;
-; CHECK-NEXT: mov.b32 {%rs3, %rs4}, %r2;
-; CHECK-NEXT: mul.lo.s16 %rs5, %rs4, %rs2;
-; CHECK-NEXT: mov.b32 {%rs6, %rs7}, %r3;
-; CHECK-NEXT: mov.b32 {%rs8, %rs9}, %r1;
-; CHECK-NEXT: mul.lo.s16 %rs10, %rs9, %rs7;
-; CHECK-NEXT: mul.lo.s16 %rs11, %rs10, %rs5;
-; CHECK-NEXT: mul.lo.s16 %rs12, %rs3, %rs1;
-; CHECK-NEXT: mul.lo.s16 %rs13, %rs8, %rs6;
-; CHECK-NEXT: mul.lo.s16 %rs14, %rs13, %rs12;
-; CHECK-NEXT: mul.lo.s16 %rs15, %rs14, %rs11;
-; CHECK-NEXT: cvt.u32.u16 %r5, %rs15;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r5;
-; CHECK-NEXT: ret;
+; CHECK-SM80-LABEL: reduce_mul_i16(
+; CHECK-SM80: {
+; CHECK-SM80-NEXT: .reg .b16 %rs<16>;
+; CHECK-SM80-NEXT: .reg .b32 %r<6>;
+; CHECK-SM80-EMPTY:
+; CHECK-SM80-NEXT: // %bb.0:
+; CHECK-SM80-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_mul_i16_param_0];
+; CHECK-SM80-NEXT: mov.b32 {%rs1, %rs2}, %r4;
+; CHECK-SM80-NEXT: mov.b32 {%rs3, %rs4}, %r2;
+; CHECK-SM80-NEXT: mul.lo.s16 %rs5, %rs4, %rs2;
+; CHECK-SM80-NEXT: mov.b32 {%rs6, %rs7}, %r3;
+; CHECK-SM80-NEXT: mov.b32 {%rs8, %rs9}, %r1;
+; CHECK-SM80-NEXT: mul.lo.s16 %rs10, %rs9, %rs7;
+; CHECK-SM80-NEXT: mul.lo.s16 %rs11, %rs10, %rs5;
+; CHECK-SM80-NEXT: mul.lo.s16 %rs12, %rs3, %rs1;
+; CHECK-SM80-NEXT: mul.lo.s16 %rs13, %rs8, %rs6;
+; CHECK-SM80-NEXT: mul.lo.s16 %rs14, %rs13, %rs12;
+; CHECK-SM80-NEXT: mul.lo.s16 %rs15, %rs14, %rs11;
+; CHECK-SM80-NEXT: cvt.u32.u16 %r5, %rs15;
+; CHECK-SM80-NEXT: st.param.b32 [func_retval0], %r5;
+; CHECK-SM80-NEXT: ret;
+;
+; CHECK-SM100-LABEL: reduce_mul_i16(
+; CHECK-SM100: {
+; CHECK-SM100-NEXT: .reg .b16 %rs<16>;
+; CHECK-SM100-NEXT: .reg .b32 %r<6>;
+; CHECK-SM100-EMPTY:
+; CHECK-SM100-NEXT: // %bb.0:
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_mul_i16_param_0];
+; CHECK-SM100-NEXT: mov.b32 {%rs1, %rs2}, %r4;
+; CHECK-SM100-NEXT: mov.b32 {%rs3, %rs4}, %r2;
+; CHECK-SM100-NEXT: mul.lo.s16 %rs5, %rs4, %rs2;
+; CHECK-SM100-NEXT: mov.b32 {%rs6, %rs7}, %r3;
+; CHECK-SM100-NEXT: mov.b32 {%rs8, %rs9}, %r1;
+; CHECK-SM100-NEXT: mul.lo.s16 %rs10, %rs9, %rs7;
+; CHECK-SM100-NEXT: mul.lo.s16 %rs11, %rs10, %rs5;
+; CHECK-SM100-NEXT: mul.lo.s16 %rs12, %rs3, %rs1;
+; CHECK-SM100-NEXT: mul.lo.s16 %rs13, %rs8, %rs6;
+; CHECK-SM100-NEXT: mul.lo.s16 %rs14, %rs13, %rs12;
+; CHECK-SM100-NEXT: mul.lo.s16 %rs15, %rs14, %rs11;
+; CHECK-SM100-NEXT: cvt.u32.u16 %r5, %rs15;
+; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r5;
+; CHECK-SM100-NEXT: ret;
%res = call i16 @llvm.vector.reduce.mul(<8 x i16> %in)
ret i16 %res
}
define i16 @reduce_mul_i16_nonpow2(<7 x i16> %in) {
-; CHECK-LABEL: reduce_mul_i16_nonpow2(
-; CHECK: {
-; CHECK-NEXT: .reg .b16 %rs<14>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b16 %rs7, [reduce_mul_i16_nonpow2_param_0+12];
-; CHECK-NEXT: ld.param.v2.b16 {%rs5, %rs6}, [reduce_mul_i16_nonpow2_param_0+8];
-; CHECK-NEXT: ld.param.v4.b16 {%rs1, %rs2, %rs3, %rs4}, [reduce_mul_i16_nonpow2_param_0];
-; CHECK-NEXT: mul.lo.s16 %rs8, %rs3, %rs7;
-; CHECK-NEXT: mul.lo.s16 %rs9, %rs1, %rs5;
-; CHECK-NEXT: mul.lo.s16 %rs10, %rs9, %rs8;
-; CHECK-NEXT: mul.lo.s16 %rs11, %rs2, %rs6;
-; CHECK-NEXT: mul.lo.s16 %rs12, %rs4, %rs11;
-; CHECK-NEXT: mul.lo.s16 %rs13, %rs10, %rs12;
-; CHECK-NEXT: cvt.u32.u16 %r1, %rs13;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
+; CHECK-SM80-LABEL: reduce_mul_i16_nonpow2(
+; CHECK-SM80: {
+; CHECK-SM80-NEXT: .reg .b16 %rs<14>;
+; CHECK-SM80-NEXT: .reg .b32 %r<2>;
+; CHECK-SM80-EMPTY:
+; CHECK-SM80-NEXT: // %bb.0:
+; CHECK-SM80-NEXT: ld.param.b16 %rs7, [reduce_mul_i16_nonpow2_param_0+12];
+; CHECK-SM80-NEXT: ld.param.v2.b16 {%rs5, %rs6}, [reduce_mul_i16_nonpow2_param_0+8];
+; CHECK-SM80-NEXT: ld.param.v4.b16 {%rs1, %rs2, %rs3, %rs4}, [reduce_mul_i16_nonpow2_param_0];
+; CHECK-SM80-NEXT: mul.lo.s16 %rs8, %rs3, %rs7;
+; CHECK-SM80-NEXT: mul.lo.s16 %rs9, %rs1, %rs5;
+; CHECK-SM80-NEXT: mul.lo.s16 %rs10, %rs9, %rs8;
+; CHECK-SM80-NEXT: mul.lo.s16 %rs11, %rs2, %rs6;
+; CHECK-SM80-NEXT: mul.lo.s16 %rs12, %rs4, %rs11;
+; CHECK-SM80-NEXT: mul.lo.s16 %rs13, %rs10, %rs12;
+; CHECK-SM80-NEXT: cvt.u32.u16 %r1, %rs13;
+; CHECK-SM80-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-SM80-NEXT: ret;
+;
+; CHECK-SM100-LABEL: reduce_mul_i16_nonpow2(
+; CHECK-SM100: {
+; CHECK-SM100-NEXT: .reg .b16 %rs<14>;
+; CHECK-SM100-NEXT: .reg .b32 %r<2>;
+; CHECK-SM100-EMPTY:
+; CHECK-SM100-NEXT: // %bb.0:
+; CHECK-SM100-NEXT: ld.param::func.b16 %rs7, [reduce_mul_i16_nonpow2_param_0+12];
+; CHECK-SM100-NEXT: ld.param::func.v2.b16 {%rs5, %rs6}, [reduce_mul_i16_nonpow2_param_0+8];
+; CHECK-SM100-NEXT: ld.param::func.v4.b16 {%rs1, %rs2, %rs3, %rs4}, [reduce_mul_i16_nonpow2_param_0];
+; CHECK-SM100-NEXT: mul.lo.s16 %rs8, %rs3, %rs7;
+; CHECK-SM100-NEXT: mul.lo.s16 %rs9, %rs1, %rs5;
+; CHECK-SM100-NEXT: mul.lo.s16 %rs10, %rs9, %rs8;
+; CHECK-SM100-NEXT: mul.lo.s16 %rs11, %rs2, %rs6;
+; CHECK-SM100-NEXT: mul.lo.s16 %rs12, %rs4, %rs11;
+; CHECK-SM100-NEXT: mul.lo.s16 %rs13, %rs10, %rs12;
+; CHECK-SM100-NEXT: cvt.u32.u16 %r1, %rs13;
+; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r1;
+; CHECK-SM100-NEXT: ret;
%res = call i16 @llvm.vector.reduce.mul(<7 x i16> %in)
ret i16 %res
}
@@ -1588,8 +2045,8 @@ define i32 @reduce_mul_i32(<8 x i32> %in) {
; CHECK-SM100-NEXT: .reg .b64 %rd<5>;
; CHECK-SM100-EMPTY:
; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param.v2.b64 {%rd3, %rd4}, [reduce_mul_i32_param_0+16];
-; CHECK-SM100-NEXT: ld.param.v2.b64 {%rd1, %rd2}, [reduce_mul_i32_param_0];
+; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd3, %rd4}, [reduce_mul_i32_param_0+16];
+; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd1, %rd2}, [reduce_mul_i32_param_0];
; CHECK-SM100-NEXT: mov.b64 {%r1, %r2}, %rd4;
; CHECK-SM100-NEXT: mov.b64 {%r3, %r4}, %rd2;
; CHECK-SM100-NEXT: mul.lo.s32 %r5, %r4, %r2;
@@ -1601,29 +2058,46 @@ define i32 @reduce_mul_i32(<8 x i32> %in) {
; CHECK-SM100-NEXT: mul.lo.s32 %r13, %r8, %r6;
; CHECK-SM100-NEXT: mul.lo.s32 %r14, %r13, %r12;
; CHECK-SM100-NEXT: mul.lo.s32 %r15, %r14, %r11;
-; CHECK-SM100-NEXT: st.param.b32 [func_retval0], %r15;
+; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r15;
; CHECK-SM100-NEXT: ret;
%res = call i32 @llvm.vector.reduce.mul(<8 x i32> %in)
ret i32 %res
}
define i32 @reduce_mul_i32_nonpow2(<7 x i32> %in) {
-; CHECK-LABEL: reduce_mul_i32_nonpow2(
-; CHECK: {
-; CHECK-NEXT: .reg .b32 %r<14>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r7, [reduce_mul_i32_nonpow2_param_0+24];
-; CHECK-NEXT: ld.param.v2.b32 {%r5, %r6}, [reduce_mul_i32_nonpow2_param_0+16];
-; CHECK-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_mul_i32_nonpow2_param_0];
-; CHECK-NEXT: mul.lo.s32 %r8, %r3, %r7;
-; CHECK-NEXT: mul.lo.s32 %r9, %r1, %r5;
-; CHECK-NEXT: mul.lo.s32 %r10, %r9, %r8;
-; CHECK-NEXT: mul.lo.s32 %r11, %r2, %r6;
-; CHECK-NEXT: mul.lo.s32 %r12, %r4, %r11;
-; CHECK-NEXT: mul.lo.s32 %r13, %r10, %r12;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r13;
-; CHECK-NEXT: ret;
+; CHECK-SM80-LABEL: reduce_mul_i32_nonpow2(
+; CHECK-SM80: {
+; CHECK-SM80-NEXT: .reg .b32 %r<14>;
+; CHECK-SM80-EMPTY:
+; CHECK-SM80-NEXT: // %bb.0:
+; CHECK-SM80-NEXT: ld.param.b32 %r7, [reduce_mul_i32_nonpow2_param_0+24];
+; CHECK-SM80-NEXT: ld.param.v2.b32 {%r5, %r6}, [reduce_mul_i32_nonpow2_param_0+16];
+; CHECK-SM80-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_mul_i32_nonpow2_param_0];
+; CHECK-SM80-NEXT: mul.lo.s32 %r8, %r3, %r7;
+; CHECK-SM80-NEXT: mul.lo.s32 %r9, %r1, %r5;
+; CHECK-SM80-NEXT: mul.lo.s32 %r10, %r9, %r8;
+; CHECK-SM80-NEXT: mul.lo.s32 %r11, %r2, %r6;
+; CHECK-SM80-NEXT: mul.lo.s32 %r12, %r4, %r11;
+; CHECK-SM80-NEXT: mul.lo.s32 %r13, %r10, %r12;
+; CHECK-SM80-NEXT: st.param.b32 [func_retval0], %r13;
+; CHECK-SM80-NEXT: ret;
+;
+; CHECK-SM100-LABEL: reduce_mul_i32_nonpow2(
+; CHECK-SM100: {
+; CHECK-SM100-NEXT: .reg .b32 %r<14>;
+; CHECK-SM100-EMPTY:
+; CHECK-SM100-NEXT: // %bb.0:
+; CHECK-SM100-NEXT: ld.param::func.b32 %r7, [reduce_mul_i32_nonpow2_param_0+24];
+; CHECK-SM100-NEXT: ld.param::func.v2.b32 {%r5, %r6}, [reduce_mul_i32_nonpow2_param_0+16];
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_mul_i32_nonpow2_param_0];
+; CHECK-SM100-NEXT: mul.lo.s32 %r8, %r3, %r7;
+; CHECK-SM100-NEXT: mul.lo.s32 %r9, %r1, %r5;
+; CHECK-SM100-NEXT: mul.lo.s32 %r10, %r9, %r8;
+; CHECK-SM100-NEXT: mul.lo.s32 %r11, %r2, %r6;
+; CHECK-SM100-NEXT: mul.lo.s32 %r12, %r4, %r11;
+; CHECK-SM100-NEXT: mul.lo.s32 %r13, %r10, %r12;
+; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r13;
+; CHECK-SM100-NEXT: ret;
%res = call i32 @llvm.vector.reduce.mul(<7 x i32> %in)
ret i32 %res
}
@@ -1657,14 +2131,14 @@ define i16 @reduce_umax_i16(<8 x i16> %in) {
; CHECK-SM100-NEXT: .reg .b32 %r<9>;
; CHECK-SM100-EMPTY:
; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_umax_i16_param_0];
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_umax_i16_param_0];
; CHECK-SM100-NEXT: max.u16x2 %r5, %r2, %r4;
; CHECK-SM100-NEXT: max.u16x2 %r6, %r1, %r3;
; CHECK-SM100-NEXT: max.u16x2 %r7, %r6, %r5;
; CHECK-SM100-NEXT: mov.b32 {%rs1, %rs2}, %r7;
; CHECK-SM100-NEXT: max.u16 %rs3, %rs1, %rs2;
; CHECK-SM100-NEXT: cvt.u32.u16 %r8, %rs3;
-; CHECK-SM100-NEXT: st.param.b32 [func_retval0], %r8;
+; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r8;
; CHECK-SM100-NEXT: ret;
%res = call i16 @llvm.vector.reduce.umax(<8 x i16> %in)
ret i16 %res
@@ -1696,12 +2170,12 @@ define i16 @reduce_umax_i16_nonpow2(<7 x i16> %in) {
; CHECK-SM100-NEXT: .reg .b32 %r<9>;
; CHECK-SM100-EMPTY:
; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param.b32 %r1, [reduce_umax_i16_nonpow2_param_0+8];
+; CHECK-SM100-NEXT: ld.param::func.b32 %r1, [reduce_umax_i16_nonpow2_param_0+8];
; CHECK-SM100-NEXT: mov.b32 {%rs5, %rs6}, %r1;
-; CHECK-SM100-NEXT: ld.param.v2.b32 {%r2, %r3}, [reduce_umax_i16_nonpow2_param_0];
+; CHECK-SM100-NEXT: ld.param::func.v2.b32 {%r2, %r3}, [reduce_umax_i16_nonpow2_param_0];
; CHECK-SM100-NEXT: mov.b32 {%rs3, %rs4}, %r3;
; CHECK-SM100-NEXT: mov.b32 {%rs1, %rs2}, %r2;
-; CHECK-SM100-NEXT: ld.param.b16 %rs7, [reduce_umax_i16_nonpow2_param_0+12];
+; CHECK-SM100-NEXT: ld.param::func.b16 %rs7, [reduce_umax_i16_nonpow2_param_0+12];
; CHECK-SM100-NEXT: max.u16x2 %r4, %r2, %r1;
; CHECK-SM100-NEXT: mov.b16 %rs8, 0;
; CHECK-SM100-NEXT: mov.b32 %r5, {%rs7, %rs8};
@@ -1710,7 +2184,7 @@ define i16 @reduce_umax_i16_nonpow2(<7 x i16> %in) {
; CHECK-SM100-NEXT: mov.b32 {%rs9, %rs10}, %r7;
; CHECK-SM100-NEXT: max.u16 %rs11, %rs9, %rs10;
; CHECK-SM100-NEXT: cvt.u32.u16 %r8, %rs11;
-; CHECK-SM100-NEXT: st.param.b32 [func_retval0], %r8;
+; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r8;
; CHECK-SM100-NEXT: ret;
%res = call i16 @llvm.vector.reduce.umax(<7 x i16> %in)
ret i16 %res
@@ -1740,8 +2214,8 @@ define i32 @reduce_umax_i32(<8 x i32> %in) {
; CHECK-SM100-NEXT: .reg .b64 %rd<5>;
; CHECK-SM100-EMPTY:
; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param.v2.b64 {%rd3, %rd4}, [reduce_umax_i32_param_0+16];
-; CHECK-SM100-NEXT: ld.param.v2.b64 {%rd1, %rd2}, [reduce_umax_i32_param_0];
+; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd3, %rd4}, [reduce_umax_i32_param_0+16];
+; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd1, %rd2}, [reduce_umax_i32_param_0];
; CHECK-SM100-NEXT: mov.b64 {%r1, %r2}, %rd4;
; CHECK-SM100-NEXT: mov.b64 {%r3, %r4}, %rd2;
; CHECK-SM100-NEXT: max.u32 %r5, %r4, %r2;
@@ -1753,29 +2227,46 @@ define i32 @reduce_umax_i32(<8 x i32> %in) {
; CHECK-SM100-NEXT: max.u32 %r13, %r8, %r6;
; CHECK-SM100-NEXT: max.u32 %r14, %r13, %r12;
; CHECK-SM100-NEXT: max.u32 %r15, %r14, %r11;
-; CHECK-SM100-NEXT: st.param.b32 [func_retval0], %r15;
+; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r15;
; CHECK-SM100-NEXT: ret;
%res = call i32 @llvm.vector.reduce.umax(<8 x i32> %in)
ret i32 %res
}
define i32 @reduce_umax_i32_nonpow2(<7 x i32> %in) {
-; CHECK-LABEL: reduce_umax_i32_nonpow2(
-; CHECK: {
-; CHECK-NEXT: .reg .b32 %r<14>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r7, [reduce_umax_i32_nonpow2_param_0+24];
-; CHECK-NEXT: ld.param.v2.b32 {%r5, %r6}, [reduce_umax_i32_nonpow2_param_0+16];
-; CHECK-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_umax_i32_nonpow2_param_0];
-; CHECK-NEXT: max.u32 %r8, %r3, %r7;
-; CHECK-NEXT: max.u32 %r9, %r1, %r5;
-; CHECK-NEXT: max.u32 %r10, %r9, %r8;
-; CHECK-NEXT: max.u32 %r11, %r2, %r6;
-; CHECK-NEXT: max.u32 %r12, %r4, %r11;
-; CHECK-NEXT: max.u32 %r13, %r10, %r12;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r13;
-; CHECK-NEXT: ret;
+; CHECK-SM80-LABEL: reduce_umax_i32_nonpow2(
+; CHECK-SM80: {
+; CHECK-SM80-NEXT: .reg .b32 %r<14>;
+; CHECK-SM80-EMPTY:
+; CHECK-SM80-NEXT: // %bb.0:
+; CHECK-SM80-NEXT: ld.param.b32 %r7, [reduce_umax_i32_nonpow2_param_0+24];
+; CHECK-SM80-NEXT: ld.param.v2.b32 {%r5, %r6}, [reduce_umax_i32_nonpow2_param_0+16];
+; CHECK-SM80-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_umax_i32_nonpow2_param_0];
+; CHECK-SM80-NEXT: max.u32 %r8, %r3, %r7;
+; CHECK-SM80-NEXT: max.u32 %r9, %r1, %r5;
+; CHECK-SM80-NEXT: max.u32 %r10, %r9, %r8;
+; CHECK-SM80-NEXT: max.u32 %r11, %r2, %r6;
+; CHECK-SM80-NEXT: max.u32 %r12, %r4, %r11;
+; CHECK-SM80-NEXT: max.u32 %r13, %r10, %r12;
+; CHECK-SM80-NEXT: st.param.b32 [func_retval0], %r13;
+; CHECK-SM80-NEXT: ret;
+;
+; CHECK-SM100-LABEL: reduce_umax_i32_nonpow2(
+; CHECK-SM100: {
+; CHECK-SM100-NEXT: .reg .b32 %r<14>;
+; CHECK-SM100-EMPTY:
+; CHECK-SM100-NEXT: // %bb.0:
+; CHECK-SM100-NEXT: ld.param::func.b32 %r7, [reduce_umax_i32_nonpow2_param_0+24];
+; CHECK-SM100-NEXT: ld.param::func.v2.b32 {%r5, %r6}, [reduce_umax_i32_nonpow2_param_0+16];
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_umax_i32_nonpow2_param_0];
+; CHECK-SM100-NEXT: max.u32 %r8, %r3, %r7;
+; CHECK-SM100-NEXT: max.u32 %r9, %r1, %r5;
+; CHECK-SM100-NEXT: max.u32 %r10, %r9, %r8;
+; CHECK-SM100-NEXT: max.u32 %r11, %r2, %r6;
+; CHECK-SM100-NEXT: max.u32 %r12, %r4, %r11;
+; CHECK-SM100-NEXT: max.u32 %r13, %r10, %r12;
+; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r13;
+; CHECK-SM100-NEXT: ret;
%res = call i32 @llvm.vector.reduce.umax(<7 x i32> %in)
ret i32 %res
}
@@ -1809,14 +2300,14 @@ define i16 @reduce_umin_i16(<8 x i16> %in) {
; CHECK-SM100-NEXT: .reg .b32 %r<9>;
; CHECK-SM100-EMPTY:
; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_umin_i16_param_0];
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_umin_i16_param_0];
; CHECK-SM100-NEXT: min.u16x2 %r5, %r2, %r4;
; CHECK-SM100-NEXT: min.u16x2 %r6, %r1, %r3;
; CHECK-SM100-NEXT: min.u16x2 %r7, %r6, %r5;
; CHECK-SM100-NEXT: mov.b32 {%rs1, %rs2}, %r7;
; CHECK-SM100-NEXT: min.u16 %rs3, %rs1, %rs2;
; CHECK-SM100-NEXT: cvt.u32.u16 %r8, %rs3;
-; CHECK-SM100-NEXT: st.param.b32 [func_retval0], %r8;
+; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r8;
; CHECK-SM100-NEXT: ret;
%res = call i16 @llvm.vector.reduce.umin(<8 x i16> %in)
ret i16 %res
@@ -1848,12 +2339,12 @@ define i16 @reduce_umin_i16_nonpow2(<7 x i16> %in) {
; CHECK-SM100-NEXT: .reg .b32 %r<9>;
; CHECK-SM100-EMPTY:
; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param.b32 %r1, [reduce_umin_i16_nonpow2_param_0+8];
+; CHECK-SM100-NEXT: ld.param::func.b32 %r1, [reduce_umin_i16_nonpow2_param_0+8];
; CHECK-SM100-NEXT: mov.b32 {%rs5, %rs6}, %r1;
-; CHECK-SM100-NEXT: ld.param.v2.b32 {%r2, %r3}, [reduce_umin_i16_nonpow2_param_0];
+; CHECK-SM100-NEXT: ld.param::func.v2.b32 {%r2, %r3}, [reduce_umin_i16_nonpow2_param_0];
; CHECK-SM100-NEXT: mov.b32 {%rs3, %rs4}, %r3;
; CHECK-SM100-NEXT: mov.b32 {%rs1, %rs2}, %r2;
-; CHECK-SM100-NEXT: ld.param.b16 %rs7, [reduce_umin_i16_nonpow2_param_0+12];
+; CHECK-SM100-NEXT: ld.param::func.b16 %rs7, [reduce_umin_i16_nonpow2_param_0+12];
; CHECK-SM100-NEXT: min.u16x2 %r4, %r2, %r1;
; CHECK-SM100-NEXT: mov.b16 %rs8, -1;
; CHECK-SM100-NEXT: mov.b32 %r5, {%rs7, %rs8};
@@ -1862,7 +2353,7 @@ define i16 @reduce_umin_i16_nonpow2(<7 x i16> %in) {
; CHECK-SM100-NEXT: mov.b32 {%rs9, %rs10}, %r7;
; CHECK-SM100-NEXT: min.u16 %rs11, %rs9, %rs10;
; CHECK-SM100-NEXT: cvt.u32.u16 %r8, %rs11;
-; CHECK-SM100-NEXT: st.param.b32 [func_retval0], %r8;
+; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r8;
; CHECK-SM100-NEXT: ret;
%res = call i16 @llvm.vector.reduce.umin(<7 x i16> %in)
ret i16 %res
@@ -1892,8 +2383,8 @@ define i32 @reduce_umin_i32(<8 x i32> %in) {
; CHECK-SM100-NEXT: .reg .b64 %rd<5>;
; CHECK-SM100-EMPTY:
; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param.v2.b64 {%rd3, %rd4}, [reduce_umin_i32_param_0+16];
-; CHECK-SM100-NEXT: ld.param.v2.b64 {%rd1, %rd2}, [reduce_umin_i32_param_0];
+; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd3, %rd4}, [reduce_umin_i32_param_0+16];
+; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd1, %rd2}, [reduce_umin_i32_param_0];
; CHECK-SM100-NEXT: mov.b64 {%r1, %r2}, %rd4;
; CHECK-SM100-NEXT: mov.b64 {%r3, %r4}, %rd2;
; CHECK-SM100-NEXT: min.u32 %r5, %r4, %r2;
@@ -1905,29 +2396,46 @@ define i32 @reduce_umin_i32(<8 x i32> %in) {
; CHECK-SM100-NEXT: min.u32 %r13, %r8, %r6;
; CHECK-SM100-NEXT: min.u32 %r14, %r13, %r12;
; CHECK-SM100-NEXT: min.u32 %r15, %r14, %r11;
-; CHECK-SM100-NEXT: st.param.b32 [func_retval0], %r15;
+; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r15;
; CHECK-SM100-NEXT: ret;
%res = call i32 @llvm.vector.reduce.umin(<8 x i32> %in)
ret i32 %res
}
define i32 @reduce_umin_i32_nonpow2(<7 x i32> %in) {
-; CHECK-LABEL: reduce_umin_i32_nonpow2(
-; CHECK: {
-; CHECK-NEXT: .reg .b32 %r<14>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r7, [reduce_umin_i32_nonpow2_param_0+24];
-; CHECK-NEXT: ld.param.v2.b32 {%r5, %r6}, [reduce_umin_i32_nonpow2_param_0+16];
-; CHECK-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_umin_i32_nonpow2_param_0];
-; CHECK-NEXT: min.u32 %r8, %r3, %r7;
-; CHECK-NEXT: min.u32 %r9, %r1, %r5;
-; CHECK-NEXT: min.u32 %r10, %r9, %r8;
-; CHECK-NEXT: min.u32 %r11, %r2, %r6;
-; CHECK-NEXT: min.u32 %r12, %r4, %r11;
-; CHECK-NEXT: min.u32 %r13, %r10, %r12;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r13;
-; CHECK-NEXT: ret;
+; CHECK-SM80-LABEL: reduce_umin_i32_nonpow2(
+; CHECK-SM80: {
+; CHECK-SM80-NEXT: .reg .b32 %r<14>;
+; CHECK-SM80-EMPTY:
+; CHECK-SM80-NEXT: // %bb.0:
+; CHECK-SM80-NEXT: ld.param.b32 %r7, [reduce_umin_i32_nonpow2_param_0+24];
+; CHECK-SM80-NEXT: ld.param.v2.b32 {%r5, %r6}, [reduce_umin_i32_nonpow2_param_0+16];
+; CHECK-SM80-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_umin_i32_nonpow2_param_0];
+; CHECK-SM80-NEXT: min.u32 %r8, %r3, %r7;
+; CHECK-SM80-NEXT: min.u32 %r9, %r1, %r5;
+; CHECK-SM80-NEXT: min.u32 %r10, %r9, %r8;
+; CHECK-SM80-NEXT: min.u32 %r11, %r2, %r6;
+; CHECK-SM80-NEXT: min.u32 %r12, %r4, %r11;
+; CHECK-SM80-NEXT: min.u32 %r13, %r10, %r12;
+; CHECK-SM80-NEXT: st.param.b32 [func_retval0], %r13;
+; CHECK-SM80-NEXT: ret;
+;
+; CHECK-SM100-LABEL: reduce_umin_i32_nonpow2(
+; CHECK-SM100: {
+; CHECK-SM100-NEXT: .reg .b32 %r<14>;
+; CHECK-SM100-EMPTY:
+; CHECK-SM100-NEXT: // %bb.0:
+; CHECK-SM100-NEXT: ld.param::func.b32 %r7, [reduce_umin_i32_nonpow2_param_0+24];
+; CHECK-SM100-NEXT: ld.param::func.v2.b32 {%r5, %r6}, [reduce_umin_i32_nonpow2_param_0+16];
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_umin_i32_nonpow2_param_0];
+; CHECK-SM100-NEXT: min.u32 %r8, %r3, %r7;
+; CHECK-SM100-NEXT: min.u32 %r9, %r1, %r5;
+; CHECK-SM100-NEXT: min.u32 %r10, %r9, %r8;
+; CHECK-SM100-NEXT: min.u32 %r11, %r2, %r6;
+; CHECK-SM100-NEXT: min.u32 %r12, %r4, %r11;
+; CHECK-SM100-NEXT: min.u32 %r13, %r10, %r12;
+; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r13;
+; CHECK-SM100-NEXT: ret;
%res = call i32 @llvm.vector.reduce.umin(<7 x i32> %in)
ret i32 %res
}
@@ -1961,14 +2469,14 @@ define i16 @reduce_smax_i16(<8 x i16> %in) {
; CHECK-SM100-NEXT: .reg .b32 %r<9>;
; CHECK-SM100-EMPTY:
; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_smax_i16_param_0];
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_smax_i16_param_0];
; CHECK-SM100-NEXT: max.s16x2 %r5, %r2, %r4;
; CHECK-SM100-NEXT: max.s16x2 %r6, %r1, %r3;
; CHECK-SM100-NEXT: max.s16x2 %r7, %r6, %r5;
; CHECK-SM100-NEXT: mov.b32 {%rs1, %rs2}, %r7;
; CHECK-SM100-NEXT: max.s16 %rs3, %rs1, %rs2;
; CHECK-SM100-NEXT: cvt.u32.u16 %r8, %rs3;
-; CHECK-SM100-NEXT: st.param.b32 [func_retval0], %r8;
+; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r8;
; CHECK-SM100-NEXT: ret;
%res = call i16 @llvm.vector.reduce.smax(<8 x i16> %in)
ret i16 %res
@@ -2000,12 +2508,12 @@ define i16 @reduce_smax_i16_nonpow2(<7 x i16> %in) {
; CHECK-SM100-NEXT: .reg .b32 %r<9>;
; CHECK-SM100-EMPTY:
; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param.b32 %r1, [reduce_smax_i16_nonpow2_param_0+8];
+; CHECK-SM100-NEXT: ld.param::func.b32 %r1, [reduce_smax_i16_nonpow2_param_0+8];
; CHECK-SM100-NEXT: mov.b32 {%rs5, %rs6}, %r1;
-; CHECK-SM100-NEXT: ld.param.v2.b32 {%r2, %r3}, [reduce_smax_i16_nonpow2_param_0];
+; CHECK-SM100-NEXT: ld.param::func.v2.b32 {%r2, %r3}, [reduce_smax_i16_nonpow2_param_0];
; CHECK-SM100-NEXT: mov.b32 {%rs3, %rs4}, %r3;
; CHECK-SM100-NEXT: mov.b32 {%rs1, %rs2}, %r2;
-; CHECK-SM100-NEXT: ld.param.b16 %rs7, [reduce_smax_i16_nonpow2_param_0+12];
+; CHECK-SM100-NEXT: ld.param::func.b16 %rs7, [reduce_smax_i16_nonpow2_param_0+12];
; CHECK-SM100-NEXT: max.s16x2 %r4, %r2, %r1;
; CHECK-SM100-NEXT: mov.b16 %rs8, -32768;
; CHECK-SM100-NEXT: mov.b32 %r5, {%rs7, %rs8};
@@ -2014,7 +2522,7 @@ define i16 @reduce_smax_i16_nonpow2(<7 x i16> %in) {
; CHECK-SM100-NEXT: mov.b32 {%rs9, %rs10}, %r7;
; CHECK-SM100-NEXT: max.s16 %rs11, %rs9, %rs10;
; CHECK-SM100-NEXT: cvt.u32.u16 %r8, %rs11;
-; CHECK-SM100-NEXT: st.param.b32 [func_retval0], %r8;
+; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r8;
; CHECK-SM100-NEXT: ret;
%res = call i16 @llvm.vector.reduce.smax(<7 x i16> %in)
ret i16 %res
@@ -2044,8 +2552,8 @@ define i32 @reduce_smax_i32(<8 x i32> %in) {
; CHECK-SM100-NEXT: .reg .b64 %rd<5>;
; CHECK-SM100-EMPTY:
; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param.v2.b64 {%rd3, %rd4}, [reduce_smax_i32_param_0+16];
-; CHECK-SM100-NEXT: ld.param.v2.b64 {%rd1, %rd2}, [reduce_smax_i32_param_0];
+; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd3, %rd4}, [reduce_smax_i32_param_0+16];
+; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd1, %rd2}, [reduce_smax_i32_param_0];
; CHECK-SM100-NEXT: mov.b64 {%r1, %r2}, %rd4;
; CHECK-SM100-NEXT: mov.b64 {%r3, %r4}, %rd2;
; CHECK-SM100-NEXT: max.s32 %r5, %r4, %r2;
@@ -2057,29 +2565,46 @@ define i32 @reduce_smax_i32(<8 x i32> %in) {
; CHECK-SM100-NEXT: max.s32 %r13, %r8, %r6;
; CHECK-SM100-NEXT: max.s32 %r14, %r13, %r12;
; CHECK-SM100-NEXT: max.s32 %r15, %r14, %r11;
-; CHECK-SM100-NEXT: st.param.b32 [func_retval0], %r15;
+; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r15;
; CHECK-SM100-NEXT: ret;
%res = call i32 @llvm.vector.reduce.smax(<8 x i32> %in)
ret i32 %res
}
define i32 @reduce_smax_i32_nonpow2(<7 x i32> %in) {
-; CHECK-LABEL: reduce_smax_i32_nonpow2(
-; CHECK: {
-; CHECK-NEXT: .reg .b32 %r<14>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r7, [reduce_smax_i32_nonpow2_param_0+24];
-; CHECK-NEXT: ld.param.v2.b32 {%r5, %r6}, [reduce_smax_i32_nonpow2_param_0+16];
-; CHECK-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_smax_i32_nonpow2_param_0];
-; CHECK-NEXT: max.s32 %r8, %r3, %r7;
-; CHECK-NEXT: max.s32 %r9, %r1, %r5;
-; CHECK-NEXT: max.s32 %r10, %r9, %r8;
-; CHECK-NEXT: max.s32 %r11, %r2, %r6;
-; CHECK-NEXT: max.s32 %r12, %r4, %r11;
-; CHECK-NEXT: max.s32 %r13, %r10, %r12;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r13;
-; CHECK-NEXT: ret;
+; CHECK-SM80-LABEL: reduce_smax_i32_nonpow2(
+; CHECK-SM80: {
+; CHECK-SM80-NEXT: .reg .b32 %r<14>;
+; CHECK-SM80-EMPTY:
+; CHECK-SM80-NEXT: // %bb.0:
+; CHECK-SM80-NEXT: ld.param.b32 %r7, [reduce_smax_i32_nonpow2_param_0+24];
+; CHECK-SM80-NEXT: ld.param.v2.b32 {%r5, %r6}, [reduce_smax_i32_nonpow2_param_0+16];
+; CHECK-SM80-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_smax_i32_nonpow2_param_0];
+; CHECK-SM80-NEXT: max.s32 %r8, %r3, %r7;
+; CHECK-SM80-NEXT: max.s32 %r9, %r1, %r5;
+; CHECK-SM80-NEXT: max.s32 %r10, %r9, %r8;
+; CHECK-SM80-NEXT: max.s32 %r11, %r2, %r6;
+; CHECK-SM80-NEXT: max.s32 %r12, %r4, %r11;
+; CHECK-SM80-NEXT: max.s32 %r13, %r10, %r12;
+; CHECK-SM80-NEXT: st.param.b32 [func_retval0], %r13;
+; CHECK-SM80-NEXT: ret;
+;
+; CHECK-SM100-LABEL: reduce_smax_i32_nonpow2(
+; CHECK-SM100: {
+; CHECK-SM100-NEXT: .reg .b32 %r<14>;
+; CHECK-SM100-EMPTY:
+; CHECK-SM100-NEXT: // %bb.0:
+; CHECK-SM100-NEXT: ld.param::func.b32 %r7, [reduce_smax_i32_nonpow2_param_0+24];
+; CHECK-SM100-NEXT: ld.param::func.v2.b32 {%r5, %r6}, [reduce_smax_i32_nonpow2_param_0+16];
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_smax_i32_nonpow2_param_0];
+; CHECK-SM100-NEXT: max.s32 %r8, %r3, %r7;
+; CHECK-SM100-NEXT: max.s32 %r9, %r1, %r5;
+; CHECK-SM100-NEXT: max.s32 %r10, %r9, %r8;
+; CHECK-SM100-NEXT: max.s32 %r11, %r2, %r6;
+; CHECK-SM100-NEXT: max.s32 %r12, %r4, %r11;
+; CHECK-SM100-NEXT: max.s32 %r13, %r10, %r12;
+; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r13;
+; CHECK-SM100-NEXT: ret;
%res = call i32 @llvm.vector.reduce.smax(<7 x i32> %in)
ret i32 %res
}
@@ -2113,14 +2638,14 @@ define i16 @reduce_smin_i16(<8 x i16> %in) {
; CHECK-SM100-NEXT: .reg .b32 %r<9>;
; CHECK-SM100-EMPTY:
; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_smin_i16_param_0];
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_smin_i16_param_0];
; CHECK-SM100-NEXT: min.s16x2 %r5, %r2, %r4;
; CHECK-SM100-NEXT: min.s16x2 %r6, %r1, %r3;
; CHECK-SM100-NEXT: min.s16x2 %r7, %r6, %r5;
; CHECK-SM100-NEXT: mov.b32 {%rs1, %rs2}, %r7;
; CHECK-SM100-NEXT: min.s16 %rs3, %rs1, %rs2;
; CHECK-SM100-NEXT: cvt.u32.u16 %r8, %rs3;
-; CHECK-SM100-NEXT: st.param.b32 [func_retval0], %r8;
+; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r8;
; CHECK-SM100-NEXT: ret;
%res = call i16 @llvm.vector.reduce.smin(<8 x i16> %in)
ret i16 %res
@@ -2152,12 +2677,12 @@ define i16 @reduce_smin_i16_nonpow2(<7 x i16> %in) {
; CHECK-SM100-NEXT: .reg .b32 %r<9>;
; CHECK-SM100-EMPTY:
; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param.b32 %r1, [reduce_smin_i16_nonpow2_param_0+8];
+; CHECK-SM100-NEXT: ld.param::func.b32 %r1, [reduce_smin_i16_nonpow2_param_0+8];
; CHECK-SM100-NEXT: mov.b32 {%rs5, %rs6}, %r1;
-; CHECK-SM100-NEXT: ld.param.v2.b32 {%r2, %r3}, [reduce_smin_i16_nonpow2_param_0];
+; CHECK-SM100-NEXT: ld.param::func.v2.b32 {%r2, %r3}, [reduce_smin_i16_nonpow2_param_0];
; CHECK-SM100-NEXT: mov.b32 {%rs3, %rs4}, %r3;
; CHECK-SM100-NEXT: mov.b32 {%rs1, %rs2}, %r2;
-; CHECK-SM100-NEXT: ld.param.b16 %rs7, [reduce_smin_i16_nonpow2_param_0+12];
+; CHECK-SM100-NEXT: ld.param::func.b16 %rs7, [reduce_smin_i16_nonpow2_param_0+12];
; CHECK-SM100-NEXT: min.s16x2 %r4, %r2, %r1;
; CHECK-SM100-NEXT: mov.b16 %rs8, 32767;
; CHECK-SM100-NEXT: mov.b32 %r5, {%rs7, %rs8};
@@ -2166,7 +2691,7 @@ define i16 @reduce_smin_i16_nonpow2(<7 x i16> %in) {
; CHECK-SM100-NEXT: mov.b32 {%rs9, %rs10}, %r7;
; CHECK-SM100-NEXT: min.s16 %rs11, %rs9, %rs10;
; CHECK-SM100-NEXT: cvt.u32.u16 %r8, %rs11;
-; CHECK-SM100-NEXT: st.param.b32 [func_retval0], %r8;
+; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r8;
; CHECK-SM100-NEXT: ret;
%res = call i16 @llvm.vector.reduce.smin(<7 x i16> %in)
ret i16 %res
@@ -2196,8 +2721,8 @@ define i32 @reduce_smin_i32(<8 x i32> %in) {
; CHECK-SM100-NEXT: .reg .b64 %rd<5>;
; CHECK-SM100-EMPTY:
; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param.v2.b64 {%rd3, %rd4}, [reduce_smin_i32_param_0+16];
-; CHECK-SM100-NEXT: ld.param.v2.b64 {%rd1, %rd2}, [reduce_smin_i32_param_0];
+; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd3, %rd4}, [reduce_smin_i32_param_0+16];
+; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd1, %rd2}, [reduce_smin_i32_param_0];
; CHECK-SM100-NEXT: mov.b64 {%r1, %r2}, %rd4;
; CHECK-SM100-NEXT: mov.b64 {%r3, %r4}, %rd2;
; CHECK-SM100-NEXT: min.s32 %r5, %r4, %r2;
@@ -2209,76 +2734,132 @@ define i32 @reduce_smin_i32(<8 x i32> %in) {
; CHECK-SM100-NEXT: min.s32 %r13, %r8, %r6;
; CHECK-SM100-NEXT: min.s32 %r14, %r13, %r12;
; CHECK-SM100-NEXT: min.s32 %r15, %r14, %r11;
-; CHECK-SM100-NEXT: st.param.b32 [func_retval0], %r15;
+; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r15;
; CHECK-SM100-NEXT: ret;
%res = call i32 @llvm.vector.reduce.smin(<8 x i32> %in)
ret i32 %res
}
define i32 @reduce_smin_i32_nonpow2(<7 x i32> %in) {
-; CHECK-LABEL: reduce_smin_i32_nonpow2(
-; CHECK: {
-; CHECK-NEXT: .reg .b32 %r<14>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r7, [reduce_smin_i32_nonpow2_param_0+24];
-; CHECK-NEXT: ld.param.v2.b32 {%r5, %r6}, [reduce_smin_i32_nonpow2_param_0+16];
-; CHECK-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_smin_i32_nonpow2_param_0];
-; CHECK-NEXT: min.s32 %r8, %r3, %r7;
-; CHECK-NEXT: min.s32 %r9, %r1, %r5;
-; CHECK-NEXT: min.s32 %r10, %r9, %r8;
-; CHECK-NEXT: min.s32 %r11, %r2, %r6;
-; CHECK-NEXT: min.s32 %r12, %r4, %r11;
-; CHECK-NEXT: min.s32 %r13, %r10, %r12;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r13;
-; CHECK-NEXT: ret;
+; CHECK-SM80-LABEL: reduce_smin_i32_nonpow2(
+; CHECK-SM80: {
+; CHECK-SM80-NEXT: .reg .b32 %r<14>;
+; CHECK-SM80-EMPTY:
+; CHECK-SM80-NEXT: // %bb.0:
+; CHECK-SM80-NEXT: ld.param.b32 %r7, [reduce_smin_i32_nonpow2_param_0+24];
+; CHECK-SM80-NEXT: ld.param.v2.b32 {%r5, %r6}, [reduce_smin_i32_nonpow2_param_0+16];
+; CHECK-SM80-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_smin_i32_nonpow2_param_0];
+; CHECK-SM80-NEXT: min.s32 %r8, %r3, %r7;
+; CHECK-SM80-NEXT: min.s32 %r9, %r1, %r5;
+; CHECK-SM80-NEXT: min.s32 %r10, %r9, %r8;
+; CHECK-SM80-NEXT: min.s32 %r11, %r2, %r6;
+; CHECK-SM80-NEXT: min.s32 %r12, %r4, %r11;
+; CHECK-SM80-NEXT: min.s32 %r13, %r10, %r12;
+; CHECK-SM80-NEXT: st.param.b32 [func_retval0], %r13;
+; CHECK-SM80-NEXT: ret;
+;
+; CHECK-SM100-LABEL: reduce_smin_i32_nonpow2(
+; CHECK-SM100: {
+; CHECK-SM100-NEXT: .reg .b32 %r<14>;
+; CHECK-SM100-EMPTY:
+; CHECK-SM100-NEXT: // %bb.0:
+; CHECK-SM100-NEXT: ld.param::func.b32 %r7, [reduce_smin_i32_nonpow2_param_0+24];
+; CHECK-SM100-NEXT: ld.param::func.v2.b32 {%r5, %r6}, [reduce_smin_i32_nonpow2_param_0+16];
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_smin_i32_nonpow2_param_0];
+; CHECK-SM100-NEXT: min.s32 %r8, %r3, %r7;
+; CHECK-SM100-NEXT: min.s32 %r9, %r1, %r5;
+; CHECK-SM100-NEXT: min.s32 %r10, %r9, %r8;
+; CHECK-SM100-NEXT: min.s32 %r11, %r2, %r6;
+; CHECK-SM100-NEXT: min.s32 %r12, %r4, %r11;
+; CHECK-SM100-NEXT: min.s32 %r13, %r10, %r12;
+; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r13;
+; CHECK-SM100-NEXT: ret;
%res = call i32 @llvm.vector.reduce.smin(<7 x i32> %in)
ret i32 %res
}
define i16 @reduce_and_i16(<8 x i16> %in) {
-; CHECK-LABEL: reduce_and_i16(
-; CHECK: {
-; CHECK-NEXT: .reg .b16 %rs<4>;
-; CHECK-NEXT: .reg .b32 %r<9>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_and_i16_param_0];
-; CHECK-NEXT: and.b32 %r5, %r2, %r4;
-; CHECK-NEXT: and.b32 %r6, %r1, %r3;
-; CHECK-NEXT: and.b32 %r7, %r6, %r5;
-; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r7;
-; CHECK-NEXT: and.b16 %rs3, %rs1, %rs2;
-; CHECK-NEXT: cvt.u32.u16 %r8, %rs3;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r8;
-; CHECK-NEXT: ret;
+; CHECK-SM80-LABEL: reduce_and_i16(
+; CHECK-SM80: {
+; CHECK-SM80-NEXT: .reg .b16 %rs<4>;
+; CHECK-SM80-NEXT: .reg .b32 %r<9>;
+; CHECK-SM80-EMPTY:
+; CHECK-SM80-NEXT: // %bb.0:
+; CHECK-SM80-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_and_i16_param_0];
+; CHECK-SM80-NEXT: and.b32 %r5, %r2, %r4;
+; CHECK-SM80-NEXT: and.b32 %r6, %r1, %r3;
+; CHECK-SM80-NEXT: and.b32 %r7, %r6, %r5;
+; CHECK-SM80-NEXT: mov.b32 {%rs1, %rs2}, %r7;
+; CHECK-SM80-NEXT: and.b16 %rs3, %rs1, %rs2;
+; CHECK-SM80-NEXT: cvt.u32.u16 %r8, %rs3;
+; CHECK-SM80-NEXT: st.param.b32 [func_retval0], %r8;
+; CHECK-SM80-NEXT: ret;
+;
+; CHECK-SM100-LABEL: reduce_and_i16(
+; CHECK-SM100: {
+; CHECK-SM100-NEXT: .reg .b16 %rs<4>;
+; CHECK-SM100-NEXT: .reg .b32 %r<9>;
+; CHECK-SM100-EMPTY:
+; CHECK-SM100-NEXT: // %bb.0:
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_and_i16_param_0];
+; CHECK-SM100-NEXT: and.b32 %r5, %r2, %r4;
+; CHECK-SM100-NEXT: and.b32 %r6, %r1, %r3;
+; CHECK-SM100-NEXT: and.b32 %r7, %r6, %r5;
+; CHECK-SM100-NEXT: mov.b32 {%rs1, %rs2}, %r7;
+; CHECK-SM100-NEXT: and.b16 %rs3, %rs1, %rs2;
+; CHECK-SM100-NEXT: cvt.u32.u16 %r8, %rs3;
+; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r8;
+; CHECK-SM100-NEXT: ret;
%res = call i16 @llvm.vector.reduce.and(<8 x i16> %in)
ret i16 %res
}
define i16 @reduce_and_i16_nonpow2(<7 x i16> %in) {
-; CHECK-LABEL: reduce_and_i16_nonpow2(
-; CHECK: {
-; CHECK-NEXT: .reg .b16 %rs<12>;
-; CHECK-NEXT: .reg .b32 %r<9>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [reduce_and_i16_nonpow2_param_0+8];
-; CHECK-NEXT: mov.b32 {%rs5, %rs6}, %r1;
-; CHECK-NEXT: ld.param.v2.b32 {%r2, %r3}, [reduce_and_i16_nonpow2_param_0];
-; CHECK-NEXT: mov.b32 {%rs3, %rs4}, %r3;
-; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r2;
-; CHECK-NEXT: ld.param.b16 %rs7, [reduce_and_i16_nonpow2_param_0+12];
-; CHECK-NEXT: and.b32 %r4, %r2, %r1;
-; CHECK-NEXT: mov.b16 %rs8, -1;
-; CHECK-NEXT: mov.b32 %r5, {%rs7, %rs8};
-; CHECK-NEXT: and.b32 %r6, %r3, %r5;
-; CHECK-NEXT: and.b32 %r7, %r4, %r6;
-; CHECK-NEXT: mov.b32 {%rs9, %rs10}, %r7;
-; CHECK-NEXT: and.b16 %rs11, %rs9, %rs10;
-; CHECK-NEXT: cvt.u32.u16 %r8, %rs11;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r8;
-; CHECK-NEXT: ret;
+; CHECK-SM80-LABEL: reduce_and_i16_nonpow2(
+; CHECK-SM80: {
+; CHECK-SM80-NEXT: .reg .b16 %rs<12>;
+; CHECK-SM80-NEXT: .reg .b32 %r<9>;
+; CHECK-SM80-EMPTY:
+; CHECK-SM80-NEXT: // %bb.0:
+; CHECK-SM80-NEXT: ld.param.b32 %r1, [reduce_and_i16_nonpow2_param_0+8];
+; CHECK-SM80-NEXT: mov.b32 {%rs5, %rs6}, %r1;
+; CHECK-SM80-NEXT: ld.param.v2.b32 {%r2, %r3}, [reduce_and_i16_nonpow2_param_0];
+; CHECK-SM80-NEXT: mov.b32 {%rs3, %rs4}, %r3;
+; CHECK-SM80-NEXT: mov.b32 {%rs1, %rs2}, %r2;
+; CHECK-SM80-NEXT: ld.param.b16 %rs7, [reduce_and_i16_nonpow2_param_0+12];
+; CHECK-SM80-NEXT: and.b32 %r4, %r2, %r1;
+; CHECK-SM80-NEXT: mov.b16 %rs8, -1;
+; CHECK-SM80-NEXT: mov.b32 %r5, {%rs7, %rs8};
+; CHECK-SM80-NEXT: and.b32 %r6, %r3, %r5;
+; CHECK-SM80-NEXT: and.b32 %r7, %r4, %r6;
+; CHECK-SM80-NEXT: mov.b32 {%rs9, %rs10}, %r7;
+; CHECK-SM80-NEXT: and.b16 %rs11, %rs9, %rs10;
+; CHECK-SM80-NEXT: cvt.u32.u16 %r8, %rs11;
+; CHECK-SM80-NEXT: st.param.b32 [func_retval0], %r8;
+; CHECK-SM80-NEXT: ret;
+;
+; CHECK-SM100-LABEL: reduce_and_i16_nonpow2(
+; CHECK-SM100: {
+; CHECK-SM100-NEXT: .reg .b16 %rs<12>;
+; CHECK-SM100-NEXT: .reg .b32 %r<9>;
+; CHECK-SM100-EMPTY:
+; CHECK-SM100-NEXT: // %bb.0:
+; CHECK-SM100-NEXT: ld.param::func.b32 %r1, [reduce_and_i16_nonpow2_param_0+8];
+; CHECK-SM100-NEXT: mov.b32 {%rs5, %rs6}, %r1;
+; CHECK-SM100-NEXT: ld.param::func.v2.b32 {%r2, %r3}, [reduce_and_i16_nonpow2_param_0];
+; CHECK-SM100-NEXT: mov.b32 {%rs3, %rs4}, %r3;
+; CHECK-SM100-NEXT: mov.b32 {%rs1, %rs2}, %r2;
+; CHECK-SM100-NEXT: ld.param::func.b16 %rs7, [reduce_and_i16_nonpow2_param_0+12];
+; CHECK-SM100-NEXT: and.b32 %r4, %r2, %r1;
+; CHECK-SM100-NEXT: mov.b16 %rs8, -1;
+; CHECK-SM100-NEXT: mov.b32 %r5, {%rs7, %rs8};
+; CHECK-SM100-NEXT: and.b32 %r6, %r3, %r5;
+; CHECK-SM100-NEXT: and.b32 %r7, %r4, %r6;
+; CHECK-SM100-NEXT: mov.b32 {%rs9, %rs10}, %r7;
+; CHECK-SM100-NEXT: and.b16 %rs11, %rs9, %rs10;
+; CHECK-SM100-NEXT: cvt.u32.u16 %r8, %rs11;
+; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r8;
+; CHECK-SM100-NEXT: ret;
%res = call i16 @llvm.vector.reduce.and(<7 x i16> %in)
ret i16 %res
}
@@ -2307,8 +2888,8 @@ define i32 @reduce_and_i32(<8 x i32> %in) {
; CHECK-SM100-NEXT: .reg .b64 %rd<5>;
; CHECK-SM100-EMPTY:
; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param.v2.b64 {%rd3, %rd4}, [reduce_and_i32_param_0+16];
-; CHECK-SM100-NEXT: ld.param.v2.b64 {%rd1, %rd2}, [reduce_and_i32_param_0];
+; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd3, %rd4}, [reduce_and_i32_param_0+16];
+; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd1, %rd2}, [reduce_and_i32_param_0];
; CHECK-SM100-NEXT: mov.b64 {%r1, %r2}, %rd4;
; CHECK-SM100-NEXT: mov.b64 {%r3, %r4}, %rd2;
; CHECK-SM100-NEXT: and.b32 %r5, %r4, %r2;
@@ -2320,76 +2901,132 @@ define i32 @reduce_and_i32(<8 x i32> %in) {
; CHECK-SM100-NEXT: and.b32 %r13, %r8, %r6;
; CHECK-SM100-NEXT: and.b32 %r14, %r13, %r12;
; CHECK-SM100-NEXT: and.b32 %r15, %r14, %r11;
-; CHECK-SM100-NEXT: st.param.b32 [func_retval0], %r15;
+; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r15;
; CHECK-SM100-NEXT: ret;
%res = call i32 @llvm.vector.reduce.and(<8 x i32> %in)
ret i32 %res
}
define i32 @reduce_and_i32_nonpow2(<7 x i32> %in) {
-; CHECK-LABEL: reduce_and_i32_nonpow2(
-; CHECK: {
-; CHECK-NEXT: .reg .b32 %r<14>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r7, [reduce_and_i32_nonpow2_param_0+24];
-; CHECK-NEXT: ld.param.v2.b32 {%r5, %r6}, [reduce_and_i32_nonpow2_param_0+16];
-; CHECK-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_and_i32_nonpow2_param_0];
-; CHECK-NEXT: and.b32 %r8, %r3, %r7;
-; CHECK-NEXT: and.b32 %r9, %r1, %r5;
-; CHECK-NEXT: and.b32 %r10, %r9, %r8;
-; CHECK-NEXT: and.b32 %r11, %r2, %r6;
-; CHECK-NEXT: and.b32 %r12, %r11, %r4;
-; CHECK-NEXT: and.b32 %r13, %r10, %r12;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r13;
-; CHECK-NEXT: ret;
+; CHECK-SM80-LABEL: reduce_and_i32_nonpow2(
+; CHECK-SM80: {
+; CHECK-SM80-NEXT: .reg .b32 %r<14>;
+; CHECK-SM80-EMPTY:
+; CHECK-SM80-NEXT: // %bb.0:
+; CHECK-SM80-NEXT: ld.param.b32 %r7, [reduce_and_i32_nonpow2_param_0+24];
+; CHECK-SM80-NEXT: ld.param.v2.b32 {%r5, %r6}, [reduce_and_i32_nonpow2_param_0+16];
+; CHECK-SM80-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_and_i32_nonpow2_param_0];
+; CHECK-SM80-NEXT: and.b32 %r8, %r3, %r7;
+; CHECK-SM80-NEXT: and.b32 %r9, %r1, %r5;
+; CHECK-SM80-NEXT: and.b32 %r10, %r9, %r8;
+; CHECK-SM80-NEXT: and.b32 %r11, %r2, %r6;
+; CHECK-SM80-NEXT: and.b32 %r12, %r11, %r4;
+; CHECK-SM80-NEXT: and.b32 %r13, %r10, %r12;
+; CHECK-SM80-NEXT: st.param.b32 [func_retval0], %r13;
+; CHECK-SM80-NEXT: ret;
+;
+; CHECK-SM100-LABEL: reduce_and_i32_nonpow2(
+; CHECK-SM100: {
+; CHECK-SM100-NEXT: .reg .b32 %r<14>;
+; CHECK-SM100-EMPTY:
+; CHECK-SM100-NEXT: // %bb.0:
+; CHECK-SM100-NEXT: ld.param::func.b32 %r7, [reduce_and_i32_nonpow2_param_0+24];
+; CHECK-SM100-NEXT: ld.param::func.v2.b32 {%r5, %r6}, [reduce_and_i32_nonpow2_param_0+16];
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_and_i32_nonpow2_param_0];
+; CHECK-SM100-NEXT: and.b32 %r8, %r3, %r7;
+; CHECK-SM100-NEXT: and.b32 %r9, %r1, %r5;
+; CHECK-SM100-NEXT: and.b32 %r10, %r9, %r8;
+; CHECK-SM100-NEXT: and.b32 %r11, %r2, %r6;
+; CHECK-SM100-NEXT: and.b32 %r12, %r11, %r4;
+; CHECK-SM100-NEXT: and.b32 %r13, %r10, %r12;
+; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r13;
+; CHECK-SM100-NEXT: ret;
%res = call i32 @llvm.vector.reduce.and(<7 x i32> %in)
ret i32 %res
}
define i16 @reduce_or_i16(<8 x i16> %in) {
-; CHECK-LABEL: reduce_or_i16(
-; CHECK: {
-; CHECK-NEXT: .reg .b16 %rs<4>;
-; CHECK-NEXT: .reg .b32 %r<9>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_or_i16_param_0];
-; CHECK-NEXT: or.b32 %r5, %r2, %r4;
-; CHECK-NEXT: or.b32 %r6, %r1, %r3;
-; CHECK-NEXT: or.b32 %r7, %r6, %r5;
-; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r7;
-; CHECK-NEXT: or.b16 %rs3, %rs1, %rs2;
-; CHECK-NEXT: cvt.u32.u16 %r8, %rs3;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r8;
-; CHECK-NEXT: ret;
+; CHECK-SM80-LABEL: reduce_or_i16(
+; CHECK-SM80: {
+; CHECK-SM80-NEXT: .reg .b16 %rs<4>;
+; CHECK-SM80-NEXT: .reg .b32 %r<9>;
+; CHECK-SM80-EMPTY:
+; CHECK-SM80-NEXT: // %bb.0:
+; CHECK-SM80-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_or_i16_param_0];
+; CHECK-SM80-NEXT: or.b32 %r5, %r2, %r4;
+; CHECK-SM80-NEXT: or.b32 %r6, %r1, %r3;
+; CHECK-SM80-NEXT: or.b32 %r7, %r6, %r5;
+; CHECK-SM80-NEXT: mov.b32 {%rs1, %rs2}, %r7;
+; CHECK-SM80-NEXT: or.b16 %rs3, %rs1, %rs2;
+; CHECK-SM80-NEXT: cvt.u32.u16 %r8, %rs3;
+; CHECK-SM80-NEXT: st.param.b32 [func_retval0], %r8;
+; CHECK-SM80-NEXT: ret;
+;
+; CHECK-SM100-LABEL: reduce_or_i16(
+; CHECK-SM100: {
+; CHECK-SM100-NEXT: .reg .b16 %rs<4>;
+; CHECK-SM100-NEXT: .reg .b32 %r<9>;
+; CHECK-SM100-EMPTY:
+; CHECK-SM100-NEXT: // %bb.0:
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_or_i16_param_0];
+; CHECK-SM100-NEXT: or.b32 %r5, %r2, %r4;
+; CHECK-SM100-NEXT: or.b32 %r6, %r1, %r3;
+; CHECK-SM100-NEXT: or.b32 %r7, %r6, %r5;
+; CHECK-SM100-NEXT: mov.b32 {%rs1, %rs2}, %r7;
+; CHECK-SM100-NEXT: or.b16 %rs3, %rs1, %rs2;
+; CHECK-SM100-NEXT: cvt.u32.u16 %r8, %rs3;
+; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r8;
+; CHECK-SM100-NEXT: ret;
%res = call i16 @llvm.vector.reduce.or(<8 x i16> %in)
ret i16 %res
}
define i16 @reduce_or_i16_nonpow2(<7 x i16> %in) {
-; CHECK-LABEL: reduce_or_i16_nonpow2(
-; CHECK: {
-; CHECK-NEXT: .reg .b16 %rs<12>;
-; CHECK-NEXT: .reg .b32 %r<9>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [reduce_or_i16_nonpow2_param_0+8];
-; CHECK-NEXT: mov.b32 {%rs5, %rs6}, %r1;
-; CHECK-NEXT: ld.param.v2.b32 {%r2, %r3}, [reduce_or_i16_nonpow2_param_0];
-; CHECK-NEXT: mov.b32 {%rs3, %rs4}, %r3;
-; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r2;
-; CHECK-NEXT: ld.param.b16 %rs7, [reduce_or_i16_nonpow2_param_0+12];
-; CHECK-NEXT: or.b32 %r4, %r2, %r1;
-; CHECK-NEXT: mov.b16 %rs8, 0;
-; CHECK-NEXT: mov.b32 %r5, {%rs7, %rs8};
-; CHECK-NEXT: or.b32 %r6, %r3, %r5;
-; CHECK-NEXT: or.b32 %r7, %r4, %r6;
-; CHECK-NEXT: mov.b32 {%rs9, %rs10}, %r7;
-; CHECK-NEXT: or.b16 %rs11, %rs9, %rs10;
-; CHECK-NEXT: cvt.u32.u16 %r8, %rs11;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r8;
-; CHECK-NEXT: ret;
+; CHECK-SM80-LABEL: reduce_or_i16_nonpow2(
+; CHECK-SM80: {
+; CHECK-SM80-NEXT: .reg .b16 %rs<12>;
+; CHECK-SM80-NEXT: .reg .b32 %r<9>;
+; CHECK-SM80-EMPTY:
+; CHECK-SM80-NEXT: // %bb.0:
+; CHECK-SM80-NEXT: ld.param.b32 %r1, [reduce_or_i16_nonpow2_param_0+8];
+; CHECK-SM80-NEXT: mov.b32 {%rs5, %rs6}, %r1;
+; CHECK-SM80-NEXT: ld.param.v2.b32 {%r2, %r3}, [reduce_or_i16_nonpow2_param_0];
+; CHECK-SM80-NEXT: mov.b32 {%rs3, %rs4}, %r3;
+; CHECK-SM80-NEXT: mov.b32 {%rs1, %rs2}, %r2;
+; CHECK-SM80-NEXT: ld.param.b16 %rs7, [reduce_or_i16_nonpow2_param_0+12];
+; CHECK-SM80-NEXT: or.b32 %r4, %r2, %r1;
+; CHECK-SM80-NEXT: mov.b16 %rs8, 0;
+; CHECK-SM80-NEXT: mov.b32 %r5, {%rs7, %rs8};
+; CHECK-SM80-NEXT: or.b32 %r6, %r3, %r5;
+; CHECK-SM80-NEXT: or.b32 %r7, %r4, %r6;
+; CHECK-SM80-NEXT: mov.b32 {%rs9, %rs10}, %r7;
+; CHECK-SM80-NEXT: or.b16 %rs11, %rs9, %rs10;
+; CHECK-SM80-NEXT: cvt.u32.u16 %r8, %rs11;
+; CHECK-SM80-NEXT: st.param.b32 [func_retval0], %r8;
+; CHECK-SM80-NEXT: ret;
+;
+; CHECK-SM100-LABEL: reduce_or_i16_nonpow2(
+; CHECK-SM100: {
+; CHECK-SM100-NEXT: .reg .b16 %rs<12>;
+; CHECK-SM100-NEXT: .reg .b32 %r<9>;
+; CHECK-SM100-EMPTY:
+; CHECK-SM100-NEXT: // %bb.0:
+; CHECK-SM100-NEXT: ld.param::func.b32 %r1, [reduce_or_i16_nonpow2_param_0+8];
+; CHECK-SM100-NEXT: mov.b32 {%rs5, %rs6}, %r1;
+; CHECK-SM100-NEXT: ld.param::func.v2.b32 {%r2, %r3}, [reduce_or_i16_nonpow2_param_0];
+; CHECK-SM100-NEXT: mov.b32 {%rs3, %rs4}, %r3;
+; CHECK-SM100-NEXT: mov.b32 {%rs1, %rs2}, %r2;
+; CHECK-SM100-NEXT: ld.param::func.b16 %rs7, [reduce_or_i16_nonpow2_param_0+12];
+; CHECK-SM100-NEXT: or.b32 %r4, %r2, %r1;
+; CHECK-SM100-NEXT: mov.b16 %rs8, 0;
+; CHECK-SM100-NEXT: mov.b32 %r5, {%rs7, %rs8};
+; CHECK-SM100-NEXT: or.b32 %r6, %r3, %r5;
+; CHECK-SM100-NEXT: or.b32 %r7, %r4, %r6;
+; CHECK-SM100-NEXT: mov.b32 {%rs9, %rs10}, %r7;
+; CHECK-SM100-NEXT: or.b16 %rs11, %rs9, %rs10;
+; CHECK-SM100-NEXT: cvt.u32.u16 %r8, %rs11;
+; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r8;
+; CHECK-SM100-NEXT: ret;
%res = call i16 @llvm.vector.reduce.or(<7 x i16> %in)
ret i16 %res
}
@@ -2418,8 +3055,8 @@ define i32 @reduce_or_i32(<8 x i32> %in) {
; CHECK-SM100-NEXT: .reg .b64 %rd<5>;
; CHECK-SM100-EMPTY:
; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param.v2.b64 {%rd3, %rd4}, [reduce_or_i32_param_0+16];
-; CHECK-SM100-NEXT: ld.param.v2.b64 {%rd1, %rd2}, [reduce_or_i32_param_0];
+; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd3, %rd4}, [reduce_or_i32_param_0+16];
+; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd1, %rd2}, [reduce_or_i32_param_0];
; CHECK-SM100-NEXT: mov.b64 {%r1, %r2}, %rd4;
; CHECK-SM100-NEXT: mov.b64 {%r3, %r4}, %rd2;
; CHECK-SM100-NEXT: or.b32 %r5, %r4, %r2;
@@ -2431,76 +3068,132 @@ define i32 @reduce_or_i32(<8 x i32> %in) {
; CHECK-SM100-NEXT: or.b32 %r13, %r8, %r6;
; CHECK-SM100-NEXT: or.b32 %r14, %r13, %r12;
; CHECK-SM100-NEXT: or.b32 %r15, %r14, %r11;
-; CHECK-SM100-NEXT: st.param.b32 [func_retval0], %r15;
+; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r15;
; CHECK-SM100-NEXT: ret;
%res = call i32 @llvm.vector.reduce.or(<8 x i32> %in)
ret i32 %res
}
define i32 @reduce_or_i32_nonpow2(<7 x i32> %in) {
-; CHECK-LABEL: reduce_or_i32_nonpow2(
-; CHECK: {
-; CHECK-NEXT: .reg .b32 %r<14>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r7, [reduce_or_i32_nonpow2_param_0+24];
-; CHECK-NEXT: ld.param.v2.b32 {%r5, %r6}, [reduce_or_i32_nonpow2_param_0+16];
-; CHECK-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_or_i32_nonpow2_param_0];
-; CHECK-NEXT: or.b32 %r8, %r3, %r7;
-; CHECK-NEXT: or.b32 %r9, %r1, %r5;
-; CHECK-NEXT: or.b32 %r10, %r9, %r8;
-; CHECK-NEXT: or.b32 %r11, %r2, %r6;
-; CHECK-NEXT: or.b32 %r12, %r11, %r4;
-; CHECK-NEXT: or.b32 %r13, %r10, %r12;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r13;
-; CHECK-NEXT: ret;
+; CHECK-SM80-LABEL: reduce_or_i32_nonpow2(
+; CHECK-SM80: {
+; CHECK-SM80-NEXT: .reg .b32 %r<14>;
+; CHECK-SM80-EMPTY:
+; CHECK-SM80-NEXT: // %bb.0:
+; CHECK-SM80-NEXT: ld.param.b32 %r7, [reduce_or_i32_nonpow2_param_0+24];
+; CHECK-SM80-NEXT: ld.param.v2.b32 {%r5, %r6}, [reduce_or_i32_nonpow2_param_0+16];
+; CHECK-SM80-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_or_i32_nonpow2_param_0];
+; CHECK-SM80-NEXT: or.b32 %r8, %r3, %r7;
+; CHECK-SM80-NEXT: or.b32 %r9, %r1, %r5;
+; CHECK-SM80-NEXT: or.b32 %r10, %r9, %r8;
+; CHECK-SM80-NEXT: or.b32 %r11, %r2, %r6;
+; CHECK-SM80-NEXT: or.b32 %r12, %r11, %r4;
+; CHECK-SM80-NEXT: or.b32 %r13, %r10, %r12;
+; CHECK-SM80-NEXT: st.param.b32 [func_retval0], %r13;
+; CHECK-SM80-NEXT: ret;
+;
+; CHECK-SM100-LABEL: reduce_or_i32_nonpow2(
+; CHECK-SM100: {
+; CHECK-SM100-NEXT: .reg .b32 %r<14>;
+; CHECK-SM100-EMPTY:
+; CHECK-SM100-NEXT: // %bb.0:
+; CHECK-SM100-NEXT: ld.param::func.b32 %r7, [reduce_or_i32_nonpow2_param_0+24];
+; CHECK-SM100-NEXT: ld.param::func.v2.b32 {%r5, %r6}, [reduce_or_i32_nonpow2_param_0+16];
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_or_i32_nonpow2_param_0];
+; CHECK-SM100-NEXT: or.b32 %r8, %r3, %r7;
+; CHECK-SM100-NEXT: or.b32 %r9, %r1, %r5;
+; CHECK-SM100-NEXT: or.b32 %r10, %r9, %r8;
+; CHECK-SM100-NEXT: or.b32 %r11, %r2, %r6;
+; CHECK-SM100-NEXT: or.b32 %r12, %r11, %r4;
+; CHECK-SM100-NEXT: or.b32 %r13, %r10, %r12;
+; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r13;
+; CHECK-SM100-NEXT: ret;
%res = call i32 @llvm.vector.reduce.or(<7 x i32> %in)
ret i32 %res
}
define i16 @reduce_xor_i16(<8 x i16> %in) {
-; CHECK-LABEL: reduce_xor_i16(
-; CHECK: {
-; CHECK-NEXT: .reg .b16 %rs<4>;
-; CHECK-NEXT: .reg .b32 %r<9>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_xor_i16_param_0];
-; CHECK-NEXT: xor.b32 %r5, %r2, %r4;
-; CHECK-NEXT: xor.b32 %r6, %r1, %r3;
-; CHECK-NEXT: xor.b32 %r7, %r6, %r5;
-; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r7;
-; CHECK-NEXT: xor.b16 %rs3, %rs1, %rs2;
-; CHECK-NEXT: cvt.u32.u16 %r8, %rs3;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r8;
-; CHECK-NEXT: ret;
+; CHECK-SM80-LABEL: reduce_xor_i16(
+; CHECK-SM80: {
+; CHECK-SM80-NEXT: .reg .b16 %rs<4>;
+; CHECK-SM80-NEXT: .reg .b32 %r<9>;
+; CHECK-SM80-EMPTY:
+; CHECK-SM80-NEXT: // %bb.0:
+; CHECK-SM80-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_xor_i16_param_0];
+; CHECK-SM80-NEXT: xor.b32 %r5, %r2, %r4;
+; CHECK-SM80-NEXT: xor.b32 %r6, %r1, %r3;
+; CHECK-SM80-NEXT: xor.b32 %r7, %r6, %r5;
+; CHECK-SM80-NEXT: mov.b32 {%rs1, %rs2}, %r7;
+; CHECK-SM80-NEXT: xor.b16 %rs3, %rs1, %rs2;
+; CHECK-SM80-NEXT: cvt.u32.u16 %r8, %rs3;
+; CHECK-SM80-NEXT: st.param.b32 [func_retval0], %r8;
+; CHECK-SM80-NEXT: ret;
+;
+; CHECK-SM100-LABEL: reduce_xor_i16(
+; CHECK-SM100: {
+; CHECK-SM100-NEXT: .reg .b16 %rs<4>;
+; CHECK-SM100-NEXT: .reg .b32 %r<9>;
+; CHECK-SM100-EMPTY:
+; CHECK-SM100-NEXT: // %bb.0:
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_xor_i16_param_0];
+; CHECK-SM100-NEXT: xor.b32 %r5, %r2, %r4;
+; CHECK-SM100-NEXT: xor.b32 %r6, %r1, %r3;
+; CHECK-SM100-NEXT: xor.b32 %r7, %r6, %r5;
+; CHECK-SM100-NEXT: mov.b32 {%rs1, %rs2}, %r7;
+; CHECK-SM100-NEXT: xor.b16 %rs3, %rs1, %rs2;
+; CHECK-SM100-NEXT: cvt.u32.u16 %r8, %rs3;
+; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r8;
+; CHECK-SM100-NEXT: ret;
%res = call i16 @llvm.vector.reduce.xor(<8 x i16> %in)
ret i16 %res
}
define i16 @reduce_xor_i16_nonpow2(<7 x i16> %in) {
-; CHECK-LABEL: reduce_xor_i16_nonpow2(
-; CHECK: {
-; CHECK-NEXT: .reg .b16 %rs<12>;
-; CHECK-NEXT: .reg .b32 %r<9>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [reduce_xor_i16_nonpow2_param_0+8];
-; CHECK-NEXT: mov.b32 {%rs5, %rs6}, %r1;
-; CHECK-NEXT: ld.param.v2.b32 {%r2, %r3}, [reduce_xor_i16_nonpow2_param_0];
-; CHECK-NEXT: mov.b32 {%rs3, %rs4}, %r3;
-; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r2;
-; CHECK-NEXT: ld.param.b16 %rs7, [reduce_xor_i16_nonpow2_param_0+12];
-; CHECK-NEXT: xor.b32 %r4, %r2, %r1;
-; CHECK-NEXT: mov.b16 %rs8, 0;
-; CHECK-NEXT: mov.b32 %r5, {%rs7, %rs8};
-; CHECK-NEXT: xor.b32 %r6, %r3, %r5;
-; CHECK-NEXT: xor.b32 %r7, %r4, %r6;
-; CHECK-NEXT: mov.b32 {%rs9, %rs10}, %r7;
-; CHECK-NEXT: xor.b16 %rs11, %rs9, %rs10;
-; CHECK-NEXT: cvt.u32.u16 %r8, %rs11;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r8;
-; CHECK-NEXT: ret;
+; CHECK-SM80-LABEL: reduce_xor_i16_nonpow2(
+; CHECK-SM80: {
+; CHECK-SM80-NEXT: .reg .b16 %rs<12>;
+; CHECK-SM80-NEXT: .reg .b32 %r<9>;
+; CHECK-SM80-EMPTY:
+; CHECK-SM80-NEXT: // %bb.0:
+; CHECK-SM80-NEXT: ld.param.b32 %r1, [reduce_xor_i16_nonpow2_param_0+8];
+; CHECK-SM80-NEXT: mov.b32 {%rs5, %rs6}, %r1;
+; CHECK-SM80-NEXT: ld.param.v2.b32 {%r2, %r3}, [reduce_xor_i16_nonpow2_param_0];
+; CHECK-SM80-NEXT: mov.b32 {%rs3, %rs4}, %r3;
+; CHECK-SM80-NEXT: mov.b32 {%rs1, %rs2}, %r2;
+; CHECK-SM80-NEXT: ld.param.b16 %rs7, [reduce_xor_i16_nonpow2_param_0+12];
+; CHECK-SM80-NEXT: xor.b32 %r4, %r2, %r1;
+; CHECK-SM80-NEXT: mov.b16 %rs8, 0;
+; CHECK-SM80-NEXT: mov.b32 %r5, {%rs7, %rs8};
+; CHECK-SM80-NEXT: xor.b32 %r6, %r3, %r5;
+; CHECK-SM80-NEXT: xor.b32 %r7, %r4, %r6;
+; CHECK-SM80-NEXT: mov.b32 {%rs9, %rs10}, %r7;
+; CHECK-SM80-NEXT: xor.b16 %rs11, %rs9, %rs10;
+; CHECK-SM80-NEXT: cvt.u32.u16 %r8, %rs11;
+; CHECK-SM80-NEXT: st.param.b32 [func_retval0], %r8;
+; CHECK-SM80-NEXT: ret;
+;
+; CHECK-SM100-LABEL: reduce_xor_i16_nonpow2(
+; CHECK-SM100: {
+; CHECK-SM100-NEXT: .reg .b16 %rs<12>;
+; CHECK-SM100-NEXT: .reg .b32 %r<9>;
+; CHECK-SM100-EMPTY:
+; CHECK-SM100-NEXT: // %bb.0:
+; CHECK-SM100-NEXT: ld.param::func.b32 %r1, [reduce_xor_i16_nonpow2_param_0+8];
+; CHECK-SM100-NEXT: mov.b32 {%rs5, %rs6}, %r1;
+; CHECK-SM100-NEXT: ld.param::func.v2.b32 {%r2, %r3}, [reduce_xor_i16_nonpow2_param_0];
+; CHECK-SM100-NEXT: mov.b32 {%rs3, %rs4}, %r3;
+; CHECK-SM100-NEXT: mov.b32 {%rs1, %rs2}, %r2;
+; CHECK-SM100-NEXT: ld.param::func.b16 %rs7, [reduce_xor_i16_nonpow2_param_0+12];
+; CHECK-SM100-NEXT: xor.b32 %r4, %r2, %r1;
+; CHECK-SM100-NEXT: mov.b16 %rs8, 0;
+; CHECK-SM100-NEXT: mov.b32 %r5, {%rs7, %rs8};
+; CHECK-SM100-NEXT: xor.b32 %r6, %r3, %r5;
+; CHECK-SM100-NEXT: xor.b32 %r7, %r4, %r6;
+; CHECK-SM100-NEXT: mov.b32 {%rs9, %rs10}, %r7;
+; CHECK-SM100-NEXT: xor.b16 %rs11, %rs9, %rs10;
+; CHECK-SM100-NEXT: cvt.u32.u16 %r8, %rs11;
+; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r8;
+; CHECK-SM100-NEXT: ret;
%res = call i16 @llvm.vector.reduce.xor(<7 x i16> %in)
ret i16 %res
}
@@ -2529,8 +3222,8 @@ define i32 @reduce_xor_i32(<8 x i32> %in) {
; CHECK-SM100-NEXT: .reg .b64 %rd<5>;
; CHECK-SM100-EMPTY:
; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param.v2.b64 {%rd3, %rd4}, [reduce_xor_i32_param_0+16];
-; CHECK-SM100-NEXT: ld.param.v2.b64 {%rd1, %rd2}, [reduce_xor_i32_param_0];
+; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd3, %rd4}, [reduce_xor_i32_param_0+16];
+; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd1, %rd2}, [reduce_xor_i32_param_0];
; CHECK-SM100-NEXT: mov.b64 {%r1, %r2}, %rd4;
; CHECK-SM100-NEXT: mov.b64 {%r3, %r4}, %rd2;
; CHECK-SM100-NEXT: xor.b32 %r5, %r4, %r2;
@@ -2542,29 +3235,48 @@ define i32 @reduce_xor_i32(<8 x i32> %in) {
; CHECK-SM100-NEXT: xor.b32 %r13, %r8, %r6;
; CHECK-SM100-NEXT: xor.b32 %r14, %r13, %r12;
; CHECK-SM100-NEXT: xor.b32 %r15, %r14, %r11;
-; CHECK-SM100-NEXT: st.param.b32 [func_retval0], %r15;
+; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r15;
; CHECK-SM100-NEXT: ret;
%res = call i32 @llvm.vector.reduce.xor(<8 x i32> %in)
ret i32 %res
}
define i32 @reduce_xor_i32_nonpow2(<7 x i32> %in) {
-; CHECK-LABEL: reduce_xor_i32_nonpow2(
-; CHECK: {
-; CHECK-NEXT: .reg .b32 %r<14>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r7, [reduce_xor_i32_nonpow2_param_0+24];
-; CHECK-NEXT: ld.param.v2.b32 {%r5, %r6}, [reduce_xor_i32_nonpow2_param_0+16];
-; CHECK-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_xor_i32_nonpow2_param_0];
-; CHECK-NEXT: xor.b32 %r8, %r3, %r7;
-; CHECK-NEXT: xor.b32 %r9, %r1, %r5;
-; CHECK-NEXT: xor.b32 %r10, %r9, %r8;
-; CHECK-NEXT: xor.b32 %r11, %r2, %r6;
-; CHECK-NEXT: xor.b32 %r12, %r11, %r4;
-; CHECK-NEXT: xor.b32 %r13, %r10, %r12;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r13;
-; CHECK-NEXT: ret;
+; CHECK-SM80-LABEL: reduce_xor_i32_nonpow2(
+; CHECK-SM80: {
+; CHECK-SM80-NEXT: .reg .b32 %r<14>;
+; CHECK-SM80-EMPTY:
+; CHECK-SM80-NEXT: // %bb.0:
+; CHECK-SM80-NEXT: ld.param.b32 %r7, [reduce_xor_i32_nonpow2_param_0+24];
+; CHECK-SM80-NEXT: ld.param.v2.b32 {%r5, %r6}, [reduce_xor_i32_nonpow2_param_0+16];
+; CHECK-SM80-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_xor_i32_nonpow2_param_0];
+; CHECK-SM80-NEXT: xor.b32 %r8, %r3, %r7;
+; CHECK-SM80-NEXT: xor.b32 %r9, %r1, %r5;
+; CHECK-SM80-NEXT: xor.b32 %r10, %r9, %r8;
+; CHECK-SM80-NEXT: xor.b32 %r11, %r2, %r6;
+; CHECK-SM80-NEXT: xor.b32 %r12, %r11, %r4;
+; CHECK-SM80-NEXT: xor.b32 %r13, %r10, %r12;
+; CHECK-SM80-NEXT: st.param.b32 [func_retval0], %r13;
+; CHECK-SM80-NEXT: ret;
+;
+; CHECK-SM100-LABEL: reduce_xor_i32_nonpow2(
+; CHECK-SM100: {
+; CHECK-SM100-NEXT: .reg .b32 %r<14>;
+; CHECK-SM100-EMPTY:
+; CHECK-SM100-NEXT: // %bb.0:
+; CHECK-SM100-NEXT: ld.param::func.b32 %r7, [reduce_xor_i32_nonpow2_param_0+24];
+; CHECK-SM100-NEXT: ld.param::func.v2.b32 {%r5, %r6}, [reduce_xor_i32_nonpow2_param_0+16];
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_xor_i32_nonpow2_param_0];
+; CHECK-SM100-NEXT: xor.b32 %r8, %r3, %r7;
+; CHECK-SM100-NEXT: xor.b32 %r9, %r1, %r5;
+; CHECK-SM100-NEXT: xor.b32 %r10, %r9, %r8;
+; CHECK-SM100-NEXT: xor.b32 %r11, %r2, %r6;
+; CHECK-SM100-NEXT: xor.b32 %r12, %r11, %r4;
+; CHECK-SM100-NEXT: xor.b32 %r13, %r10, %r12;
+; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r13;
+; CHECK-SM100-NEXT: ret;
%res = call i32 @llvm.vector.reduce.xor(<7 x i32> %in)
ret i32 %res
}
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK: {{.*}}
diff --git a/llvm/test/CodeGen/NVPTX/redux-sync-f32.ll b/llvm/test/CodeGen/NVPTX/redux-sync-f32.ll
index ddbe49f0c20b3..13f5e76e9d2bd 100644
--- a/llvm/test/CodeGen/NVPTX/redux-sync-f32.ll
+++ b/llvm/test/CodeGen/NVPTX/redux-sync-f32.ll
@@ -11,10 +11,10 @@ define float @redux_sync_fmin(float %src, i32 %mask) {
; CHECK-NEXT: .reg .b32 %r<4>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [redux_sync_fmin_param_0];
-; CHECK-NEXT: ld.param.b32 %r2, [redux_sync_fmin_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r1, [redux_sync_fmin_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r2, [redux_sync_fmin_param_1];
; CHECK-NEXT: redux.sync.min.f32 %r3, %r1, %r2;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r3;
; CHECK-NEXT: ret;
%val = call float @llvm.nvvm.redux.sync.fmin(float %src, i32 %mask)
ret float %val
@@ -27,10 +27,10 @@ define float @redux_sync_fmin_abs(float %src, i32 %mask) {
; CHECK-NEXT: .reg .b32 %r<4>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [redux_sync_fmin_abs_param_0];
-; CHECK-NEXT: ld.param.b32 %r2, [redux_sync_fmin_abs_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r1, [redux_sync_fmin_abs_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r2, [redux_sync_fmin_abs_param_1];
; CHECK-NEXT: redux.sync.min.abs.f32 %r3, %r1, %r2;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r3;
; CHECK-NEXT: ret;
%val = call float @llvm.nvvm.redux.sync.fmin.abs(float %src, i32 %mask)
ret float %val
@@ -43,10 +43,10 @@ define float @redux_sync_fmin_NaN(float %src, i32 %mask) {
; CHECK-NEXT: .reg .b32 %r<4>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [redux_sync_fmin_NaN_param_0];
-; CHECK-NEXT: ld.param.b32 %r2, [redux_sync_fmin_NaN_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r1, [redux_sync_fmin_NaN_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r2, [redux_sync_fmin_NaN_param_1];
; CHECK-NEXT: redux.sync.min.NaN.f32 %r3, %r1, %r2;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r3;
; CHECK-NEXT: ret;
%val = call float @llvm.nvvm.redux.sync.fmin.NaN(float %src, i32 %mask)
ret float %val
@@ -59,10 +59,10 @@ define float @redux_sync_fmin_abs_NaN(float %src, i32 %mask) {
; CHECK-NEXT: .reg .b32 %r<4>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [redux_sync_fmin_abs_NaN_param_0];
-; CHECK-NEXT: ld.param.b32 %r2, [redux_sync_fmin_abs_NaN_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r1, [redux_sync_fmin_abs_NaN_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r2, [redux_sync_fmin_abs_NaN_param_1];
; CHECK-NEXT: redux.sync.min.abs.NaN.f32 %r3, %r1, %r2;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r3;
; CHECK-NEXT: ret;
%val = call float @llvm.nvvm.redux.sync.fmin.abs.NaN(float %src, i32 %mask)
ret float %val
@@ -75,10 +75,10 @@ define float @redux_sync_fmax(float %src, i32 %mask) {
; CHECK-NEXT: .reg .b32 %r<4>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [redux_sync_fmax_param_0];
-; CHECK-NEXT: ld.param.b32 %r2, [redux_sync_fmax_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r1, [redux_sync_fmax_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r2, [redux_sync_fmax_param_1];
; CHECK-NEXT: redux.sync.max.f32 %r3, %r1, %r2;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r3;
; CHECK-NEXT: ret;
%val = call float @llvm.nvvm.redux.sync.fmax(float %src, i32 %mask)
ret float %val
@@ -91,10 +91,10 @@ define float @redux_sync_fmax_abs(float %src, i32 %mask) {
; CHECK-NEXT: .reg .b32 %r<4>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [redux_sync_fmax_abs_param_0];
-; CHECK-NEXT: ld.param.b32 %r2, [redux_sync_fmax_abs_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r1, [redux_sync_fmax_abs_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r2, [redux_sync_fmax_abs_param_1];
; CHECK-NEXT: redux.sync.max.abs.f32 %r3, %r1, %r2;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r3;
; CHECK-NEXT: ret;
%val = call float @llvm.nvvm.redux.sync.fmax.abs(float %src, i32 %mask)
ret float %val
@@ -107,10 +107,10 @@ define float @redux_sync_fmax_NaN(float %src, i32 %mask) {
; CHECK-NEXT: .reg .b32 %r<4>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [redux_sync_fmax_NaN_param_0];
-; CHECK-NEXT: ld.param.b32 %r2, [redux_sync_fmax_NaN_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r1, [redux_sync_fmax_NaN_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r2, [redux_sync_fmax_NaN_param_1];
; CHECK-NEXT: redux.sync.max.NaN.f32 %r3, %r1, %r2;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r3;
; CHECK-NEXT: ret;
%val = call float @llvm.nvvm.redux.sync.fmax.NaN(float %src, i32 %mask)
ret float %val
@@ -123,10 +123,10 @@ define float @redux_sync_fmax_abs_NaN(float %src, i32 %mask) {
; CHECK-NEXT: .reg .b32 %r<4>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [redux_sync_fmax_abs_NaN_param_0];
-; CHECK-NEXT: ld.param.b32 %r2, [redux_sync_fmax_abs_NaN_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r1, [redux_sync_fmax_abs_NaN_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r2, [redux_sync_fmax_abs_NaN_param_1];
; CHECK-NEXT: redux.sync.max.abs.NaN.f32 %r3, %r1, %r2;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r3;
; CHECK-NEXT: ret;
%val = call float @llvm.nvvm.redux.sync.fmax.abs.NaN(float %src, i32 %mask)
ret float %val
diff --git a/llvm/test/CodeGen/NVPTX/scalarize-non-coalescable-v2f32.ll b/llvm/test/CodeGen/NVPTX/scalarize-non-coalescable-v2f32.ll
index f953b865a004e..53f3984157fe4 100644
--- a/llvm/test/CodeGen/NVPTX/scalarize-non-coalescable-v2f32.ll
+++ b/llvm/test/CodeGen/NVPTX/scalarize-non-coalescable-v2f32.ll
@@ -11,13 +11,13 @@ define <2 x float> @fma_non_coalescable(ptr addrspace(3) %p, <2 x float> %a, <2
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [fma_non_coalescable_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [fma_non_coalescable_param_0];
; CHECK-NEXT: ld.shared.v4.b32 {%r1, %r2, %r3, %r4}, [%rd1];
-; CHECK-NEXT: ld.param.v2.b32 {%r5, %r6}, [fma_non_coalescable_param_1];
-; CHECK-NEXT: ld.param.v2.b32 {%r7, %r8}, [fma_non_coalescable_param_2];
+; CHECK-NEXT: ld.param::func.v2.b32 {%r5, %r6}, [fma_non_coalescable_param_1];
+; CHECK-NEXT: ld.param::func.v2.b32 {%r7, %r8}, [fma_non_coalescable_param_2];
; CHECK-NEXT: fma.rn.f32 %r9, %r6, %r3, %r8;
; CHECK-NEXT: fma.rn.f32 %r10, %r5, %r1, %r7;
-; CHECK-NEXT: st.param.v2.b32 [func_retval0], {%r10, %r9};
+; CHECK-NEXT: st.param::func.v2.b32 [func_retval0], {%r10, %r9};
; CHECK-NEXT: ret;
%ld = load <4 x float>, ptr addrspace(3) %p, align 16
%e0 = extractelement <4 x float> %ld, i32 0
@@ -41,22 +41,22 @@ define <2 x float> @fma_constant_and_dynamic_index(i32 %idx, ptr addrspace(3) %p
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: mov.b64 %SPL, __local_depot1;
; CHECK-NEXT: cvta.local.u64 %SP, %SPL;
-; CHECK-NEXT: ld.param.b32 %rd1, [fma_constant_and_dynamic_index_param_0];
+; CHECK-NEXT: ld.param::func.b32 %rd1, [fma_constant_and_dynamic_index_param_0];
; CHECK-NEXT: and.b64 %rd2, %rd1, 3;
; CHECK-NEXT: shl.b64 %rd3, %rd2, 2;
; CHECK-NEXT: add.u64 %rd4, %SP, 0;
; CHECK-NEXT: add.s64 %rd5, %rd4, %rd3;
-; CHECK-NEXT: ld.param.b64 %rd6, [fma_constant_and_dynamic_index_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd6, [fma_constant_and_dynamic_index_param_1];
; CHECK-NEXT: ld.shared.v2.b64 {%rd7, %rd8}, [%rd6];
; CHECK-NEXT: mov.b64 {%r1, _}, %rd7;
-; CHECK-NEXT: ld.param.v2.b32 {%r2, %r3}, [fma_constant_and_dynamic_index_param_2];
+; CHECK-NEXT: ld.param::func.v2.b32 {%r2, %r3}, [fma_constant_and_dynamic_index_param_2];
; CHECK-NEXT: st.b64 [%SP+8], %rd8;
; CHECK-NEXT: st.b64 [%SP], %rd7;
; CHECK-NEXT: ld.b32 %r4, [%rd5];
-; CHECK-NEXT: ld.param.v2.b32 {%r5, %r6}, [fma_constant_and_dynamic_index_param_3];
+; CHECK-NEXT: ld.param::func.v2.b32 {%r5, %r6}, [fma_constant_and_dynamic_index_param_3];
; CHECK-NEXT: fma.rn.f32 %r7, %r2, %r1, %r5;
; CHECK-NEXT: fma.rn.f32 %r8, %r3, %r4, %r6;
-; CHECK-NEXT: st.param.v2.b32 [func_retval0], {%r7, %r8};
+; CHECK-NEXT: st.param::func.v2.b32 [func_retval0], {%r7, %r8};
; CHECK-NEXT: ret;
%ld = load <4 x float>, ptr addrspace(3) %p, align 16
%e0 = extractelement <4 x float> %ld, i32 0
@@ -75,13 +75,13 @@ define <2 x float> @fma_shufflevector_non_coalescable(ptr addrspace(3) %p, <2 x
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [fma_shufflevector_non_coalescable_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [fma_shufflevector_non_coalescable_param_0];
; CHECK-NEXT: ld.shared.v4.b32 {%r1, %r2, %r3, %r4}, [%rd1];
-; CHECK-NEXT: ld.param.v2.b32 {%r5, %r6}, [fma_shufflevector_non_coalescable_param_1];
-; CHECK-NEXT: ld.param.v2.b32 {%r7, %r8}, [fma_shufflevector_non_coalescable_param_2];
+; CHECK-NEXT: ld.param::func.v2.b32 {%r5, %r6}, [fma_shufflevector_non_coalescable_param_1];
+; CHECK-NEXT: ld.param::func.v2.b32 {%r7, %r8}, [fma_shufflevector_non_coalescable_param_2];
; CHECK-NEXT: fma.rn.f32 %r9, %r6, %r3, %r8;
; CHECK-NEXT: fma.rn.f32 %r10, %r5, %r1, %r7;
-; CHECK-NEXT: st.param.v2.b32 [func_retval0], {%r10, %r9};
+; CHECK-NEXT: st.param::func.v2.b32 [func_retval0], {%r10, %r9};
; CHECK-NEXT: ret;
%ld = load <4 x float>, ptr addrspace(3) %p, align 16
%bv = shufflevector <4 x float> %ld, <4 x float> poison, <2 x i32> <i32 0, i32 2>
@@ -97,14 +97,14 @@ define <2 x float> @fma_mixed_extract_and_scalar(ptr addrspace(3) %p, float %s,
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [fma_mixed_extract_and_scalar_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [fma_mixed_extract_and_scalar_param_0];
; CHECK-NEXT: ld.shared.v4.b32 {%r1, %r2, %r3, %r4}, [%rd1];
-; CHECK-NEXT: ld.param.b32 %r5, [fma_mixed_extract_and_scalar_param_1];
-; CHECK-NEXT: ld.param.v2.b32 {%r6, %r7}, [fma_mixed_extract_and_scalar_param_2];
-; CHECK-NEXT: ld.param.v2.b32 {%r8, %r9}, [fma_mixed_extract_and_scalar_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r5, [fma_mixed_extract_and_scalar_param_1];
+; CHECK-NEXT: ld.param::func.v2.b32 {%r6, %r7}, [fma_mixed_extract_and_scalar_param_2];
+; CHECK-NEXT: ld.param::func.v2.b32 {%r8, %r9}, [fma_mixed_extract_and_scalar_param_3];
; CHECK-NEXT: fma.rn.f32 %r10, %r7, %r5, %r9;
; CHECK-NEXT: fma.rn.f32 %r11, %r6, %r3, %r8;
-; CHECK-NEXT: st.param.v2.b32 [func_retval0], {%r11, %r10};
+; CHECK-NEXT: st.param::func.v2.b32 [func_retval0], {%r11, %r10};
; CHECK-NEXT: ret;
%ld = load <4 x float>, ptr addrspace(3) %p, align 16
%e2 = extractelement <4 x float> %ld, i32 2
@@ -122,12 +122,12 @@ define <2 x float> @fadd_non_coalescable(ptr addrspace(3) %p, <2 x float> %a) {
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [fadd_non_coalescable_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [fadd_non_coalescable_param_0];
; CHECK-NEXT: ld.shared.v4.b32 {%r1, %r2, %r3, %r4}, [%rd1];
-; CHECK-NEXT: ld.param.v2.b32 {%r5, %r6}, [fadd_non_coalescable_param_1];
+; CHECK-NEXT: ld.param::func.v2.b32 {%r5, %r6}, [fadd_non_coalescable_param_1];
; CHECK-NEXT: add.f32 %r7, %r6, %r3;
; CHECK-NEXT: add.f32 %r8, %r5, %r1;
-; CHECK-NEXT: st.param.v2.b32 [func_retval0], {%r8, %r7};
+; CHECK-NEXT: st.param::func.v2.b32 [func_retval0], {%r8, %r7};
; CHECK-NEXT: ret;
%ld = load <4 x float>, ptr addrspace(3) %p, align 16
%e0 = extractelement <4 x float> %ld, i32 0
@@ -145,12 +145,12 @@ define <2 x float> @fmul_non_coalescable(ptr addrspace(3) %p, <2 x float> %a) {
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [fmul_non_coalescable_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [fmul_non_coalescable_param_0];
; CHECK-NEXT: ld.shared.v4.b32 {%r1, %r2, %r3, %r4}, [%rd1];
-; CHECK-NEXT: ld.param.v2.b32 {%r5, %r6}, [fmul_non_coalescable_param_1];
+; CHECK-NEXT: ld.param::func.v2.b32 {%r5, %r6}, [fmul_non_coalescable_param_1];
; CHECK-NEXT: mul.f32 %r7, %r6, %r3;
; CHECK-NEXT: mul.f32 %r8, %r5, %r1;
-; CHECK-NEXT: st.param.v2.b32 [func_retval0], {%r8, %r7};
+; CHECK-NEXT: st.param::func.v2.b32 [func_retval0], {%r8, %r7};
; CHECK-NEXT: ret;
%ld = load <4 x float>, ptr addrspace(3) %p, align 16
%e0 = extractelement <4 x float> %ld, i32 0
@@ -168,12 +168,12 @@ define <2 x float> @fsub_non_coalescable(ptr addrspace(3) %p, <2 x float> %a) {
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [fsub_non_coalescable_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [fsub_non_coalescable_param_0];
; CHECK-NEXT: ld.shared.v4.b32 {%r1, %r2, %r3, %r4}, [%rd1];
-; CHECK-NEXT: ld.param.v2.b32 {%r5, %r6}, [fsub_non_coalescable_param_1];
+; CHECK-NEXT: ld.param::func.v2.b32 {%r5, %r6}, [fsub_non_coalescable_param_1];
; CHECK-NEXT: sub.f32 %r7, %r6, %r3;
; CHECK-NEXT: sub.f32 %r8, %r5, %r1;
-; CHECK-NEXT: st.param.v2.b32 [func_retval0], {%r8, %r7};
+; CHECK-NEXT: st.param::func.v2.b32 [func_retval0], {%r8, %r7};
; CHECK-NEXT: ret;
%ld = load <4 x float>, ptr addrspace(3) %p, align 16
%e0 = extractelement <4 x float> %ld, i32 0
@@ -191,13 +191,13 @@ define <4 x float> @fma_adjacent_elements(ptr addrspace(3) %p, <2 x float> %a, <
; CHECK-NEXT: .reg .b64 %rd<8>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [fma_adjacent_elements_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [fma_adjacent_elements_param_0];
; CHECK-NEXT: ld.shared.v2.b64 {%rd2, %rd3}, [%rd1];
-; CHECK-NEXT: ld.param.b64 %rd4, [fma_adjacent_elements_param_1];
-; CHECK-NEXT: ld.param.b64 %rd5, [fma_adjacent_elements_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd4, [fma_adjacent_elements_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd5, [fma_adjacent_elements_param_2];
; CHECK-NEXT: fma.rn.f32x2 %rd6, %rd4, %rd2, %rd5;
; CHECK-NEXT: fma.rn.f32x2 %rd7, %rd4, %rd3, %rd5;
-; CHECK-NEXT: st.param.v2.b64 [func_retval0], {%rd6, %rd7};
+; CHECK-NEXT: st.param::func.v2.b64 [func_retval0], {%rd6, %rd7};
; CHECK-NEXT: ret;
%ld = load <4 x float>, ptr addrspace(3) %p, align 16
%e0 = extractelement <4 x float> %ld, i32 0
@@ -223,15 +223,15 @@ define <4 x float> @fma_adjacent_swapped_elements(ptr addrspace(3) %p, <2 x floa
; CHECK-NEXT: .reg .b64 %rd<8>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [fma_adjacent_swapped_elements_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [fma_adjacent_swapped_elements_param_0];
; CHECK-NEXT: ld.shared.v4.b32 {%r1, %r2, %r3, %r4}, [%rd1];
-; CHECK-NEXT: ld.param.b64 %rd2, [fma_adjacent_swapped_elements_param_1];
-; CHECK-NEXT: ld.param.b64 %rd3, [fma_adjacent_swapped_elements_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [fma_adjacent_swapped_elements_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd3, [fma_adjacent_swapped_elements_param_2];
; CHECK-NEXT: mov.b64 %rd4, {%r2, %r1};
; CHECK-NEXT: mov.b64 %rd5, {%r4, %r3};
; CHECK-NEXT: fma.rn.f32x2 %rd6, %rd2, %rd4, %rd3;
; CHECK-NEXT: fma.rn.f32x2 %rd7, %rd2, %rd5, %rd3;
-; CHECK-NEXT: st.param.v2.b64 [func_retval0], {%rd6, %rd7};
+; CHECK-NEXT: st.param::func.v2.b64 [func_retval0], {%rd6, %rd7};
; CHECK-NEXT: ret;
%ld = load <4 x float>, ptr addrspace(3) %p, align 16
%e0 = extractelement <4 x float> %ld, i32 0
@@ -262,17 +262,17 @@ define <2 x float> @fma_both_dynamic_indices(i32 %i0, i32 %i1, ptr addrspace(3)
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: mov.b64 %SPL, __local_depot9;
; CHECK-NEXT: cvta.local.u64 %SP, %SPL;
-; CHECK-NEXT: ld.param.b32 %rd1, [fma_both_dynamic_indices_param_0];
+; CHECK-NEXT: ld.param::func.b32 %rd1, [fma_both_dynamic_indices_param_0];
; CHECK-NEXT: and.b64 %rd2, %rd1, 3;
; CHECK-NEXT: shl.b64 %rd3, %rd2, 2;
; CHECK-NEXT: add.u64 %rd4, %SP, 16;
; CHECK-NEXT: add.s64 %rd5, %rd4, %rd3;
-; CHECK-NEXT: ld.param.b32 %rd6, [fma_both_dynamic_indices_param_1];
+; CHECK-NEXT: ld.param::func.b32 %rd6, [fma_both_dynamic_indices_param_1];
; CHECK-NEXT: and.b64 %rd7, %rd6, 3;
; CHECK-NEXT: shl.b64 %rd8, %rd7, 2;
; CHECK-NEXT: add.u64 %rd9, %SP, 0;
; CHECK-NEXT: add.s64 %rd10, %rd9, %rd8;
-; CHECK-NEXT: ld.param.b64 %rd11, [fma_both_dynamic_indices_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd11, [fma_both_dynamic_indices_param_2];
; CHECK-NEXT: ld.shared.v2.b64 {%rd12, %rd13}, [%rd11];
; CHECK-NEXT: st.b64 [%SP+24], %rd13;
; CHECK-NEXT: st.b64 [%SP+16], %rd12;
@@ -280,11 +280,11 @@ define <2 x float> @fma_both_dynamic_indices(i32 %i0, i32 %i1, ptr addrspace(3)
; CHECK-NEXT: st.b64 [%SP+8], %rd13;
; CHECK-NEXT: st.b64 [%SP], %rd12;
; CHECK-NEXT: ld.b32 %r2, [%rd10];
-; CHECK-NEXT: ld.param.b64 %rd14, [fma_both_dynamic_indices_param_3];
-; CHECK-NEXT: ld.param.b64 %rd15, [fma_both_dynamic_indices_param_4];
+; CHECK-NEXT: ld.param::func.b64 %rd14, [fma_both_dynamic_indices_param_3];
+; CHECK-NEXT: ld.param::func.b64 %rd15, [fma_both_dynamic_indices_param_4];
; CHECK-NEXT: mov.b64 %rd16, {%r1, %r2};
; CHECK-NEXT: fma.rn.f32x2 %rd17, %rd14, %rd16, %rd15;
-; CHECK-NEXT: st.param.b64 [func_retval0], %rd17;
+; CHECK-NEXT: st.param::func.b64 [func_retval0], %rd17;
; CHECK-NEXT: ret;
%ld = load <4 x float>, ptr addrspace(3) %p, align 16
%e0 = extractelement <4 x float> %ld, i32 %i0
@@ -302,12 +302,12 @@ define <2 x float> @fma_shufflevector_adjacent_elements(ptr addrspace(3) %p, <2
; CHECK-NEXT: .reg .b64 %rd<6>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [fma_shufflevector_adjacent_elements_param_0];
-; CHECK-NEXT: ld.param.b64 %rd2, [fma_shufflevector_adjacent_elements_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [fma_shufflevector_adjacent_elements_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [fma_shufflevector_adjacent_elements_param_1];
; CHECK-NEXT: ld.shared.b64 %rd3, [%rd1];
-; CHECK-NEXT: ld.param.b64 %rd4, [fma_shufflevector_adjacent_elements_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd4, [fma_shufflevector_adjacent_elements_param_2];
; CHECK-NEXT: fma.rn.f32x2 %rd5, %rd2, %rd3, %rd4;
-; CHECK-NEXT: st.param.b64 [func_retval0], %rd5;
+; CHECK-NEXT: st.param::func.b64 [func_retval0], %rd5;
; CHECK-NEXT: ret;
%ld = load <4 x float>, ptr addrspace(3) %p, align 16
%bv = shufflevector <4 x float> %ld, <4 x float> poison, <2 x i32> <i32 0, i32 1>
@@ -322,11 +322,11 @@ define <2 x float> @fma_naturally_paired(<2 x float> %a, <2 x float> %b, <2 x fl
; CHECK-NEXT: .reg .b64 %rd<5>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [fma_naturally_paired_param_0];
-; CHECK-NEXT: ld.param.b64 %rd2, [fma_naturally_paired_param_1];
-; CHECK-NEXT: ld.param.b64 %rd3, [fma_naturally_paired_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [fma_naturally_paired_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [fma_naturally_paired_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd3, [fma_naturally_paired_param_2];
; CHECK-NEXT: fma.rn.f32x2 %rd4, %rd1, %rd2, %rd3;
-; CHECK-NEXT: st.param.b64 [func_retval0], %rd4;
+; CHECK-NEXT: st.param::func.b64 [func_retval0], %rd4;
; CHECK-NEXT: ret;
%mul = fmul <2 x float> %a, %b
%res = fadd <2 x float> %mul, %c
@@ -340,13 +340,13 @@ define <2 x float> @fma_coalescable_scalars(float %x, float %y, <2 x float> %b,
; CHECK-NEXT: .reg .b64 %rd<5>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [fma_coalescable_scalars_param_0];
-; CHECK-NEXT: ld.param.b32 %r2, [fma_coalescable_scalars_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r1, [fma_coalescable_scalars_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r2, [fma_coalescable_scalars_param_1];
; CHECK-NEXT: mov.b64 %rd1, {%r1, %r2};
-; CHECK-NEXT: ld.param.b64 %rd2, [fma_coalescable_scalars_param_2];
-; CHECK-NEXT: ld.param.b64 %rd3, [fma_coalescable_scalars_param_3];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [fma_coalescable_scalars_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd3, [fma_coalescable_scalars_param_3];
; CHECK-NEXT: fma.rn.f32x2 %rd4, %rd1, %rd2, %rd3;
-; CHECK-NEXT: st.param.b64 [func_retval0], %rd4;
+; CHECK-NEXT: st.param::func.b64 [func_retval0], %rd4;
; CHECK-NEXT: ret;
%v0 = insertelement <2 x float> poison, float %x, i32 0
%v = insertelement <2 x float> %v0, float %y, i32 1
diff --git a/llvm/test/CodeGen/NVPTX/st_async_mbarrier_b128.ll b/llvm/test/CodeGen/NVPTX/st_async_mbarrier_b128.ll
index 8b1fff1b17263..bf213f34a9d9c 100644
--- a/llvm/test/CodeGen/NVPTX/st_async_mbarrier_b128.ll
+++ b/llvm/test/CodeGen/NVPTX/st_async_mbarrier_b128.ll
@@ -10,9 +10,9 @@ define void @test_st_async_mbarrier_b128(ptr addrspace(7) %addr, i128 %value, pt
; CHECK-PTX64-NEXT: .reg .b64 %rd<5>;
; CHECK-PTX64-EMPTY:
; CHECK-PTX64-NEXT: // %bb.0:
-; CHECK-PTX64-NEXT: ld.param.b64 %rd1, [test_st_async_mbarrier_b128_param_0];
-; CHECK-PTX64-NEXT: ld.param.v2.b64 {%rd2, %rd3}, [test_st_async_mbarrier_b128_param_1];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd4, [test_st_async_mbarrier_b128_param_2];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd1, [test_st_async_mbarrier_b128_param_0];
+; CHECK-PTX64-NEXT: ld.param::func.v2.b64 {%rd2, %rd3}, [test_st_async_mbarrier_b128_param_1];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd4, [test_st_async_mbarrier_b128_param_2];
; CHECK-PTX64-NEXT: {
; CHECK-PTX64-NEXT: .reg .b128 %in_128;
; CHECK-PTX64-NEXT: mov.b128 %in_128, {%rd2, %rd3};
@@ -26,9 +26,9 @@ define void @test_st_async_mbarrier_b128(ptr addrspace(7) %addr, i128 %value, pt
; CHECK-SHARED32-NEXT: .reg .b64 %rd<3>;
; CHECK-SHARED32-EMPTY:
; CHECK-SHARED32-NEXT: // %bb.0:
-; CHECK-SHARED32-NEXT: ld.param.b32 %r1, [test_st_async_mbarrier_b128_param_0];
-; CHECK-SHARED32-NEXT: ld.param.v2.b64 {%rd1, %rd2}, [test_st_async_mbarrier_b128_param_1];
-; CHECK-SHARED32-NEXT: ld.param.b32 %r2, [test_st_async_mbarrier_b128_param_2];
+; CHECK-SHARED32-NEXT: ld.param::func.b32 %r1, [test_st_async_mbarrier_b128_param_0];
+; CHECK-SHARED32-NEXT: ld.param::func.v2.b64 {%rd1, %rd2}, [test_st_async_mbarrier_b128_param_1];
+; CHECK-SHARED32-NEXT: ld.param::func.b32 %r2, [test_st_async_mbarrier_b128_param_2];
; CHECK-SHARED32-NEXT: {
; CHECK-SHARED32-NEXT: .reg .b128 %in_128;
; CHECK-SHARED32-NEXT: mov.b128 %in_128, {%rd1, %rd2};
diff --git a/llvm/test/CodeGen/NVPTX/st_async_release.ll b/llvm/test/CodeGen/NVPTX/st_async_release.ll
index 3df7642d5ed1a..5f41ea5bf8d52 100644
--- a/llvm/test/CodeGen/NVPTX/st_async_release.ll
+++ b/llvm/test/CodeGen/NVPTX/st_async_release.ll
@@ -9,8 +9,8 @@ define void @test_st_async_release_sys_b8(ptr addrspace(1) %addr, i8 %value) {
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [test_st_async_release_sys_b8_param_0];
-; CHECK-NEXT: ld.param.b8 %rs1, [test_st_async_release_sys_b8_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_st_async_release_sys_b8_param_0];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [test_st_async_release_sys_b8_param_1];
; CHECK-NEXT: {
; CHECK-NEXT: .reg .b8 %st_async_val;
; CHECK-NEXT: cvt.u8.u16 %st_async_val, %rs1;
@@ -28,8 +28,8 @@ define void @test_st_async_release_sys_b16(ptr addrspace(1) %addr, i16 %value) {
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [test_st_async_release_sys_b16_param_0];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_st_async_release_sys_b16_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_st_async_release_sys_b16_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_st_async_release_sys_b16_param_1];
; CHECK-NEXT: st.async.release.sys.global.b16 [%rd1], %rs1;
; CHECK-NEXT: ret;
call void @llvm.nvvm.st.async.sys.i16(ptr addrspace(1) %addr, i16 %value, /* isMultimem= */ i1 false)
@@ -43,8 +43,8 @@ define void @test_st_async_release_sys_b32(ptr addrspace(1) %addr, i32 %value) {
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [test_st_async_release_sys_b32_param_0];
-; CHECK-NEXT: ld.param.b32 %r1, [test_st_async_release_sys_b32_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_st_async_release_sys_b32_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_st_async_release_sys_b32_param_1];
; CHECK-NEXT: st.async.release.sys.global.b32 [%rd1], %r1;
; CHECK-NEXT: ret;
call void @llvm.nvvm.st.async.sys.i32(ptr addrspace(1) %addr, i32 %value, /* isMultimem= */ i1 false)
@@ -57,8 +57,8 @@ define void @test_st_async_release_sys_b64(ptr addrspace(1) %addr, i64 %value) {
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [test_st_async_release_sys_b64_param_0];
-; CHECK-NEXT: ld.param.b64 %rd2, [test_st_async_release_sys_b64_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_st_async_release_sys_b64_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [test_st_async_release_sys_b64_param_1];
; CHECK-NEXT: st.async.release.sys.global.b64 [%rd1], %rd2;
; CHECK-NEXT: ret;
call void @llvm.nvvm.st.async.sys.i64(ptr addrspace(1) %addr, i64 %value, /* isMultimem= */ i1 false)
@@ -72,8 +72,8 @@ define void @test_st_async_release_gpu_b8(ptr addrspace(1) %addr, i8 %value) {
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [test_st_async_release_gpu_b8_param_0];
-; CHECK-NEXT: ld.param.b8 %rs1, [test_st_async_release_gpu_b8_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_st_async_release_gpu_b8_param_0];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [test_st_async_release_gpu_b8_param_1];
; CHECK-NEXT: {
; CHECK-NEXT: .reg .b8 %st_async_val;
; CHECK-NEXT: cvt.u8.u16 %st_async_val, %rs1;
@@ -91,8 +91,8 @@ define void @test_st_async_release_gpu_b16(ptr addrspace(1) %addr, i16 %value) {
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [test_st_async_release_gpu_b16_param_0];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_st_async_release_gpu_b16_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_st_async_release_gpu_b16_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_st_async_release_gpu_b16_param_1];
; CHECK-NEXT: st.async.release.gpu.global.b16 [%rd1], %rs1;
; CHECK-NEXT: ret;
call void @llvm.nvvm.st.async.gpu.i16(ptr addrspace(1) %addr, i16 %value, /* isMultimem= */ i1 false)
@@ -106,8 +106,8 @@ define void @test_st_async_release_gpu_b32(ptr addrspace(1) %addr, i32 %value) {
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [test_st_async_release_gpu_b32_param_0];
-; CHECK-NEXT: ld.param.b32 %r1, [test_st_async_release_gpu_b32_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_st_async_release_gpu_b32_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_st_async_release_gpu_b32_param_1];
; CHECK-NEXT: st.async.release.gpu.global.b32 [%rd1], %r1;
; CHECK-NEXT: ret;
call void @llvm.nvvm.st.async.gpu.i32(ptr addrspace(1) %addr, i32 %value, /* isMultimem= */ i1 false)
@@ -120,8 +120,8 @@ define void @test_st_async_release_gpu_b64(ptr addrspace(1) %addr, i64 %value) {
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [test_st_async_release_gpu_b64_param_0];
-; CHECK-NEXT: ld.param.b64 %rd2, [test_st_async_release_gpu_b64_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_st_async_release_gpu_b64_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [test_st_async_release_gpu_b64_param_1];
; CHECK-NEXT: st.async.release.gpu.global.b64 [%rd1], %rd2;
; CHECK-NEXT: ret;
call void @llvm.nvvm.st.async.gpu.i64(ptr addrspace(1) %addr, i64 %value, /* isMultimem= */ i1 false)
@@ -135,8 +135,8 @@ define void @test_st_async_mmio_release_sys_b8(ptr addrspace(1) %addr, i8 %value
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [test_st_async_mmio_release_sys_b8_param_0];
-; CHECK-NEXT: ld.param.b8 %rs1, [test_st_async_mmio_release_sys_b8_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_st_async_mmio_release_sys_b8_param_0];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [test_st_async_mmio_release_sys_b8_param_1];
; CHECK-NEXT: {
; CHECK-NEXT: .reg .b8 %st_async_val;
; CHECK-NEXT: cvt.u8.u16 %st_async_val, %rs1;
@@ -154,8 +154,8 @@ define void @test_st_async_mmio_release_sys_b16(ptr addrspace(1) %addr, i16 %val
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [test_st_async_mmio_release_sys_b16_param_0];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_st_async_mmio_release_sys_b16_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_st_async_mmio_release_sys_b16_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_st_async_mmio_release_sys_b16_param_1];
; CHECK-NEXT: st.async.mmio.release.sys.global.b16 [%rd1], %rs1;
; CHECK-NEXT: ret;
call void @llvm.nvvm.st.async.mmio.sys.i16(ptr addrspace(1) %addr, i16 %value)
@@ -169,8 +169,8 @@ define void @test_st_async_mmio_release_sys_b32(ptr addrspace(1) %addr, i32 %val
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [test_st_async_mmio_release_sys_b32_param_0];
-; CHECK-NEXT: ld.param.b32 %r1, [test_st_async_mmio_release_sys_b32_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_st_async_mmio_release_sys_b32_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_st_async_mmio_release_sys_b32_param_1];
; CHECK-NEXT: st.async.mmio.release.sys.global.b32 [%rd1], %r1;
; CHECK-NEXT: ret;
call void @llvm.nvvm.st.async.mmio.sys.i32(ptr addrspace(1) %addr, i32 %value)
@@ -183,8 +183,8 @@ define void @test_st_async_mmio_release_sys_b64(ptr addrspace(1) %addr, i64 %val
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [test_st_async_mmio_release_sys_b64_param_0];
-; CHECK-NEXT: ld.param.b64 %rd2, [test_st_async_mmio_release_sys_b64_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_st_async_mmio_release_sys_b64_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [test_st_async_mmio_release_sys_b64_param_1];
; CHECK-NEXT: st.async.mmio.release.sys.global.b64 [%rd1], %rd2;
; CHECK-NEXT: ret;
call void @llvm.nvvm.st.async.mmio.sys.i64(ptr addrspace(1) %addr, i64 %value)
diff --git a/llvm/test/CodeGen/NVPTX/st_async_release_multimem.ll b/llvm/test/CodeGen/NVPTX/st_async_release_multimem.ll
index 5ad6850bcd990..04b2e2a930152 100644
--- a/llvm/test/CodeGen/NVPTX/st_async_release_multimem.ll
+++ b/llvm/test/CodeGen/NVPTX/st_async_release_multimem.ll
@@ -9,8 +9,8 @@ define void @test_multimem_st_async_release_sys_b8(ptr addrspace(1) %addr, i8 %v
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [test_multimem_st_async_release_sys_b8_param_0];
-; CHECK-NEXT: ld.param.b8 %rs1, [test_multimem_st_async_release_sys_b8_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_multimem_st_async_release_sys_b8_param_0];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [test_multimem_st_async_release_sys_b8_param_1];
; CHECK-NEXT: {
; CHECK-NEXT: .reg .b8 %st_async_val;
; CHECK-NEXT: cvt.u8.u16 %st_async_val, %rs1;
@@ -28,8 +28,8 @@ define void @test_multimem_st_async_release_sys_b16(ptr addrspace(1) %addr, i16
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [test_multimem_st_async_release_sys_b16_param_0];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_multimem_st_async_release_sys_b16_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_multimem_st_async_release_sys_b16_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_multimem_st_async_release_sys_b16_param_1];
; CHECK-NEXT: multimem.st.async.release.sys.global.b16 [%rd1], %rs1;
; CHECK-NEXT: ret;
call void @llvm.nvvm.st.async.sys.i16(ptr addrspace(1) %addr, i16 %value, /* isMultimem= */ i1 true)
@@ -43,8 +43,8 @@ define void @test_multimem_st_async_release_sys_b32(ptr addrspace(1) %addr, i32
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [test_multimem_st_async_release_sys_b32_param_0];
-; CHECK-NEXT: ld.param.b32 %r1, [test_multimem_st_async_release_sys_b32_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_multimem_st_async_release_sys_b32_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_multimem_st_async_release_sys_b32_param_1];
; CHECK-NEXT: multimem.st.async.release.sys.global.b32 [%rd1], %r1;
; CHECK-NEXT: ret;
call void @llvm.nvvm.st.async.sys.i32(ptr addrspace(1) %addr, i32 %value, /* isMultimem= */ i1 true)
@@ -57,8 +57,8 @@ define void @test_multimem_st_async_release_sys_b64(ptr addrspace(1) %addr, i64
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [test_multimem_st_async_release_sys_b64_param_0];
-; CHECK-NEXT: ld.param.b64 %rd2, [test_multimem_st_async_release_sys_b64_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_multimem_st_async_release_sys_b64_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [test_multimem_st_async_release_sys_b64_param_1];
; CHECK-NEXT: multimem.st.async.release.sys.global.b64 [%rd1], %rd2;
; CHECK-NEXT: ret;
call void @llvm.nvvm.st.async.sys.i64(ptr addrspace(1) %addr, i64 %value, /* isMultimem= */ i1 true)
@@ -72,8 +72,8 @@ define void @test_multimem_st_async_release_gpu_b8(ptr addrspace(1) %addr, i8 %v
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [test_multimem_st_async_release_gpu_b8_param_0];
-; CHECK-NEXT: ld.param.b8 %rs1, [test_multimem_st_async_release_gpu_b8_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_multimem_st_async_release_gpu_b8_param_0];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [test_multimem_st_async_release_gpu_b8_param_1];
; CHECK-NEXT: {
; CHECK-NEXT: .reg .b8 %st_async_val;
; CHECK-NEXT: cvt.u8.u16 %st_async_val, %rs1;
@@ -91,8 +91,8 @@ define void @test_multimem_st_async_release_gpu_b16(ptr addrspace(1) %addr, i16
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [test_multimem_st_async_release_gpu_b16_param_0];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_multimem_st_async_release_gpu_b16_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_multimem_st_async_release_gpu_b16_param_0];
+; CHECK-NEXT: ld.param::func.b16 %rs1, [test_multimem_st_async_release_gpu_b16_param_1];
; CHECK-NEXT: multimem.st.async.release.gpu.global.b16 [%rd1], %rs1;
; CHECK-NEXT: ret;
call void @llvm.nvvm.st.async.gpu.i16(ptr addrspace(1) %addr, i16 %value, /* isMultimem= */ i1 true)
@@ -106,8 +106,8 @@ define void @test_multimem_st_async_release_gpu_b32(ptr addrspace(1) %addr, i32
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [test_multimem_st_async_release_gpu_b32_param_0];
-; CHECK-NEXT: ld.param.b32 %r1, [test_multimem_st_async_release_gpu_b32_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_multimem_st_async_release_gpu_b32_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_multimem_st_async_release_gpu_b32_param_1];
; CHECK-NEXT: multimem.st.async.release.gpu.global.b32 [%rd1], %r1;
; CHECK-NEXT: ret;
call void @llvm.nvvm.st.async.gpu.i32(ptr addrspace(1) %addr, i32 %value, /* isMultimem= */ i1 true)
@@ -120,8 +120,8 @@ define void @test_multimem_st_async_release_gpu_b64(ptr addrspace(1) %addr, i64
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [test_multimem_st_async_release_gpu_b64_param_0];
-; CHECK-NEXT: ld.param.b64 %rd2, [test_multimem_st_async_release_gpu_b64_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_multimem_st_async_release_gpu_b64_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [test_multimem_st_async_release_gpu_b64_param_1];
; CHECK-NEXT: multimem.st.async.release.gpu.global.b64 [%rd1], %rd2;
; CHECK-NEXT: ret;
call void @llvm.nvvm.st.async.gpu.i64(ptr addrspace(1) %addr, i64 %value, /* isMultimem= */ i1 true)
diff --git a/llvm/test/CodeGen/NVPTX/st_bulk.ll b/llvm/test/CodeGen/NVPTX/st_bulk.ll
index 80232d10e5f03..9ac0da5620991 100644
--- a/llvm/test/CodeGen/NVPTX/st_bulk.ll
+++ b/llvm/test/CodeGen/NVPTX/st_bulk.ll
@@ -11,8 +11,8 @@ define void @st_bulk(ptr %dest_addr, i64 %size) {
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [st_bulk_param_0];
-; CHECK-NEXT: ld.param.b64 %rd2, [st_bulk_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [st_bulk_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [st_bulk_param_1];
; CHECK-NEXT: st.bulk [%rd1], %rd2, 0;
; CHECK-NEXT: ret;
call void @llvm.nvvm.st.bulk(ptr %dest_addr, i64 %size, i64 0)
@@ -26,8 +26,8 @@ define void @st_bulk_shared_cta(ptr addrspace(3) %dest_addr, i64 %size) {
; CHECK-PTX64-NEXT: .reg .b64 %rd<3>;
; CHECK-PTX64-EMPTY:
; CHECK-PTX64-NEXT: // %bb.0:
-; CHECK-PTX64-NEXT: ld.param.b64 %rd1, [st_bulk_shared_cta_param_0];
-; CHECK-PTX64-NEXT: ld.param.b64 %rd2, [st_bulk_shared_cta_param_1];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd1, [st_bulk_shared_cta_param_0];
+; CHECK-PTX64-NEXT: ld.param::func.b64 %rd2, [st_bulk_shared_cta_param_1];
; CHECK-PTX64-NEXT: st.bulk.shared::cta [%rd1], %rd2, 0;
; CHECK-PTX64-NEXT: ret;
;
@@ -37,8 +37,8 @@ define void @st_bulk_shared_cta(ptr addrspace(3) %dest_addr, i64 %size) {
; CHECK-PTX-SHARED32-NEXT: .reg .b64 %rd<2>;
; CHECK-PTX-SHARED32-EMPTY:
; CHECK-PTX-SHARED32-NEXT: // %bb.0:
-; CHECK-PTX-SHARED32-NEXT: ld.param.b32 %r1, [st_bulk_shared_cta_param_0];
-; CHECK-PTX-SHARED32-NEXT: ld.param.b64 %rd1, [st_bulk_shared_cta_param_1];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b32 %r1, [st_bulk_shared_cta_param_0];
+; CHECK-PTX-SHARED32-NEXT: ld.param::func.b64 %rd1, [st_bulk_shared_cta_param_1];
; CHECK-PTX-SHARED32-NEXT: st.bulk.shared::cta [%r1], %rd1, 0;
; CHECK-PTX-SHARED32-NEXT: ret;
call void @llvm.nvvm.st.bulk.shared.cta(ptr addrspace(3) %dest_addr, i64 %size, i64 0)
diff --git a/llvm/test/CodeGen/NVPTX/sub-byte-constant-vector-convert.ll b/llvm/test/CodeGen/NVPTX/sub-byte-constant-vector-convert.ll
index 90bf9afc8da0a..1e0d27172e037 100644
--- a/llvm/test/CodeGen/NVPTX/sub-byte-constant-vector-convert.ll
+++ b/llvm/test/CodeGen/NVPTX/sub-byte-constant-vector-convert.ll
@@ -23,7 +23,7 @@ define <2 x half> @foo() {
; CHECK-NEXT: cvt.u8.u16 %e2m1x2_in, %rs1;
; CHECK-NEXT: cvt.rn.f16x2.e2m1x2 %r1, %e2m1x2_in;
; CHECK-NEXT: }
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
%ld = load i8, ptr addrspace(1) @test0, align 1
%in = zext nneg i8 %ld to i16
diff --git a/llvm/test/CodeGen/NVPTX/tcgen05-alloc.ll b/llvm/test/CodeGen/NVPTX/tcgen05-alloc.ll
index 7420806ea8150..43cd82615491b 100644
--- a/llvm/test/CodeGen/NVPTX/tcgen05-alloc.ll
+++ b/llvm/test/CodeGen/NVPTX/tcgen05-alloc.ll
@@ -23,8 +23,8 @@ define void @test_tcgen05_alloc_cg1(ptr %addr, i32 %ncols) {
; CHECK_PTX64-NEXT: .reg .b64 %rd<2>;
; CHECK_PTX64-EMPTY:
; CHECK_PTX64-NEXT: // %bb.0:
-; CHECK_PTX64-NEXT: ld.param.b64 %rd1, [test_tcgen05_alloc_cg1_param_0];
-; CHECK_PTX64-NEXT: ld.param.b32 %r1, [test_tcgen05_alloc_cg1_param_1];
+; CHECK_PTX64-NEXT: ld.param::func.b64 %rd1, [test_tcgen05_alloc_cg1_param_0];
+; CHECK_PTX64-NEXT: ld.param::func.b32 %r1, [test_tcgen05_alloc_cg1_param_1];
; CHECK_PTX64-NEXT: tcgen05.alloc.cta_group::1.sync.aligned.b32 [%rd1], %r1;
; CHECK_PTX64-NEXT: ret;
;
@@ -34,8 +34,8 @@ define void @test_tcgen05_alloc_cg1(ptr %addr, i32 %ncols) {
; CHECK_PTX64_SHARED32-NEXT: .reg .b64 %rd<2>;
; CHECK_PTX64_SHARED32-EMPTY:
; CHECK_PTX64_SHARED32-NEXT: // %bb.0:
-; CHECK_PTX64_SHARED32-NEXT: ld.param.b64 %rd1, [test_tcgen05_alloc_cg1_param_0];
-; CHECK_PTX64_SHARED32-NEXT: ld.param.b32 %r1, [test_tcgen05_alloc_cg1_param_1];
+; CHECK_PTX64_SHARED32-NEXT: ld.param::func.b64 %rd1, [test_tcgen05_alloc_cg1_param_0];
+; CHECK_PTX64_SHARED32-NEXT: ld.param::func.b32 %r1, [test_tcgen05_alloc_cg1_param_1];
; CHECK_PTX64_SHARED32-NEXT: tcgen05.alloc.cta_group::1.sync.aligned.b32 [%rd1], %r1;
; CHECK_PTX64_SHARED32-NEXT: ret;
call void @llvm.nvvm.tcgen05.alloc.cg1(ptr %addr, i32 %ncols)
@@ -49,8 +49,8 @@ define void @test_tcgen05_alloc_cg2(ptr %addr, i32 %ncols) {
; CHECK_PTX64-NEXT: .reg .b64 %rd<2>;
; CHECK_PTX64-EMPTY:
; CHECK_PTX64-NEXT: // %bb.0:
-; CHECK_PTX64-NEXT: ld.param.b64 %rd1, [test_tcgen05_alloc_cg2_param_0];
-; CHECK_PTX64-NEXT: ld.param.b32 %r1, [test_tcgen05_alloc_cg2_param_1];
+; CHECK_PTX64-NEXT: ld.param::func.b64 %rd1, [test_tcgen05_alloc_cg2_param_0];
+; CHECK_PTX64-NEXT: ld.param::func.b32 %r1, [test_tcgen05_alloc_cg2_param_1];
; CHECK_PTX64-NEXT: tcgen05.alloc.cta_group::2.sync.aligned.b32 [%rd1], %r1;
; CHECK_PTX64-NEXT: ret;
;
@@ -60,8 +60,8 @@ define void @test_tcgen05_alloc_cg2(ptr %addr, i32 %ncols) {
; CHECK_PTX64_SHARED32-NEXT: .reg .b64 %rd<2>;
; CHECK_PTX64_SHARED32-EMPTY:
; CHECK_PTX64_SHARED32-NEXT: // %bb.0:
-; CHECK_PTX64_SHARED32-NEXT: ld.param.b64 %rd1, [test_tcgen05_alloc_cg2_param_0];
-; CHECK_PTX64_SHARED32-NEXT: ld.param.b32 %r1, [test_tcgen05_alloc_cg2_param_1];
+; CHECK_PTX64_SHARED32-NEXT: ld.param::func.b64 %rd1, [test_tcgen05_alloc_cg2_param_0];
+; CHECK_PTX64_SHARED32-NEXT: ld.param::func.b32 %r1, [test_tcgen05_alloc_cg2_param_1];
; CHECK_PTX64_SHARED32-NEXT: tcgen05.alloc.cta_group::2.sync.aligned.b32 [%rd1], %r1;
; CHECK_PTX64_SHARED32-NEXT: ret;
call void @llvm.nvvm.tcgen05.alloc.cg2(ptr %addr, i32 %ncols)
@@ -75,8 +75,8 @@ define void @test_tcgen05_alloc_shared_cg1(ptr addrspace(3) %addr, i32 %ncols) {
; CHECK_PTX64-NEXT: .reg .b64 %rd<2>;
; CHECK_PTX64-EMPTY:
; CHECK_PTX64-NEXT: // %bb.0:
-; CHECK_PTX64-NEXT: ld.param.b64 %rd1, [test_tcgen05_alloc_shared_cg1_param_0];
-; CHECK_PTX64-NEXT: ld.param.b32 %r1, [test_tcgen05_alloc_shared_cg1_param_1];
+; CHECK_PTX64-NEXT: ld.param::func.b64 %rd1, [test_tcgen05_alloc_shared_cg1_param_0];
+; CHECK_PTX64-NEXT: ld.param::func.b32 %r1, [test_tcgen05_alloc_shared_cg1_param_1];
; CHECK_PTX64-NEXT: tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%rd1], %r1;
; CHECK_PTX64-NEXT: ret;
;
@@ -85,8 +85,8 @@ define void @test_tcgen05_alloc_shared_cg1(ptr addrspace(3) %addr, i32 %ncols) {
; CHECK_PTX64_SHARED32-NEXT: .reg .b32 %r<3>;
; CHECK_PTX64_SHARED32-EMPTY:
; CHECK_PTX64_SHARED32-NEXT: // %bb.0:
-; CHECK_PTX64_SHARED32-NEXT: ld.param.b32 %r1, [test_tcgen05_alloc_shared_cg1_param_0];
-; CHECK_PTX64_SHARED32-NEXT: ld.param.b32 %r2, [test_tcgen05_alloc_shared_cg1_param_1];
+; CHECK_PTX64_SHARED32-NEXT: ld.param::func.b32 %r1, [test_tcgen05_alloc_shared_cg1_param_0];
+; CHECK_PTX64_SHARED32-NEXT: ld.param::func.b32 %r2, [test_tcgen05_alloc_shared_cg1_param_1];
; CHECK_PTX64_SHARED32-NEXT: tcgen05.alloc.cta_group::1.sync.aligned.shared::cta.b32 [%r1], %r2;
; CHECK_PTX64_SHARED32-NEXT: ret;
call void @llvm.nvvm.tcgen05.alloc.shared.cg1(ptr addrspace(3) %addr, i32 %ncols)
@@ -100,8 +100,8 @@ define void @test_tcgen05_alloc_shared_cg2(ptr addrspace(3) %addr, i32 %ncols) {
; CHECK_PTX64-NEXT: .reg .b64 %rd<2>;
; CHECK_PTX64-EMPTY:
; CHECK_PTX64-NEXT: // %bb.0:
-; CHECK_PTX64-NEXT: ld.param.b64 %rd1, [test_tcgen05_alloc_shared_cg2_param_0];
-; CHECK_PTX64-NEXT: ld.param.b32 %r1, [test_tcgen05_alloc_shared_cg2_param_1];
+; CHECK_PTX64-NEXT: ld.param::func.b64 %rd1, [test_tcgen05_alloc_shared_cg2_param_0];
+; CHECK_PTX64-NEXT: ld.param::func.b32 %r1, [test_tcgen05_alloc_shared_cg2_param_1];
; CHECK_PTX64-NEXT: tcgen05.alloc.cta_group::2.sync.aligned.shared::cta.b32 [%rd1], %r1;
; CHECK_PTX64-NEXT: ret;
;
@@ -110,8 +110,8 @@ define void @test_tcgen05_alloc_shared_cg2(ptr addrspace(3) %addr, i32 %ncols) {
; CHECK_PTX64_SHARED32-NEXT: .reg .b32 %r<3>;
; CHECK_PTX64_SHARED32-EMPTY:
; CHECK_PTX64_SHARED32-NEXT: // %bb.0:
-; CHECK_PTX64_SHARED32-NEXT: ld.param.b32 %r1, [test_tcgen05_alloc_shared_cg2_param_0];
-; CHECK_PTX64_SHARED32-NEXT: ld.param.b32 %r2, [test_tcgen05_alloc_shared_cg2_param_1];
+; CHECK_PTX64_SHARED32-NEXT: ld.param::func.b32 %r1, [test_tcgen05_alloc_shared_cg2_param_0];
+; CHECK_PTX64_SHARED32-NEXT: ld.param::func.b32 %r2, [test_tcgen05_alloc_shared_cg2_param_1];
; CHECK_PTX64_SHARED32-NEXT: tcgen05.alloc.cta_group::2.sync.aligned.shared::cta.b32 [%r1], %r2;
; CHECK_PTX64_SHARED32-NEXT: ret;
call void @llvm.nvvm.tcgen05.alloc.shared.cg2(ptr addrspace(3) %addr, i32 %ncols)
@@ -127,8 +127,8 @@ define void @test_tcgen05_dealloc_cg1(ptr addrspace(6) %tmem_addr, i32 %ncols) {
; CHECK_PTX64-NEXT: .reg .b32 %r<3>;
; CHECK_PTX64-EMPTY:
; CHECK_PTX64-NEXT: // %bb.0:
-; CHECK_PTX64-NEXT: ld.param.b32 %r1, [test_tcgen05_dealloc_cg1_param_0];
-; CHECK_PTX64-NEXT: ld.param.b32 %r2, [test_tcgen05_dealloc_cg1_param_1];
+; CHECK_PTX64-NEXT: ld.param::func.b32 %r1, [test_tcgen05_dealloc_cg1_param_0];
+; CHECK_PTX64-NEXT: ld.param::func.b32 %r2, [test_tcgen05_dealloc_cg1_param_1];
; CHECK_PTX64-NEXT: tcgen05.dealloc.cta_group::1.sync.aligned.b32 %r1, %r2;
; CHECK_PTX64-NEXT: ret;
;
@@ -137,8 +137,8 @@ define void @test_tcgen05_dealloc_cg1(ptr addrspace(6) %tmem_addr, i32 %ncols) {
; CHECK_PTX64_SHARED32-NEXT: .reg .b32 %r<3>;
; CHECK_PTX64_SHARED32-EMPTY:
; CHECK_PTX64_SHARED32-NEXT: // %bb.0:
-; CHECK_PTX64_SHARED32-NEXT: ld.param.b32 %r1, [test_tcgen05_dealloc_cg1_param_0];
-; CHECK_PTX64_SHARED32-NEXT: ld.param.b32 %r2, [test_tcgen05_dealloc_cg1_param_1];
+; CHECK_PTX64_SHARED32-NEXT: ld.param::func.b32 %r1, [test_tcgen05_dealloc_cg1_param_0];
+; CHECK_PTX64_SHARED32-NEXT: ld.param::func.b32 %r2, [test_tcgen05_dealloc_cg1_param_1];
; CHECK_PTX64_SHARED32-NEXT: tcgen05.dealloc.cta_group::1.sync.aligned.b32 %r1, %r2;
; CHECK_PTX64_SHARED32-NEXT: ret;
call void @llvm.nvvm.tcgen05.dealloc.cg1(ptr addrspace(6) %tmem_addr, i32 %ncols)
@@ -151,8 +151,8 @@ define void @test_tcgen05_dealloc_cg2(ptr addrspace(6) %tmem_addr, i32 %ncols) {
; CHECK_PTX64-NEXT: .reg .b32 %r<3>;
; CHECK_PTX64-EMPTY:
; CHECK_PTX64-NEXT: // %bb.0:
-; CHECK_PTX64-NEXT: ld.param.b32 %r1, [test_tcgen05_dealloc_cg2_param_0];
-; CHECK_PTX64-NEXT: ld.param.b32 %r2, [test_tcgen05_dealloc_cg2_param_1];
+; CHECK_PTX64-NEXT: ld.param::func.b32 %r1, [test_tcgen05_dealloc_cg2_param_0];
+; CHECK_PTX64-NEXT: ld.param::func.b32 %r2, [test_tcgen05_dealloc_cg2_param_1];
; CHECK_PTX64-NEXT: tcgen05.dealloc.cta_group::2.sync.aligned.b32 %r1, %r2;
; CHECK_PTX64-NEXT: ret;
;
@@ -161,8 +161,8 @@ define void @test_tcgen05_dealloc_cg2(ptr addrspace(6) %tmem_addr, i32 %ncols) {
; CHECK_PTX64_SHARED32-NEXT: .reg .b32 %r<3>;
; CHECK_PTX64_SHARED32-EMPTY:
; CHECK_PTX64_SHARED32-NEXT: // %bb.0:
-; CHECK_PTX64_SHARED32-NEXT: ld.param.b32 %r1, [test_tcgen05_dealloc_cg2_param_0];
-; CHECK_PTX64_SHARED32-NEXT: ld.param.b32 %r2, [test_tcgen05_dealloc_cg2_param_1];
+; CHECK_PTX64_SHARED32-NEXT: ld.param::func.b32 %r1, [test_tcgen05_dealloc_cg2_param_0];
+; CHECK_PTX64_SHARED32-NEXT: ld.param::func.b32 %r2, [test_tcgen05_dealloc_cg2_param_1];
; CHECK_PTX64_SHARED32-NEXT: tcgen05.dealloc.cta_group::2.sync.aligned.b32 %r1, %r2;
; CHECK_PTX64_SHARED32-NEXT: ret;
call void @llvm.nvvm.tcgen05.dealloc.cg2(ptr addrspace(6) %tmem_addr, i32 %ncols)
diff --git a/llvm/test/CodeGen/NVPTX/tcgen05-commit-sm107.ll b/llvm/test/CodeGen/NVPTX/tcgen05-commit-sm107.ll
index 5541ed1a97c24..ae3d99f3e1f82 100644
--- a/llvm/test/CodeGen/NVPTX/tcgen05-commit-sm107.ll
+++ b/llvm/test/CodeGen/NVPTX/tcgen05-commit-sm107.ll
@@ -16,7 +16,7 @@ define void @test_tcgen05_commit_smem_a_read_cg1(ptr %bar_addr) {
; CHECK_PTX64-NEXT: .reg .b64 %rd<2>;
; CHECK_PTX64-EMPTY:
; CHECK_PTX64-NEXT: // %bb.0:
-; CHECK_PTX64-NEXT: ld.param.b64 %rd1, [test_tcgen05_commit_smem_a_read_cg1_param_0];
+; CHECK_PTX64-NEXT: ld.param::func.b64 %rd1, [test_tcgen05_commit_smem_a_read_cg1_param_0];
; CHECK_PTX64-NEXT: tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.sync_restrict::shared::read::mma::a.b64 [%rd1];
; CHECK_PTX64-NEXT: ret;
;
@@ -25,7 +25,7 @@ define void @test_tcgen05_commit_smem_a_read_cg1(ptr %bar_addr) {
; CHECK_PTX64_SHARED32-NEXT: .reg .b64 %rd<2>;
; CHECK_PTX64_SHARED32-EMPTY:
; CHECK_PTX64_SHARED32-NEXT: // %bb.0:
-; CHECK_PTX64_SHARED32-NEXT: ld.param.b64 %rd1, [test_tcgen05_commit_smem_a_read_cg1_param_0];
+; CHECK_PTX64_SHARED32-NEXT: ld.param::func.b64 %rd1, [test_tcgen05_commit_smem_a_read_cg1_param_0];
; CHECK_PTX64_SHARED32-NEXT: tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.sync_restrict::shared::read::mma::a.b64 [%rd1];
; CHECK_PTX64_SHARED32-NEXT: ret;
call void @llvm.nvvm.tcgen05.commit.smem.a.read.cg1.p0(ptr %bar_addr)
@@ -39,7 +39,7 @@ define void @test_tcgen05_commit_smem_a_read_cg2(ptr %bar_addr) {
; CHECK_PTX64-NEXT: .reg .b64 %rd<2>;
; CHECK_PTX64-EMPTY:
; CHECK_PTX64-NEXT: // %bb.0:
-; CHECK_PTX64-NEXT: ld.param.b64 %rd1, [test_tcgen05_commit_smem_a_read_cg2_param_0];
+; CHECK_PTX64-NEXT: ld.param::func.b64 %rd1, [test_tcgen05_commit_smem_a_read_cg2_param_0];
; CHECK_PTX64-NEXT: tcgen05.commit.cta_group::2.mbarrier::arrive::one.shared::cluster.sync_restrict::shared::read::mma::a.b64 [%rd1];
; CHECK_PTX64-NEXT: ret;
;
@@ -48,7 +48,7 @@ define void @test_tcgen05_commit_smem_a_read_cg2(ptr %bar_addr) {
; CHECK_PTX64_SHARED32-NEXT: .reg .b64 %rd<2>;
; CHECK_PTX64_SHARED32-EMPTY:
; CHECK_PTX64_SHARED32-NEXT: // %bb.0:
-; CHECK_PTX64_SHARED32-NEXT: ld.param.b64 %rd1, [test_tcgen05_commit_smem_a_read_cg2_param_0];
+; CHECK_PTX64_SHARED32-NEXT: ld.param::func.b64 %rd1, [test_tcgen05_commit_smem_a_read_cg2_param_0];
; CHECK_PTX64_SHARED32-NEXT: tcgen05.commit.cta_group::2.mbarrier::arrive::one.shared::cluster.sync_restrict::shared::read::mma::a.b64 [%rd1];
; CHECK_PTX64_SHARED32-NEXT: ret;
call void @llvm.nvvm.tcgen05.commit.smem.a.read.cg2.p0(ptr %bar_addr)
@@ -62,7 +62,7 @@ define void @test_tcgen05_commit_smem_a_read_shared_cg1(ptr addrspace(3) %bar_ad
; CHECK_PTX64-NEXT: .reg .b64 %rd<2>;
; CHECK_PTX64-EMPTY:
; CHECK_PTX64-NEXT: // %bb.0:
-; CHECK_PTX64-NEXT: ld.param.b64 %rd1, [test_tcgen05_commit_smem_a_read_shared_cg1_param_0];
+; CHECK_PTX64-NEXT: ld.param::func.b64 %rd1, [test_tcgen05_commit_smem_a_read_shared_cg1_param_0];
; CHECK_PTX64-NEXT: tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.sync_restrict::shared::read::mma::a.b64 [%rd1];
; CHECK_PTX64-NEXT: ret;
;
@@ -71,7 +71,7 @@ define void @test_tcgen05_commit_smem_a_read_shared_cg1(ptr addrspace(3) %bar_ad
; CHECK_PTX64_SHARED32-NEXT: .reg .b32 %r<2>;
; CHECK_PTX64_SHARED32-EMPTY:
; CHECK_PTX64_SHARED32-NEXT: // %bb.0:
-; CHECK_PTX64_SHARED32-NEXT: ld.param.b32 %r1, [test_tcgen05_commit_smem_a_read_shared_cg1_param_0];
+; CHECK_PTX64_SHARED32-NEXT: ld.param::func.b32 %r1, [test_tcgen05_commit_smem_a_read_shared_cg1_param_0];
; CHECK_PTX64_SHARED32-NEXT: tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.sync_restrict::shared::read::mma::a.b64 [%r1];
; CHECK_PTX64_SHARED32-NEXT: ret;
call void @llvm.nvvm.tcgen05.commit.smem.a.read.cg1.p3(ptr addrspace(3) %bar_addr)
@@ -85,7 +85,7 @@ define void @test_tcgen05_commit_smem_a_read_shared_cg2(ptr addrspace(3) %bar_ad
; CHECK_PTX64-NEXT: .reg .b64 %rd<2>;
; CHECK_PTX64-EMPTY:
; CHECK_PTX64-NEXT: // %bb.0:
-; CHECK_PTX64-NEXT: ld.param.b64 %rd1, [test_tcgen05_commit_smem_a_read_shared_cg2_param_0];
+; CHECK_PTX64-NEXT: ld.param::func.b64 %rd1, [test_tcgen05_commit_smem_a_read_shared_cg2_param_0];
; CHECK_PTX64-NEXT: tcgen05.commit.cta_group::2.mbarrier::arrive::one.shared::cluster.sync_restrict::shared::read::mma::a.b64 [%rd1];
; CHECK_PTX64-NEXT: ret;
;
@@ -94,7 +94,7 @@ define void @test_tcgen05_commit_smem_a_read_shared_cg2(ptr addrspace(3) %bar_ad
; CHECK_PTX64_SHARED32-NEXT: .reg .b32 %r<2>;
; CHECK_PTX64_SHARED32-EMPTY:
; CHECK_PTX64_SHARED32-NEXT: // %bb.0:
-; CHECK_PTX64_SHARED32-NEXT: ld.param.b32 %r1, [test_tcgen05_commit_smem_a_read_shared_cg2_param_0];
+; CHECK_PTX64_SHARED32-NEXT: ld.param::func.b32 %r1, [test_tcgen05_commit_smem_a_read_shared_cg2_param_0];
; CHECK_PTX64_SHARED32-NEXT: tcgen05.commit.cta_group::2.mbarrier::arrive::one.shared::cluster.sync_restrict::shared::read::mma::a.b64 [%r1];
; CHECK_PTX64_SHARED32-NEXT: ret;
call void @llvm.nvvm.tcgen05.commit.smem.a.read.cg2.p3(ptr addrspace(3) %bar_addr)
@@ -114,8 +114,8 @@ define void @test_tcgen05_commit_smem_a_read_mc_cg1(ptr %bar_addr, i16 %cta_mask
; CHECK_PTX64-NEXT: .reg .b64 %rd<2>;
; CHECK_PTX64-EMPTY:
; CHECK_PTX64-NEXT: // %bb.0:
-; CHECK_PTX64-NEXT: ld.param.b64 %rd1, [test_tcgen05_commit_smem_a_read_mc_cg1_param_0];
-; CHECK_PTX64-NEXT: ld.param.b16 %rs1, [test_tcgen05_commit_smem_a_read_mc_cg1_param_1];
+; CHECK_PTX64-NEXT: ld.param::func.b64 %rd1, [test_tcgen05_commit_smem_a_read_mc_cg1_param_0];
+; CHECK_PTX64-NEXT: ld.param::func.b16 %rs1, [test_tcgen05_commit_smem_a_read_mc_cg1_param_1];
; CHECK_PTX64-NEXT: tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.sync_restrict::shared::read::mma::a.multicast::cluster.b64 [%rd1], %rs1;
; CHECK_PTX64-NEXT: ret;
;
@@ -125,8 +125,8 @@ define void @test_tcgen05_commit_smem_a_read_mc_cg1(ptr %bar_addr, i16 %cta_mask
; CHECK_PTX64_SHARED32-NEXT: .reg .b64 %rd<2>;
; CHECK_PTX64_SHARED32-EMPTY:
; CHECK_PTX64_SHARED32-NEXT: // %bb.0:
-; CHECK_PTX64_SHARED32-NEXT: ld.param.b64 %rd1, [test_tcgen05_commit_smem_a_read_mc_cg1_param_0];
-; CHECK_PTX64_SHARED32-NEXT: ld.param.b16 %rs1, [test_tcgen05_commit_smem_a_read_mc_cg1_param_1];
+; CHECK_PTX64_SHARED32-NEXT: ld.param::func.b64 %rd1, [test_tcgen05_commit_smem_a_read_mc_cg1_param_0];
+; CHECK_PTX64_SHARED32-NEXT: ld.param::func.b16 %rs1, [test_tcgen05_commit_smem_a_read_mc_cg1_param_1];
; CHECK_PTX64_SHARED32-NEXT: tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.sync_restrict::shared::read::mma::a.multicast::cluster.b64 [%rd1], %rs1;
; CHECK_PTX64_SHARED32-NEXT: ret;
call void @llvm.nvvm.tcgen05.commit.smem.a.read.mc.cg1.p0.i16(ptr %bar_addr, i16 %cta_mask)
@@ -141,8 +141,8 @@ define void @test_tcgen05_commit_smem_a_read_mc_cg2(ptr %bar_addr, i16 %cta_mask
; CHECK_PTX64-NEXT: .reg .b64 %rd<2>;
; CHECK_PTX64-EMPTY:
; CHECK_PTX64-NEXT: // %bb.0:
-; CHECK_PTX64-NEXT: ld.param.b64 %rd1, [test_tcgen05_commit_smem_a_read_mc_cg2_param_0];
-; CHECK_PTX64-NEXT: ld.param.b16 %rs1, [test_tcgen05_commit_smem_a_read_mc_cg2_param_1];
+; CHECK_PTX64-NEXT: ld.param::func.b64 %rd1, [test_tcgen05_commit_smem_a_read_mc_cg2_param_0];
+; CHECK_PTX64-NEXT: ld.param::func.b16 %rs1, [test_tcgen05_commit_smem_a_read_mc_cg2_param_1];
; CHECK_PTX64-NEXT: tcgen05.commit.cta_group::2.mbarrier::arrive::one.shared::cluster.sync_restrict::shared::read::mma::a.multicast::cluster.b64 [%rd1], %rs1;
; CHECK_PTX64-NEXT: ret;
;
@@ -152,8 +152,8 @@ define void @test_tcgen05_commit_smem_a_read_mc_cg2(ptr %bar_addr, i16 %cta_mask
; CHECK_PTX64_SHARED32-NEXT: .reg .b64 %rd<2>;
; CHECK_PTX64_SHARED32-EMPTY:
; CHECK_PTX64_SHARED32-NEXT: // %bb.0:
-; CHECK_PTX64_SHARED32-NEXT: ld.param.b64 %rd1, [test_tcgen05_commit_smem_a_read_mc_cg2_param_0];
-; CHECK_PTX64_SHARED32-NEXT: ld.param.b16 %rs1, [test_tcgen05_commit_smem_a_read_mc_cg2_param_1];
+; CHECK_PTX64_SHARED32-NEXT: ld.param::func.b64 %rd1, [test_tcgen05_commit_smem_a_read_mc_cg2_param_0];
+; CHECK_PTX64_SHARED32-NEXT: ld.param::func.b16 %rs1, [test_tcgen05_commit_smem_a_read_mc_cg2_param_1];
; CHECK_PTX64_SHARED32-NEXT: tcgen05.commit.cta_group::2.mbarrier::arrive::one.shared::cluster.sync_restrict::shared::read::mma::a.multicast::cluster.b64 [%rd1], %rs1;
; CHECK_PTX64_SHARED32-NEXT: ret;
call void @llvm.nvvm.tcgen05.commit.smem.a.read.mc.cg2.p0.i16(ptr %bar_addr, i16 %cta_mask)
@@ -168,8 +168,8 @@ define void @test_tcgen05_commit_smem_a_read_mc_shared_cg1(ptr addrspace(3) %bar
; CHECK_PTX64-NEXT: .reg .b64 %rd<2>;
; CHECK_PTX64-EMPTY:
; CHECK_PTX64-NEXT: // %bb.0:
-; CHECK_PTX64-NEXT: ld.param.b64 %rd1, [test_tcgen05_commit_smem_a_read_mc_shared_cg1_param_0];
-; CHECK_PTX64-NEXT: ld.param.b16 %rs1, [test_tcgen05_commit_smem_a_read_mc_shared_cg1_param_1];
+; CHECK_PTX64-NEXT: ld.param::func.b64 %rd1, [test_tcgen05_commit_smem_a_read_mc_shared_cg1_param_0];
+; CHECK_PTX64-NEXT: ld.param::func.b16 %rs1, [test_tcgen05_commit_smem_a_read_mc_shared_cg1_param_1];
; CHECK_PTX64-NEXT: tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.sync_restrict::shared::read::mma::a.multicast::cluster.b64 [%rd1], %rs1;
; CHECK_PTX64-NEXT: ret;
;
@@ -179,8 +179,8 @@ define void @test_tcgen05_commit_smem_a_read_mc_shared_cg1(ptr addrspace(3) %bar
; CHECK_PTX64_SHARED32-NEXT: .reg .b32 %r<2>;
; CHECK_PTX64_SHARED32-EMPTY:
; CHECK_PTX64_SHARED32-NEXT: // %bb.0:
-; CHECK_PTX64_SHARED32-NEXT: ld.param.b32 %r1, [test_tcgen05_commit_smem_a_read_mc_shared_cg1_param_0];
-; CHECK_PTX64_SHARED32-NEXT: ld.param.b16 %rs1, [test_tcgen05_commit_smem_a_read_mc_shared_cg1_param_1];
+; CHECK_PTX64_SHARED32-NEXT: ld.param::func.b32 %r1, [test_tcgen05_commit_smem_a_read_mc_shared_cg1_param_0];
+; CHECK_PTX64_SHARED32-NEXT: ld.param::func.b16 %rs1, [test_tcgen05_commit_smem_a_read_mc_shared_cg1_param_1];
; CHECK_PTX64_SHARED32-NEXT: tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.sync_restrict::shared::read::mma::a.multicast::cluster.b64 [%r1], %rs1;
; CHECK_PTX64_SHARED32-NEXT: ret;
call void @llvm.nvvm.tcgen05.commit.smem.a.read.mc.cg1.p3.i16(ptr addrspace(3) %bar_addr, i16 %cta_mask)
@@ -195,8 +195,8 @@ define void @test_tcgen05_commit_smem_a_read_mc_shared_cg2(ptr addrspace(3) %bar
; CHECK_PTX64-NEXT: .reg .b64 %rd<2>;
; CHECK_PTX64-EMPTY:
; CHECK_PTX64-NEXT: // %bb.0:
-; CHECK_PTX64-NEXT: ld.param.b64 %rd1, [test_tcgen05_commit_smem_a_read_mc_shared_cg2_param_0];
-; CHECK_PTX64-NEXT: ld.param.b16 %rs1, [test_tcgen05_commit_smem_a_read_mc_shared_cg2_param_1];
+; CHECK_PTX64-NEXT: ld.param::func.b64 %rd1, [test_tcgen05_commit_smem_a_read_mc_shared_cg2_param_0];
+; CHECK_PTX64-NEXT: ld.param::func.b16 %rs1, [test_tcgen05_commit_smem_a_read_mc_shared_cg2_param_1];
; CHECK_PTX64-NEXT: tcgen05.commit.cta_group::2.mbarrier::arrive::one.shared::cluster.sync_restrict::shared::read::mma::a.multicast::cluster.b64 [%rd1], %rs1;
; CHECK_PTX64-NEXT: ret;
;
@@ -206,8 +206,8 @@ define void @test_tcgen05_commit_smem_a_read_mc_shared_cg2(ptr addrspace(3) %bar
; CHECK_PTX64_SHARED32-NEXT: .reg .b32 %r<2>;
; CHECK_PTX64_SHARED32-EMPTY:
; CHECK_PTX64_SHARED32-NEXT: // %bb.0:
-; CHECK_PTX64_SHARED32-NEXT: ld.param.b32 %r1, [test_tcgen05_commit_smem_a_read_mc_shared_cg2_param_0];
-; CHECK_PTX64_SHARED32-NEXT: ld.param.b16 %rs1, [test_tcgen05_commit_smem_a_read_mc_shared_cg2_param_1];
+; CHECK_PTX64_SHARED32-NEXT: ld.param::func.b32 %r1, [test_tcgen05_commit_smem_a_read_mc_shared_cg2_param_0];
+; CHECK_PTX64_SHARED32-NEXT: ld.param::func.b16 %rs1, [test_tcgen05_commit_smem_a_read_mc_shared_cg2_param_1];
; CHECK_PTX64_SHARED32-NEXT: tcgen05.commit.cta_group::2.mbarrier::arrive::one.shared::cluster.sync_restrict::shared::read::mma::a.multicast::cluster.b64 [%r1], %rs1;
; CHECK_PTX64_SHARED32-NEXT: ret;
call void @llvm.nvvm.tcgen05.commit.smem.a.read.mc.cg2.p3.i16(ptr addrspace(3) %bar_addr, i16 %cta_mask)
@@ -227,8 +227,8 @@ define void @test_tcgen05_commit_smem_a_read_mc_cg1_i32(ptr %bar_addr, i32 %cta_
; CHECK_PTX64-NEXT: .reg .b64 %rd<2>;
; CHECK_PTX64-EMPTY:
; CHECK_PTX64-NEXT: // %bb.0:
-; CHECK_PTX64-NEXT: ld.param.b64 %rd1, [test_tcgen05_commit_smem_a_read_mc_cg1_i32_param_0];
-; CHECK_PTX64-NEXT: ld.param.b32 %r1, [test_tcgen05_commit_smem_a_read_mc_cg1_i32_param_1];
+; CHECK_PTX64-NEXT: ld.param::func.b64 %rd1, [test_tcgen05_commit_smem_a_read_mc_cg1_i32_param_0];
+; CHECK_PTX64-NEXT: ld.param::func.b32 %r1, [test_tcgen05_commit_smem_a_read_mc_cg1_i32_param_1];
; CHECK_PTX64-NEXT: tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.sync_restrict::shared::read::mma::a.multicast::cluster::32b.b64 [%rd1], %r1;
; CHECK_PTX64-NEXT: ret;
;
@@ -238,8 +238,8 @@ define void @test_tcgen05_commit_smem_a_read_mc_cg1_i32(ptr %bar_addr, i32 %cta_
; CHECK_PTX64_SHARED32-NEXT: .reg .b64 %rd<2>;
; CHECK_PTX64_SHARED32-EMPTY:
; CHECK_PTX64_SHARED32-NEXT: // %bb.0:
-; CHECK_PTX64_SHARED32-NEXT: ld.param.b64 %rd1, [test_tcgen05_commit_smem_a_read_mc_cg1_i32_param_0];
-; CHECK_PTX64_SHARED32-NEXT: ld.param.b32 %r1, [test_tcgen05_commit_smem_a_read_mc_cg1_i32_param_1];
+; CHECK_PTX64_SHARED32-NEXT: ld.param::func.b64 %rd1, [test_tcgen05_commit_smem_a_read_mc_cg1_i32_param_0];
+; CHECK_PTX64_SHARED32-NEXT: ld.param::func.b32 %r1, [test_tcgen05_commit_smem_a_read_mc_cg1_i32_param_1];
; CHECK_PTX64_SHARED32-NEXT: tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.sync_restrict::shared::read::mma::a.multicast::cluster::32b.b64 [%rd1], %r1;
; CHECK_PTX64_SHARED32-NEXT: ret;
call void @llvm.nvvm.tcgen05.commit.smem.a.read.mc.cg1.p0.i32(ptr %bar_addr, i32 %cta_mask)
@@ -254,8 +254,8 @@ define void @test_tcgen05_commit_smem_a_read_mc_cg2_i32(ptr %bar_addr, i32 %cta_
; CHECK_PTX64-NEXT: .reg .b64 %rd<2>;
; CHECK_PTX64-EMPTY:
; CHECK_PTX64-NEXT: // %bb.0:
-; CHECK_PTX64-NEXT: ld.param.b64 %rd1, [test_tcgen05_commit_smem_a_read_mc_cg2_i32_param_0];
-; CHECK_PTX64-NEXT: ld.param.b32 %r1, [test_tcgen05_commit_smem_a_read_mc_cg2_i32_param_1];
+; CHECK_PTX64-NEXT: ld.param::func.b64 %rd1, [test_tcgen05_commit_smem_a_read_mc_cg2_i32_param_0];
+; CHECK_PTX64-NEXT: ld.param::func.b32 %r1, [test_tcgen05_commit_smem_a_read_mc_cg2_i32_param_1];
; CHECK_PTX64-NEXT: tcgen05.commit.cta_group::2.mbarrier::arrive::one.shared::cluster.sync_restrict::shared::read::mma::a.multicast::cluster::32b.b64 [%rd1], %r1;
; CHECK_PTX64-NEXT: ret;
;
@@ -265,8 +265,8 @@ define void @test_tcgen05_commit_smem_a_read_mc_cg2_i32(ptr %bar_addr, i32 %cta_
; CHECK_PTX64_SHARED32-NEXT: .reg .b64 %rd<2>;
; CHECK_PTX64_SHARED32-EMPTY:
; CHECK_PTX64_SHARED32-NEXT: // %bb.0:
-; CHECK_PTX64_SHARED32-NEXT: ld.param.b64 %rd1, [test_tcgen05_commit_smem_a_read_mc_cg2_i32_param_0];
-; CHECK_PTX64_SHARED32-NEXT: ld.param.b32 %r1, [test_tcgen05_commit_smem_a_read_mc_cg2_i32_param_1];
+; CHECK_PTX64_SHARED32-NEXT: ld.param::func.b64 %rd1, [test_tcgen05_commit_smem_a_read_mc_cg2_i32_param_0];
+; CHECK_PTX64_SHARED32-NEXT: ld.param::func.b32 %r1, [test_tcgen05_commit_smem_a_read_mc_cg2_i32_param_1];
; CHECK_PTX64_SHARED32-NEXT: tcgen05.commit.cta_group::2.mbarrier::arrive::one.shared::cluster.sync_restrict::shared::read::mma::a.multicast::cluster::32b.b64 [%rd1], %r1;
; CHECK_PTX64_SHARED32-NEXT: ret;
call void @llvm.nvvm.tcgen05.commit.smem.a.read.mc.cg2.p0.i32(ptr %bar_addr, i32 %cta_mask)
@@ -281,8 +281,8 @@ define void @test_tcgen05_commit_smem_a_read_mc_shared_cg1_i32(ptr addrspace(3)
; CHECK_PTX64-NEXT: .reg .b64 %rd<2>;
; CHECK_PTX64-EMPTY:
; CHECK_PTX64-NEXT: // %bb.0:
-; CHECK_PTX64-NEXT: ld.param.b64 %rd1, [test_tcgen05_commit_smem_a_read_mc_shared_cg1_i32_param_0];
-; CHECK_PTX64-NEXT: ld.param.b32 %r1, [test_tcgen05_commit_smem_a_read_mc_shared_cg1_i32_param_1];
+; CHECK_PTX64-NEXT: ld.param::func.b64 %rd1, [test_tcgen05_commit_smem_a_read_mc_shared_cg1_i32_param_0];
+; CHECK_PTX64-NEXT: ld.param::func.b32 %r1, [test_tcgen05_commit_smem_a_read_mc_shared_cg1_i32_param_1];
; CHECK_PTX64-NEXT: tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.sync_restrict::shared::read::mma::a.multicast::cluster::32b.b64 [%rd1], %r1;
; CHECK_PTX64-NEXT: ret;
;
@@ -291,8 +291,8 @@ define void @test_tcgen05_commit_smem_a_read_mc_shared_cg1_i32(ptr addrspace(3)
; CHECK_PTX64_SHARED32-NEXT: .reg .b32 %r<3>;
; CHECK_PTX64_SHARED32-EMPTY:
; CHECK_PTX64_SHARED32-NEXT: // %bb.0:
-; CHECK_PTX64_SHARED32-NEXT: ld.param.b32 %r1, [test_tcgen05_commit_smem_a_read_mc_shared_cg1_i32_param_0];
-; CHECK_PTX64_SHARED32-NEXT: ld.param.b32 %r2, [test_tcgen05_commit_smem_a_read_mc_shared_cg1_i32_param_1];
+; CHECK_PTX64_SHARED32-NEXT: ld.param::func.b32 %r1, [test_tcgen05_commit_smem_a_read_mc_shared_cg1_i32_param_0];
+; CHECK_PTX64_SHARED32-NEXT: ld.param::func.b32 %r2, [test_tcgen05_commit_smem_a_read_mc_shared_cg1_i32_param_1];
; CHECK_PTX64_SHARED32-NEXT: tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.sync_restrict::shared::read::mma::a.multicast::cluster::32b.b64 [%r1], %r2;
; CHECK_PTX64_SHARED32-NEXT: ret;
call void @llvm.nvvm.tcgen05.commit.smem.a.read.mc.cg1.p3.i32(ptr addrspace(3) %bar_addr, i32 %cta_mask)
@@ -307,8 +307,8 @@ define void @test_tcgen05_commit_smem_a_read_mc_shared_cg2_i32(ptr addrspace(3)
; CHECK_PTX64-NEXT: .reg .b64 %rd<2>;
; CHECK_PTX64-EMPTY:
; CHECK_PTX64-NEXT: // %bb.0:
-; CHECK_PTX64-NEXT: ld.param.b64 %rd1, [test_tcgen05_commit_smem_a_read_mc_shared_cg2_i32_param_0];
-; CHECK_PTX64-NEXT: ld.param.b32 %r1, [test_tcgen05_commit_smem_a_read_mc_shared_cg2_i32_param_1];
+; CHECK_PTX64-NEXT: ld.param::func.b64 %rd1, [test_tcgen05_commit_smem_a_read_mc_shared_cg2_i32_param_0];
+; CHECK_PTX64-NEXT: ld.param::func.b32 %r1, [test_tcgen05_commit_smem_a_read_mc_shared_cg2_i32_param_1];
; CHECK_PTX64-NEXT: tcgen05.commit.cta_group::2.mbarrier::arrive::one.shared::cluster.sync_restrict::shared::read::mma::a.multicast::cluster::32b.b64 [%rd1], %r1;
; CHECK_PTX64-NEXT: ret;
;
@@ -317,8 +317,8 @@ define void @test_tcgen05_commit_smem_a_read_mc_shared_cg2_i32(ptr addrspace(3)
; CHECK_PTX64_SHARED32-NEXT: .reg .b32 %r<3>;
; CHECK_PTX64_SHARED32-EMPTY:
; CHECK_PTX64_SHARED32-NEXT: // %bb.0:
-; CHECK_PTX64_SHARED32-NEXT: ld.param.b32 %r1, [test_tcgen05_commit_smem_a_read_mc_shared_cg2_i32_param_0];
-; CHECK_PTX64_SHARED32-NEXT: ld.param.b32 %r2, [test_tcgen05_commit_smem_a_read_mc_shared_cg2_i32_param_1];
+; CHECK_PTX64_SHARED32-NEXT: ld.param::func.b32 %r1, [test_tcgen05_commit_smem_a_read_mc_shared_cg2_i32_param_0];
+; CHECK_PTX64_SHARED32-NEXT: ld.param::func.b32 %r2, [test_tcgen05_commit_smem_a_read_mc_shared_cg2_i32_param_1];
; CHECK_PTX64_SHARED32-NEXT: tcgen05.commit.cta_group::2.mbarrier::arrive::one.shared::cluster.sync_restrict::shared::read::mma::a.multicast::cluster::32b.b64 [%r1], %r2;
; CHECK_PTX64_SHARED32-NEXT: ret;
call void @llvm.nvvm.tcgen05.commit.smem.a.read.mc.cg2.p3.i32(ptr addrspace(3) %bar_addr, i32 %cta_mask)
@@ -338,8 +338,8 @@ define void @test_tcgen05_commit_mc_cg1_i32(ptr %bar_addr, i32 %cta_mask) {
; CHECK_PTX64-NEXT: .reg .b64 %rd<2>;
; CHECK_PTX64-EMPTY:
; CHECK_PTX64-NEXT: // %bb.0:
-; CHECK_PTX64-NEXT: ld.param.b64 %rd1, [test_tcgen05_commit_mc_cg1_i32_param_0];
-; CHECK_PTX64-NEXT: ld.param.b32 %r1, [test_tcgen05_commit_mc_cg1_i32_param_1];
+; CHECK_PTX64-NEXT: ld.param::func.b64 %rd1, [test_tcgen05_commit_mc_cg1_i32_param_0];
+; CHECK_PTX64-NEXT: ld.param::func.b32 %r1, [test_tcgen05_commit_mc_cg1_i32_param_1];
; CHECK_PTX64-NEXT: tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.multicast::cluster::32b.b64 [%rd1], %r1;
; CHECK_PTX64-NEXT: ret;
;
@@ -349,8 +349,8 @@ define void @test_tcgen05_commit_mc_cg1_i32(ptr %bar_addr, i32 %cta_mask) {
; CHECK_PTX64_SHARED32-NEXT: .reg .b64 %rd<2>;
; CHECK_PTX64_SHARED32-EMPTY:
; CHECK_PTX64_SHARED32-NEXT: // %bb.0:
-; CHECK_PTX64_SHARED32-NEXT: ld.param.b64 %rd1, [test_tcgen05_commit_mc_cg1_i32_param_0];
-; CHECK_PTX64_SHARED32-NEXT: ld.param.b32 %r1, [test_tcgen05_commit_mc_cg1_i32_param_1];
+; CHECK_PTX64_SHARED32-NEXT: ld.param::func.b64 %rd1, [test_tcgen05_commit_mc_cg1_i32_param_0];
+; CHECK_PTX64_SHARED32-NEXT: ld.param::func.b32 %r1, [test_tcgen05_commit_mc_cg1_i32_param_1];
; CHECK_PTX64_SHARED32-NEXT: tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.multicast::cluster::32b.b64 [%rd1], %r1;
; CHECK_PTX64_SHARED32-NEXT: ret;
call void @llvm.nvvm.tcgen05.commit.mc.cg1.p0.i32(ptr %bar_addr, i32 %cta_mask)
@@ -365,8 +365,8 @@ define void @test_tcgen05_commit_mc_cg2_i32(ptr %bar_addr, i32 %cta_mask) {
; CHECK_PTX64-NEXT: .reg .b64 %rd<2>;
; CHECK_PTX64-EMPTY:
; CHECK_PTX64-NEXT: // %bb.0:
-; CHECK_PTX64-NEXT: ld.param.b64 %rd1, [test_tcgen05_commit_mc_cg2_i32_param_0];
-; CHECK_PTX64-NEXT: ld.param.b32 %r1, [test_tcgen05_commit_mc_cg2_i32_param_1];
+; CHECK_PTX64-NEXT: ld.param::func.b64 %rd1, [test_tcgen05_commit_mc_cg2_i32_param_0];
+; CHECK_PTX64-NEXT: ld.param::func.b32 %r1, [test_tcgen05_commit_mc_cg2_i32_param_1];
; CHECK_PTX64-NEXT: tcgen05.commit.cta_group::2.mbarrier::arrive::one.shared::cluster.multicast::cluster::32b.b64 [%rd1], %r1;
; CHECK_PTX64-NEXT: ret;
;
@@ -376,8 +376,8 @@ define void @test_tcgen05_commit_mc_cg2_i32(ptr %bar_addr, i32 %cta_mask) {
; CHECK_PTX64_SHARED32-NEXT: .reg .b64 %rd<2>;
; CHECK_PTX64_SHARED32-EMPTY:
; CHECK_PTX64_SHARED32-NEXT: // %bb.0:
-; CHECK_PTX64_SHARED32-NEXT: ld.param.b64 %rd1, [test_tcgen05_commit_mc_cg2_i32_param_0];
-; CHECK_PTX64_SHARED32-NEXT: ld.param.b32 %r1, [test_tcgen05_commit_mc_cg2_i32_param_1];
+; CHECK_PTX64_SHARED32-NEXT: ld.param::func.b64 %rd1, [test_tcgen05_commit_mc_cg2_i32_param_0];
+; CHECK_PTX64_SHARED32-NEXT: ld.param::func.b32 %r1, [test_tcgen05_commit_mc_cg2_i32_param_1];
; CHECK_PTX64_SHARED32-NEXT: tcgen05.commit.cta_group::2.mbarrier::arrive::one.shared::cluster.multicast::cluster::32b.b64 [%rd1], %r1;
; CHECK_PTX64_SHARED32-NEXT: ret;
call void @llvm.nvvm.tcgen05.commit.mc.cg2.p0.i32(ptr %bar_addr, i32 %cta_mask)
@@ -392,8 +392,8 @@ define void @test_tcgen05_commit_mc_shared_cg1_i32(ptr addrspace(3) %bar_addr, i
; CHECK_PTX64-NEXT: .reg .b64 %rd<2>;
; CHECK_PTX64-EMPTY:
; CHECK_PTX64-NEXT: // %bb.0:
-; CHECK_PTX64-NEXT: ld.param.b64 %rd1, [test_tcgen05_commit_mc_shared_cg1_i32_param_0];
-; CHECK_PTX64-NEXT: ld.param.b32 %r1, [test_tcgen05_commit_mc_shared_cg1_i32_param_1];
+; CHECK_PTX64-NEXT: ld.param::func.b64 %rd1, [test_tcgen05_commit_mc_shared_cg1_i32_param_0];
+; CHECK_PTX64-NEXT: ld.param::func.b32 %r1, [test_tcgen05_commit_mc_shared_cg1_i32_param_1];
; CHECK_PTX64-NEXT: tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.multicast::cluster::32b.b64 [%rd1], %r1;
; CHECK_PTX64-NEXT: ret;
;
@@ -402,8 +402,8 @@ define void @test_tcgen05_commit_mc_shared_cg1_i32(ptr addrspace(3) %bar_addr, i
; CHECK_PTX64_SHARED32-NEXT: .reg .b32 %r<3>;
; CHECK_PTX64_SHARED32-EMPTY:
; CHECK_PTX64_SHARED32-NEXT: // %bb.0:
-; CHECK_PTX64_SHARED32-NEXT: ld.param.b32 %r1, [test_tcgen05_commit_mc_shared_cg1_i32_param_0];
-; CHECK_PTX64_SHARED32-NEXT: ld.param.b32 %r2, [test_tcgen05_commit_mc_shared_cg1_i32_param_1];
+; CHECK_PTX64_SHARED32-NEXT: ld.param::func.b32 %r1, [test_tcgen05_commit_mc_shared_cg1_i32_param_0];
+; CHECK_PTX64_SHARED32-NEXT: ld.param::func.b32 %r2, [test_tcgen05_commit_mc_shared_cg1_i32_param_1];
; CHECK_PTX64_SHARED32-NEXT: tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.multicast::cluster::32b.b64 [%r1], %r2;
; CHECK_PTX64_SHARED32-NEXT: ret;
call void @llvm.nvvm.tcgen05.commit.mc.cg1.p3.i32(ptr addrspace(3) %bar_addr, i32 %cta_mask)
@@ -418,8 +418,8 @@ define void @test_tcgen05_commit_mc_shared_cg2_i32(ptr addrspace(3) %bar_addr, i
; CHECK_PTX64-NEXT: .reg .b64 %rd<2>;
; CHECK_PTX64-EMPTY:
; CHECK_PTX64-NEXT: // %bb.0:
-; CHECK_PTX64-NEXT: ld.param.b64 %rd1, [test_tcgen05_commit_mc_shared_cg2_i32_param_0];
-; CHECK_PTX64-NEXT: ld.param.b32 %r1, [test_tcgen05_commit_mc_shared_cg2_i32_param_1];
+; CHECK_PTX64-NEXT: ld.param::func.b64 %rd1, [test_tcgen05_commit_mc_shared_cg2_i32_param_0];
+; CHECK_PTX64-NEXT: ld.param::func.b32 %r1, [test_tcgen05_commit_mc_shared_cg2_i32_param_1];
; CHECK_PTX64-NEXT: tcgen05.commit.cta_group::2.mbarrier::arrive::one.shared::cluster.multicast::cluster::32b.b64 [%rd1], %r1;
; CHECK_PTX64-NEXT: ret;
;
@@ -428,8 +428,8 @@ define void @test_tcgen05_commit_mc_shared_cg2_i32(ptr addrspace(3) %bar_addr, i
; CHECK_PTX64_SHARED32-NEXT: .reg .b32 %r<3>;
; CHECK_PTX64_SHARED32-EMPTY:
; CHECK_PTX64_SHARED32-NEXT: // %bb.0:
-; CHECK_PTX64_SHARED32-NEXT: ld.param.b32 %r1, [test_tcgen05_commit_mc_shared_cg2_i32_param_0];
-; CHECK_PTX64_SHARED32-NEXT: ld.param.b32 %r2, [test_tcgen05_commit_mc_shared_cg2_i32_param_1];
+; CHECK_PTX64_SHARED32-NEXT: ld.param::func.b32 %r1, [test_tcgen05_commit_mc_shared_cg2_i32_param_0];
+; CHECK_PTX64_SHARED32-NEXT: ld.param::func.b32 %r2, [test_tcgen05_commit_mc_shared_cg2_i32_param_1];
; CHECK_PTX64_SHARED32-NEXT: tcgen05.commit.cta_group::2.mbarrier::arrive::one.shared::cluster.multicast::cluster::32b.b64 [%r1], %r2;
; CHECK_PTX64_SHARED32-NEXT: ret;
call void @llvm.nvvm.tcgen05.commit.mc.cg2.p3.i32(ptr addrspace(3) %bar_addr, i32 %cta_mask)
diff --git a/llvm/test/CodeGen/NVPTX/tcgen05-commit.ll b/llvm/test/CodeGen/NVPTX/tcgen05-commit.ll
index 51e3c65b9926d..a4ee0734c07f6 100644
--- a/llvm/test/CodeGen/NVPTX/tcgen05-commit.ll
+++ b/llvm/test/CodeGen/NVPTX/tcgen05-commit.ll
@@ -21,7 +21,7 @@ define void @test_tcgen05_commit_cg1(ptr %bar_addr) {
; CHECK_PTX64-NEXT: .reg .b64 %rd<2>;
; CHECK_PTX64-EMPTY:
; CHECK_PTX64-NEXT: // %bb.0:
-; CHECK_PTX64-NEXT: ld.param.b64 %rd1, [test_tcgen05_commit_cg1_param_0];
+; CHECK_PTX64-NEXT: ld.param::func.b64 %rd1, [test_tcgen05_commit_cg1_param_0];
; CHECK_PTX64-NEXT: tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.b64 [%rd1];
; CHECK_PTX64-NEXT: ret;
;
@@ -30,7 +30,7 @@ define void @test_tcgen05_commit_cg1(ptr %bar_addr) {
; CHECK_PTX64_SHARED32-NEXT: .reg .b64 %rd<2>;
; CHECK_PTX64_SHARED32-EMPTY:
; CHECK_PTX64_SHARED32-NEXT: // %bb.0:
-; CHECK_PTX64_SHARED32-NEXT: ld.param.b64 %rd1, [test_tcgen05_commit_cg1_param_0];
+; CHECK_PTX64_SHARED32-NEXT: ld.param::func.b64 %rd1, [test_tcgen05_commit_cg1_param_0];
; CHECK_PTX64_SHARED32-NEXT: tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.b64 [%rd1];
; CHECK_PTX64_SHARED32-NEXT: ret;
call void @llvm.nvvm.tcgen05.commit.cg1.p0(ptr %bar_addr)
@@ -44,7 +44,7 @@ define void @test_tcgen05_commit_cg2(ptr %bar_addr) {
; CHECK_PTX64-NEXT: .reg .b64 %rd<2>;
; CHECK_PTX64-EMPTY:
; CHECK_PTX64-NEXT: // %bb.0:
-; CHECK_PTX64-NEXT: ld.param.b64 %rd1, [test_tcgen05_commit_cg2_param_0];
+; CHECK_PTX64-NEXT: ld.param::func.b64 %rd1, [test_tcgen05_commit_cg2_param_0];
; CHECK_PTX64-NEXT: tcgen05.commit.cta_group::2.mbarrier::arrive::one.shared::cluster.b64 [%rd1];
; CHECK_PTX64-NEXT: ret;
;
@@ -53,7 +53,7 @@ define void @test_tcgen05_commit_cg2(ptr %bar_addr) {
; CHECK_PTX64_SHARED32-NEXT: .reg .b64 %rd<2>;
; CHECK_PTX64_SHARED32-EMPTY:
; CHECK_PTX64_SHARED32-NEXT: // %bb.0:
-; CHECK_PTX64_SHARED32-NEXT: ld.param.b64 %rd1, [test_tcgen05_commit_cg2_param_0];
+; CHECK_PTX64_SHARED32-NEXT: ld.param::func.b64 %rd1, [test_tcgen05_commit_cg2_param_0];
; CHECK_PTX64_SHARED32-NEXT: tcgen05.commit.cta_group::2.mbarrier::arrive::one.shared::cluster.b64 [%rd1];
; CHECK_PTX64_SHARED32-NEXT: ret;
call void @llvm.nvvm.tcgen05.commit.cg2.p0(ptr %bar_addr)
@@ -67,7 +67,7 @@ define void @test_tcgen05_commit_shared_cg1(ptr addrspace(3) %bar_addr) {
; CHECK_PTX64-NEXT: .reg .b64 %rd<2>;
; CHECK_PTX64-EMPTY:
; CHECK_PTX64-NEXT: // %bb.0:
-; CHECK_PTX64-NEXT: ld.param.b64 %rd1, [test_tcgen05_commit_shared_cg1_param_0];
+; CHECK_PTX64-NEXT: ld.param::func.b64 %rd1, [test_tcgen05_commit_shared_cg1_param_0];
; CHECK_PTX64-NEXT: tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.b64 [%rd1];
; CHECK_PTX64-NEXT: ret;
;
@@ -76,7 +76,7 @@ define void @test_tcgen05_commit_shared_cg1(ptr addrspace(3) %bar_addr) {
; CHECK_PTX64_SHARED32-NEXT: .reg .b32 %r<2>;
; CHECK_PTX64_SHARED32-EMPTY:
; CHECK_PTX64_SHARED32-NEXT: // %bb.0:
-; CHECK_PTX64_SHARED32-NEXT: ld.param.b32 %r1, [test_tcgen05_commit_shared_cg1_param_0];
+; CHECK_PTX64_SHARED32-NEXT: ld.param::func.b32 %r1, [test_tcgen05_commit_shared_cg1_param_0];
; CHECK_PTX64_SHARED32-NEXT: tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.b64 [%r1];
; CHECK_PTX64_SHARED32-NEXT: ret;
call void @llvm.nvvm.tcgen05.commit.cg1.p3(ptr addrspace(3) %bar_addr)
@@ -90,7 +90,7 @@ define void @test_tcgen05_commit_shared_cg2(ptr addrspace(3) %bar_addr) {
; CHECK_PTX64-NEXT: .reg .b64 %rd<2>;
; CHECK_PTX64-EMPTY:
; CHECK_PTX64-NEXT: // %bb.0:
-; CHECK_PTX64-NEXT: ld.param.b64 %rd1, [test_tcgen05_commit_shared_cg2_param_0];
+; CHECK_PTX64-NEXT: ld.param::func.b64 %rd1, [test_tcgen05_commit_shared_cg2_param_0];
; CHECK_PTX64-NEXT: tcgen05.commit.cta_group::2.mbarrier::arrive::one.shared::cluster.b64 [%rd1];
; CHECK_PTX64-NEXT: ret;
;
@@ -99,7 +99,7 @@ define void @test_tcgen05_commit_shared_cg2(ptr addrspace(3) %bar_addr) {
; CHECK_PTX64_SHARED32-NEXT: .reg .b32 %r<2>;
; CHECK_PTX64_SHARED32-EMPTY:
; CHECK_PTX64_SHARED32-NEXT: // %bb.0:
-; CHECK_PTX64_SHARED32-NEXT: ld.param.b32 %r1, [test_tcgen05_commit_shared_cg2_param_0];
+; CHECK_PTX64_SHARED32-NEXT: ld.param::func.b32 %r1, [test_tcgen05_commit_shared_cg2_param_0];
; CHECK_PTX64_SHARED32-NEXT: tcgen05.commit.cta_group::2.mbarrier::arrive::one.shared::cluster.b64 [%r1];
; CHECK_PTX64_SHARED32-NEXT: ret;
call void @llvm.nvvm.tcgen05.commit.cg2.p3(ptr addrspace(3) %bar_addr)
@@ -119,8 +119,8 @@ define void @test_tcgen05_commit_mc_cg1(ptr %bar_addr, i16 %cta_mask) {
; CHECK_PTX64-NEXT: .reg .b64 %rd<2>;
; CHECK_PTX64-EMPTY:
; CHECK_PTX64-NEXT: // %bb.0:
-; CHECK_PTX64-NEXT: ld.param.b64 %rd1, [test_tcgen05_commit_mc_cg1_param_0];
-; CHECK_PTX64-NEXT: ld.param.b16 %rs1, [test_tcgen05_commit_mc_cg1_param_1];
+; CHECK_PTX64-NEXT: ld.param::func.b64 %rd1, [test_tcgen05_commit_mc_cg1_param_0];
+; CHECK_PTX64-NEXT: ld.param::func.b16 %rs1, [test_tcgen05_commit_mc_cg1_param_1];
; CHECK_PTX64-NEXT: tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.multicast::cluster.b64 [%rd1], %rs1;
; CHECK_PTX64-NEXT: ret;
;
@@ -130,8 +130,8 @@ define void @test_tcgen05_commit_mc_cg1(ptr %bar_addr, i16 %cta_mask) {
; CHECK_PTX64_SHARED32-NEXT: .reg .b64 %rd<2>;
; CHECK_PTX64_SHARED32-EMPTY:
; CHECK_PTX64_SHARED32-NEXT: // %bb.0:
-; CHECK_PTX64_SHARED32-NEXT: ld.param.b64 %rd1, [test_tcgen05_commit_mc_cg1_param_0];
-; CHECK_PTX64_SHARED32-NEXT: ld.param.b16 %rs1, [test_tcgen05_commit_mc_cg1_param_1];
+; CHECK_PTX64_SHARED32-NEXT: ld.param::func.b64 %rd1, [test_tcgen05_commit_mc_cg1_param_0];
+; CHECK_PTX64_SHARED32-NEXT: ld.param::func.b16 %rs1, [test_tcgen05_commit_mc_cg1_param_1];
; CHECK_PTX64_SHARED32-NEXT: tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.multicast::cluster.b64 [%rd1], %rs1;
; CHECK_PTX64_SHARED32-NEXT: ret;
call void @llvm.nvvm.tcgen05.commit.mc.cg1.p0.i16(ptr %bar_addr, i16 %cta_mask)
@@ -145,8 +145,8 @@ define void @test_tcgen05_commit_mc_cg2(ptr %bar_addr, i16 %cta_mask) {
; CHECK_PTX64-NEXT: .reg .b64 %rd<2>;
; CHECK_PTX64-EMPTY:
; CHECK_PTX64-NEXT: // %bb.0:
-; CHECK_PTX64-NEXT: ld.param.b64 %rd1, [test_tcgen05_commit_mc_cg2_param_0];
-; CHECK_PTX64-NEXT: ld.param.b16 %rs1, [test_tcgen05_commit_mc_cg2_param_1];
+; CHECK_PTX64-NEXT: ld.param::func.b64 %rd1, [test_tcgen05_commit_mc_cg2_param_0];
+; CHECK_PTX64-NEXT: ld.param::func.b16 %rs1, [test_tcgen05_commit_mc_cg2_param_1];
; CHECK_PTX64-NEXT: tcgen05.commit.cta_group::2.mbarrier::arrive::one.shared::cluster.multicast::cluster.b64 [%rd1], %rs1;
; CHECK_PTX64-NEXT: ret;
;
@@ -156,8 +156,8 @@ define void @test_tcgen05_commit_mc_cg2(ptr %bar_addr, i16 %cta_mask) {
; CHECK_PTX64_SHARED32-NEXT: .reg .b64 %rd<2>;
; CHECK_PTX64_SHARED32-EMPTY:
; CHECK_PTX64_SHARED32-NEXT: // %bb.0:
-; CHECK_PTX64_SHARED32-NEXT: ld.param.b64 %rd1, [test_tcgen05_commit_mc_cg2_param_0];
-; CHECK_PTX64_SHARED32-NEXT: ld.param.b16 %rs1, [test_tcgen05_commit_mc_cg2_param_1];
+; CHECK_PTX64_SHARED32-NEXT: ld.param::func.b64 %rd1, [test_tcgen05_commit_mc_cg2_param_0];
+; CHECK_PTX64_SHARED32-NEXT: ld.param::func.b16 %rs1, [test_tcgen05_commit_mc_cg2_param_1];
; CHECK_PTX64_SHARED32-NEXT: tcgen05.commit.cta_group::2.mbarrier::arrive::one.shared::cluster.multicast::cluster.b64 [%rd1], %rs1;
; CHECK_PTX64_SHARED32-NEXT: ret;
call void @llvm.nvvm.tcgen05.commit.mc.cg2.p0.i16(ptr %bar_addr, i16 %cta_mask)
@@ -171,8 +171,8 @@ define void @test_tcgen05_commit_mc_shared_cg1(ptr addrspace(3) %bar_addr, i16 %
; CHECK_PTX64-NEXT: .reg .b64 %rd<2>;
; CHECK_PTX64-EMPTY:
; CHECK_PTX64-NEXT: // %bb.0:
-; CHECK_PTX64-NEXT: ld.param.b64 %rd1, [test_tcgen05_commit_mc_shared_cg1_param_0];
-; CHECK_PTX64-NEXT: ld.param.b16 %rs1, [test_tcgen05_commit_mc_shared_cg1_param_1];
+; CHECK_PTX64-NEXT: ld.param::func.b64 %rd1, [test_tcgen05_commit_mc_shared_cg1_param_0];
+; CHECK_PTX64-NEXT: ld.param::func.b16 %rs1, [test_tcgen05_commit_mc_shared_cg1_param_1];
; CHECK_PTX64-NEXT: tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.multicast::cluster.b64 [%rd1], %rs1;
; CHECK_PTX64-NEXT: ret;
;
@@ -182,8 +182,8 @@ define void @test_tcgen05_commit_mc_shared_cg1(ptr addrspace(3) %bar_addr, i16 %
; CHECK_PTX64_SHARED32-NEXT: .reg .b32 %r<2>;
; CHECK_PTX64_SHARED32-EMPTY:
; CHECK_PTX64_SHARED32-NEXT: // %bb.0:
-; CHECK_PTX64_SHARED32-NEXT: ld.param.b32 %r1, [test_tcgen05_commit_mc_shared_cg1_param_0];
-; CHECK_PTX64_SHARED32-NEXT: ld.param.b16 %rs1, [test_tcgen05_commit_mc_shared_cg1_param_1];
+; CHECK_PTX64_SHARED32-NEXT: ld.param::func.b32 %r1, [test_tcgen05_commit_mc_shared_cg1_param_0];
+; CHECK_PTX64_SHARED32-NEXT: ld.param::func.b16 %rs1, [test_tcgen05_commit_mc_shared_cg1_param_1];
; CHECK_PTX64_SHARED32-NEXT: tcgen05.commit.cta_group::1.mbarrier::arrive::one.shared::cluster.multicast::cluster.b64 [%r1], %rs1;
; CHECK_PTX64_SHARED32-NEXT: ret;
call void @llvm.nvvm.tcgen05.commit.mc.cg1.p3.i16(ptr addrspace(3) %bar_addr, i16 %cta_mask)
@@ -197,8 +197,8 @@ define void @test_tcgen05_commit_mc_shared_cg2(ptr addrspace(3) %bar_addr, i16 %
; CHECK_PTX64-NEXT: .reg .b64 %rd<2>;
; CHECK_PTX64-EMPTY:
; CHECK_PTX64-NEXT: // %bb.0:
-; CHECK_PTX64-NEXT: ld.param.b64 %rd1, [test_tcgen05_commit_mc_shared_cg2_param_0];
-; CHECK_PTX64-NEXT: ld.param.b16 %rs1, [test_tcgen05_commit_mc_shared_cg2_param_1];
+; CHECK_PTX64-NEXT: ld.param::func.b64 %rd1, [test_tcgen05_commit_mc_shared_cg2_param_0];
+; CHECK_PTX64-NEXT: ld.param::func.b16 %rs1, [test_tcgen05_commit_mc_shared_cg2_param_1];
; CHECK_PTX64-NEXT: tcgen05.commit.cta_group::2.mbarrier::arrive::one.shared::cluster.multicast::cluster.b64 [%rd1], %rs1;
; CHECK_PTX64-NEXT: ret;
;
@@ -208,8 +208,8 @@ define void @test_tcgen05_commit_mc_shared_cg2(ptr addrspace(3) %bar_addr, i16 %
; CHECK_PTX64_SHARED32-NEXT: .reg .b32 %r<2>;
; CHECK_PTX64_SHARED32-EMPTY:
; CHECK_PTX64_SHARED32-NEXT: // %bb.0:
-; CHECK_PTX64_SHARED32-NEXT: ld.param.b32 %r1, [test_tcgen05_commit_mc_shared_cg2_param_0];
-; CHECK_PTX64_SHARED32-NEXT: ld.param.b16 %rs1, [test_tcgen05_commit_mc_shared_cg2_param_1];
+; CHECK_PTX64_SHARED32-NEXT: ld.param::func.b32 %r1, [test_tcgen05_commit_mc_shared_cg2_param_0];
+; CHECK_PTX64_SHARED32-NEXT: ld.param::func.b16 %rs1, [test_tcgen05_commit_mc_shared_cg2_param_1];
; CHECK_PTX64_SHARED32-NEXT: tcgen05.commit.cta_group::2.mbarrier::arrive::one.shared::cluster.multicast::cluster.b64 [%r1], %rs1;
; CHECK_PTX64_SHARED32-NEXT: ret;
call void @llvm.nvvm.tcgen05.commit.mc.cg2.p3.i16(ptr addrspace(3) %bar_addr, i16 %cta_mask)
diff --git a/llvm/test/CodeGen/NVPTX/tcgen05-cp.ll b/llvm/test/CodeGen/NVPTX/tcgen05-cp.ll
index 4e463a14e7537..10b47a4d8008c 100644
--- a/llvm/test/CodeGen/NVPTX/tcgen05-cp.ll
+++ b/llvm/test/CodeGen/NVPTX/tcgen05-cp.ll
@@ -15,8 +15,8 @@ define void @test_tcgen05_cp_64x128_v1_cg1(ptr addrspace(6) %addr, i64 %sdesc) {
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [test_tcgen05_cp_64x128_v1_cg1_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [test_tcgen05_cp_64x128_v1_cg1_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_tcgen05_cp_64x128_v1_cg1_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_tcgen05_cp_64x128_v1_cg1_param_1];
; CHECK-NEXT: tcgen05.cp.cta_group::1.64x128b.warpx2::02_13 [%r1], %rd1;
; CHECK-NEXT: ret;
call void @llvm.nvvm.tcgen05.cp.64x128b_warpx2_02_13.cg1(ptr addrspace(6) %addr, i64 %sdesc)
@@ -31,8 +31,8 @@ define void @test_tcgen05_cp_64x128_v1_cg2(ptr addrspace(6) %addr, i64 %sdesc) {
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [test_tcgen05_cp_64x128_v1_cg2_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [test_tcgen05_cp_64x128_v1_cg2_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_tcgen05_cp_64x128_v1_cg2_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_tcgen05_cp_64x128_v1_cg2_param_1];
; CHECK-NEXT: tcgen05.cp.cta_group::2.64x128b.warpx2::02_13 [%r1], %rd1;
; CHECK-NEXT: ret;
call void @llvm.nvvm.tcgen05.cp.64x128b_warpx2_02_13.cg2(ptr addrspace(6) %addr, i64 %sdesc)
@@ -47,8 +47,8 @@ define void @test_tcgen05_cp_64x128_v2_cg1(ptr addrspace(6) %addr, i64 %sdesc) {
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [test_tcgen05_cp_64x128_v2_cg1_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [test_tcgen05_cp_64x128_v2_cg1_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_tcgen05_cp_64x128_v2_cg1_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_tcgen05_cp_64x128_v2_cg1_param_1];
; CHECK-NEXT: tcgen05.cp.cta_group::1.64x128b.warpx2::01_23 [%r1], %rd1;
; CHECK-NEXT: ret;
call void @llvm.nvvm.tcgen05.cp.64x128b_warpx2_01_23.cg1(ptr addrspace(6) %addr, i64 %sdesc)
@@ -63,8 +63,8 @@ define void @test_tcgen05_cp_64x128_v2_cg2(ptr addrspace(6) %addr, i64 %sdesc) {
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [test_tcgen05_cp_64x128_v2_cg2_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [test_tcgen05_cp_64x128_v2_cg2_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_tcgen05_cp_64x128_v2_cg2_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_tcgen05_cp_64x128_v2_cg2_param_1];
; CHECK-NEXT: tcgen05.cp.cta_group::2.64x128b.warpx2::01_23 [%r1], %rd1;
; CHECK-NEXT: ret;
call void @llvm.nvvm.tcgen05.cp.64x128b_warpx2_01_23.cg2(ptr addrspace(6) %addr, i64 %sdesc)
@@ -79,8 +79,8 @@ define void @test_tcgen05_cp_32x128_cg1(ptr addrspace(6) %addr, i64 %sdesc) {
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [test_tcgen05_cp_32x128_cg1_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [test_tcgen05_cp_32x128_cg1_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_tcgen05_cp_32x128_cg1_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_tcgen05_cp_32x128_cg1_param_1];
; CHECK-NEXT: tcgen05.cp.cta_group::1.32x128b.warpx4 [%r1], %rd1;
; CHECK-NEXT: ret;
call void @llvm.nvvm.tcgen05.cp.32x128b_warpx4.cg1(ptr addrspace(6) %addr, i64 %sdesc)
@@ -95,8 +95,8 @@ define void @test_tcgen05_cp_32x128_cg2(ptr addrspace(6) %addr, i64 %sdesc) {
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [test_tcgen05_cp_32x128_cg2_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [test_tcgen05_cp_32x128_cg2_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_tcgen05_cp_32x128_cg2_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_tcgen05_cp_32x128_cg2_param_1];
; CHECK-NEXT: tcgen05.cp.cta_group::2.32x128b.warpx4 [%r1], %rd1;
; CHECK-NEXT: ret;
call void @llvm.nvvm.tcgen05.cp.32x128b_warpx4.cg2(ptr addrspace(6) %addr, i64 %sdesc)
@@ -112,8 +112,8 @@ define void @test_tcgen05_cp_128x128b_cg1(ptr addrspace(6) %addr, i64 %sdesc) {
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [test_tcgen05_cp_128x128b_cg1_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [test_tcgen05_cp_128x128b_cg1_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_tcgen05_cp_128x128b_cg1_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_tcgen05_cp_128x128b_cg1_param_1];
; CHECK-NEXT: tcgen05.cp.cta_group::1.128x128b [%r1], %rd1;
; CHECK-NEXT: ret;
call void @llvm.nvvm.tcgen05.cp.128x128b.cg1(ptr addrspace(6) %addr, i64 %sdesc)
@@ -128,8 +128,8 @@ define void @test_tcgen05_cp_128x128b_cg2(ptr addrspace(6) %addr, i64 %sdesc) {
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [test_tcgen05_cp_128x128b_cg2_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [test_tcgen05_cp_128x128b_cg2_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_tcgen05_cp_128x128b_cg2_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_tcgen05_cp_128x128b_cg2_param_1];
; CHECK-NEXT: tcgen05.cp.cta_group::2.128x128b [%r1], %rd1;
; CHECK-NEXT: ret;
call void @llvm.nvvm.tcgen05.cp.128x128b.cg2(ptr addrspace(6) %addr, i64 %sdesc)
@@ -144,8 +144,8 @@ define void @test_tcgen05_cp_128x256b_cg1(ptr addrspace(6) %addr, i64 %sdesc) {
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [test_tcgen05_cp_128x256b_cg1_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [test_tcgen05_cp_128x256b_cg1_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_tcgen05_cp_128x256b_cg1_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_tcgen05_cp_128x256b_cg1_param_1];
; CHECK-NEXT: tcgen05.cp.cta_group::1.128x256b [%r1], %rd1;
; CHECK-NEXT: ret;
call void @llvm.nvvm.tcgen05.cp.128x256b.cg1(ptr addrspace(6) %addr, i64 %sdesc)
@@ -160,8 +160,8 @@ define void @test_tcgen05_cp_128x256b_cg2(ptr addrspace(6) %addr, i64 %sdesc) {
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [test_tcgen05_cp_128x256b_cg2_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [test_tcgen05_cp_128x256b_cg2_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_tcgen05_cp_128x256b_cg2_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_tcgen05_cp_128x256b_cg2_param_1];
; CHECK-NEXT: tcgen05.cp.cta_group::2.128x256b [%r1], %rd1;
; CHECK-NEXT: ret;
call void @llvm.nvvm.tcgen05.cp.128x256b.cg2(ptr addrspace(6) %addr, i64 %sdesc)
@@ -176,8 +176,8 @@ define void @test_tcgen05_cp_4x256b_cg1(ptr addrspace(6) %addr, i64 %sdesc) {
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [test_tcgen05_cp_4x256b_cg1_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [test_tcgen05_cp_4x256b_cg1_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_tcgen05_cp_4x256b_cg1_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_tcgen05_cp_4x256b_cg1_param_1];
; CHECK-NEXT: tcgen05.cp.cta_group::1.4x256b [%r1], %rd1;
; CHECK-NEXT: ret;
call void @llvm.nvvm.tcgen05.cp.4x256b.cg1(ptr addrspace(6) %addr, i64 %sdesc)
@@ -192,8 +192,8 @@ define void @test_tcgen05_cp_4x256b_cg2(ptr addrspace(6) %addr, i64 %sdesc) {
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [test_tcgen05_cp_4x256b_cg2_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [test_tcgen05_cp_4x256b_cg2_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_tcgen05_cp_4x256b_cg2_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_tcgen05_cp_4x256b_cg2_param_1];
; CHECK-NEXT: tcgen05.cp.cta_group::2.4x256b [%r1], %rd1;
; CHECK-NEXT: ret;
call void @llvm.nvvm.tcgen05.cp.4x256b.cg2(ptr addrspace(6) %addr, i64 %sdesc)
@@ -209,8 +209,8 @@ define void @test_tcgen05_cp_128x256b_b6x16_p32_cg1(ptr addrspace(6) %addr, i64
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [test_tcgen05_cp_128x256b_b6x16_p32_cg1_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [test_tcgen05_cp_128x256b_b6x16_p32_cg1_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_tcgen05_cp_128x256b_b6x16_p32_cg1_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_tcgen05_cp_128x256b_b6x16_p32_cg1_param_1];
; CHECK-NEXT: tcgen05.cp.cta_group::1.128x256b.b8x16.b6x16_p32 [%r1], %rd1;
; CHECK-NEXT: ret;
call void @llvm.nvvm.tcgen05.cp.128x256b.b6x16_p32.cg1(ptr addrspace(6) %addr, i64 %sdesc)
@@ -225,8 +225,8 @@ define void @test_tcgen05_cp_128x256b_b6x16_p32_cg2(ptr addrspace(6) %addr, i64
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [test_tcgen05_cp_128x256b_b6x16_p32_cg2_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [test_tcgen05_cp_128x256b_b6x16_p32_cg2_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_tcgen05_cp_128x256b_b6x16_p32_cg2_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_tcgen05_cp_128x256b_b6x16_p32_cg2_param_1];
; CHECK-NEXT: tcgen05.cp.cta_group::2.128x256b.b8x16.b6x16_p32 [%r1], %rd1;
; CHECK-NEXT: ret;
call void @llvm.nvvm.tcgen05.cp.128x256b.b6x16_p32.cg2(ptr addrspace(6) %addr, i64 %sdesc)
@@ -241,8 +241,8 @@ define void @test_tcgen05_cp_4x256b_b6x16_p32_cg1(ptr addrspace(6) %addr, i64 %s
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [test_tcgen05_cp_4x256b_b6x16_p32_cg1_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [test_tcgen05_cp_4x256b_b6x16_p32_cg1_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_tcgen05_cp_4x256b_b6x16_p32_cg1_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_tcgen05_cp_4x256b_b6x16_p32_cg1_param_1];
; CHECK-NEXT: tcgen05.cp.cta_group::1.4x256b.b8x16.b6x16_p32 [%r1], %rd1;
; CHECK-NEXT: ret;
call void @llvm.nvvm.tcgen05.cp.4x256b.b6x16_p32.cg1(ptr addrspace(6) %addr, i64 %sdesc)
@@ -257,8 +257,8 @@ define void @test_tcgen05_cp_4x256b_b6x16_p32_cg2(ptr addrspace(6) %addr, i64 %s
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [test_tcgen05_cp_4x256b_b6x16_p32_cg2_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [test_tcgen05_cp_4x256b_b6x16_p32_cg2_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_tcgen05_cp_4x256b_b6x16_p32_cg2_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_tcgen05_cp_4x256b_b6x16_p32_cg2_param_1];
; CHECK-NEXT: tcgen05.cp.cta_group::2.4x256b.b8x16.b6x16_p32 [%r1], %rd1;
; CHECK-NEXT: ret;
call void @llvm.nvvm.tcgen05.cp.4x256b.b6x16_p32.cg2(ptr addrspace(6) %addr, i64 %sdesc)
@@ -273,8 +273,8 @@ define void @test_tcgen05_cp_128x128b_b6x16_p32_cg1(ptr addrspace(6) %addr, i64
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [test_tcgen05_cp_128x128b_b6x16_p32_cg1_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [test_tcgen05_cp_128x128b_b6x16_p32_cg1_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_tcgen05_cp_128x128b_b6x16_p32_cg1_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_tcgen05_cp_128x128b_b6x16_p32_cg1_param_1];
; CHECK-NEXT: tcgen05.cp.cta_group::1.128x128b.b8x16.b6x16_p32 [%r1], %rd1;
; CHECK-NEXT: ret;
call void @llvm.nvvm.tcgen05.cp.128x128b.b6x16_p32.cg1(ptr addrspace(6) %addr, i64 %sdesc)
@@ -289,8 +289,8 @@ define void @test_tcgen05_cp_128x128b_b6x16_p32_cg2(ptr addrspace(6) %addr, i64
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [test_tcgen05_cp_128x128b_b6x16_p32_cg2_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [test_tcgen05_cp_128x128b_b6x16_p32_cg2_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_tcgen05_cp_128x128b_b6x16_p32_cg2_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_tcgen05_cp_128x128b_b6x16_p32_cg2_param_1];
; CHECK-NEXT: tcgen05.cp.cta_group::2.128x128b.b8x16.b6x16_p32 [%r1], %rd1;
; CHECK-NEXT: ret;
call void @llvm.nvvm.tcgen05.cp.128x128b.b6x16_p32.cg2(ptr addrspace(6) %addr, i64 %sdesc)
@@ -305,8 +305,8 @@ define void @test_tcgen05_cp_64x128_v1_b6x16_p32_cg1(ptr addrspace(6) %addr, i64
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [test_tcgen05_cp_64x128_v1_b6x16_p32_cg1_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [test_tcgen05_cp_64x128_v1_b6x16_p32_cg1_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_tcgen05_cp_64x128_v1_b6x16_p32_cg1_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_tcgen05_cp_64x128_v1_b6x16_p32_cg1_param_1];
; CHECK-NEXT: tcgen05.cp.cta_group::1.64x128b.warpx2::02_13.b8x16.b6x16_p32 [%r1], %rd1;
; CHECK-NEXT: ret;
call void @llvm.nvvm.tcgen05.cp.64x128b_warpx2_02_13.b6x16_p32.cg1(ptr addrspace(6) %addr, i64 %sdesc)
@@ -321,8 +321,8 @@ define void @test_tcgen05_cp_64x128_v1_b6x16_p32_cg2(ptr addrspace(6) %addr, i64
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [test_tcgen05_cp_64x128_v1_b6x16_p32_cg2_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [test_tcgen05_cp_64x128_v1_b6x16_p32_cg2_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_tcgen05_cp_64x128_v1_b6x16_p32_cg2_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_tcgen05_cp_64x128_v1_b6x16_p32_cg2_param_1];
; CHECK-NEXT: tcgen05.cp.cta_group::2.64x128b.warpx2::02_13.b8x16.b6x16_p32 [%r1], %rd1;
; CHECK-NEXT: ret;
call void @llvm.nvvm.tcgen05.cp.64x128b_warpx2_02_13.b6x16_p32.cg2(ptr addrspace(6) %addr, i64 %sdesc)
@@ -337,8 +337,8 @@ define void @test_tcgen05_cp_64x128_v2_b6x16_p32_cg1(ptr addrspace(6) %addr, i64
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [test_tcgen05_cp_64x128_v2_b6x16_p32_cg1_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [test_tcgen05_cp_64x128_v2_b6x16_p32_cg1_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_tcgen05_cp_64x128_v2_b6x16_p32_cg1_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_tcgen05_cp_64x128_v2_b6x16_p32_cg1_param_1];
; CHECK-NEXT: tcgen05.cp.cta_group::1.64x128b.warpx2::01_23.b8x16.b6x16_p32 [%r1], %rd1;
; CHECK-NEXT: ret;
call void @llvm.nvvm.tcgen05.cp.64x128b_warpx2_01_23.b6x16_p32.cg1(ptr addrspace(6) %addr, i64 %sdesc)
@@ -353,8 +353,8 @@ define void @test_tcgen05_cp_64x128_v2_b6x16_p32_cg2(ptr addrspace(6) %addr, i64
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [test_tcgen05_cp_64x128_v2_b6x16_p32_cg2_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [test_tcgen05_cp_64x128_v2_b6x16_p32_cg2_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_tcgen05_cp_64x128_v2_b6x16_p32_cg2_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_tcgen05_cp_64x128_v2_b6x16_p32_cg2_param_1];
; CHECK-NEXT: tcgen05.cp.cta_group::2.64x128b.warpx2::01_23.b8x16.b6x16_p32 [%r1], %rd1;
; CHECK-NEXT: ret;
call void @llvm.nvvm.tcgen05.cp.64x128b_warpx2_01_23.b6x16_p32.cg2(ptr addrspace(6) %addr, i64 %sdesc)
@@ -369,8 +369,8 @@ define void @test_tcgen05_cp_32x128_b6x16_p32_cg1(ptr addrspace(6) %addr, i64 %s
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [test_tcgen05_cp_32x128_b6x16_p32_cg1_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [test_tcgen05_cp_32x128_b6x16_p32_cg1_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_tcgen05_cp_32x128_b6x16_p32_cg1_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_tcgen05_cp_32x128_b6x16_p32_cg1_param_1];
; CHECK-NEXT: tcgen05.cp.cta_group::1.32x128b.warpx4.b8x16.b6x16_p32 [%r1], %rd1;
; CHECK-NEXT: ret;
call void @llvm.nvvm.tcgen05.cp.32x128b_warpx4.b6x16_p32.cg1(ptr addrspace(6) %addr, i64 %sdesc)
@@ -385,8 +385,8 @@ define void @test_tcgen05_cp_32x128_b6x16_p32_cg2(ptr addrspace(6) %addr, i64 %s
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [test_tcgen05_cp_32x128_b6x16_p32_cg2_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [test_tcgen05_cp_32x128_b6x16_p32_cg2_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_tcgen05_cp_32x128_b6x16_p32_cg2_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_tcgen05_cp_32x128_b6x16_p32_cg2_param_1];
; CHECK-NEXT: tcgen05.cp.cta_group::2.32x128b.warpx4.b8x16.b6x16_p32 [%r1], %rd1;
; CHECK-NEXT: ret;
call void @llvm.nvvm.tcgen05.cp.32x128b_warpx4.b6x16_p32.cg2(ptr addrspace(6) %addr, i64 %sdesc)
@@ -402,8 +402,8 @@ define void @test_tcgen05_cp_128x256b_b4x16_p64_cg1(ptr addrspace(6) %addr, i64
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [test_tcgen05_cp_128x256b_b4x16_p64_cg1_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [test_tcgen05_cp_128x256b_b4x16_p64_cg1_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_tcgen05_cp_128x256b_b4x16_p64_cg1_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_tcgen05_cp_128x256b_b4x16_p64_cg1_param_1];
; CHECK-NEXT: tcgen05.cp.cta_group::1.128x256b.b8x16.b4x16_p64 [%r1], %rd1;
; CHECK-NEXT: ret;
call void @llvm.nvvm.tcgen05.cp.128x256b.b4x16_p64.cg1(ptr addrspace(6) %addr, i64 %sdesc)
@@ -418,8 +418,8 @@ define void @test_tcgen05_cp_128x256b_b4x16_p64_cg2(ptr addrspace(6) %addr, i64
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [test_tcgen05_cp_128x256b_b4x16_p64_cg2_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [test_tcgen05_cp_128x256b_b4x16_p64_cg2_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_tcgen05_cp_128x256b_b4x16_p64_cg2_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_tcgen05_cp_128x256b_b4x16_p64_cg2_param_1];
; CHECK-NEXT: tcgen05.cp.cta_group::2.128x256b.b8x16.b4x16_p64 [%r1], %rd1;
; CHECK-NEXT: ret;
call void @llvm.nvvm.tcgen05.cp.128x256b.b4x16_p64.cg2(ptr addrspace(6) %addr, i64 %sdesc)
@@ -434,8 +434,8 @@ define void @test_tcgen05_cp_4x256b_b4x16_p64_cg1(ptr addrspace(6) %addr, i64 %s
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [test_tcgen05_cp_4x256b_b4x16_p64_cg1_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [test_tcgen05_cp_4x256b_b4x16_p64_cg1_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_tcgen05_cp_4x256b_b4x16_p64_cg1_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_tcgen05_cp_4x256b_b4x16_p64_cg1_param_1];
; CHECK-NEXT: tcgen05.cp.cta_group::1.4x256b.b8x16.b4x16_p64 [%r1], %rd1;
; CHECK-NEXT: ret;
call void @llvm.nvvm.tcgen05.cp.4x256b.b4x16_p64.cg1(ptr addrspace(6) %addr, i64 %sdesc)
@@ -450,8 +450,8 @@ define void @test_tcgen05_cp_4x256b_b4x16_p64_cg2(ptr addrspace(6) %addr, i64 %s
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [test_tcgen05_cp_4x256b_b4x16_p64_cg2_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [test_tcgen05_cp_4x256b_b4x16_p64_cg2_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_tcgen05_cp_4x256b_b4x16_p64_cg2_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_tcgen05_cp_4x256b_b4x16_p64_cg2_param_1];
; CHECK-NEXT: tcgen05.cp.cta_group::2.4x256b.b8x16.b4x16_p64 [%r1], %rd1;
; CHECK-NEXT: ret;
call void @llvm.nvvm.tcgen05.cp.4x256b.b4x16_p64.cg2(ptr addrspace(6) %addr, i64 %sdesc)
@@ -466,8 +466,8 @@ define void @test_tcgen05_cp_128x128b_b4x16_p64_cg1(ptr addrspace(6) %addr, i64
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [test_tcgen05_cp_128x128b_b4x16_p64_cg1_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [test_tcgen05_cp_128x128b_b4x16_p64_cg1_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_tcgen05_cp_128x128b_b4x16_p64_cg1_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_tcgen05_cp_128x128b_b4x16_p64_cg1_param_1];
; CHECK-NEXT: tcgen05.cp.cta_group::1.128x128b.b8x16.b4x16_p64 [%r1], %rd1;
; CHECK-NEXT: ret;
call void @llvm.nvvm.tcgen05.cp.128x128b.b4x16_p64.cg1(ptr addrspace(6) %addr, i64 %sdesc)
@@ -482,8 +482,8 @@ define void @test_tcgen05_cp_128x128b_b4x16_p64_cg2(ptr addrspace(6) %addr, i64
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [test_tcgen05_cp_128x128b_b4x16_p64_cg2_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [test_tcgen05_cp_128x128b_b4x16_p64_cg2_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_tcgen05_cp_128x128b_b4x16_p64_cg2_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_tcgen05_cp_128x128b_b4x16_p64_cg2_param_1];
; CHECK-NEXT: tcgen05.cp.cta_group::2.128x128b.b8x16.b4x16_p64 [%r1], %rd1;
; CHECK-NEXT: ret;
call void @llvm.nvvm.tcgen05.cp.128x128b.b4x16_p64.cg2(ptr addrspace(6) %addr, i64 %sdesc)
@@ -498,8 +498,8 @@ define void @test_tcgen05_cp_64x128_v1_b4x16_p64_cg1(ptr addrspace(6) %addr, i64
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [test_tcgen05_cp_64x128_v1_b4x16_p64_cg1_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [test_tcgen05_cp_64x128_v1_b4x16_p64_cg1_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_tcgen05_cp_64x128_v1_b4x16_p64_cg1_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_tcgen05_cp_64x128_v1_b4x16_p64_cg1_param_1];
; CHECK-NEXT: tcgen05.cp.cta_group::1.64x128b.warpx2::02_13.b8x16.b4x16_p64 [%r1], %rd1;
; CHECK-NEXT: ret;
call void @llvm.nvvm.tcgen05.cp.64x128b_warpx2_02_13.b4x16_p64.cg1(ptr addrspace(6) %addr, i64 %sdesc)
@@ -514,8 +514,8 @@ define void @test_tcgen05_cp_64x128_v1_b4x16_p64_cg2(ptr addrspace(6) %addr, i64
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [test_tcgen05_cp_64x128_v1_b4x16_p64_cg2_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [test_tcgen05_cp_64x128_v1_b4x16_p64_cg2_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_tcgen05_cp_64x128_v1_b4x16_p64_cg2_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_tcgen05_cp_64x128_v1_b4x16_p64_cg2_param_1];
; CHECK-NEXT: tcgen05.cp.cta_group::2.64x128b.warpx2::02_13.b8x16.b4x16_p64 [%r1], %rd1;
; CHECK-NEXT: ret;
call void @llvm.nvvm.tcgen05.cp.64x128b_warpx2_02_13.b4x16_p64.cg2(ptr addrspace(6) %addr, i64 %sdesc)
@@ -530,8 +530,8 @@ define void @test_tcgen05_cp_64x128_v2_b4x16_p64_cg1(ptr addrspace(6) %addr, i64
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [test_tcgen05_cp_64x128_v2_b4x16_p64_cg1_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [test_tcgen05_cp_64x128_v2_b4x16_p64_cg1_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_tcgen05_cp_64x128_v2_b4x16_p64_cg1_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_tcgen05_cp_64x128_v2_b4x16_p64_cg1_param_1];
; CHECK-NEXT: tcgen05.cp.cta_group::1.64x128b.warpx2::01_23.b8x16.b4x16_p64 [%r1], %rd1;
; CHECK-NEXT: ret;
call void @llvm.nvvm.tcgen05.cp.64x128b_warpx2_01_23.b4x16_p64.cg1(ptr addrspace(6) %addr, i64 %sdesc)
@@ -546,8 +546,8 @@ define void @test_tcgen05_cp_64x128_v2_b4x16_p64_cg2(ptr addrspace(6) %addr, i64
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [test_tcgen05_cp_64x128_v2_b4x16_p64_cg2_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [test_tcgen05_cp_64x128_v2_b4x16_p64_cg2_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_tcgen05_cp_64x128_v2_b4x16_p64_cg2_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_tcgen05_cp_64x128_v2_b4x16_p64_cg2_param_1];
; CHECK-NEXT: tcgen05.cp.cta_group::2.64x128b.warpx2::01_23.b8x16.b4x16_p64 [%r1], %rd1;
; CHECK-NEXT: ret;
call void @llvm.nvvm.tcgen05.cp.64x128b_warpx2_01_23.b4x16_p64.cg2(ptr addrspace(6) %addr, i64 %sdesc)
@@ -562,8 +562,8 @@ define void @test_tcgen05_cp_32x128_b4x16_p64_cg1(ptr addrspace(6) %addr, i64 %s
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [test_tcgen05_cp_32x128_b4x16_p64_cg1_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [test_tcgen05_cp_32x128_b4x16_p64_cg1_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_tcgen05_cp_32x128_b4x16_p64_cg1_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_tcgen05_cp_32x128_b4x16_p64_cg1_param_1];
; CHECK-NEXT: tcgen05.cp.cta_group::1.32x128b.warpx4.b8x16.b4x16_p64 [%r1], %rd1;
; CHECK-NEXT: ret;
call void @llvm.nvvm.tcgen05.cp.32x128b_warpx4.b4x16_p64.cg1(ptr addrspace(6) %addr, i64 %sdesc)
@@ -578,8 +578,8 @@ define void @test_tcgen05_cp_32x128_b4x16_p64_cg2(ptr addrspace(6) %addr, i64 %s
; CHECK-NEXT: .reg .b64 %rd<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [test_tcgen05_cp_32x128_b4x16_p64_cg2_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [test_tcgen05_cp_32x128_b4x16_p64_cg2_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_tcgen05_cp_32x128_b4x16_p64_cg2_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [test_tcgen05_cp_32x128_b4x16_p64_cg2_param_1];
; CHECK-NEXT: tcgen05.cp.cta_group::2.32x128b.warpx4.b8x16.b4x16_p64 [%r1], %rd1;
; CHECK-NEXT: ret;
call void @llvm.nvvm.tcgen05.cp.32x128b_warpx4.b4x16_p64.cg2(ptr addrspace(6) %addr, i64 %sdesc)
diff --git a/llvm/test/CodeGen/NVPTX/tcgen05-ld-red.ll b/llvm/test/CodeGen/NVPTX/tcgen05-ld-red.ll
index 229d30d9c640c..cf69744700d67 100644
--- a/llvm/test/CodeGen/NVPTX/tcgen05-ld-red.ll
+++ b/llvm/test/CodeGen/NVPTX/tcgen05-ld-red.ll
@@ -14,7 +14,7 @@ define void @nvvm_tcgen05_ld_32x32b_min_i32(ptr addrspace(6) %taddr) {
; CHECK-NEXT: .reg .b32 %r<263>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [nvvm_tcgen05_ld_32x32b_min_i32_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r1, [nvvm_tcgen05_ld_32x32b_min_i32_param_0];
; CHECK-NEXT: tcgen05.ld.red.sync.aligned.32x32b.x2.min.u32 {%r2, %r3}, %r4, [%r1];
; CHECK-NEXT: tcgen05.ld.red.sync.aligned.32x32b.x4.min.u32 {%r5, %r6, %r7, %r8}, %r9, [%r1];
; CHECK-NEXT: tcgen05.ld.red.sync.aligned.32x32b.x8.min.u32 {%r10, %r11, %r12, %r13, %r14, %r15, %r16, %r17}, %r18, [%r1];
@@ -39,7 +39,7 @@ define void @nvvm_tcgen05_ld_32x32b_max_i32(ptr addrspace(6) %taddr) {
; CHECK-NEXT: .reg .b32 %r<263>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [nvvm_tcgen05_ld_32x32b_max_i32_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r1, [nvvm_tcgen05_ld_32x32b_max_i32_param_0];
; CHECK-NEXT: tcgen05.ld.red.sync.aligned.32x32b.x2.max.u32 {%r2, %r3}, %r4, [%r1];
; CHECK-NEXT: tcgen05.ld.red.sync.aligned.32x32b.x4.max.u32 {%r5, %r6, %r7, %r8}, %r9, [%r1];
; CHECK-NEXT: tcgen05.ld.red.sync.aligned.32x32b.x8.max.u32 {%r10, %r11, %r12, %r13, %r14, %r15, %r16, %r17}, %r18, [%r1];
@@ -64,7 +64,7 @@ define void @nvvm_tcgen05_ld_16x32bx2_min_i32(ptr addrspace(6) %taddr) {
; CHECK-NEXT: .reg .b32 %r<263>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [nvvm_tcgen05_ld_16x32bx2_min_i32_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r1, [nvvm_tcgen05_ld_16x32bx2_min_i32_param_0];
; CHECK-NEXT: tcgen05.ld.red.sync.aligned.16x32bx2.x2.min.u32 {%r2, %r3}, %r4, [%r1], 0;
; CHECK-NEXT: tcgen05.ld.red.sync.aligned.16x32bx2.x4.min.u32 {%r5, %r6, %r7, %r8}, %r9, [%r1], 0;
; CHECK-NEXT: tcgen05.ld.red.sync.aligned.16x32bx2.x8.min.u32 {%r10, %r11, %r12, %r13, %r14, %r15, %r16, %r17}, %r18, [%r1], 0;
@@ -89,7 +89,7 @@ define void @nvvm_tcgen05_ld_16x32bx2_max_i32(ptr addrspace(6) %taddr) {
; CHECK-NEXT: .reg .b32 %r<263>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [nvvm_tcgen05_ld_16x32bx2_max_i32_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r1, [nvvm_tcgen05_ld_16x32bx2_max_i32_param_0];
; CHECK-NEXT: tcgen05.ld.red.sync.aligned.16x32bx2.x2.max.u32 {%r2, %r3}, %r4, [%r1], 0;
; CHECK-NEXT: tcgen05.ld.red.sync.aligned.16x32bx2.x4.max.u32 {%r5, %r6, %r7, %r8}, %r9, [%r1], 0;
; CHECK-NEXT: tcgen05.ld.red.sync.aligned.16x32bx2.x8.max.u32 {%r10, %r11, %r12, %r13, %r14, %r15, %r16, %r17}, %r18, [%r1], 0;
@@ -114,7 +114,7 @@ define void @nvvm_tcgen05_ld_32x32b_min_f32(ptr addrspace(6) %taddr) {
; CHECK-NEXT: .reg .b32 %r<1046>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [nvvm_tcgen05_ld_32x32b_min_f32_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r1, [nvvm_tcgen05_ld_32x32b_min_f32_param_0];
; CHECK-NEXT: tcgen05.ld.red.sync.aligned.32x32b.x2.min.f32 {%r2, %r3}, %r4, [%r1];
; CHECK-NEXT: tcgen05.ld.red.sync.aligned.32x32b.x4.min.f32 {%r5, %r6, %r7, %r8}, %r9, [%r1];
; CHECK-NEXT: tcgen05.ld.red.sync.aligned.32x32b.x8.min.f32 {%r10, %r11, %r12, %r13, %r14, %r15, %r16, %r17}, %r18, [%r1];
@@ -184,7 +184,7 @@ define void @nvvm_tcgen05_ld_32x32b_max_f32(ptr addrspace(6) %taddr) {
; CHECK-NEXT: .reg .b32 %r<1046>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [nvvm_tcgen05_ld_32x32b_max_f32_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r1, [nvvm_tcgen05_ld_32x32b_max_f32_param_0];
; CHECK-NEXT: tcgen05.ld.red.sync.aligned.32x32b.x2.max.f32 {%r2, %r3}, %r4, [%r1];
; CHECK-NEXT: tcgen05.ld.red.sync.aligned.32x32b.x4.max.f32 {%r5, %r6, %r7, %r8}, %r9, [%r1];
; CHECK-NEXT: tcgen05.ld.red.sync.aligned.32x32b.x8.max.f32 {%r10, %r11, %r12, %r13, %r14, %r15, %r16, %r17}, %r18, [%r1];
@@ -254,7 +254,7 @@ define void @nvvm_tcgen05_ld_16x32bx2_min_f32(ptr addrspace(6) %taddr) {
; CHECK-NEXT: .reg .b32 %r<1046>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [nvvm_tcgen05_ld_16x32bx2_min_f32_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r1, [nvvm_tcgen05_ld_16x32bx2_min_f32_param_0];
; CHECK-NEXT: tcgen05.ld.red.sync.aligned.16x32bx2.x2.min.f32 {%r2, %r3}, %r4, [%r1], 0;
; CHECK-NEXT: tcgen05.ld.red.sync.aligned.16x32bx2.x4.min.f32 {%r5, %r6, %r7, %r8}, %r9, [%r1], 0;
; CHECK-NEXT: tcgen05.ld.red.sync.aligned.16x32bx2.x8.min.f32 {%r10, %r11, %r12, %r13, %r14, %r15, %r16, %r17}, %r18, [%r1], 0;
@@ -324,7 +324,7 @@ define void @nvvm_tcgen05_ld_16x32bx2_max_f32(ptr addrspace(6) %taddr) {
; CHECK-NEXT: .reg .b32 %r<1046>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [nvvm_tcgen05_ld_16x32bx2_max_f32_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r1, [nvvm_tcgen05_ld_16x32bx2_max_f32_param_0];
; CHECK-NEXT: tcgen05.ld.red.sync.aligned.16x32bx2.x2.max.f32 {%r2, %r3}, %r4, [%r1], 0;
; CHECK-NEXT: tcgen05.ld.red.sync.aligned.16x32bx2.x4.max.f32 {%r5, %r6, %r7, %r8}, %r9, [%r1], 0;
; CHECK-NEXT: tcgen05.ld.red.sync.aligned.16x32bx2.x8.max.f32 {%r10, %r11, %r12, %r13, %r14, %r15, %r16, %r17}, %r18, [%r1], 0;
diff --git a/llvm/test/CodeGen/NVPTX/tcgen05-ld.ll b/llvm/test/CodeGen/NVPTX/tcgen05-ld.ll
index 33eb39ac7701e..d06ccd5938803 100644
--- a/llvm/test/CodeGen/NVPTX/tcgen05-ld.ll
+++ b/llvm/test/CodeGen/NVPTX/tcgen05-ld.ll
@@ -17,7 +17,7 @@ define void @nvvm_tcgen05_ld_16x64b(ptr addrspace(6) %taddr) {
; CHECK-NEXT: .reg .b32 %r<257>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [nvvm_tcgen05_ld_16x64b_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r1, [nvvm_tcgen05_ld_16x64b_param_0];
; CHECK-NEXT: tcgen05.ld.sync.aligned.16x64b.x1.b32 {%r2}, [%r1];
; CHECK-NEXT: tcgen05.ld.sync.aligned.16x64b.x2.b32 {%r3, %r4}, [%r1];
; CHECK-NEXT: tcgen05.ld.sync.aligned.16x64b.x4.b32 {%r5, %r6, %r7, %r8}, [%r1];
@@ -52,7 +52,7 @@ define void @nvvm_tcgen05_ld_16x64b_pack(ptr addrspace(6) %taddr) {
; CHECK-NEXT: .reg .b32 %r<257>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [nvvm_tcgen05_ld_16x64b_pack_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r1, [nvvm_tcgen05_ld_16x64b_pack_param_0];
; CHECK-NEXT: tcgen05.ld.sync.aligned.16x64b.x1.pack::16b.b32 {%r2}, [%r1];
; CHECK-NEXT: tcgen05.ld.sync.aligned.16x64b.x2.pack::16b.b32 {%r3, %r4}, [%r1];
; CHECK-NEXT: tcgen05.ld.sync.aligned.16x64b.x4.pack::16b.b32 {%r5, %r6, %r7, %r8}, [%r1];
@@ -87,7 +87,7 @@ define void @nvvm_tcgen05_ld_16x128b(ptr addrspace(6) %taddr) {
; CHECK-NEXT: .reg .b32 %r<256>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [nvvm_tcgen05_ld_16x128b_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r1, [nvvm_tcgen05_ld_16x128b_param_0];
; CHECK-NEXT: tcgen05.ld.sync.aligned.16x128b.x1.b32 {%r2, %r3}, [%r1];
; CHECK-NEXT: tcgen05.ld.sync.aligned.16x128b.x2.b32 {%r4, %r5, %r6, %r7}, [%r1];
; CHECK-NEXT: tcgen05.ld.sync.aligned.16x128b.x4.b32 {%r8, %r9, %r10, %r11, %r12, %r13, %r14, %r15}, [%r1];
@@ -119,7 +119,7 @@ define void @nvvm_tcgen05_ld_16x128b_pack(ptr addrspace(6) %taddr) {
; CHECK-NEXT: .reg .b32 %r<256>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [nvvm_tcgen05_ld_16x128b_pack_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r1, [nvvm_tcgen05_ld_16x128b_pack_param_0];
; CHECK-NEXT: tcgen05.ld.sync.aligned.16x128b.x1.pack::16b.b32 {%r2, %r3}, [%r1];
; CHECK-NEXT: tcgen05.ld.sync.aligned.16x128b.x2.pack::16b.b32 {%r4, %r5, %r6, %r7}, [%r1];
; CHECK-NEXT: tcgen05.ld.sync.aligned.16x128b.x4.pack::16b.b32 {%r8, %r9, %r10, %r11, %r12, %r13, %r14, %r15}, [%r1];
@@ -151,7 +151,7 @@ define void @nvvm_tcgen05_ld_16x256b(ptr addrspace(6) %taddr) {
; CHECK-NEXT: .reg .b32 %r<254>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [nvvm_tcgen05_ld_16x256b_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r1, [nvvm_tcgen05_ld_16x256b_param_0];
; CHECK-NEXT: tcgen05.ld.sync.aligned.16x256b.x1.b32 {%r2, %r3, %r4, %r5}, [%r1];
; CHECK-NEXT: tcgen05.ld.sync.aligned.16x256b.x2.b32 {%r6, %r7, %r8, %r9, %r10, %r11, %r12, %r13}, [%r1];
; CHECK-NEXT: tcgen05.ld.sync.aligned.16x256b.x4.b32 {%r14, %r15, %r16, %r17, %r18, %r19, %r20, %r21, %r22, %r23, %r24, %r25, %r26, %r27, %r28, %r29}, [%r1];
@@ -180,7 +180,7 @@ define void @nvvm_tcgen05_ld_16x256b_pack(ptr addrspace(6) %taddr) {
; CHECK-NEXT: .reg .b32 %r<254>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [nvvm_tcgen05_ld_16x256b_pack_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r1, [nvvm_tcgen05_ld_16x256b_pack_param_0];
; CHECK-NEXT: tcgen05.ld.sync.aligned.16x256b.x1.pack::16b.b32 {%r2, %r3, %r4, %r5}, [%r1];
; CHECK-NEXT: tcgen05.ld.sync.aligned.16x256b.x2.pack::16b.b32 {%r6, %r7, %r8, %r9, %r10, %r11, %r12, %r13}, [%r1];
; CHECK-NEXT: tcgen05.ld.sync.aligned.16x256b.x4.pack::16b.b32 {%r14, %r15, %r16, %r17, %r18, %r19, %r20, %r21, %r22, %r23, %r24, %r25, %r26, %r27, %r28, %r29}, [%r1];
@@ -209,7 +209,7 @@ define void @nvvm_tcgen05_ld_32x32b(ptr addrspace(6) %taddr) {
; CHECK-NEXT: .reg .b32 %r<257>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [nvvm_tcgen05_ld_32x32b_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r1, [nvvm_tcgen05_ld_32x32b_param_0];
; CHECK-NEXT: tcgen05.ld.sync.aligned.32x32b.x1.b32 {%r2}, [%r1];
; CHECK-NEXT: tcgen05.ld.sync.aligned.32x32b.x2.b32 {%r3, %r4}, [%r1];
; CHECK-NEXT: tcgen05.ld.sync.aligned.32x32b.x4.b32 {%r5, %r6, %r7, %r8}, [%r1];
@@ -243,7 +243,7 @@ define void @nvvm_tcgen05_ld_32x32b_pack(ptr addrspace(6) %taddr) {
; CHECK-NEXT: .reg .b32 %r<257>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [nvvm_tcgen05_ld_32x32b_pack_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r1, [nvvm_tcgen05_ld_32x32b_pack_param_0];
; CHECK-NEXT: tcgen05.ld.sync.aligned.32x32b.x1.pack::16b.b32 {%r2}, [%r1];
; CHECK-NEXT: tcgen05.ld.sync.aligned.32x32b.x2.pack::16b.b32 {%r3, %r4}, [%r1];
; CHECK-NEXT: tcgen05.ld.sync.aligned.32x32b.x4.pack::16b.b32 {%r5, %r6, %r7, %r8}, [%r1];
@@ -278,7 +278,7 @@ define void @nvvm_tcgen05_ld_16x32bx2(ptr addrspace(6) %taddr) {
; CHECK-NEXT: .reg .b32 %r<257>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [nvvm_tcgen05_ld_16x32bx2_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r1, [nvvm_tcgen05_ld_16x32bx2_param_0];
; CHECK-NEXT: tcgen05.ld.sync.aligned.16x32bx2.x1.b32 {%r2}, [%r1], 2;
; CHECK-NEXT: tcgen05.ld.sync.aligned.16x32bx2.x2.b32 {%r3, %r4}, [%r1], 2;
; CHECK-NEXT: tcgen05.ld.sync.aligned.16x32bx2.x4.b32 {%r5, %r6, %r7, %r8}, [%r1], 2;
@@ -312,7 +312,7 @@ define void @nvvm_tcgen05_ld_16x32bx2_pack(ptr addrspace(6) %taddr) {
; CHECK-NEXT: .reg .b32 %r<257>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [nvvm_tcgen05_ld_16x32bx2_pack_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r1, [nvvm_tcgen05_ld_16x32bx2_pack_param_0];
; CHECK-NEXT: tcgen05.ld.sync.aligned.16x32bx2.x1.pack::16b.b32 {%r2}, [%r1], 2;
; CHECK-NEXT: tcgen05.ld.sync.aligned.16x32bx2.x2.pack::16b.b32 {%r3, %r4}, [%r1], 2;
; CHECK-NEXT: tcgen05.ld.sync.aligned.16x32bx2.x4.pack::16b.b32 {%r5, %r6, %r7, %r8}, [%r1], 2;
diff --git a/llvm/test/CodeGen/NVPTX/tcgen05-mma-block-scale-ptx88-aa.ll b/llvm/test/CodeGen/NVPTX/tcgen05-mma-block-scale-ptx88-aa.ll
index cf1f274f84f21..71e19f0f4d27b 100644
--- a/llvm/test/CodeGen/NVPTX/tcgen05-mma-block-scale-ptx88-aa.ll
+++ b/llvm/test/CodeGen/NVPTX/tcgen05-mma-block-scale-ptx88-aa.ll
@@ -15,18 +15,18 @@ define void @tcgen05_mma_sp_mxf4_cta1(ptr addrspace(6) %dtmem, ptr addrspace(6)
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_sp_mxf4_cta1_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_sp_mxf4_cta1_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_sp_mxf4_cta1_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_sp_mxf4_cta1_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_sp_mxf4_cta1_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_sp_mxf4_cta1_param_4];
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_sp_mxf4_cta1_param_6];
-; CHECK-NEXT: ld.param.b32 %r4, [tcgen05_mma_sp_mxf4_cta1_param_7];
-; CHECK-NEXT: ld.param.b32 %r5, [tcgen05_mma_sp_mxf4_cta1_param_8];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_sp_mxf4_cta1_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_sp_mxf4_cta1_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_sp_mxf4_cta1_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_sp_mxf4_cta1_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_sp_mxf4_cta1_param_6];
+; CHECK-NEXT: ld.param::func.b32 %r4, [tcgen05_mma_sp_mxf4_cta1_param_7];
+; CHECK-NEXT: ld.param::func.b32 %r5, [tcgen05_mma_sp_mxf4_cta1_param_8];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::mxf4.block_scale.block32.collector::a::discard [%r1], %rd1, %rd2, [%r5], %r2, [%r3], [%r4], %p1;
-; CHECK-NEXT: ld.param.b32 %r6, [tcgen05_mma_sp_mxf4_cta1_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r6, [tcgen05_mma_sp_mxf4_cta1_param_1];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::mxf4.block_scale.block32.collector::a::discard [%r1], [%r6], %rd2, [%r5], %r2, [%r3], [%r4], %p1;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::mxf4.block_scale.block32.collector::a::lastuse [%r1], %rd1, %rd2, [%r5], %r2, [%r3], [%r4], %p1;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::mxf4.block_scale.block32.collector::a::lastuse [%r1], [%r6], %rd2, [%r5], %r2, [%r3], [%r4], %p1;
@@ -62,18 +62,18 @@ define void @tcgen05_mma_sp_mxf4_cta2(ptr addrspace(6) %dtmem, ptr addrspace(6)
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_sp_mxf4_cta2_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_sp_mxf4_cta2_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_sp_mxf4_cta2_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_sp_mxf4_cta2_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_sp_mxf4_cta2_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_sp_mxf4_cta2_param_4];
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_sp_mxf4_cta2_param_6];
-; CHECK-NEXT: ld.param.b32 %r4, [tcgen05_mma_sp_mxf4_cta2_param_7];
-; CHECK-NEXT: ld.param.b32 %r5, [tcgen05_mma_sp_mxf4_cta2_param_8];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_sp_mxf4_cta2_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_sp_mxf4_cta2_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_sp_mxf4_cta2_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_sp_mxf4_cta2_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_sp_mxf4_cta2_param_6];
+; CHECK-NEXT: ld.param::func.b32 %r4, [tcgen05_mma_sp_mxf4_cta2_param_7];
+; CHECK-NEXT: ld.param::func.b32 %r5, [tcgen05_mma_sp_mxf4_cta2_param_8];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::mxf4.block_scale.block32.collector::a::discard [%r1], %rd1, %rd2, [%r5], %r2, [%r3], [%r4], %p1;
-; CHECK-NEXT: ld.param.b32 %r6, [tcgen05_mma_sp_mxf4_cta2_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r6, [tcgen05_mma_sp_mxf4_cta2_param_1];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::mxf4.block_scale.block32.collector::a::discard [%r1], [%r6], %rd2, [%r5], %r2, [%r3], [%r4], %p1;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::mxf4.block_scale.block32.collector::a::lastuse [%r1], %rd1, %rd2, [%r5], %r2, [%r3], [%r4], %p1;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::mxf4.block_scale.block32.collector::a::lastuse [%r1], [%r6], %rd2, [%r5], %r2, [%r3], [%r4], %p1;
@@ -110,18 +110,18 @@ define void @tcgen05_mma_sp_mxf4nvf4_cta1(ptr addrspace(6) %dtmem, ptr addrspace
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_sp_mxf4nvf4_cta1_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_sp_mxf4nvf4_cta1_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_sp_mxf4nvf4_cta1_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_sp_mxf4nvf4_cta1_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_sp_mxf4nvf4_cta1_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_sp_mxf4nvf4_cta1_param_4];
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_sp_mxf4nvf4_cta1_param_6];
-; CHECK-NEXT: ld.param.b32 %r4, [tcgen05_mma_sp_mxf4nvf4_cta1_param_7];
-; CHECK-NEXT: ld.param.b32 %r5, [tcgen05_mma_sp_mxf4nvf4_cta1_param_8];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_sp_mxf4nvf4_cta1_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_sp_mxf4nvf4_cta1_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_sp_mxf4nvf4_cta1_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_sp_mxf4nvf4_cta1_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_sp_mxf4nvf4_cta1_param_6];
+; CHECK-NEXT: ld.param::func.b32 %r4, [tcgen05_mma_sp_mxf4nvf4_cta1_param_7];
+; CHECK-NEXT: ld.param::func.b32 %r5, [tcgen05_mma_sp_mxf4nvf4_cta1_param_8];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::mxf4nvf4.block_scale.block16.collector::a::discard [%r1], %rd1, %rd2, [%r5], %r2, [%r3], [%r4], %p1;
-; CHECK-NEXT: ld.param.b32 %r6, [tcgen05_mma_sp_mxf4nvf4_cta1_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r6, [tcgen05_mma_sp_mxf4nvf4_cta1_param_1];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::mxf4nvf4.block_scale.block16.collector::a::discard [%r1], [%r6], %rd2, [%r5], %r2, [%r3], [%r4], %p1;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::mxf4nvf4.block_scale.block32.collector::a::discard [%r1], %rd1, %rd2, [%r5], %r2, [%r3], [%r4], %p1;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::mxf4nvf4.block_scale.block32.collector::a::discard [%r1], [%r6], %rd2, [%r5], %r2, [%r3], [%r4], %p1;
@@ -182,18 +182,18 @@ define void @tcgen05_mma_sp_mxf4nvf4_cta2(ptr addrspace(6) %dtmem, ptr addrspace
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_sp_mxf4nvf4_cta2_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_sp_mxf4nvf4_cta2_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_sp_mxf4nvf4_cta2_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_sp_mxf4nvf4_cta2_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_sp_mxf4nvf4_cta2_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_sp_mxf4nvf4_cta2_param_4];
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_sp_mxf4nvf4_cta2_param_6];
-; CHECK-NEXT: ld.param.b32 %r4, [tcgen05_mma_sp_mxf4nvf4_cta2_param_7];
-; CHECK-NEXT: ld.param.b32 %r5, [tcgen05_mma_sp_mxf4nvf4_cta2_param_8];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_sp_mxf4nvf4_cta2_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_sp_mxf4nvf4_cta2_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_sp_mxf4nvf4_cta2_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_sp_mxf4nvf4_cta2_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_sp_mxf4nvf4_cta2_param_6];
+; CHECK-NEXT: ld.param::func.b32 %r4, [tcgen05_mma_sp_mxf4nvf4_cta2_param_7];
+; CHECK-NEXT: ld.param::func.b32 %r5, [tcgen05_mma_sp_mxf4nvf4_cta2_param_8];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::mxf4nvf4.block_scale.block16.collector::a::discard [%r1], %rd1, %rd2, [%r5], %r2, [%r3], [%r4], %p1;
-; CHECK-NEXT: ld.param.b32 %r6, [tcgen05_mma_sp_mxf4nvf4_cta2_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r6, [tcgen05_mma_sp_mxf4nvf4_cta2_param_1];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::mxf4nvf4.block_scale.block16.collector::a::discard [%r1], [%r6], %rd2, [%r5], %r2, [%r3], [%r4], %p1;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::mxf4nvf4.block_scale.block32.collector::a::discard [%r1], %rd1, %rd2, [%r5], %r2, [%r3], [%r4], %p1;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::mxf4nvf4.block_scale.block32.collector::a::discard [%r1], [%r6], %rd2, [%r5], %r2, [%r3], [%r4], %p1;
diff --git a/llvm/test/CodeGen/NVPTX/tcgen05-mma-block-scale-ptx88.ll b/llvm/test/CodeGen/NVPTX/tcgen05-mma-block-scale-ptx88.ll
index 7cfc7913900de..a4e80e7a2f3b4 100644
--- a/llvm/test/CodeGen/NVPTX/tcgen05-mma-block-scale-ptx88.ll
+++ b/llvm/test/CodeGen/NVPTX/tcgen05-mma-block-scale-ptx88.ll
@@ -19,17 +19,17 @@ define void @tcgen05_mma_mxf8f6f4_cta1(ptr addrspace(6) %dtmem, ptr addrspace(6)
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_mxf8f6f4_cta1_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_mxf8f6f4_cta1_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_mxf8f6f4_cta1_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_mxf8f6f4_cta1_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_mxf8f6f4_cta1_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_mxf8f6f4_cta1_param_4];
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_mxf8f6f4_cta1_param_6];
-; CHECK-NEXT: ld.param.b32 %r4, [tcgen05_mma_mxf8f6f4_cta1_param_7];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_mxf8f6f4_cta1_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_mxf8f6f4_cta1_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_mxf8f6f4_cta1_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_mxf8f6f4_cta1_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_mxf8f6f4_cta1_param_6];
+; CHECK-NEXT: ld.param::func.b32 %r4, [tcgen05_mma_mxf8f6f4_cta1_param_7];
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::mxf8f6f4.block_scale.block32.collector::a::discard [%r1], %rd1, %rd2, %r2, [%r3], [%r4], %p1;
-; CHECK-NEXT: ld.param.b32 %r5, [tcgen05_mma_mxf8f6f4_cta1_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r5, [tcgen05_mma_mxf8f6f4_cta1_param_1];
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::mxf8f6f4.block_scale.block32.collector::a::discard [%r1], [%r5], %rd2, %r2, [%r3], [%r4], %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::mxf8f6f4.block_scale.block32.collector::a::lastuse [%r1], %rd1, %rd2, %r2, [%r3], [%r4], %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::mxf8f6f4.block_scale.block32.collector::a::lastuse [%r1], [%r5], %rd2, %r2, [%r3], [%r4], %p1;
@@ -65,17 +65,17 @@ define void @tcgen05_mma_mxf8f6f4_cta2(ptr addrspace(6) %dtmem, ptr addrspace(6)
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_mxf8f6f4_cta2_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_mxf8f6f4_cta2_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_mxf8f6f4_cta2_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_mxf8f6f4_cta2_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_mxf8f6f4_cta2_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_mxf8f6f4_cta2_param_4];
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_mxf8f6f4_cta2_param_6];
-; CHECK-NEXT: ld.param.b32 %r4, [tcgen05_mma_mxf8f6f4_cta2_param_7];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_mxf8f6f4_cta2_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_mxf8f6f4_cta2_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_mxf8f6f4_cta2_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_mxf8f6f4_cta2_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_mxf8f6f4_cta2_param_6];
+; CHECK-NEXT: ld.param::func.b32 %r4, [tcgen05_mma_mxf8f6f4_cta2_param_7];
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::mxf8f6f4.block_scale.block32.collector::a::discard [%r1], %rd1, %rd2, %r2, [%r3], [%r4], %p1;
-; CHECK-NEXT: ld.param.b32 %r5, [tcgen05_mma_mxf8f6f4_cta2_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r5, [tcgen05_mma_mxf8f6f4_cta2_param_1];
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::mxf8f6f4.block_scale.block32.collector::a::discard [%r1], [%r5], %rd2, %r2, [%r3], [%r4], %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::mxf8f6f4.block_scale.block32.collector::a::lastuse [%r1], %rd1, %rd2, %r2, [%r3], [%r4], %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::mxf8f6f4.block_scale.block32.collector::a::lastuse [%r1], [%r5], %rd2, %r2, [%r3], [%r4], %p1;
@@ -112,17 +112,17 @@ define void @tcgen05_mma_mxf4_cta1(ptr addrspace(6) %dtmem, ptr addrspace(6) %at
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_mxf4_cta1_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_mxf4_cta1_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_mxf4_cta1_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_mxf4_cta1_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_mxf4_cta1_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_mxf4_cta1_param_4];
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_mxf4_cta1_param_6];
-; CHECK-NEXT: ld.param.b32 %r4, [tcgen05_mma_mxf4_cta1_param_7];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_mxf4_cta1_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_mxf4_cta1_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_mxf4_cta1_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_mxf4_cta1_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_mxf4_cta1_param_6];
+; CHECK-NEXT: ld.param::func.b32 %r4, [tcgen05_mma_mxf4_cta1_param_7];
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::mxf4.block_scale.block32.collector::a::discard [%r1], %rd1, %rd2, %r2, [%r3], [%r4], %p1;
-; CHECK-NEXT: ld.param.b32 %r5, [tcgen05_mma_mxf4_cta1_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r5, [tcgen05_mma_mxf4_cta1_param_1];
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::mxf4.block_scale.block32.collector::a::discard [%r1], [%r5], %rd2, %r2, [%r3], [%r4], %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::mxf4.block_scale.block32.collector::a::lastuse [%r1], %rd1, %rd2, %r2, [%r3], [%r4], %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::mxf4.block_scale.block32.collector::a::lastuse [%r1], [%r5], %rd2, %r2, [%r3], [%r4], %p1;
@@ -158,17 +158,17 @@ define void @tcgen05_mma_mxf4_cta2(ptr addrspace(6) %dtmem, ptr addrspace(6) %at
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_mxf4_cta2_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_mxf4_cta2_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_mxf4_cta2_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_mxf4_cta2_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_mxf4_cta2_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_mxf4_cta2_param_4];
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_mxf4_cta2_param_6];
-; CHECK-NEXT: ld.param.b32 %r4, [tcgen05_mma_mxf4_cta2_param_7];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_mxf4_cta2_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_mxf4_cta2_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_mxf4_cta2_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_mxf4_cta2_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_mxf4_cta2_param_6];
+; CHECK-NEXT: ld.param::func.b32 %r4, [tcgen05_mma_mxf4_cta2_param_7];
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::mxf4.block_scale.block32.collector::a::discard [%r1], %rd1, %rd2, %r2, [%r3], [%r4], %p1;
-; CHECK-NEXT: ld.param.b32 %r5, [tcgen05_mma_mxf4_cta2_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r5, [tcgen05_mma_mxf4_cta2_param_1];
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::mxf4.block_scale.block32.collector::a::discard [%r1], [%r5], %rd2, %r2, [%r3], [%r4], %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::mxf4.block_scale.block32.collector::a::lastuse [%r1], %rd1, %rd2, %r2, [%r3], [%r4], %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::mxf4.block_scale.block32.collector::a::lastuse [%r1], [%r5], %rd2, %r2, [%r3], [%r4], %p1;
@@ -205,17 +205,17 @@ define void @tcgen05_mma_mxf4nvf4_cta1(ptr addrspace(6) %dtmem, ptr addrspace(6)
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_mxf4nvf4_cta1_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_mxf4nvf4_cta1_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_mxf4nvf4_cta1_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_mxf4nvf4_cta1_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_mxf4nvf4_cta1_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_mxf4nvf4_cta1_param_4];
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_mxf4nvf4_cta1_param_6];
-; CHECK-NEXT: ld.param.b32 %r4, [tcgen05_mma_mxf4nvf4_cta1_param_7];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_mxf4nvf4_cta1_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_mxf4nvf4_cta1_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_mxf4nvf4_cta1_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_mxf4nvf4_cta1_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_mxf4nvf4_cta1_param_6];
+; CHECK-NEXT: ld.param::func.b32 %r4, [tcgen05_mma_mxf4nvf4_cta1_param_7];
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.block16.collector::a::discard [%r1], %rd1, %rd2, %r2, [%r3], [%r4], %p1;
-; CHECK-NEXT: ld.param.b32 %r5, [tcgen05_mma_mxf4nvf4_cta1_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r5, [tcgen05_mma_mxf4nvf4_cta1_param_1];
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.block16.collector::a::discard [%r1], [%r5], %rd2, %r2, [%r3], [%r4], %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.block32.collector::a::discard [%r1], %rd1, %rd2, %r2, [%r3], [%r4], %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.block32.collector::a::discard [%r1], [%r5], %rd2, %r2, [%r3], [%r4], %p1;
@@ -276,17 +276,17 @@ define void @tcgen05_mma_mxf4nvf4_cta2(ptr addrspace(6) %dtmem, ptr addrspace(6)
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_mxf4nvf4_cta2_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_mxf4nvf4_cta2_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_mxf4nvf4_cta2_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_mxf4nvf4_cta2_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_mxf4nvf4_cta2_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_mxf4nvf4_cta2_param_4];
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_mxf4nvf4_cta2_param_6];
-; CHECK-NEXT: ld.param.b32 %r4, [tcgen05_mma_mxf4nvf4_cta2_param_7];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_mxf4nvf4_cta2_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_mxf4nvf4_cta2_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_mxf4nvf4_cta2_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_mxf4nvf4_cta2_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_mxf4nvf4_cta2_param_6];
+; CHECK-NEXT: ld.param::func.b32 %r4, [tcgen05_mma_mxf4nvf4_cta2_param_7];
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.block16.collector::a::discard [%r1], %rd1, %rd2, %r2, [%r3], [%r4], %p1;
-; CHECK-NEXT: ld.param.b32 %r5, [tcgen05_mma_mxf4nvf4_cta2_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r5, [tcgen05_mma_mxf4nvf4_cta2_param_1];
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.block16.collector::a::discard [%r1], [%r5], %rd2, %r2, [%r3], [%r4], %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.block32.collector::a::discard [%r1], %rd1, %rd2, %r2, [%r3], [%r4], %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.block32.collector::a::discard [%r1], [%r5], %rd2, %r2, [%r3], [%r4], %p1;
@@ -347,18 +347,18 @@ define void @tcgen05_mma_sp_mxf8f6f4_cta1(ptr addrspace(6) %dtmem, ptr addrspace
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_sp_mxf8f6f4_cta1_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_sp_mxf8f6f4_cta1_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_sp_mxf8f6f4_cta1_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_sp_mxf8f6f4_cta1_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_sp_mxf8f6f4_cta1_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_sp_mxf8f6f4_cta1_param_4];
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_sp_mxf8f6f4_cta1_param_6];
-; CHECK-NEXT: ld.param.b32 %r4, [tcgen05_mma_sp_mxf8f6f4_cta1_param_7];
-; CHECK-NEXT: ld.param.b32 %r5, [tcgen05_mma_sp_mxf8f6f4_cta1_param_8];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_sp_mxf8f6f4_cta1_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_sp_mxf8f6f4_cta1_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_sp_mxf8f6f4_cta1_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_sp_mxf8f6f4_cta1_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_sp_mxf8f6f4_cta1_param_6];
+; CHECK-NEXT: ld.param::func.b32 %r4, [tcgen05_mma_sp_mxf8f6f4_cta1_param_7];
+; CHECK-NEXT: ld.param::func.b32 %r5, [tcgen05_mma_sp_mxf8f6f4_cta1_param_8];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::mxf8f6f4.block_scale.block32.collector::a::discard [%r1], %rd1, %rd2, [%r5], %r2, [%r3], [%r4], %p1;
-; CHECK-NEXT: ld.param.b32 %r6, [tcgen05_mma_sp_mxf8f6f4_cta1_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r6, [tcgen05_mma_sp_mxf8f6f4_cta1_param_1];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::mxf8f6f4.block_scale.block32.collector::a::discard [%r1], [%r6], %rd2, [%r5], %r2, [%r3], [%r4], %p1;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::mxf8f6f4.block_scale.block32.collector::a::lastuse [%r1], %rd1, %rd2, [%r5], %r2, [%r3], [%r4], %p1;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::mxf8f6f4.block_scale.block32.collector::a::lastuse [%r1], [%r6], %rd2, [%r5], %r2, [%r3], [%r4], %p1;
@@ -395,18 +395,18 @@ define void @tcgen05_mma_sp_mxf8f6f4_cta2(ptr addrspace(6) %dtmem, ptr addrspace
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_sp_mxf8f6f4_cta2_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_sp_mxf8f6f4_cta2_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_sp_mxf8f6f4_cta2_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_sp_mxf8f6f4_cta2_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_sp_mxf8f6f4_cta2_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_sp_mxf8f6f4_cta2_param_4];
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_sp_mxf8f6f4_cta2_param_6];
-; CHECK-NEXT: ld.param.b32 %r4, [tcgen05_mma_sp_mxf8f6f4_cta2_param_7];
-; CHECK-NEXT: ld.param.b32 %r5, [tcgen05_mma_sp_mxf8f6f4_cta2_param_8];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_sp_mxf8f6f4_cta2_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_sp_mxf8f6f4_cta2_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_sp_mxf8f6f4_cta2_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_sp_mxf8f6f4_cta2_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_sp_mxf8f6f4_cta2_param_6];
+; CHECK-NEXT: ld.param::func.b32 %r4, [tcgen05_mma_sp_mxf8f6f4_cta2_param_7];
+; CHECK-NEXT: ld.param::func.b32 %r5, [tcgen05_mma_sp_mxf8f6f4_cta2_param_8];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::mxf8f6f4.block_scale.block32.collector::a::discard [%r1], %rd1, %rd2, [%r5], %r2, [%r3], [%r4], %p1;
-; CHECK-NEXT: ld.param.b32 %r6, [tcgen05_mma_sp_mxf8f6f4_cta2_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r6, [tcgen05_mma_sp_mxf8f6f4_cta2_param_1];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::mxf8f6f4.block_scale.block32.collector::a::discard [%r1], [%r6], %rd2, [%r5], %r2, [%r3], [%r4], %p1;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::mxf8f6f4.block_scale.block32.collector::a::lastuse [%r1], %rd1, %rd2, [%r5], %r2, [%r3], [%r4], %p1;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::mxf8f6f4.block_scale.block32.collector::a::lastuse [%r1], [%r6], %rd2, [%r5], %r2, [%r3], [%r4], %p1;
diff --git a/llvm/test/CodeGen/NVPTX/tcgen05-mma-block-scale.ll b/llvm/test/CodeGen/NVPTX/tcgen05-mma-block-scale.ll
index e071eaaf107fc..d55839acc91f4 100644
--- a/llvm/test/CodeGen/NVPTX/tcgen05-mma-block-scale.ll
+++ b/llvm/test/CodeGen/NVPTX/tcgen05-mma-block-scale.ll
@@ -15,17 +15,17 @@ define void @tcgen05_mma_mxf8f6f4_cta1(ptr addrspace(6) %dtmem, ptr addrspace(6)
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_mxf8f6f4_cta1_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_mxf8f6f4_cta1_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_mxf8f6f4_cta1_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_mxf8f6f4_cta1_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_mxf8f6f4_cta1_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_mxf8f6f4_cta1_param_4];
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_mxf8f6f4_cta1_param_6];
-; CHECK-NEXT: ld.param.b32 %r4, [tcgen05_mma_mxf8f6f4_cta1_param_7];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_mxf8f6f4_cta1_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_mxf8f6f4_cta1_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_mxf8f6f4_cta1_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_mxf8f6f4_cta1_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_mxf8f6f4_cta1_param_6];
+; CHECK-NEXT: ld.param::func.b32 %r4, [tcgen05_mma_mxf8f6f4_cta1_param_7];
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::mxf8f6f4.block_scale.collector::a::discard [%r1], %rd1, %rd2, %r2, [%r3], [%r4], %p1;
-; CHECK-NEXT: ld.param.b32 %r5, [tcgen05_mma_mxf8f6f4_cta1_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r5, [tcgen05_mma_mxf8f6f4_cta1_param_1];
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::mxf8f6f4.block_scale.collector::a::discard [%r1], [%r5], %rd2, %r2, [%r3], [%r4], %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::mxf8f6f4.block_scale.collector::a::lastuse [%r1], %rd1, %rd2, %r2, [%r3], [%r4], %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::mxf8f6f4.block_scale.collector::a::lastuse [%r1], [%r5], %rd2, %r2, [%r3], [%r4], %p1;
@@ -62,17 +62,17 @@ define void @tcgen05_mma_mxf8f6f4_cta2(ptr addrspace(6) %dtmem, ptr addrspace(6)
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_mxf8f6f4_cta2_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_mxf8f6f4_cta2_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_mxf8f6f4_cta2_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_mxf8f6f4_cta2_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_mxf8f6f4_cta2_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_mxf8f6f4_cta2_param_4];
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_mxf8f6f4_cta2_param_6];
-; CHECK-NEXT: ld.param.b32 %r4, [tcgen05_mma_mxf8f6f4_cta2_param_7];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_mxf8f6f4_cta2_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_mxf8f6f4_cta2_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_mxf8f6f4_cta2_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_mxf8f6f4_cta2_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_mxf8f6f4_cta2_param_6];
+; CHECK-NEXT: ld.param::func.b32 %r4, [tcgen05_mma_mxf8f6f4_cta2_param_7];
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::mxf8f6f4.block_scale.collector::a::discard [%r1], %rd1, %rd2, %r2, [%r3], [%r4], %p1;
-; CHECK-NEXT: ld.param.b32 %r5, [tcgen05_mma_mxf8f6f4_cta2_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r5, [tcgen05_mma_mxf8f6f4_cta2_param_1];
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::mxf8f6f4.block_scale.collector::a::discard [%r1], [%r5], %rd2, %r2, [%r3], [%r4], %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::mxf8f6f4.block_scale.collector::a::lastuse [%r1], %rd1, %rd2, %r2, [%r3], [%r4], %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::mxf8f6f4.block_scale.collector::a::lastuse [%r1], [%r5], %rd2, %r2, [%r3], [%r4], %p1;
@@ -109,18 +109,18 @@ define void @tcgen05_mma_sp_mxf8f6f4_cta1(ptr addrspace(6) %dtmem, ptr addrspace
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_sp_mxf8f6f4_cta1_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_sp_mxf8f6f4_cta1_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_sp_mxf8f6f4_cta1_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_sp_mxf8f6f4_cta1_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_sp_mxf8f6f4_cta1_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_sp_mxf8f6f4_cta1_param_4];
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_sp_mxf8f6f4_cta1_param_6];
-; CHECK-NEXT: ld.param.b32 %r4, [tcgen05_mma_sp_mxf8f6f4_cta1_param_7];
-; CHECK-NEXT: ld.param.b32 %r5, [tcgen05_mma_sp_mxf8f6f4_cta1_param_8];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_sp_mxf8f6f4_cta1_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_sp_mxf8f6f4_cta1_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_sp_mxf8f6f4_cta1_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_sp_mxf8f6f4_cta1_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_sp_mxf8f6f4_cta1_param_6];
+; CHECK-NEXT: ld.param::func.b32 %r4, [tcgen05_mma_sp_mxf8f6f4_cta1_param_7];
+; CHECK-NEXT: ld.param::func.b32 %r5, [tcgen05_mma_sp_mxf8f6f4_cta1_param_8];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::mxf8f6f4.block_scale.collector::a::discard [%r1], %rd1, %rd2, [%r5], %r2, [%r3], [%r4], %p1;
-; CHECK-NEXT: ld.param.b32 %r6, [tcgen05_mma_sp_mxf8f6f4_cta1_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r6, [tcgen05_mma_sp_mxf8f6f4_cta1_param_1];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::mxf8f6f4.block_scale.collector::a::discard [%r1], [%r6], %rd2, [%r5], %r2, [%r3], [%r4], %p1;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::mxf8f6f4.block_scale.collector::a::lastuse [%r1], %rd1, %rd2, [%r5], %r2, [%r3], [%r4], %p1;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::mxf8f6f4.block_scale.collector::a::lastuse [%r1], [%r6], %rd2, [%r5], %r2, [%r3], [%r4], %p1;
@@ -157,18 +157,18 @@ define void @tcgen05_mma_sp_mxf8f6f4_cta2(ptr addrspace(6) %dtmem, ptr addrspace
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_sp_mxf8f6f4_cta2_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_sp_mxf8f6f4_cta2_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_sp_mxf8f6f4_cta2_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_sp_mxf8f6f4_cta2_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_sp_mxf8f6f4_cta2_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_sp_mxf8f6f4_cta2_param_4];
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_sp_mxf8f6f4_cta2_param_6];
-; CHECK-NEXT: ld.param.b32 %r4, [tcgen05_mma_sp_mxf8f6f4_cta2_param_7];
-; CHECK-NEXT: ld.param.b32 %r5, [tcgen05_mma_sp_mxf8f6f4_cta2_param_8];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_sp_mxf8f6f4_cta2_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_sp_mxf8f6f4_cta2_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_sp_mxf8f6f4_cta2_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_sp_mxf8f6f4_cta2_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_sp_mxf8f6f4_cta2_param_6];
+; CHECK-NEXT: ld.param::func.b32 %r4, [tcgen05_mma_sp_mxf8f6f4_cta2_param_7];
+; CHECK-NEXT: ld.param::func.b32 %r5, [tcgen05_mma_sp_mxf8f6f4_cta2_param_8];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::mxf8f6f4.block_scale.collector::a::discard [%r1], %rd1, %rd2, [%r5], %r2, [%r3], [%r4], %p1;
-; CHECK-NEXT: ld.param.b32 %r6, [tcgen05_mma_sp_mxf8f6f4_cta2_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r6, [tcgen05_mma_sp_mxf8f6f4_cta2_param_1];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::mxf8f6f4.block_scale.collector::a::discard [%r1], [%r6], %rd2, [%r5], %r2, [%r3], [%r4], %p1;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::mxf8f6f4.block_scale.collector::a::lastuse [%r1], %rd1, %rd2, [%r5], %r2, [%r3], [%r4], %p1;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::mxf8f6f4.block_scale.collector::a::lastuse [%r1], [%r6], %rd2, [%r5], %r2, [%r3], [%r4], %p1;
@@ -205,17 +205,17 @@ define void @tcgen05_mma_mxf4_cta1(ptr addrspace(6) %dtmem, ptr addrspace(6) %at
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_mxf4_cta1_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_mxf4_cta1_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_mxf4_cta1_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_mxf4_cta1_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_mxf4_cta1_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_mxf4_cta1_param_4];
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_mxf4_cta1_param_6];
-; CHECK-NEXT: ld.param.b32 %r4, [tcgen05_mma_mxf4_cta1_param_7];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_mxf4_cta1_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_mxf4_cta1_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_mxf4_cta1_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_mxf4_cta1_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_mxf4_cta1_param_6];
+; CHECK-NEXT: ld.param::func.b32 %r4, [tcgen05_mma_mxf4_cta1_param_7];
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::mxf4.block_scale.collector::a::discard [%r1], %rd1, %rd2, %r2, [%r3], [%r4], %p1;
-; CHECK-NEXT: ld.param.b32 %r5, [tcgen05_mma_mxf4_cta1_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r5, [tcgen05_mma_mxf4_cta1_param_1];
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::mxf4.block_scale.collector::a::discard [%r1], [%r5], %rd2, %r2, [%r3], [%r4], %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::mxf4.block_scale.collector::a::lastuse [%r1], %rd1, %rd2, %r2, [%r3], [%r4], %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::mxf4.block_scale.collector::a::lastuse [%r1], [%r5], %rd2, %r2, [%r3], [%r4], %p1;
@@ -252,17 +252,17 @@ define void @tcgen05_mma_mxf4_cta2(ptr addrspace(6) %dtmem, ptr addrspace(6) %at
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_mxf4_cta2_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_mxf4_cta2_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_mxf4_cta2_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_mxf4_cta2_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_mxf4_cta2_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_mxf4_cta2_param_4];
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_mxf4_cta2_param_6];
-; CHECK-NEXT: ld.param.b32 %r4, [tcgen05_mma_mxf4_cta2_param_7];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_mxf4_cta2_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_mxf4_cta2_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_mxf4_cta2_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_mxf4_cta2_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_mxf4_cta2_param_6];
+; CHECK-NEXT: ld.param::func.b32 %r4, [tcgen05_mma_mxf4_cta2_param_7];
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::mxf4.block_scale.collector::a::discard [%r1], %rd1, %rd2, %r2, [%r3], [%r4], %p1;
-; CHECK-NEXT: ld.param.b32 %r5, [tcgen05_mma_mxf4_cta2_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r5, [tcgen05_mma_mxf4_cta2_param_1];
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::mxf4.block_scale.collector::a::discard [%r1], [%r5], %rd2, %r2, [%r3], [%r4], %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::mxf4.block_scale.collector::a::lastuse [%r1], %rd1, %rd2, %r2, [%r3], [%r4], %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::mxf4.block_scale.collector::a::lastuse [%r1], [%r5], %rd2, %r2, [%r3], [%r4], %p1;
@@ -299,18 +299,18 @@ define void @tcgen05_mma_sp_mxf4_cta1(ptr addrspace(6) %dtmem, ptr addrspace(6)
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_sp_mxf4_cta1_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_sp_mxf4_cta1_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_sp_mxf4_cta1_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_sp_mxf4_cta1_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_sp_mxf4_cta1_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_sp_mxf4_cta1_param_4];
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_sp_mxf4_cta1_param_6];
-; CHECK-NEXT: ld.param.b32 %r4, [tcgen05_mma_sp_mxf4_cta1_param_7];
-; CHECK-NEXT: ld.param.b32 %r5, [tcgen05_mma_sp_mxf4_cta1_param_8];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_sp_mxf4_cta1_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_sp_mxf4_cta1_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_sp_mxf4_cta1_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_sp_mxf4_cta1_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_sp_mxf4_cta1_param_6];
+; CHECK-NEXT: ld.param::func.b32 %r4, [tcgen05_mma_sp_mxf4_cta1_param_7];
+; CHECK-NEXT: ld.param::func.b32 %r5, [tcgen05_mma_sp_mxf4_cta1_param_8];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::mxf4.block_scale.collector::a::discard [%r1], %rd1, %rd2, [%r5], %r2, [%r3], [%r4], %p1;
-; CHECK-NEXT: ld.param.b32 %r6, [tcgen05_mma_sp_mxf4_cta1_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r6, [tcgen05_mma_sp_mxf4_cta1_param_1];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::mxf4.block_scale.collector::a::discard [%r1], [%r6], %rd2, [%r5], %r2, [%r3], [%r4], %p1;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::mxf4.block_scale.collector::a::lastuse [%r1], %rd1, %rd2, [%r5], %r2, [%r3], [%r4], %p1;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::mxf4.block_scale.collector::a::lastuse [%r1], [%r6], %rd2, [%r5], %r2, [%r3], [%r4], %p1;
@@ -347,18 +347,18 @@ define void @tcgen05_mma_sp_mxf4_cta2(ptr addrspace(6) %dtmem, ptr addrspace(6)
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_sp_mxf4_cta2_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_sp_mxf4_cta2_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_sp_mxf4_cta2_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_sp_mxf4_cta2_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_sp_mxf4_cta2_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_sp_mxf4_cta2_param_4];
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_sp_mxf4_cta2_param_6];
-; CHECK-NEXT: ld.param.b32 %r4, [tcgen05_mma_sp_mxf4_cta2_param_7];
-; CHECK-NEXT: ld.param.b32 %r5, [tcgen05_mma_sp_mxf4_cta2_param_8];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_sp_mxf4_cta2_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_sp_mxf4_cta2_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_sp_mxf4_cta2_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_sp_mxf4_cta2_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_sp_mxf4_cta2_param_6];
+; CHECK-NEXT: ld.param::func.b32 %r4, [tcgen05_mma_sp_mxf4_cta2_param_7];
+; CHECK-NEXT: ld.param::func.b32 %r5, [tcgen05_mma_sp_mxf4_cta2_param_8];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::mxf4.block_scale.collector::a::discard [%r1], %rd1, %rd2, [%r5], %r2, [%r3], [%r4], %p1;
-; CHECK-NEXT: ld.param.b32 %r6, [tcgen05_mma_sp_mxf4_cta2_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r6, [tcgen05_mma_sp_mxf4_cta2_param_1];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::mxf4.block_scale.collector::a::discard [%r1], [%r6], %rd2, [%r5], %r2, [%r3], [%r4], %p1;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::mxf4.block_scale.collector::a::lastuse [%r1], %rd1, %rd2, [%r5], %r2, [%r3], [%r4], %p1;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::mxf4.block_scale.collector::a::lastuse [%r1], [%r6], %rd2, [%r5], %r2, [%r3], [%r4], %p1;
diff --git a/llvm/test/CodeGen/NVPTX/tcgen05-mma-collector-b.ll b/llvm/test/CodeGen/NVPTX/tcgen05-mma-collector-b.ll
index b4d9acb8f8a7e..0eff949aaf277 100644
--- a/llvm/test/CodeGen/NVPTX/tcgen05-mma-collector-b.ll
+++ b/llvm/test/CodeGen/NVPTX/tcgen05-mma-collector-b.ll
@@ -30,15 +30,15 @@ define void @tcgen05_mma_collector_b_f16_cta1(ptr addrspace(6) %dtmem, ptr addrs
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_collector_b_f16_cta1_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_collector_b_f16_cta1_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_collector_b_f16_cta1_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_collector_b_f16_cta1_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_collector_b_f16_cta1_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_collector_b_f16_cta1_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_collector_b_f16_cta1_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_collector_b_f16_cta1_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_collector_b_f16_cta1_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_collector_b_f16_cta1_param_4];
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::f16.collector::a::discard.collector::b::lastuse [%r1], %rd1, %rd2, %r2, %p1;
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_collector_b_f16_cta1_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_collector_b_f16_cta1_param_1];
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::f16.collector::a::discard.collector::b::fill [%r1], %rd1, %rd2, %r2, %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::f16.collector::a::discard.collector::b::use [%r1], %rd1, %rd2, %r2, %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::f16.collector::a::discard.collector::b::lastuse [%r1], [%r3], %rd2, %r2, %p1;
@@ -88,15 +88,15 @@ define void @tcgen05_mma_collector_b_f16_cta2(ptr addrspace(6) %dtmem, ptr addrs
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_collector_b_f16_cta2_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_collector_b_f16_cta2_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_collector_b_f16_cta2_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_collector_b_f16_cta2_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_collector_b_f16_cta2_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_collector_b_f16_cta2_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_collector_b_f16_cta2_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_collector_b_f16_cta2_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_collector_b_f16_cta2_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_collector_b_f16_cta2_param_4];
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::f16.collector::a::discard.collector::b::lastuse [%r1], %rd1, %rd2, %r2, %p1;
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_collector_b_f16_cta2_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_collector_b_f16_cta2_param_1];
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::f16.collector::a::discard.collector::b::lastuse [%r1], [%r3], %rd2, %r2, %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::f16.ashift.collector::a::discard.collector::b::lastuse [%r1], [%r3], %rd2, %r2, %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::f16.collector::a::lastuse.collector::b::fill [%r1], %rd1, %rd2, %r2, %p1;
@@ -137,15 +137,15 @@ define void @tcgen05_mma_collector_b_tf32_cta1(ptr addrspace(6) %dtmem, ptr addr
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_collector_b_tf32_cta1_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_collector_b_tf32_cta1_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_collector_b_tf32_cta1_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_collector_b_tf32_cta1_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_collector_b_tf32_cta1_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_collector_b_tf32_cta1_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_collector_b_tf32_cta1_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_collector_b_tf32_cta1_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_collector_b_tf32_cta1_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_collector_b_tf32_cta1_param_4];
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::tf32.collector::a::discard.collector::b::lastuse [%r1], %rd1, %rd2, %r2, %p1;
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_collector_b_tf32_cta1_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_collector_b_tf32_cta1_param_1];
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::tf32.collector::a::discard.collector::b::fill [%r1], %rd1, %rd2, %r2, %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::tf32.collector::a::discard.collector::b::use [%r1], %rd1, %rd2, %r2, %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::tf32.collector::a::discard.collector::b::lastuse [%r1], [%r3], %rd2, %r2, %p1;
@@ -196,15 +196,15 @@ define void @tcgen05_mma_collector_b_f8f6f4_cta1(ptr addrspace(6) %dtmem, ptr ad
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_collector_b_f8f6f4_cta1_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_collector_b_f8f6f4_cta1_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_collector_b_f8f6f4_cta1_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_collector_b_f8f6f4_cta1_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_collector_b_f8f6f4_cta1_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_collector_b_f8f6f4_cta1_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_collector_b_f8f6f4_cta1_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_collector_b_f8f6f4_cta1_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_collector_b_f8f6f4_cta1_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_collector_b_f8f6f4_cta1_param_4];
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::f8f6f4.collector::a::discard.collector::b::lastuse [%r1], %rd1, %rd2, %r2, %p1;
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_collector_b_f8f6f4_cta1_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_collector_b_f8f6f4_cta1_param_1];
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::f8f6f4.collector::a::discard.collector::b::fill [%r1], %rd1, %rd2, %r2, %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::f8f6f4.collector::a::discard.collector::b::use [%r1], %rd1, %rd2, %r2, %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::f8f6f4.collector::a::discard.collector::b::lastuse [%r1], [%r3], %rd2, %r2, %p1;
@@ -250,15 +250,15 @@ define void @tcgen05_mma_collector_b_tf32_cta2(ptr addrspace(6) %dtmem, ptr addr
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_collector_b_tf32_cta2_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_collector_b_tf32_cta2_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_collector_b_tf32_cta2_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_collector_b_tf32_cta2_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_collector_b_tf32_cta2_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_collector_b_tf32_cta2_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_collector_b_tf32_cta2_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_collector_b_tf32_cta2_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_collector_b_tf32_cta2_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_collector_b_tf32_cta2_param_4];
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::tf32.collector::a::discard.collector::b::lastuse [%r1], %rd1, %rd2, %r2, %p1;
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_collector_b_tf32_cta2_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_collector_b_tf32_cta2_param_1];
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::tf32.collector::a::discard.collector::b::lastuse [%r1], [%r3], %rd2, %r2, %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::tf32.ashift.collector::a::discard.collector::b::lastuse [%r1], [%r3], %rd2, %r2, %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::tf32.collector::a::lastuse.collector::b::fill [%r1], %rd1, %rd2, %r2, %p1;
@@ -299,15 +299,15 @@ define void @tcgen05_mma_collector_b_f8f6f4_cta2(ptr addrspace(6) %dtmem, ptr ad
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_collector_b_f8f6f4_cta2_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_collector_b_f8f6f4_cta2_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_collector_b_f8f6f4_cta2_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_collector_b_f8f6f4_cta2_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_collector_b_f8f6f4_cta2_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_collector_b_f8f6f4_cta2_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_collector_b_f8f6f4_cta2_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_collector_b_f8f6f4_cta2_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_collector_b_f8f6f4_cta2_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_collector_b_f8f6f4_cta2_param_4];
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::f8f6f4.collector::a::discard.collector::b::lastuse [%r1], %rd1, %rd2, %r2, %p1;
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_collector_b_f8f6f4_cta2_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_collector_b_f8f6f4_cta2_param_1];
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::f8f6f4.collector::a::discard.collector::b::fill [%r1], %rd1, %rd2, %r2, %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::f8f6f4.collector::a::discard.collector::b::use [%r1], %rd1, %rd2, %r2, %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::f8f6f4.collector::a::discard.collector::b::lastuse [%r1], [%r3], %rd2, %r2, %p1;
@@ -358,17 +358,17 @@ define void @tcgen05_mma_collector_b_block_scale_mxf8f6f4_cta1(ptr addrspace(6)
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_collector_b_block_scale_mxf8f6f4_cta1_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_collector_b_block_scale_mxf8f6f4_cta1_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_collector_b_block_scale_mxf8f6f4_cta1_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_collector_b_block_scale_mxf8f6f4_cta1_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_collector_b_block_scale_mxf8f6f4_cta1_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_collector_b_block_scale_mxf8f6f4_cta1_param_4];
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_collector_b_block_scale_mxf8f6f4_cta1_param_6];
-; CHECK-NEXT: ld.param.b32 %r4, [tcgen05_mma_collector_b_block_scale_mxf8f6f4_cta1_param_7];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_collector_b_block_scale_mxf8f6f4_cta1_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_collector_b_block_scale_mxf8f6f4_cta1_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_collector_b_block_scale_mxf8f6f4_cta1_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_collector_b_block_scale_mxf8f6f4_cta1_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_collector_b_block_scale_mxf8f6f4_cta1_param_6];
+; CHECK-NEXT: ld.param::func.b32 %r4, [tcgen05_mma_collector_b_block_scale_mxf8f6f4_cta1_param_7];
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::mxf8f6f4.block_scale.collector::a::discard.collector::b::lastuse [%r1], %rd1, %rd2, %r2, [%r3], [%r4], %p1;
-; CHECK-NEXT: ld.param.b32 %r5, [tcgen05_mma_collector_b_block_scale_mxf8f6f4_cta1_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r5, [tcgen05_mma_collector_b_block_scale_mxf8f6f4_cta1_param_1];
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::mxf8f6f4.block_scale.collector::a::discard.collector::b::fill [%r1], %rd1, %rd2, %r2, [%r3], [%r4], %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::mxf8f6f4.block_scale.collector::a::discard.collector::b::use [%r1], %rd1, %rd2, %r2, [%r3], [%r4], %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::mxf8f6f4.block_scale.collector::a::lastuse.collector::b::lastuse [%r1], %rd1, %rd2, %r2, [%r3], [%r4], %p1;
@@ -412,17 +412,17 @@ define void @tcgen05_mma_collector_b_block_scale_mxf8f6f4_cta2(ptr addrspace(6)
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_collector_b_block_scale_mxf8f6f4_cta2_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_collector_b_block_scale_mxf8f6f4_cta2_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_collector_b_block_scale_mxf8f6f4_cta2_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_collector_b_block_scale_mxf8f6f4_cta2_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_collector_b_block_scale_mxf8f6f4_cta2_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_collector_b_block_scale_mxf8f6f4_cta2_param_4];
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_collector_b_block_scale_mxf8f6f4_cta2_param_6];
-; CHECK-NEXT: ld.param.b32 %r4, [tcgen05_mma_collector_b_block_scale_mxf8f6f4_cta2_param_7];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_collector_b_block_scale_mxf8f6f4_cta2_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_collector_b_block_scale_mxf8f6f4_cta2_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_collector_b_block_scale_mxf8f6f4_cta2_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_collector_b_block_scale_mxf8f6f4_cta2_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_collector_b_block_scale_mxf8f6f4_cta2_param_6];
+; CHECK-NEXT: ld.param::func.b32 %r4, [tcgen05_mma_collector_b_block_scale_mxf8f6f4_cta2_param_7];
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::mxf8f6f4.block_scale.collector::a::discard.collector::b::lastuse [%r1], %rd1, %rd2, %r2, [%r3], [%r4], %p1;
-; CHECK-NEXT: ld.param.b32 %r5, [tcgen05_mma_collector_b_block_scale_mxf8f6f4_cta2_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r5, [tcgen05_mma_collector_b_block_scale_mxf8f6f4_cta2_param_1];
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::mxf8f6f4.block_scale.collector::a::lastuse.collector::b::lastuse [%r1], %rd1, %rd2, %r2, [%r3], [%r4], %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::mxf8f6f4.block_scale.collector::a::discard.collector::b::lastuse [%r1], [%r5], %rd2, %r2, [%r3], [%r4], %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::mxf8f6f4.block_scale.collector::a::fill.collector::b::use [%r1], [%r5], %rd2, %r2, [%r3], [%r4], %p1;
@@ -458,17 +458,17 @@ define void @tcgen05_mma_collector_b_block_scale_mxf4_cta1(ptr addrspace(6) %dtm
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_collector_b_block_scale_mxf4_cta1_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_collector_b_block_scale_mxf4_cta1_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_collector_b_block_scale_mxf4_cta1_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_collector_b_block_scale_mxf4_cta1_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_collector_b_block_scale_mxf4_cta1_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_collector_b_block_scale_mxf4_cta1_param_4];
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_collector_b_block_scale_mxf4_cta1_param_6];
-; CHECK-NEXT: ld.param.b32 %r4, [tcgen05_mma_collector_b_block_scale_mxf4_cta1_param_7];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_collector_b_block_scale_mxf4_cta1_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_collector_b_block_scale_mxf4_cta1_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_collector_b_block_scale_mxf4_cta1_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_collector_b_block_scale_mxf4_cta1_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_collector_b_block_scale_mxf4_cta1_param_6];
+; CHECK-NEXT: ld.param::func.b32 %r4, [tcgen05_mma_collector_b_block_scale_mxf4_cta1_param_7];
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::mxf4.block_scale.collector::a::discard.collector::b::lastuse [%r1], %rd1, %rd2, %r2, [%r3], [%r4], %p1;
-; CHECK-NEXT: ld.param.b32 %r5, [tcgen05_mma_collector_b_block_scale_mxf4_cta1_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r5, [tcgen05_mma_collector_b_block_scale_mxf4_cta1_param_1];
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::mxf4.block_scale.collector::a::lastuse.collector::b::fill [%r1], %rd1, %rd2, %r2, [%r3], [%r4], %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::mxf4.block_scale.collector::a::discard.collector::b::lastuse [%r1], [%r5], %rd2, %r2, [%r3], [%r4], %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::mxf4.block_scale.collector::a::fill.collector::b::use [%r1], [%r5], %rd2, %r2, [%r3], [%r4], %p1;
@@ -504,17 +504,17 @@ define void @tcgen05_mma_collector_b_block_scale_mxf4nvf4_cta1(ptr addrspace(6)
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_collector_b_block_scale_mxf4nvf4_cta1_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_collector_b_block_scale_mxf4nvf4_cta1_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_collector_b_block_scale_mxf4nvf4_cta1_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_collector_b_block_scale_mxf4nvf4_cta1_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_collector_b_block_scale_mxf4nvf4_cta1_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_collector_b_block_scale_mxf4nvf4_cta1_param_4];
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_collector_b_block_scale_mxf4nvf4_cta1_param_6];
-; CHECK-NEXT: ld.param.b32 %r4, [tcgen05_mma_collector_b_block_scale_mxf4nvf4_cta1_param_7];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_collector_b_block_scale_mxf4nvf4_cta1_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_collector_b_block_scale_mxf4nvf4_cta1_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_collector_b_block_scale_mxf4nvf4_cta1_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_collector_b_block_scale_mxf4nvf4_cta1_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_collector_b_block_scale_mxf4nvf4_cta1_param_6];
+; CHECK-NEXT: ld.param::func.b32 %r4, [tcgen05_mma_collector_b_block_scale_mxf4nvf4_cta1_param_7];
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.block16.collector::a::discard.collector::b::lastuse [%r1], %rd1, %rd2, %r2, [%r3], [%r4], %p1;
-; CHECK-NEXT: ld.param.b32 %r5, [tcgen05_mma_collector_b_block_scale_mxf4nvf4_cta1_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r5, [tcgen05_mma_collector_b_block_scale_mxf4nvf4_cta1_param_1];
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.block16.collector::a::lastuse.collector::b::fill [%r1], %rd1, %rd2, %r2, [%r3], [%r4], %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.block16.collector::a::discard.collector::b::lastuse [%r1], [%r5], %rd2, %r2, [%r3], [%r4], %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.block16.collector::a::fill.collector::b::use [%r1], [%r5], %rd2, %r2, [%r3], [%r4], %p1;
@@ -550,17 +550,17 @@ define void @tcgen05_mma_collector_b_block_scale_mxf4_cta2(ptr addrspace(6) %dtm
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_collector_b_block_scale_mxf4_cta2_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_collector_b_block_scale_mxf4_cta2_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_collector_b_block_scale_mxf4_cta2_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_collector_b_block_scale_mxf4_cta2_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_collector_b_block_scale_mxf4_cta2_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_collector_b_block_scale_mxf4_cta2_param_4];
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_collector_b_block_scale_mxf4_cta2_param_6];
-; CHECK-NEXT: ld.param.b32 %r4, [tcgen05_mma_collector_b_block_scale_mxf4_cta2_param_7];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_collector_b_block_scale_mxf4_cta2_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_collector_b_block_scale_mxf4_cta2_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_collector_b_block_scale_mxf4_cta2_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_collector_b_block_scale_mxf4_cta2_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_collector_b_block_scale_mxf4_cta2_param_6];
+; CHECK-NEXT: ld.param::func.b32 %r4, [tcgen05_mma_collector_b_block_scale_mxf4_cta2_param_7];
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::mxf4.block_scale.collector::a::discard.collector::b::lastuse [%r1], %rd1, %rd2, %r2, [%r3], [%r4], %p1;
-; CHECK-NEXT: ld.param.b32 %r5, [tcgen05_mma_collector_b_block_scale_mxf4_cta2_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r5, [tcgen05_mma_collector_b_block_scale_mxf4_cta2_param_1];
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::mxf4.block_scale.collector::a::lastuse.collector::b::lastuse [%r1], %rd1, %rd2, %r2, [%r3], [%r4], %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::mxf4.block_scale.collector::a::discard.collector::b::lastuse [%r1], [%r5], %rd2, %r2, [%r3], [%r4], %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::mxf4.block_scale.collector::a::fill.collector::b::use [%r1], [%r5], %rd2, %r2, [%r3], [%r4], %p1;
@@ -595,17 +595,17 @@ define void @tcgen05_mma_collector_b_block_scale_mxf4_block32_cta1(ptr addrspace
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_collector_b_block_scale_mxf4_block32_cta1_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_collector_b_block_scale_mxf4_block32_cta1_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_collector_b_block_scale_mxf4_block32_cta1_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_collector_b_block_scale_mxf4_block32_cta1_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_collector_b_block_scale_mxf4_block32_cta1_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_collector_b_block_scale_mxf4_block32_cta1_param_4];
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_collector_b_block_scale_mxf4_block32_cta1_param_6];
-; CHECK-NEXT: ld.param.b32 %r4, [tcgen05_mma_collector_b_block_scale_mxf4_block32_cta1_param_7];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_collector_b_block_scale_mxf4_block32_cta1_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_collector_b_block_scale_mxf4_block32_cta1_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_collector_b_block_scale_mxf4_block32_cta1_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_collector_b_block_scale_mxf4_block32_cta1_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_collector_b_block_scale_mxf4_block32_cta1_param_6];
+; CHECK-NEXT: ld.param::func.b32 %r4, [tcgen05_mma_collector_b_block_scale_mxf4_block32_cta1_param_7];
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::mxf4.block_scale.block32.collector::a::discard.collector::b::lastuse [%r1], %rd1, %rd2, %r2, [%r3], [%r4], %p1;
-; CHECK-NEXT: ld.param.b32 %r5, [tcgen05_mma_collector_b_block_scale_mxf4_block32_cta1_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r5, [tcgen05_mma_collector_b_block_scale_mxf4_block32_cta1_param_1];
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::mxf4.block_scale.block32.collector::a::lastuse.collector::b::fill [%r1], %rd1, %rd2, %r2, [%r3], [%r4], %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::mxf4.block_scale.block32.collector::a::discard.collector::b::lastuse [%r1], [%r5], %rd2, %r2, [%r3], [%r4], %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::mxf4.block_scale.block32.collector::a::discard [%r1], [%r5], %rd2, %r2, [%r3], [%r4], %p1;
@@ -638,17 +638,17 @@ define void @tcgen05_mma_collector_b_block_scale_mxf4nvf4_block16_cta2(ptr addrs
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_collector_b_block_scale_mxf4nvf4_block16_cta2_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_collector_b_block_scale_mxf4nvf4_block16_cta2_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_collector_b_block_scale_mxf4nvf4_block16_cta2_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_collector_b_block_scale_mxf4nvf4_block16_cta2_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_collector_b_block_scale_mxf4nvf4_block16_cta2_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_collector_b_block_scale_mxf4nvf4_block16_cta2_param_4];
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_collector_b_block_scale_mxf4nvf4_block16_cta2_param_6];
-; CHECK-NEXT: ld.param.b32 %r4, [tcgen05_mma_collector_b_block_scale_mxf4nvf4_block16_cta2_param_7];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_collector_b_block_scale_mxf4nvf4_block16_cta2_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_collector_b_block_scale_mxf4nvf4_block16_cta2_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_collector_b_block_scale_mxf4nvf4_block16_cta2_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_collector_b_block_scale_mxf4nvf4_block16_cta2_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_collector_b_block_scale_mxf4nvf4_block16_cta2_param_6];
+; CHECK-NEXT: ld.param::func.b32 %r4, [tcgen05_mma_collector_b_block_scale_mxf4nvf4_block16_cta2_param_7];
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.block16.collector::a::discard.collector::b::lastuse [%r1], %rd1, %rd2, %r2, [%r3], [%r4], %p1;
-; CHECK-NEXT: ld.param.b32 %r5, [tcgen05_mma_collector_b_block_scale_mxf4nvf4_block16_cta2_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r5, [tcgen05_mma_collector_b_block_scale_mxf4nvf4_block16_cta2_param_1];
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.block16.collector::a::lastuse.collector::b::lastuse [%r1], %rd1, %rd2, %r2, [%r3], [%r4], %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.block16.collector::a::discard.collector::b::lastuse [%r1], [%r5], %rd2, %r2, [%r3], [%r4], %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.block16.collector::a::discard [%r1], [%r5], %rd2, %r2, [%r3], [%r4], %p1;
@@ -681,17 +681,17 @@ define void @tcgen05_mma_collector_b_block_scale_mxf4nvf4_block32_cta1(ptr addrs
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_collector_b_block_scale_mxf4nvf4_block32_cta1_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_collector_b_block_scale_mxf4nvf4_block32_cta1_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_collector_b_block_scale_mxf4nvf4_block32_cta1_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_collector_b_block_scale_mxf4nvf4_block32_cta1_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_collector_b_block_scale_mxf4nvf4_block32_cta1_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_collector_b_block_scale_mxf4nvf4_block32_cta1_param_4];
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_collector_b_block_scale_mxf4nvf4_block32_cta1_param_6];
-; CHECK-NEXT: ld.param.b32 %r4, [tcgen05_mma_collector_b_block_scale_mxf4nvf4_block32_cta1_param_7];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_collector_b_block_scale_mxf4nvf4_block32_cta1_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_collector_b_block_scale_mxf4nvf4_block32_cta1_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_collector_b_block_scale_mxf4nvf4_block32_cta1_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_collector_b_block_scale_mxf4nvf4_block32_cta1_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_collector_b_block_scale_mxf4nvf4_block32_cta1_param_6];
+; CHECK-NEXT: ld.param::func.b32 %r4, [tcgen05_mma_collector_b_block_scale_mxf4nvf4_block32_cta1_param_7];
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.block32.collector::a::discard.collector::b::lastuse [%r1], %rd1, %rd2, %r2, [%r3], [%r4], %p1;
-; CHECK-NEXT: ld.param.b32 %r5, [tcgen05_mma_collector_b_block_scale_mxf4nvf4_block32_cta1_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r5, [tcgen05_mma_collector_b_block_scale_mxf4nvf4_block32_cta1_param_1];
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.block32.collector::a::lastuse.collector::b::fill [%r1], %rd1, %rd2, %r2, [%r3], [%r4], %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.block32.collector::a::discard.collector::b::lastuse [%r1], [%r5], %rd2, %r2, [%r3], [%r4], %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::mxf4nvf4.block_scale.block32.collector::a::discard [%r1], [%r5], %rd2, %r2, [%r3], [%r4], %p1;
@@ -724,17 +724,17 @@ define void @tcgen05_mma_collector_b_block_scale_mxf8f6f4_block32_cta1(ptr addrs
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_collector_b_block_scale_mxf8f6f4_block32_cta1_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_collector_b_block_scale_mxf8f6f4_block32_cta1_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_collector_b_block_scale_mxf8f6f4_block32_cta1_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_collector_b_block_scale_mxf8f6f4_block32_cta1_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_collector_b_block_scale_mxf8f6f4_block32_cta1_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_collector_b_block_scale_mxf8f6f4_block32_cta1_param_4];
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_collector_b_block_scale_mxf8f6f4_block32_cta1_param_6];
-; CHECK-NEXT: ld.param.b32 %r4, [tcgen05_mma_collector_b_block_scale_mxf8f6f4_block32_cta1_param_7];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_collector_b_block_scale_mxf8f6f4_block32_cta1_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_collector_b_block_scale_mxf8f6f4_block32_cta1_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_collector_b_block_scale_mxf8f6f4_block32_cta1_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_collector_b_block_scale_mxf8f6f4_block32_cta1_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_collector_b_block_scale_mxf8f6f4_block32_cta1_param_6];
+; CHECK-NEXT: ld.param::func.b32 %r4, [tcgen05_mma_collector_b_block_scale_mxf8f6f4_block32_cta1_param_7];
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::mxf8f6f4.block_scale.block32.collector::a::discard.collector::b::lastuse [%r1], %rd1, %rd2, %r2, [%r3], [%r4], %p1;
-; CHECK-NEXT: ld.param.b32 %r5, [tcgen05_mma_collector_b_block_scale_mxf8f6f4_block32_cta1_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r5, [tcgen05_mma_collector_b_block_scale_mxf8f6f4_block32_cta1_param_1];
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::mxf8f6f4.block_scale.block32.collector::a::lastuse.collector::b::lastuse [%r1], %rd1, %rd2, %r2, [%r3], [%r4], %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::mxf8f6f4.block_scale.block32.collector::a::discard.collector::b::lastuse [%r1], [%r5], %rd2, %r2, [%r3], [%r4], %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::mxf8f6f4.block_scale.block32.collector::a::discard [%r1], [%r5], %rd2, %r2, [%r3], [%r4], %p1;
@@ -770,15 +770,15 @@ define void @tcgen05_mma_collector_b_scale_d_f16_cta1(ptr addrspace(6) %dtmem, p
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_collector_b_scale_d_f16_cta1_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_collector_b_scale_d_f16_cta1_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_collector_b_scale_d_f16_cta1_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_collector_b_scale_d_f16_cta1_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_collector_b_scale_d_f16_cta1_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_collector_b_scale_d_f16_cta1_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_collector_b_scale_d_f16_cta1_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_collector_b_scale_d_f16_cta1_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_collector_b_scale_d_f16_cta1_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_collector_b_scale_d_f16_cta1_param_4];
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::f16.collector::a::discard.collector::b::lastuse [%r1], %rd1, %rd2, %r2, %p1, 0;
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_collector_b_scale_d_f16_cta1_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_collector_b_scale_d_f16_cta1_param_1];
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::f16.collector::a::discard.collector::b::fill [%r1], %rd1, %rd2, %r2, %p1, 0;
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::f16.collector::a::lastuse.collector::b::lastuse [%r1], %rd1, %rd2, %r2, %p1, 0;
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::f16.collector::a::discard.collector::b::lastuse [%r1], [%r3], %rd2, %r2, %p1, 0;
@@ -817,15 +817,15 @@ define void @tcgen05_mma_collector_b_scale_d_f16_cta2(ptr addrspace(6) %dtmem, p
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_collector_b_scale_d_f16_cta2_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_collector_b_scale_d_f16_cta2_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_collector_b_scale_d_f16_cta2_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_collector_b_scale_d_f16_cta2_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_collector_b_scale_d_f16_cta2_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_collector_b_scale_d_f16_cta2_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_collector_b_scale_d_f16_cta2_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_collector_b_scale_d_f16_cta2_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_collector_b_scale_d_f16_cta2_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_collector_b_scale_d_f16_cta2_param_4];
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::f16.collector::a::discard.collector::b::lastuse [%r1], %rd1, %rd2, %r2, %p1, 0;
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_collector_b_scale_d_f16_cta2_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_collector_b_scale_d_f16_cta2_param_1];
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::f16.collector::a::discard.collector::b::lastuse [%r1], [%r3], %rd2, %r2, %p1, 0;
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::f16.ashift.collector::a::lastuse.collector::b::lastuse [%r1], [%r3], %rd2, %r2, %p1, 0;
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::f16.ashift.collector::a::lastuse [%r1], [%r3], %rd2, %r2, %p1, 0;
@@ -858,15 +858,15 @@ define void @tcgen05_mma_collector_b_scale_d_tf32_cta2(ptr addrspace(6) %dtmem,
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_collector_b_scale_d_tf32_cta2_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_collector_b_scale_d_tf32_cta2_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_collector_b_scale_d_tf32_cta2_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_collector_b_scale_d_tf32_cta2_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_collector_b_scale_d_tf32_cta2_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_collector_b_scale_d_tf32_cta2_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_collector_b_scale_d_tf32_cta2_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_collector_b_scale_d_tf32_cta2_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_collector_b_scale_d_tf32_cta2_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_collector_b_scale_d_tf32_cta2_param_4];
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::tf32.collector::a::discard.collector::b::lastuse [%r1], %rd1, %rd2, %r2, %p1, 0;
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_collector_b_scale_d_tf32_cta2_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_collector_b_scale_d_tf32_cta2_param_1];
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::tf32.collector::a::discard.collector::b::lastuse [%r1], [%r3], %rd2, %r2, %p1, 0;
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::tf32.ashift.collector::a::lastuse.collector::b::lastuse [%r1], [%r3], %rd2, %r2, %p1, 0;
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::tf32.ashift.collector::a::lastuse [%r1], [%r3], %rd2, %r2, %p1, 0;
@@ -900,15 +900,15 @@ define void @tcgen05_mma_collector_b_scale_d_tf32_cta1(ptr addrspace(6) %dtmem,
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_collector_b_scale_d_tf32_cta1_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_collector_b_scale_d_tf32_cta1_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_collector_b_scale_d_tf32_cta1_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_collector_b_scale_d_tf32_cta1_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_collector_b_scale_d_tf32_cta1_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_collector_b_scale_d_tf32_cta1_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_collector_b_scale_d_tf32_cta1_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_collector_b_scale_d_tf32_cta1_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_collector_b_scale_d_tf32_cta1_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_collector_b_scale_d_tf32_cta1_param_4];
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::tf32.collector::a::discard.collector::b::lastuse [%r1], %rd1, %rd2, %r2, %p1, 0;
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_collector_b_scale_d_tf32_cta1_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_collector_b_scale_d_tf32_cta1_param_1];
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::tf32.collector::a::lastuse.collector::b::fill [%r1], %rd1, %rd2, %r2, %p1, 0;
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::tf32.collector::a::discard.collector::b::lastuse [%r1], [%r3], %rd2, %r2, %p1, 0;
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::tf32.ashift.collector::a::discard.collector::b::lastuse [%r1], [%r3], %rd2, %r2, %p1, 0;
@@ -943,17 +943,17 @@ define void @tcgen05_mma_collector_b_block_scale_mxf8f6f4_block32_cta2(ptr addrs
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_collector_b_block_scale_mxf8f6f4_block32_cta2_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_collector_b_block_scale_mxf8f6f4_block32_cta2_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_collector_b_block_scale_mxf8f6f4_block32_cta2_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_collector_b_block_scale_mxf8f6f4_block32_cta2_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_collector_b_block_scale_mxf8f6f4_block32_cta2_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_collector_b_block_scale_mxf8f6f4_block32_cta2_param_4];
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_collector_b_block_scale_mxf8f6f4_block32_cta2_param_6];
-; CHECK-NEXT: ld.param.b32 %r4, [tcgen05_mma_collector_b_block_scale_mxf8f6f4_block32_cta2_param_7];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_collector_b_block_scale_mxf8f6f4_block32_cta2_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_collector_b_block_scale_mxf8f6f4_block32_cta2_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_collector_b_block_scale_mxf8f6f4_block32_cta2_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_collector_b_block_scale_mxf8f6f4_block32_cta2_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_collector_b_block_scale_mxf8f6f4_block32_cta2_param_6];
+; CHECK-NEXT: ld.param::func.b32 %r4, [tcgen05_mma_collector_b_block_scale_mxf8f6f4_block32_cta2_param_7];
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::mxf8f6f4.block_scale.block32.collector::a::discard.collector::b::lastuse [%r1], %rd1, %rd2, %r2, [%r3], [%r4], %p1;
-; CHECK-NEXT: ld.param.b32 %r5, [tcgen05_mma_collector_b_block_scale_mxf8f6f4_block32_cta2_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r5, [tcgen05_mma_collector_b_block_scale_mxf8f6f4_block32_cta2_param_1];
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::mxf8f6f4.block_scale.block32.collector::a::lastuse.collector::b::lastuse [%r1], %rd1, %rd2, %r2, [%r3], [%r4], %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::mxf8f6f4.block_scale.block32.collector::a::discard.collector::b::lastuse [%r1], [%r5], %rd2, %r2, [%r3], [%r4], %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::mxf8f6f4.block_scale.block32.collector::a::discard [%r1], [%r5], %rd2, %r2, [%r3], [%r4], %p1;
@@ -986,17 +986,17 @@ define void @tcgen05_mma_collector_b_block_scale_mxf4_block32_cta2(ptr addrspace
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_collector_b_block_scale_mxf4_block32_cta2_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_collector_b_block_scale_mxf4_block32_cta2_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_collector_b_block_scale_mxf4_block32_cta2_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_collector_b_block_scale_mxf4_block32_cta2_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_collector_b_block_scale_mxf4_block32_cta2_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_collector_b_block_scale_mxf4_block32_cta2_param_4];
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_collector_b_block_scale_mxf4_block32_cta2_param_6];
-; CHECK-NEXT: ld.param.b32 %r4, [tcgen05_mma_collector_b_block_scale_mxf4_block32_cta2_param_7];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_collector_b_block_scale_mxf4_block32_cta2_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_collector_b_block_scale_mxf4_block32_cta2_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_collector_b_block_scale_mxf4_block32_cta2_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_collector_b_block_scale_mxf4_block32_cta2_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_collector_b_block_scale_mxf4_block32_cta2_param_6];
+; CHECK-NEXT: ld.param::func.b32 %r4, [tcgen05_mma_collector_b_block_scale_mxf4_block32_cta2_param_7];
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::mxf4.block_scale.block32.collector::a::discard.collector::b::lastuse [%r1], %rd1, %rd2, %r2, [%r3], [%r4], %p1;
-; CHECK-NEXT: ld.param.b32 %r5, [tcgen05_mma_collector_b_block_scale_mxf4_block32_cta2_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r5, [tcgen05_mma_collector_b_block_scale_mxf4_block32_cta2_param_1];
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::mxf4.block_scale.block32.collector::a::lastuse.collector::b::fill [%r1], %rd1, %rd2, %r2, [%r3], [%r4], %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::mxf4.block_scale.block32.collector::a::discard.collector::b::lastuse [%r1], [%r5], %rd2, %r2, [%r3], [%r4], %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::mxf4.block_scale.block32.collector::a::discard [%r1], [%r5], %rd2, %r2, [%r3], [%r4], %p1;
@@ -1029,17 +1029,17 @@ define void @tcgen05_mma_collector_b_block_scale_mxf4nvf4_block32_cta2(ptr addrs
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_collector_b_block_scale_mxf4nvf4_block32_cta2_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_collector_b_block_scale_mxf4nvf4_block32_cta2_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_collector_b_block_scale_mxf4nvf4_block32_cta2_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_collector_b_block_scale_mxf4nvf4_block32_cta2_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_collector_b_block_scale_mxf4nvf4_block32_cta2_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_collector_b_block_scale_mxf4nvf4_block32_cta2_param_4];
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_collector_b_block_scale_mxf4nvf4_block32_cta2_param_6];
-; CHECK-NEXT: ld.param.b32 %r4, [tcgen05_mma_collector_b_block_scale_mxf4nvf4_block32_cta2_param_7];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_collector_b_block_scale_mxf4nvf4_block32_cta2_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_collector_b_block_scale_mxf4nvf4_block32_cta2_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_collector_b_block_scale_mxf4nvf4_block32_cta2_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_collector_b_block_scale_mxf4nvf4_block32_cta2_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_collector_b_block_scale_mxf4nvf4_block32_cta2_param_6];
+; CHECK-NEXT: ld.param::func.b32 %r4, [tcgen05_mma_collector_b_block_scale_mxf4nvf4_block32_cta2_param_7];
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.block32.collector::a::discard.collector::b::lastuse [%r1], %rd1, %rd2, %r2, [%r3], [%r4], %p1;
-; CHECK-NEXT: ld.param.b32 %r5, [tcgen05_mma_collector_b_block_scale_mxf4nvf4_block32_cta2_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r5, [tcgen05_mma_collector_b_block_scale_mxf4nvf4_block32_cta2_param_1];
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.block32.collector::a::lastuse.collector::b::fill [%r1], %rd1, %rd2, %r2, [%r3], [%r4], %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.block32.collector::a::discard.collector::b::lastuse [%r1], [%r5], %rd2, %r2, [%r3], [%r4], %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::mxf4nvf4.block_scale.block32.collector::a::discard [%r1], [%r5], %rd2, %r2, [%r3], [%r4], %p1;
diff --git a/llvm/test/CodeGen/NVPTX/tcgen05-mma-disable-output-lane-collector-b.ll b/llvm/test/CodeGen/NVPTX/tcgen05-mma-disable-output-lane-collector-b.ll
index 886f7f7930276..ce878e31769c3 100644
--- a/llvm/test/CodeGen/NVPTX/tcgen05-mma-disable-output-lane-collector-b.ll
+++ b/llvm/test/CodeGen/NVPTX/tcgen05-mma-disable-output-lane-collector-b.ll
@@ -16,16 +16,16 @@ define void @tcgen05_mma_disable_output_lane_collector_b_f16_cta1(ptr addrspace(
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_disable_output_lane_collector_b_f16_cta1_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_disable_output_lane_collector_b_f16_cta1_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_disable_output_lane_collector_b_f16_cta1_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_disable_output_lane_collector_b_f16_cta1_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_disable_output_lane_collector_b_f16_cta1_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_disable_output_lane_collector_b_f16_cta1_param_4];
-; CHECK-NEXT: ld.param.v4.b32 {%r3, %r4, %r5, %r6}, [tcgen05_mma_disable_output_lane_collector_b_f16_cta1_param_6];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_disable_output_lane_collector_b_f16_cta1_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_disable_output_lane_collector_b_f16_cta1_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_disable_output_lane_collector_b_f16_cta1_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_disable_output_lane_collector_b_f16_cta1_param_4];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r3, %r4, %r5, %r6}, [tcgen05_mma_disable_output_lane_collector_b_f16_cta1_param_6];
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::f16.collector::a::discard.collector::b::lastuse [%r1], %rd1, %rd2, %r2, {%r3, %r4, %r5, %r6}, %p1;
-; CHECK-NEXT: ld.param.b32 %r7, [tcgen05_mma_disable_output_lane_collector_b_f16_cta1_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r7, [tcgen05_mma_disable_output_lane_collector_b_f16_cta1_param_1];
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::f16.collector::a::discard.collector::b::fill [%r1], %rd1, %rd2, %r2, {%r3, %r4, %r5, %r6}, %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::f16.collector::a::discard.collector::b::use [%r1], %rd1, %rd2, %r2, {%r3, %r4, %r5, %r6}, %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::f16.collector::a::discard.collector::b::lastuse [%r1], [%r7], %rd2, %r2, {%r3, %r4, %r5, %r6}, %p1;
@@ -78,17 +78,17 @@ define void @tcgen05_mma_disable_output_lane_collector_b_f16_cta2(ptr addrspace(
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_disable_output_lane_collector_b_f16_cta2_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_disable_output_lane_collector_b_f16_cta2_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_disable_output_lane_collector_b_f16_cta2_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_disable_output_lane_collector_b_f16_cta2_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_disable_output_lane_collector_b_f16_cta2_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_disable_output_lane_collector_b_f16_cta2_param_4];
-; CHECK-NEXT: ld.param.v4.b32 {%r3, %r4, %r5, %r6}, [tcgen05_mma_disable_output_lane_collector_b_f16_cta2_param_6+16];
-; CHECK-NEXT: ld.param.v4.b32 {%r7, %r8, %r9, %r10}, [tcgen05_mma_disable_output_lane_collector_b_f16_cta2_param_6];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_disable_output_lane_collector_b_f16_cta2_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_disable_output_lane_collector_b_f16_cta2_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_disable_output_lane_collector_b_f16_cta2_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_disable_output_lane_collector_b_f16_cta2_param_4];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r3, %r4, %r5, %r6}, [tcgen05_mma_disable_output_lane_collector_b_f16_cta2_param_6+16];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r7, %r8, %r9, %r10}, [tcgen05_mma_disable_output_lane_collector_b_f16_cta2_param_6];
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::f16.collector::a::discard.collector::b::lastuse [%r1], %rd1, %rd2, %r2, {%r7, %r8, %r9, %r10, %r3, %r4, %r5, %r6}, %p1;
-; CHECK-NEXT: ld.param.b32 %r11, [tcgen05_mma_disable_output_lane_collector_b_f16_cta2_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r11, [tcgen05_mma_disable_output_lane_collector_b_f16_cta2_param_1];
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::f16.collector::a::discard.collector::b::fill [%r1], %rd1, %rd2, %r2, {%r7, %r8, %r9, %r10, %r3, %r4, %r5, %r6}, %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::f16.collector::a::discard.collector::b::lastuse [%r1], [%r11], %rd2, %r2, {%r7, %r8, %r9, %r10, %r3, %r4, %r5, %r6}, %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::f16.ashift.collector::a::discard.collector::b::use [%r1], [%r11], %rd2, %r2, {%r7, %r8, %r9, %r10, %r3, %r4, %r5, %r6}, %p1;
@@ -126,16 +126,16 @@ define void @tcgen05_mma_disable_output_lane_collector_b_tf32_cta1(ptr addrspace
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_disable_output_lane_collector_b_tf32_cta1_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_disable_output_lane_collector_b_tf32_cta1_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_disable_output_lane_collector_b_tf32_cta1_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_disable_output_lane_collector_b_tf32_cta1_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_disable_output_lane_collector_b_tf32_cta1_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_disable_output_lane_collector_b_tf32_cta1_param_4];
-; CHECK-NEXT: ld.param.v4.b32 {%r3, %r4, %r5, %r6}, [tcgen05_mma_disable_output_lane_collector_b_tf32_cta1_param_6];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_disable_output_lane_collector_b_tf32_cta1_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_disable_output_lane_collector_b_tf32_cta1_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_disable_output_lane_collector_b_tf32_cta1_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_disable_output_lane_collector_b_tf32_cta1_param_4];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r3, %r4, %r5, %r6}, [tcgen05_mma_disable_output_lane_collector_b_tf32_cta1_param_6];
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::tf32.collector::a::discard.collector::b::lastuse [%r1], %rd1, %rd2, %r2, {%r3, %r4, %r5, %r6}, %p1;
-; CHECK-NEXT: ld.param.b32 %r7, [tcgen05_mma_disable_output_lane_collector_b_tf32_cta1_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r7, [tcgen05_mma_disable_output_lane_collector_b_tf32_cta1_param_1];
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::tf32.collector::a::discard.collector::b::fill [%r1], [%r7], %rd2, %r2, {%r3, %r4, %r5, %r6}, %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::tf32.ashift.collector::a::discard.collector::b::use [%r1], [%r7], %rd2, %r2, {%r3, %r4, %r5, %r6}, %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::tf32.collector::a::lastuse.collector::b::lastuse [%r1], %rd1, %rd2, %r2, {%r3, %r4, %r5, %r6}, %p1;
@@ -173,17 +173,17 @@ define void @tcgen05_mma_disable_output_lane_collector_b_tf32_cta2(ptr addrspace
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_disable_output_lane_collector_b_tf32_cta2_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_disable_output_lane_collector_b_tf32_cta2_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_disable_output_lane_collector_b_tf32_cta2_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_disable_output_lane_collector_b_tf32_cta2_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_disable_output_lane_collector_b_tf32_cta2_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_disable_output_lane_collector_b_tf32_cta2_param_4];
-; CHECK-NEXT: ld.param.v4.b32 {%r3, %r4, %r5, %r6}, [tcgen05_mma_disable_output_lane_collector_b_tf32_cta2_param_6+16];
-; CHECK-NEXT: ld.param.v4.b32 {%r7, %r8, %r9, %r10}, [tcgen05_mma_disable_output_lane_collector_b_tf32_cta2_param_6];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_disable_output_lane_collector_b_tf32_cta2_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_disable_output_lane_collector_b_tf32_cta2_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_disable_output_lane_collector_b_tf32_cta2_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_disable_output_lane_collector_b_tf32_cta2_param_4];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r3, %r4, %r5, %r6}, [tcgen05_mma_disable_output_lane_collector_b_tf32_cta2_param_6+16];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r7, %r8, %r9, %r10}, [tcgen05_mma_disable_output_lane_collector_b_tf32_cta2_param_6];
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::tf32.collector::a::discard.collector::b::fill [%r1], %rd1, %rd2, %r2, {%r7, %r8, %r9, %r10, %r3, %r4, %r5, %r6}, %p1;
-; CHECK-NEXT: ld.param.b32 %r11, [tcgen05_mma_disable_output_lane_collector_b_tf32_cta2_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r11, [tcgen05_mma_disable_output_lane_collector_b_tf32_cta2_param_1];
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::tf32.collector::a::discard.collector::b::use [%r1], [%r11], %rd2, %r2, {%r7, %r8, %r9, %r10, %r3, %r4, %r5, %r6}, %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::tf32.ashift.collector::a::lastuse.collector::b::lastuse [%r1], [%r11], %rd2, %r2, {%r7, %r8, %r9, %r10, %r3, %r4, %r5, %r6}, %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::tf32.ashift.collector::a::lastuse [%r1], [%r11], %rd2, %r2, {%r7, %r8, %r9, %r10, %r3, %r4, %r5, %r6}, %p1;
@@ -215,16 +215,16 @@ define void @tcgen05_mma_disable_output_lane_collector_b_f8f6f4_cta1(ptr addrspa
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_disable_output_lane_collector_b_f8f6f4_cta1_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_disable_output_lane_collector_b_f8f6f4_cta1_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_disable_output_lane_collector_b_f8f6f4_cta1_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_disable_output_lane_collector_b_f8f6f4_cta1_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_disable_output_lane_collector_b_f8f6f4_cta1_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_disable_output_lane_collector_b_f8f6f4_cta1_param_4];
-; CHECK-NEXT: ld.param.v4.b32 {%r3, %r4, %r5, %r6}, [tcgen05_mma_disable_output_lane_collector_b_f8f6f4_cta1_param_6];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_disable_output_lane_collector_b_f8f6f4_cta1_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_disable_output_lane_collector_b_f8f6f4_cta1_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_disable_output_lane_collector_b_f8f6f4_cta1_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_disable_output_lane_collector_b_f8f6f4_cta1_param_4];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r3, %r4, %r5, %r6}, [tcgen05_mma_disable_output_lane_collector_b_f8f6f4_cta1_param_6];
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::f8f6f4.collector::a::discard.collector::b::lastuse [%r1], %rd1, %rd2, %r2, {%r3, %r4, %r5, %r6}, %p1;
-; CHECK-NEXT: ld.param.b32 %r7, [tcgen05_mma_disable_output_lane_collector_b_f8f6f4_cta1_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r7, [tcgen05_mma_disable_output_lane_collector_b_f8f6f4_cta1_param_1];
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::f8f6f4.collector::a::discard.collector::b::fill [%r1], [%r7], %rd2, %r2, {%r3, %r4, %r5, %r6}, %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::f8f6f4.ashift.collector::a::discard.collector::b::use [%r1], [%r7], %rd2, %r2, {%r3, %r4, %r5, %r6}, %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::f8f6f4.collector::a::fill.collector::b::lastuse [%r1], %rd1, %rd2, %r2, {%r3, %r4, %r5, %r6}, %p1;
@@ -259,17 +259,17 @@ define void @tcgen05_mma_disable_output_lane_collector_b_f8f6f4_cta2(ptr addrspa
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_disable_output_lane_collector_b_f8f6f4_cta2_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_disable_output_lane_collector_b_f8f6f4_cta2_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_disable_output_lane_collector_b_f8f6f4_cta2_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_disable_output_lane_collector_b_f8f6f4_cta2_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_disable_output_lane_collector_b_f8f6f4_cta2_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_disable_output_lane_collector_b_f8f6f4_cta2_param_4];
-; CHECK-NEXT: ld.param.v4.b32 {%r3, %r4, %r5, %r6}, [tcgen05_mma_disable_output_lane_collector_b_f8f6f4_cta2_param_6+16];
-; CHECK-NEXT: ld.param.v4.b32 {%r7, %r8, %r9, %r10}, [tcgen05_mma_disable_output_lane_collector_b_f8f6f4_cta2_param_6];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_disable_output_lane_collector_b_f8f6f4_cta2_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_disable_output_lane_collector_b_f8f6f4_cta2_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_disable_output_lane_collector_b_f8f6f4_cta2_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_disable_output_lane_collector_b_f8f6f4_cta2_param_4];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r3, %r4, %r5, %r6}, [tcgen05_mma_disable_output_lane_collector_b_f8f6f4_cta2_param_6+16];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r7, %r8, %r9, %r10}, [tcgen05_mma_disable_output_lane_collector_b_f8f6f4_cta2_param_6];
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::f8f6f4.collector::a::discard.collector::b::lastuse [%r1], %rd1, %rd2, %r2, {%r7, %r8, %r9, %r10, %r3, %r4, %r5, %r6}, %p1;
-; CHECK-NEXT: ld.param.b32 %r11, [tcgen05_mma_disable_output_lane_collector_b_f8f6f4_cta2_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r11, [tcgen05_mma_disable_output_lane_collector_b_f8f6f4_cta2_param_1];
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::f8f6f4.collector::a::discard.collector::b::use [%r1], [%r11], %rd2, %r2, {%r7, %r8, %r9, %r10, %r3, %r4, %r5, %r6}, %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::f8f6f4.ashift.collector::a::lastuse.collector::b::fill [%r1], [%r11], %rd2, %r2, {%r7, %r8, %r9, %r10, %r3, %r4, %r5, %r6}, %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::f8f6f4.ashift.collector::a::lastuse [%r1], [%r11], %rd2, %r2, {%r7, %r8, %r9, %r10, %r3, %r4, %r5, %r6}, %p1;
@@ -301,16 +301,16 @@ define void @tcgen05_mma_disable_output_lane_collector_b_f16_scale_d_cta1(ptr ad
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_disable_output_lane_collector_b_f16_scale_d_cta1_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_disable_output_lane_collector_b_f16_scale_d_cta1_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_disable_output_lane_collector_b_f16_scale_d_cta1_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_disable_output_lane_collector_b_f16_scale_d_cta1_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_disable_output_lane_collector_b_f16_scale_d_cta1_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_disable_output_lane_collector_b_f16_scale_d_cta1_param_4];
-; CHECK-NEXT: ld.param.v4.b32 {%r3, %r4, %r5, %r6}, [tcgen05_mma_disable_output_lane_collector_b_f16_scale_d_cta1_param_6];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_disable_output_lane_collector_b_f16_scale_d_cta1_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_disable_output_lane_collector_b_f16_scale_d_cta1_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_disable_output_lane_collector_b_f16_scale_d_cta1_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_disable_output_lane_collector_b_f16_scale_d_cta1_param_4];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r3, %r4, %r5, %r6}, [tcgen05_mma_disable_output_lane_collector_b_f16_scale_d_cta1_param_6];
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::f16.collector::a::discard.collector::b::lastuse [%r1], %rd1, %rd2, %r2, {%r3, %r4, %r5, %r6}, %p1, 5;
-; CHECK-NEXT: ld.param.b32 %r7, [tcgen05_mma_disable_output_lane_collector_b_f16_scale_d_cta1_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r7, [tcgen05_mma_disable_output_lane_collector_b_f16_scale_d_cta1_param_1];
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::f16.collector::a::discard.collector::b::fill [%r1], [%r7], %rd2, %r2, {%r3, %r4, %r5, %r6}, %p1, 3;
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::f16.ashift.collector::a::discard.collector::b::use [%r1], [%r7], %rd2, %r2, {%r3, %r4, %r5, %r6}, %p1, 7;
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::f16.collector::a::lastuse.collector::b::lastuse [%r1], %rd1, %rd2, %r2, {%r3, %r4, %r5, %r6}, %p1, 2;
@@ -345,16 +345,16 @@ define void @tcgen05_mma_disable_output_lane_collector_b_tf32_scale_d_cta1(ptr a
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_disable_output_lane_collector_b_tf32_scale_d_cta1_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_disable_output_lane_collector_b_tf32_scale_d_cta1_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_disable_output_lane_collector_b_tf32_scale_d_cta1_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_disable_output_lane_collector_b_tf32_scale_d_cta1_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_disable_output_lane_collector_b_tf32_scale_d_cta1_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_disable_output_lane_collector_b_tf32_scale_d_cta1_param_4];
-; CHECK-NEXT: ld.param.v4.b32 {%r3, %r4, %r5, %r6}, [tcgen05_mma_disable_output_lane_collector_b_tf32_scale_d_cta1_param_6];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_disable_output_lane_collector_b_tf32_scale_d_cta1_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_disable_output_lane_collector_b_tf32_scale_d_cta1_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_disable_output_lane_collector_b_tf32_scale_d_cta1_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_disable_output_lane_collector_b_tf32_scale_d_cta1_param_4];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r3, %r4, %r5, %r6}, [tcgen05_mma_disable_output_lane_collector_b_tf32_scale_d_cta1_param_6];
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::tf32.collector::a::discard.collector::b::fill [%r1], %rd1, %rd2, %r2, {%r3, %r4, %r5, %r6}, %p1, 4;
-; CHECK-NEXT: ld.param.b32 %r7, [tcgen05_mma_disable_output_lane_collector_b_tf32_scale_d_cta1_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r7, [tcgen05_mma_disable_output_lane_collector_b_tf32_scale_d_cta1_param_1];
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::tf32.collector::a::discard.collector::b::use [%r1], [%r7], %rd2, %r2, {%r3, %r4, %r5, %r6}, %p1, 6;
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::tf32.ashift.collector::a::lastuse.collector::b::lastuse [%r1], [%r7], %rd2, %r2, {%r3, %r4, %r5, %r6}, %p1, 1;
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::tf32.ashift.collector::a::lastuse [%r1], [%r7], %rd2, %r2, {%r3, %r4, %r5, %r6}, %p1, 1;
@@ -386,17 +386,17 @@ define void @tcgen05_mma_disable_output_lane_collector_b_f16_scale_d_cta2(ptr ad
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_disable_output_lane_collector_b_f16_scale_d_cta2_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_disable_output_lane_collector_b_f16_scale_d_cta2_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_disable_output_lane_collector_b_f16_scale_d_cta2_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_disable_output_lane_collector_b_f16_scale_d_cta2_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_disable_output_lane_collector_b_f16_scale_d_cta2_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_disable_output_lane_collector_b_f16_scale_d_cta2_param_4];
-; CHECK-NEXT: ld.param.v4.b32 {%r3, %r4, %r5, %r6}, [tcgen05_mma_disable_output_lane_collector_b_f16_scale_d_cta2_param_6+16];
-; CHECK-NEXT: ld.param.v4.b32 {%r7, %r8, %r9, %r10}, [tcgen05_mma_disable_output_lane_collector_b_f16_scale_d_cta2_param_6];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_disable_output_lane_collector_b_f16_scale_d_cta2_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_disable_output_lane_collector_b_f16_scale_d_cta2_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_disable_output_lane_collector_b_f16_scale_d_cta2_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_disable_output_lane_collector_b_f16_scale_d_cta2_param_4];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r3, %r4, %r5, %r6}, [tcgen05_mma_disable_output_lane_collector_b_f16_scale_d_cta2_param_6+16];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r7, %r8, %r9, %r10}, [tcgen05_mma_disable_output_lane_collector_b_f16_scale_d_cta2_param_6];
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::f16.collector::a::discard.collector::b::lastuse [%r1], %rd1, %rd2, %r2, {%r7, %r8, %r9, %r10, %r3, %r4, %r5, %r6}, %p1, 5;
-; CHECK-NEXT: ld.param.b32 %r11, [tcgen05_mma_disable_output_lane_collector_b_f16_scale_d_cta2_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r11, [tcgen05_mma_disable_output_lane_collector_b_f16_scale_d_cta2_param_1];
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::f16.collector::a::discard.collector::b::fill [%r1], [%r11], %rd2, %r2, {%r7, %r8, %r9, %r10, %r3, %r4, %r5, %r6}, %p1, 3;
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::f16.ashift.collector::a::lastuse.collector::b::use [%r1], [%r11], %rd2, %r2, {%r7, %r8, %r9, %r10, %r3, %r4, %r5, %r6}, %p1, 7;
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::f16.ashift.collector::a::lastuse [%r1], [%r11], %rd2, %r2, {%r7, %r8, %r9, %r10, %r3, %r4, %r5, %r6}, %p1, 7;
@@ -428,17 +428,17 @@ define void @tcgen05_mma_disable_output_lane_collector_b_tf32_scale_d_cta2(ptr a
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_disable_output_lane_collector_b_tf32_scale_d_cta2_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_disable_output_lane_collector_b_tf32_scale_d_cta2_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_disable_output_lane_collector_b_tf32_scale_d_cta2_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_disable_output_lane_collector_b_tf32_scale_d_cta2_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_disable_output_lane_collector_b_tf32_scale_d_cta2_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_disable_output_lane_collector_b_tf32_scale_d_cta2_param_4];
-; CHECK-NEXT: ld.param.v4.b32 {%r3, %r4, %r5, %r6}, [tcgen05_mma_disable_output_lane_collector_b_tf32_scale_d_cta2_param_6+16];
-; CHECK-NEXT: ld.param.v4.b32 {%r7, %r8, %r9, %r10}, [tcgen05_mma_disable_output_lane_collector_b_tf32_scale_d_cta2_param_6];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_disable_output_lane_collector_b_tf32_scale_d_cta2_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_disable_output_lane_collector_b_tf32_scale_d_cta2_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_disable_output_lane_collector_b_tf32_scale_d_cta2_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_disable_output_lane_collector_b_tf32_scale_d_cta2_param_4];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r3, %r4, %r5, %r6}, [tcgen05_mma_disable_output_lane_collector_b_tf32_scale_d_cta2_param_6+16];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r7, %r8, %r9, %r10}, [tcgen05_mma_disable_output_lane_collector_b_tf32_scale_d_cta2_param_6];
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::tf32.collector::a::discard.collector::b::fill [%r1], %rd1, %rd2, %r2, {%r7, %r8, %r9, %r10, %r3, %r4, %r5, %r6}, %p1, 4;
-; CHECK-NEXT: ld.param.b32 %r11, [tcgen05_mma_disable_output_lane_collector_b_tf32_scale_d_cta2_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r11, [tcgen05_mma_disable_output_lane_collector_b_tf32_scale_d_cta2_param_1];
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::tf32.collector::a::discard.collector::b::use [%r1], [%r11], %rd2, %r2, {%r7, %r8, %r9, %r10, %r3, %r4, %r5, %r6}, %p1, 6;
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::tf32.ashift.collector::a::lastuse.collector::b::lastuse [%r1], [%r11], %rd2, %r2, {%r7, %r8, %r9, %r10, %r3, %r4, %r5, %r6}, %p1, 1;
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::tf32.ashift.collector::a::lastuse [%r1], [%r11], %rd2, %r2, {%r7, %r8, %r9, %r10, %r3, %r4, %r5, %r6}, %p1, 1;
diff --git a/llvm/test/CodeGen/NVPTX/tcgen05-mma-disable-output-lane-i8.ll b/llvm/test/CodeGen/NVPTX/tcgen05-mma-disable-output-lane-i8.ll
index 0905b0a467b52..2c74dc7e884f7 100644
--- a/llvm/test/CodeGen/NVPTX/tcgen05-mma-disable-output-lane-i8.ll
+++ b/llvm/test/CodeGen/NVPTX/tcgen05-mma-disable-output-lane-i8.ll
@@ -15,16 +15,16 @@ define void @tcgen05_mma_i8_shared_disable_output_lane_cg1(ptr addrspace(6) %dtm
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_i8_shared_disable_output_lane_cg1_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_i8_shared_disable_output_lane_cg1_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_i8_shared_disable_output_lane_cg1_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_i8_shared_disable_output_lane_cg1_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_i8_shared_disable_output_lane_cg1_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_i8_shared_disable_output_lane_cg1_param_4];
-; CHECK-NEXT: ld.param.v4.b32 {%r3, %r4, %r5, %r6}, [tcgen05_mma_i8_shared_disable_output_lane_cg1_param_6];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_i8_shared_disable_output_lane_cg1_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_i8_shared_disable_output_lane_cg1_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_i8_shared_disable_output_lane_cg1_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_i8_shared_disable_output_lane_cg1_param_4];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r3, %r4, %r5, %r6}, [tcgen05_mma_i8_shared_disable_output_lane_cg1_param_6];
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::i8.collector::a::discard [%r1], %rd1, %rd2, %r2, {%r3, %r4, %r5, %r6}, %p1;
-; CHECK-NEXT: ld.param.b32 %r7, [tcgen05_mma_i8_shared_disable_output_lane_cg1_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r7, [tcgen05_mma_i8_shared_disable_output_lane_cg1_param_1];
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::i8.collector::a::discard [%r1], [%r7], %rd2, %r2, {%r3, %r4, %r5, %r6}, %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::i8.ashift.collector::a::discard [%r1], [%r7], %rd2, %r2, {%r3, %r4, %r5, %r6}, %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::i8.collector::a::lastuse [%r1], %rd1, %rd2, %r2, {%r3, %r4, %r5, %r6}, %p1;
@@ -67,17 +67,17 @@ define void @tcgen05_mma_i8_shared_disable_output_lane_cg2(ptr addrspace(6) %dtm
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_i8_shared_disable_output_lane_cg2_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_i8_shared_disable_output_lane_cg2_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_i8_shared_disable_output_lane_cg2_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_i8_shared_disable_output_lane_cg2_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_i8_shared_disable_output_lane_cg2_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_i8_shared_disable_output_lane_cg2_param_4];
-; CHECK-NEXT: ld.param.v4.b32 {%r3, %r4, %r5, %r6}, [tcgen05_mma_i8_shared_disable_output_lane_cg2_param_7+16];
-; CHECK-NEXT: ld.param.v4.b32 {%r7, %r8, %r9, %r10}, [tcgen05_mma_i8_shared_disable_output_lane_cg2_param_7];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_i8_shared_disable_output_lane_cg2_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_i8_shared_disable_output_lane_cg2_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_i8_shared_disable_output_lane_cg2_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_i8_shared_disable_output_lane_cg2_param_4];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r3, %r4, %r5, %r6}, [tcgen05_mma_i8_shared_disable_output_lane_cg2_param_7+16];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r7, %r8, %r9, %r10}, [tcgen05_mma_i8_shared_disable_output_lane_cg2_param_7];
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::i8.collector::a::discard [%r1], %rd1, %rd2, %r2, {%r7, %r8, %r9, %r10, %r3, %r4, %r5, %r6}, %p1;
-; CHECK-NEXT: ld.param.b32 %r11, [tcgen05_mma_i8_shared_disable_output_lane_cg2_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r11, [tcgen05_mma_i8_shared_disable_output_lane_cg2_param_1];
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::i8.collector::a::discard [%r1], [%r11], %rd2, %r2, {%r7, %r8, %r9, %r10, %r3, %r4, %r5, %r6}, %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::i8.ashift.collector::a::discard [%r1], [%r11], %rd2, %r2, {%r7, %r8, %r9, %r10, %r3, %r4, %r5, %r6}, %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::i8.collector::a::lastuse [%r1], %rd1, %rd2, %r2, {%r7, %r8, %r9, %r10, %r3, %r4, %r5, %r6}, %p1;
@@ -120,17 +120,17 @@ define void @tcgen05_mma_sp_i8_shared_disable_output_lane_cg1(ptr addrspace(6) %
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_sp_i8_shared_disable_output_lane_cg1_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_sp_i8_shared_disable_output_lane_cg1_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_sp_i8_shared_disable_output_lane_cg1_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_sp_i8_shared_disable_output_lane_cg1_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_sp_i8_shared_disable_output_lane_cg1_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_sp_i8_shared_disable_output_lane_cg1_param_4];
-; CHECK-NEXT: ld.param.v4.b32 {%r3, %r4, %r5, %r6}, [tcgen05_mma_sp_i8_shared_disable_output_lane_cg1_param_6];
-; CHECK-NEXT: ld.param.b32 %r7, [tcgen05_mma_sp_i8_shared_disable_output_lane_cg1_param_8];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_sp_i8_shared_disable_output_lane_cg1_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_sp_i8_shared_disable_output_lane_cg1_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_sp_i8_shared_disable_output_lane_cg1_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_sp_i8_shared_disable_output_lane_cg1_param_4];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r3, %r4, %r5, %r6}, [tcgen05_mma_sp_i8_shared_disable_output_lane_cg1_param_6];
+; CHECK-NEXT: ld.param::func.b32 %r7, [tcgen05_mma_sp_i8_shared_disable_output_lane_cg1_param_8];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::i8.collector::a::discard [%r1], %rd1, %rd2, [%r7], %r2, {%r3, %r4, %r5, %r6}, %p1;
-; CHECK-NEXT: ld.param.b32 %r8, [tcgen05_mma_sp_i8_shared_disable_output_lane_cg1_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r8, [tcgen05_mma_sp_i8_shared_disable_output_lane_cg1_param_1];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::i8.collector::a::discard [%r1], [%r8], %rd2, [%r7], %r2, {%r3, %r4, %r5, %r6}, %p1;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::i8.ashift.collector::a::discard [%r1], [%r8], %rd2, [%r7], %r2, {%r3, %r4, %r5, %r6}, %p1;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::i8.collector::a::lastuse [%r1], %rd1, %rd2, [%r7], %r2, {%r3, %r4, %r5, %r6}, %p1;
@@ -173,18 +173,18 @@ define void @tcgen05_mma_sp_i8_shared_disable_output_lane_cg2(ptr addrspace(6) %
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_sp_i8_shared_disable_output_lane_cg2_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_sp_i8_shared_disable_output_lane_cg2_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_sp_i8_shared_disable_output_lane_cg2_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_sp_i8_shared_disable_output_lane_cg2_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_sp_i8_shared_disable_output_lane_cg2_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_sp_i8_shared_disable_output_lane_cg2_param_4];
-; CHECK-NEXT: ld.param.v4.b32 {%r3, %r4, %r5, %r6}, [tcgen05_mma_sp_i8_shared_disable_output_lane_cg2_param_7+16];
-; CHECK-NEXT: ld.param.v4.b32 {%r7, %r8, %r9, %r10}, [tcgen05_mma_sp_i8_shared_disable_output_lane_cg2_param_7];
-; CHECK-NEXT: ld.param.b32 %r11, [tcgen05_mma_sp_i8_shared_disable_output_lane_cg2_param_8];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_sp_i8_shared_disable_output_lane_cg2_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_sp_i8_shared_disable_output_lane_cg2_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_sp_i8_shared_disable_output_lane_cg2_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_sp_i8_shared_disable_output_lane_cg2_param_4];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r3, %r4, %r5, %r6}, [tcgen05_mma_sp_i8_shared_disable_output_lane_cg2_param_7+16];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r7, %r8, %r9, %r10}, [tcgen05_mma_sp_i8_shared_disable_output_lane_cg2_param_7];
+; CHECK-NEXT: ld.param::func.b32 %r11, [tcgen05_mma_sp_i8_shared_disable_output_lane_cg2_param_8];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::i8.collector::a::discard [%r1], %rd1, %rd2, [%r11], %r2, {%r7, %r8, %r9, %r10, %r3, %r4, %r5, %r6}, %p1;
-; CHECK-NEXT: ld.param.b32 %r12, [tcgen05_mma_sp_i8_shared_disable_output_lane_cg2_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r12, [tcgen05_mma_sp_i8_shared_disable_output_lane_cg2_param_1];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::i8.collector::a::discard [%r1], [%r12], %rd2, [%r11], %r2, {%r7, %r8, %r9, %r10, %r3, %r4, %r5, %r6}, %p1;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::i8.ashift.collector::a::discard [%r1], [%r12], %rd2, [%r11], %r2, {%r7, %r8, %r9, %r10, %r3, %r4, %r5, %r6}, %p1;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::i8.collector::a::lastuse [%r1], %rd1, %rd2, [%r11], %r2, {%r7, %r8, %r9, %r10, %r3, %r4, %r5, %r6}, %p1;
diff --git a/llvm/test/CodeGen/NVPTX/tcgen05-mma-disable-output-lane.ll b/llvm/test/CodeGen/NVPTX/tcgen05-mma-disable-output-lane.ll
index a482f11904b55..5dd923b76558f 100644
--- a/llvm/test/CodeGen/NVPTX/tcgen05-mma-disable-output-lane.ll
+++ b/llvm/test/CodeGen/NVPTX/tcgen05-mma-disable-output-lane.ll
@@ -19,16 +19,16 @@ define void @tcgen05_mma_fp16_shared_disable_output_lane_cta1(ptr addrspace(6) %
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_fp16_shared_disable_output_lane_cta1_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_fp16_shared_disable_output_lane_cta1_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_fp16_shared_disable_output_lane_cta1_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_fp16_shared_disable_output_lane_cta1_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_fp16_shared_disable_output_lane_cta1_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_fp16_shared_disable_output_lane_cta1_param_4];
-; CHECK-NEXT: ld.param.v4.b32 {%r3, %r4, %r5, %r6}, [tcgen05_mma_fp16_shared_disable_output_lane_cta1_param_6];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_fp16_shared_disable_output_lane_cta1_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_fp16_shared_disable_output_lane_cta1_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_fp16_shared_disable_output_lane_cta1_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_fp16_shared_disable_output_lane_cta1_param_4];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r3, %r4, %r5, %r6}, [tcgen05_mma_fp16_shared_disable_output_lane_cta1_param_6];
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::f16.collector::a::discard [%r1], %rd1, %rd2, %r2, {%r3, %r4, %r5, %r6}, %p1;
-; CHECK-NEXT: ld.param.b32 %r7, [tcgen05_mma_fp16_shared_disable_output_lane_cta1_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r7, [tcgen05_mma_fp16_shared_disable_output_lane_cta1_param_1];
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::f16.collector::a::discard [%r1], [%r7], %rd2, %r2, {%r3, %r4, %r5, %r6}, %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::f16.ashift.collector::a::discard [%r1], [%r7], %rd2, %r2, {%r3, %r4, %r5, %r6}, %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::f16.collector::a::lastuse [%r1], %rd1, %rd2, %r2, {%r3, %r4, %r5, %r6}, %p1;
@@ -71,17 +71,17 @@ define void @tcgen05_mma_fp16_shared_disable_output_lane_cta2(ptr addrspace(6) %
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_fp16_shared_disable_output_lane_cta2_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_fp16_shared_disable_output_lane_cta2_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_fp16_shared_disable_output_lane_cta2_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_fp16_shared_disable_output_lane_cta2_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_fp16_shared_disable_output_lane_cta2_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_fp16_shared_disable_output_lane_cta2_param_4];
-; CHECK-NEXT: ld.param.v4.b32 {%r3, %r4, %r5, %r6}, [tcgen05_mma_fp16_shared_disable_output_lane_cta2_param_7+16];
-; CHECK-NEXT: ld.param.v4.b32 {%r7, %r8, %r9, %r10}, [tcgen05_mma_fp16_shared_disable_output_lane_cta2_param_7];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_fp16_shared_disable_output_lane_cta2_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_fp16_shared_disable_output_lane_cta2_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_fp16_shared_disable_output_lane_cta2_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_fp16_shared_disable_output_lane_cta2_param_4];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r3, %r4, %r5, %r6}, [tcgen05_mma_fp16_shared_disable_output_lane_cta2_param_7+16];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r7, %r8, %r9, %r10}, [tcgen05_mma_fp16_shared_disable_output_lane_cta2_param_7];
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::f16.collector::a::discard [%r1], %rd1, %rd2, %r2, {%r7, %r8, %r9, %r10, %r3, %r4, %r5, %r6}, %p1;
-; CHECK-NEXT: ld.param.b32 %r11, [tcgen05_mma_fp16_shared_disable_output_lane_cta2_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r11, [tcgen05_mma_fp16_shared_disable_output_lane_cta2_param_1];
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::f16.collector::a::discard [%r1], [%r11], %rd2, %r2, {%r7, %r8, %r9, %r10, %r3, %r4, %r5, %r6}, %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::f16.ashift.collector::a::discard [%r1], [%r11], %rd2, %r2, {%r7, %r8, %r9, %r10, %r3, %r4, %r5, %r6}, %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::f16.collector::a::lastuse [%r1], %rd1, %rd2, %r2, {%r7, %r8, %r9, %r10, %r3, %r4, %r5, %r6}, %p1;
@@ -124,17 +124,17 @@ define void @tcgen05_mma_sp_fp16_shared_disable_output_lane_cta1(ptr addrspace(6
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_sp_fp16_shared_disable_output_lane_cta1_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_sp_fp16_shared_disable_output_lane_cta1_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_sp_fp16_shared_disable_output_lane_cta1_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_sp_fp16_shared_disable_output_lane_cta1_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_sp_fp16_shared_disable_output_lane_cta1_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_sp_fp16_shared_disable_output_lane_cta1_param_4];
-; CHECK-NEXT: ld.param.v4.b32 {%r3, %r4, %r5, %r6}, [tcgen05_mma_sp_fp16_shared_disable_output_lane_cta1_param_6];
-; CHECK-NEXT: ld.param.b32 %r7, [tcgen05_mma_sp_fp16_shared_disable_output_lane_cta1_param_8];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_sp_fp16_shared_disable_output_lane_cta1_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_sp_fp16_shared_disable_output_lane_cta1_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_sp_fp16_shared_disable_output_lane_cta1_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_sp_fp16_shared_disable_output_lane_cta1_param_4];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r3, %r4, %r5, %r6}, [tcgen05_mma_sp_fp16_shared_disable_output_lane_cta1_param_6];
+; CHECK-NEXT: ld.param::func.b32 %r7, [tcgen05_mma_sp_fp16_shared_disable_output_lane_cta1_param_8];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::f16.collector::a::discard [%r1], %rd1, %rd2, [%r7], %r2, {%r3, %r4, %r5, %r6}, %p1;
-; CHECK-NEXT: ld.param.b32 %r8, [tcgen05_mma_sp_fp16_shared_disable_output_lane_cta1_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r8, [tcgen05_mma_sp_fp16_shared_disable_output_lane_cta1_param_1];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::f16.collector::a::discard [%r1], [%r8], %rd2, [%r7], %r2, {%r3, %r4, %r5, %r6}, %p1;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::f16.ashift.collector::a::discard [%r1], [%r8], %rd2, [%r7], %r2, {%r3, %r4, %r5, %r6}, %p1;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::f16.collector::a::lastuse [%r1], %rd1, %rd2, [%r7], %r2, {%r3, %r4, %r5, %r6}, %p1;
@@ -177,18 +177,18 @@ define void @tcgen05_mma_sp_fp16_shared_disable_output_lane_cta2(ptr addrspace(6
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_sp_fp16_shared_disable_output_lane_cta2_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_sp_fp16_shared_disable_output_lane_cta2_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_sp_fp16_shared_disable_output_lane_cta2_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_sp_fp16_shared_disable_output_lane_cta2_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_sp_fp16_shared_disable_output_lane_cta2_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_sp_fp16_shared_disable_output_lane_cta2_param_4];
-; CHECK-NEXT: ld.param.v4.b32 {%r3, %r4, %r5, %r6}, [tcgen05_mma_sp_fp16_shared_disable_output_lane_cta2_param_7+16];
-; CHECK-NEXT: ld.param.v4.b32 {%r7, %r8, %r9, %r10}, [tcgen05_mma_sp_fp16_shared_disable_output_lane_cta2_param_7];
-; CHECK-NEXT: ld.param.b32 %r11, [tcgen05_mma_sp_fp16_shared_disable_output_lane_cta2_param_8];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_sp_fp16_shared_disable_output_lane_cta2_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_sp_fp16_shared_disable_output_lane_cta2_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_sp_fp16_shared_disable_output_lane_cta2_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_sp_fp16_shared_disable_output_lane_cta2_param_4];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r3, %r4, %r5, %r6}, [tcgen05_mma_sp_fp16_shared_disable_output_lane_cta2_param_7+16];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r7, %r8, %r9, %r10}, [tcgen05_mma_sp_fp16_shared_disable_output_lane_cta2_param_7];
+; CHECK-NEXT: ld.param::func.b32 %r11, [tcgen05_mma_sp_fp16_shared_disable_output_lane_cta2_param_8];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::f16.collector::a::discard [%r1], %rd1, %rd2, [%r11], %r2, {%r7, %r8, %r9, %r10, %r3, %r4, %r5, %r6}, %p1;
-; CHECK-NEXT: ld.param.b32 %r12, [tcgen05_mma_sp_fp16_shared_disable_output_lane_cta2_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r12, [tcgen05_mma_sp_fp16_shared_disable_output_lane_cta2_param_1];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::f16.collector::a::discard [%r1], [%r12], %rd2, [%r11], %r2, {%r7, %r8, %r9, %r10, %r3, %r4, %r5, %r6}, %p1;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::f16.ashift.collector::a::discard [%r1], [%r12], %rd2, [%r11], %r2, {%r7, %r8, %r9, %r10, %r3, %r4, %r5, %r6}, %p1;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::f16.collector::a::lastuse [%r1], %rd1, %rd2, [%r11], %r2, {%r7, %r8, %r9, %r10, %r3, %r4, %r5, %r6}, %p1;
@@ -231,16 +231,16 @@ define void @tcgen05_mma_tf32_shared_disable_output_lane_cg1(ptr addrspace(6) %d
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_tf32_shared_disable_output_lane_cg1_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_tf32_shared_disable_output_lane_cg1_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_tf32_shared_disable_output_lane_cg1_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_tf32_shared_disable_output_lane_cg1_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_tf32_shared_disable_output_lane_cg1_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_tf32_shared_disable_output_lane_cg1_param_4];
-; CHECK-NEXT: ld.param.v4.b32 {%r3, %r4, %r5, %r6}, [tcgen05_mma_tf32_shared_disable_output_lane_cg1_param_6];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_tf32_shared_disable_output_lane_cg1_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_tf32_shared_disable_output_lane_cg1_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_tf32_shared_disable_output_lane_cg1_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_tf32_shared_disable_output_lane_cg1_param_4];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r3, %r4, %r5, %r6}, [tcgen05_mma_tf32_shared_disable_output_lane_cg1_param_6];
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::tf32.collector::a::discard [%r1], %rd1, %rd2, %r2, {%r3, %r4, %r5, %r6}, %p1;
-; CHECK-NEXT: ld.param.b32 %r7, [tcgen05_mma_tf32_shared_disable_output_lane_cg1_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r7, [tcgen05_mma_tf32_shared_disable_output_lane_cg1_param_1];
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::tf32.collector::a::discard [%r1], [%r7], %rd2, %r2, {%r3, %r4, %r5, %r6}, %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::tf32.ashift.collector::a::discard [%r1], [%r7], %rd2, %r2, {%r3, %r4, %r5, %r6}, %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::tf32.collector::a::lastuse [%r1], %rd1, %rd2, %r2, {%r3, %r4, %r5, %r6}, %p1;
@@ -283,17 +283,17 @@ define void @tcgen05_mma_tf32_shared_disable_output_lane_cg2(ptr addrspace(6) %d
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_tf32_shared_disable_output_lane_cg2_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_tf32_shared_disable_output_lane_cg2_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_tf32_shared_disable_output_lane_cg2_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_tf32_shared_disable_output_lane_cg2_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_tf32_shared_disable_output_lane_cg2_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_tf32_shared_disable_output_lane_cg2_param_4];
-; CHECK-NEXT: ld.param.v4.b32 {%r3, %r4, %r5, %r6}, [tcgen05_mma_tf32_shared_disable_output_lane_cg2_param_7+16];
-; CHECK-NEXT: ld.param.v4.b32 {%r7, %r8, %r9, %r10}, [tcgen05_mma_tf32_shared_disable_output_lane_cg2_param_7];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_tf32_shared_disable_output_lane_cg2_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_tf32_shared_disable_output_lane_cg2_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_tf32_shared_disable_output_lane_cg2_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_tf32_shared_disable_output_lane_cg2_param_4];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r3, %r4, %r5, %r6}, [tcgen05_mma_tf32_shared_disable_output_lane_cg2_param_7+16];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r7, %r8, %r9, %r10}, [tcgen05_mma_tf32_shared_disable_output_lane_cg2_param_7];
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::tf32.collector::a::discard [%r1], %rd1, %rd2, %r2, {%r7, %r8, %r9, %r10, %r3, %r4, %r5, %r6}, %p1;
-; CHECK-NEXT: ld.param.b32 %r11, [tcgen05_mma_tf32_shared_disable_output_lane_cg2_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r11, [tcgen05_mma_tf32_shared_disable_output_lane_cg2_param_1];
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::tf32.collector::a::discard [%r1], [%r11], %rd2, %r2, {%r7, %r8, %r9, %r10, %r3, %r4, %r5, %r6}, %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::tf32.ashift.collector::a::discard [%r1], [%r11], %rd2, %r2, {%r7, %r8, %r9, %r10, %r3, %r4, %r5, %r6}, %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::tf32.collector::a::lastuse [%r1], %rd1, %rd2, %r2, {%r7, %r8, %r9, %r10, %r3, %r4, %r5, %r6}, %p1;
@@ -335,17 +335,17 @@ define void @tcgen05_mma_sp_tf32_shared_disable_output_lane_cg1(ptr addrspace(6)
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_sp_tf32_shared_disable_output_lane_cg1_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_sp_tf32_shared_disable_output_lane_cg1_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_sp_tf32_shared_disable_output_lane_cg1_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_sp_tf32_shared_disable_output_lane_cg1_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_sp_tf32_shared_disable_output_lane_cg1_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_sp_tf32_shared_disable_output_lane_cg1_param_4];
-; CHECK-NEXT: ld.param.v4.b32 {%r3, %r4, %r5, %r6}, [tcgen05_mma_sp_tf32_shared_disable_output_lane_cg1_param_6];
-; CHECK-NEXT: ld.param.b32 %r7, [tcgen05_mma_sp_tf32_shared_disable_output_lane_cg1_param_8];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_sp_tf32_shared_disable_output_lane_cg1_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_sp_tf32_shared_disable_output_lane_cg1_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_sp_tf32_shared_disable_output_lane_cg1_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_sp_tf32_shared_disable_output_lane_cg1_param_4];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r3, %r4, %r5, %r6}, [tcgen05_mma_sp_tf32_shared_disable_output_lane_cg1_param_6];
+; CHECK-NEXT: ld.param::func.b32 %r7, [tcgen05_mma_sp_tf32_shared_disable_output_lane_cg1_param_8];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::tf32.collector::a::discard [%r1], %rd1, %rd2, [%r7], %r2, {%r3, %r4, %r5, %r6}, %p1;
-; CHECK-NEXT: ld.param.b32 %r8, [tcgen05_mma_sp_tf32_shared_disable_output_lane_cg1_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r8, [tcgen05_mma_sp_tf32_shared_disable_output_lane_cg1_param_1];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::tf32.collector::a::discard [%r1], [%r8], %rd2, [%r7], %r2, {%r3, %r4, %r5, %r6}, %p1;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::tf32.ashift.collector::a::discard [%r1], [%r8], %rd2, [%r7], %r2, {%r3, %r4, %r5, %r6}, %p1;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::tf32.collector::a::lastuse [%r1], %rd1, %rd2, [%r7], %r2, {%r3, %r4, %r5, %r6}, %p1;
@@ -388,18 +388,18 @@ define void @tcgen05_mma_sp_tf32_shared_disable_output_lane_cg2(ptr addrspace(6)
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_sp_tf32_shared_disable_output_lane_cg2_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_sp_tf32_shared_disable_output_lane_cg2_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_sp_tf32_shared_disable_output_lane_cg2_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_sp_tf32_shared_disable_output_lane_cg2_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_sp_tf32_shared_disable_output_lane_cg2_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_sp_tf32_shared_disable_output_lane_cg2_param_4];
-; CHECK-NEXT: ld.param.v4.b32 {%r3, %r4, %r5, %r6}, [tcgen05_mma_sp_tf32_shared_disable_output_lane_cg2_param_7+16];
-; CHECK-NEXT: ld.param.v4.b32 {%r7, %r8, %r9, %r10}, [tcgen05_mma_sp_tf32_shared_disable_output_lane_cg2_param_7];
-; CHECK-NEXT: ld.param.b32 %r11, [tcgen05_mma_sp_tf32_shared_disable_output_lane_cg2_param_8];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_sp_tf32_shared_disable_output_lane_cg2_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_sp_tf32_shared_disable_output_lane_cg2_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_sp_tf32_shared_disable_output_lane_cg2_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_sp_tf32_shared_disable_output_lane_cg2_param_4];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r3, %r4, %r5, %r6}, [tcgen05_mma_sp_tf32_shared_disable_output_lane_cg2_param_7+16];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r7, %r8, %r9, %r10}, [tcgen05_mma_sp_tf32_shared_disable_output_lane_cg2_param_7];
+; CHECK-NEXT: ld.param::func.b32 %r11, [tcgen05_mma_sp_tf32_shared_disable_output_lane_cg2_param_8];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::tf32.collector::a::discard [%r1], %rd1, %rd2, [%r11], %r2, {%r7, %r8, %r9, %r10, %r3, %r4, %r5, %r6}, %p1;
-; CHECK-NEXT: ld.param.b32 %r12, [tcgen05_mma_sp_tf32_shared_disable_output_lane_cg2_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r12, [tcgen05_mma_sp_tf32_shared_disable_output_lane_cg2_param_1];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::tf32.collector::a::discard [%r1], [%r12], %rd2, [%r11], %r2, {%r7, %r8, %r9, %r10, %r3, %r4, %r5, %r6}, %p1;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::tf32.ashift.collector::a::discard [%r1], [%r12], %rd2, [%r11], %r2, {%r7, %r8, %r9, %r10, %r3, %r4, %r5, %r6}, %p1;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::tf32.collector::a::lastuse [%r1], %rd1, %rd2, [%r11], %r2, {%r7, %r8, %r9, %r10, %r3, %r4, %r5, %r6}, %p1;
@@ -442,16 +442,16 @@ define void @tcgen05_mma_f8f6f4_shared_disable_output_lane_cg1(ptr addrspace(6)
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_f8f6f4_shared_disable_output_lane_cg1_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_f8f6f4_shared_disable_output_lane_cg1_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_f8f6f4_shared_disable_output_lane_cg1_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_f8f6f4_shared_disable_output_lane_cg1_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_f8f6f4_shared_disable_output_lane_cg1_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_f8f6f4_shared_disable_output_lane_cg1_param_4];
-; CHECK-NEXT: ld.param.v4.b32 {%r3, %r4, %r5, %r6}, [tcgen05_mma_f8f6f4_shared_disable_output_lane_cg1_param_6];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_f8f6f4_shared_disable_output_lane_cg1_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_f8f6f4_shared_disable_output_lane_cg1_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_f8f6f4_shared_disable_output_lane_cg1_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_f8f6f4_shared_disable_output_lane_cg1_param_4];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r3, %r4, %r5, %r6}, [tcgen05_mma_f8f6f4_shared_disable_output_lane_cg1_param_6];
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::f8f6f4.collector::a::discard [%r1], %rd1, %rd2, %r2, {%r3, %r4, %r5, %r6}, %p1;
-; CHECK-NEXT: ld.param.b32 %r7, [tcgen05_mma_f8f6f4_shared_disable_output_lane_cg1_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r7, [tcgen05_mma_f8f6f4_shared_disable_output_lane_cg1_param_1];
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::f8f6f4.collector::a::discard [%r1], [%r7], %rd2, %r2, {%r3, %r4, %r5, %r6}, %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::f8f6f4.ashift.collector::a::discard [%r1], [%r7], %rd2, %r2, {%r3, %r4, %r5, %r6}, %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::f8f6f4.collector::a::lastuse [%r1], %rd1, %rd2, %r2, {%r3, %r4, %r5, %r6}, %p1;
@@ -494,17 +494,17 @@ define void @tcgen05_mma_f8f6f4_shared_disable_output_lane_cg2(ptr addrspace(6)
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_f8f6f4_shared_disable_output_lane_cg2_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_f8f6f4_shared_disable_output_lane_cg2_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_f8f6f4_shared_disable_output_lane_cg2_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_f8f6f4_shared_disable_output_lane_cg2_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_f8f6f4_shared_disable_output_lane_cg2_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_f8f6f4_shared_disable_output_lane_cg2_param_4];
-; CHECK-NEXT: ld.param.v4.b32 {%r3, %r4, %r5, %r6}, [tcgen05_mma_f8f6f4_shared_disable_output_lane_cg2_param_7+16];
-; CHECK-NEXT: ld.param.v4.b32 {%r7, %r8, %r9, %r10}, [tcgen05_mma_f8f6f4_shared_disable_output_lane_cg2_param_7];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_f8f6f4_shared_disable_output_lane_cg2_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_f8f6f4_shared_disable_output_lane_cg2_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_f8f6f4_shared_disable_output_lane_cg2_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_f8f6f4_shared_disable_output_lane_cg2_param_4];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r3, %r4, %r5, %r6}, [tcgen05_mma_f8f6f4_shared_disable_output_lane_cg2_param_7+16];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r7, %r8, %r9, %r10}, [tcgen05_mma_f8f6f4_shared_disable_output_lane_cg2_param_7];
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::f8f6f4.collector::a::discard [%r1], %rd1, %rd2, %r2, {%r7, %r8, %r9, %r10, %r3, %r4, %r5, %r6}, %p1;
-; CHECK-NEXT: ld.param.b32 %r11, [tcgen05_mma_f8f6f4_shared_disable_output_lane_cg2_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r11, [tcgen05_mma_f8f6f4_shared_disable_output_lane_cg2_param_1];
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::f8f6f4.collector::a::discard [%r1], [%r11], %rd2, %r2, {%r7, %r8, %r9, %r10, %r3, %r4, %r5, %r6}, %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::f8f6f4.ashift.collector::a::discard [%r1], [%r11], %rd2, %r2, {%r7, %r8, %r9, %r10, %r3, %r4, %r5, %r6}, %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::f8f6f4.collector::a::lastuse [%r1], %rd1, %rd2, %r2, {%r7, %r8, %r9, %r10, %r3, %r4, %r5, %r6}, %p1;
@@ -547,17 +547,17 @@ define void @tcgen05_mma_sp_f8f6f4_shared_disable_output_lane_cg1(ptr addrspace(
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_sp_f8f6f4_shared_disable_output_lane_cg1_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_sp_f8f6f4_shared_disable_output_lane_cg1_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_sp_f8f6f4_shared_disable_output_lane_cg1_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_sp_f8f6f4_shared_disable_output_lane_cg1_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_sp_f8f6f4_shared_disable_output_lane_cg1_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_sp_f8f6f4_shared_disable_output_lane_cg1_param_4];
-; CHECK-NEXT: ld.param.v4.b32 {%r3, %r4, %r5, %r6}, [tcgen05_mma_sp_f8f6f4_shared_disable_output_lane_cg1_param_6];
-; CHECK-NEXT: ld.param.b32 %r7, [tcgen05_mma_sp_f8f6f4_shared_disable_output_lane_cg1_param_8];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_sp_f8f6f4_shared_disable_output_lane_cg1_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_sp_f8f6f4_shared_disable_output_lane_cg1_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_sp_f8f6f4_shared_disable_output_lane_cg1_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_sp_f8f6f4_shared_disable_output_lane_cg1_param_4];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r3, %r4, %r5, %r6}, [tcgen05_mma_sp_f8f6f4_shared_disable_output_lane_cg1_param_6];
+; CHECK-NEXT: ld.param::func.b32 %r7, [tcgen05_mma_sp_f8f6f4_shared_disable_output_lane_cg1_param_8];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::f8f6f4.collector::a::discard [%r1], %rd1, %rd2, [%r7], %r2, {%r3, %r4, %r5, %r6}, %p1;
-; CHECK-NEXT: ld.param.b32 %r8, [tcgen05_mma_sp_f8f6f4_shared_disable_output_lane_cg1_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r8, [tcgen05_mma_sp_f8f6f4_shared_disable_output_lane_cg1_param_1];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::f8f6f4.collector::a::discard [%r1], [%r8], %rd2, [%r7], %r2, {%r3, %r4, %r5, %r6}, %p1;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::f8f6f4.ashift.collector::a::discard [%r1], [%r8], %rd2, [%r7], %r2, {%r3, %r4, %r5, %r6}, %p1;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::f8f6f4.collector::a::lastuse [%r1], %rd1, %rd2, [%r7], %r2, {%r3, %r4, %r5, %r6}, %p1;
@@ -600,18 +600,18 @@ define void @tcgen05_mma_sp_f8f6f4_shared_disable_output_lane_cg2(ptr addrspace(
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_sp_f8f6f4_shared_disable_output_lane_cg2_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_sp_f8f6f4_shared_disable_output_lane_cg2_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_sp_f8f6f4_shared_disable_output_lane_cg2_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_sp_f8f6f4_shared_disable_output_lane_cg2_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_sp_f8f6f4_shared_disable_output_lane_cg2_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_sp_f8f6f4_shared_disable_output_lane_cg2_param_4];
-; CHECK-NEXT: ld.param.v4.b32 {%r3, %r4, %r5, %r6}, [tcgen05_mma_sp_f8f6f4_shared_disable_output_lane_cg2_param_7+16];
-; CHECK-NEXT: ld.param.v4.b32 {%r7, %r8, %r9, %r10}, [tcgen05_mma_sp_f8f6f4_shared_disable_output_lane_cg2_param_7];
-; CHECK-NEXT: ld.param.b32 %r11, [tcgen05_mma_sp_f8f6f4_shared_disable_output_lane_cg2_param_8];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_sp_f8f6f4_shared_disable_output_lane_cg2_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_sp_f8f6f4_shared_disable_output_lane_cg2_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_sp_f8f6f4_shared_disable_output_lane_cg2_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_sp_f8f6f4_shared_disable_output_lane_cg2_param_4];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r3, %r4, %r5, %r6}, [tcgen05_mma_sp_f8f6f4_shared_disable_output_lane_cg2_param_7+16];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r7, %r8, %r9, %r10}, [tcgen05_mma_sp_f8f6f4_shared_disable_output_lane_cg2_param_7];
+; CHECK-NEXT: ld.param::func.b32 %r11, [tcgen05_mma_sp_f8f6f4_shared_disable_output_lane_cg2_param_8];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::f8f6f4.collector::a::discard [%r1], %rd1, %rd2, [%r11], %r2, {%r7, %r8, %r9, %r10, %r3, %r4, %r5, %r6}, %p1;
-; CHECK-NEXT: ld.param.b32 %r12, [tcgen05_mma_sp_f8f6f4_shared_disable_output_lane_cg2_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r12, [tcgen05_mma_sp_f8f6f4_shared_disable_output_lane_cg2_param_1];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::f8f6f4.collector::a::discard [%r1], [%r12], %rd2, [%r11], %r2, {%r7, %r8, %r9, %r10, %r3, %r4, %r5, %r6}, %p1;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::f8f6f4.ashift.collector::a::discard [%r1], [%r12], %rd2, [%r11], %r2, {%r7, %r8, %r9, %r10, %r3, %r4, %r5, %r6}, %p1;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::f8f6f4.collector::a::lastuse [%r1], %rd1, %rd2, [%r11], %r2, {%r7, %r8, %r9, %r10, %r3, %r4, %r5, %r6}, %p1;
diff --git a/llvm/test/CodeGen/NVPTX/tcgen05-mma-i8.ll b/llvm/test/CodeGen/NVPTX/tcgen05-mma-i8.ll
index d8c0860426b16..7dc72bf6c3b31 100644
--- a/llvm/test/CodeGen/NVPTX/tcgen05-mma-i8.ll
+++ b/llvm/test/CodeGen/NVPTX/tcgen05-mma-i8.ll
@@ -16,15 +16,15 @@ define void @tcgen05_mma_i8_cta1(ptr addrspace(6) %dtmem, ptr addrspace(6) %aten
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_i8_cta1_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_i8_cta1_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_i8_cta1_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_i8_cta1_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_i8_cta1_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_i8_cta1_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_i8_cta1_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_i8_cta1_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_i8_cta1_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_i8_cta1_param_4];
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::i8.collector::a::discard [%r1], %rd1, %rd2, %r2, %p1;
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_i8_cta1_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_i8_cta1_param_1];
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::i8.collector::a::discard [%r1], [%r3], %rd2, %r2, %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::i8.ashift.collector::a::discard [%r1], [%r3], %rd2, %r2, %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::i8.collector::a::lastuse [%r1], %rd1, %rd2, %r2, %p1;
@@ -55,16 +55,16 @@ define void @tcgen05_mma_sp_i8_cta1(ptr addrspace(6) %dtmem, ptr addrspace(6) %a
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_sp_i8_cta1_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_sp_i8_cta1_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_sp_i8_cta1_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_sp_i8_cta1_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_sp_i8_cta1_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_sp_i8_cta1_param_4];
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_sp_i8_cta1_param_6];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_sp_i8_cta1_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_sp_i8_cta1_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_sp_i8_cta1_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_sp_i8_cta1_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_sp_i8_cta1_param_6];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::i8.collector::a::discard [%r1], %rd1, %rd2, [%r3], %r2, %p1;
-; CHECK-NEXT: ld.param.b32 %r4, [tcgen05_mma_sp_i8_cta1_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r4, [tcgen05_mma_sp_i8_cta1_param_1];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::i8.collector::a::discard [%r1], [%r4], %rd2, [%r3], %r2, %p1;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::i8.ashift.collector::a::discard [%r1], [%r4], %rd2, [%r3], %r2, %p1;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::i8.collector::a::lastuse [%r1], %rd1, %rd2, [%r3], %r2, %p1;
@@ -95,15 +95,15 @@ define void @tcgen05_mma_i8_cta2(ptr addrspace(6) %dtmem, ptr addrspace(6) %aten
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_i8_cta2_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_i8_cta2_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_i8_cta2_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_i8_cta2_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_i8_cta2_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_i8_cta2_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_i8_cta2_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_i8_cta2_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_i8_cta2_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_i8_cta2_param_4];
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::i8.collector::a::discard [%r1], %rd1, %rd2, %r2, %p1;
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_i8_cta2_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_i8_cta2_param_1];
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::i8.collector::a::discard [%r1], [%r3], %rd2, %r2, %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::i8.ashift.collector::a::discard [%r1], [%r3], %rd2, %r2, %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::i8.collector::a::lastuse [%r1], %rd1, %rd2, %r2, %p1;
@@ -134,16 +134,16 @@ define void @tcgen05_mma_sp_i8_cta2(ptr addrspace(6) %dtmem, ptr addrspace(6) %a
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_sp_i8_cta2_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_sp_i8_cta2_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_sp_i8_cta2_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_sp_i8_cta2_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_sp_i8_cta2_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_sp_i8_cta2_param_4];
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_sp_i8_cta2_param_6];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_sp_i8_cta2_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_sp_i8_cta2_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_sp_i8_cta2_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_sp_i8_cta2_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_sp_i8_cta2_param_6];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::i8.collector::a::discard [%r1], %rd1, %rd2, [%r3], %r2, %p1;
-; CHECK-NEXT: ld.param.b32 %r4, [tcgen05_mma_sp_i8_cta2_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r4, [tcgen05_mma_sp_i8_cta2_param_1];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::i8.collector::a::discard [%r1], [%r4], %rd2, [%r3], %r2, %p1;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::i8.ashift.collector::a::discard [%r1], [%r4], %rd2, [%r3], %r2, %p1;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::i8.collector::a::lastuse [%r1], %rd1, %rd2, [%r3], %r2, %p1;
diff --git a/llvm/test/CodeGen/NVPTX/tcgen05-mma-scale-d.ll b/llvm/test/CodeGen/NVPTX/tcgen05-mma-scale-d.ll
index cc30a26c75c50..b714144f528e5 100644
--- a/llvm/test/CodeGen/NVPTX/tcgen05-mma-scale-d.ll
+++ b/llvm/test/CodeGen/NVPTX/tcgen05-mma-scale-d.ll
@@ -13,15 +13,15 @@ define void @tcgen05_mma_fp16_cg1(ptr addrspace(6) %dtmem, ptr addrspace(6) %ate
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_fp16_cg1_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_fp16_cg1_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_fp16_cg1_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_fp16_cg1_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_fp16_cg1_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_fp16_cg1_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_fp16_cg1_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_fp16_cg1_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_fp16_cg1_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_fp16_cg1_param_4];
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::f16.collector::a::discard [%r1], %rd1, %rd2, %r2, %p1, 0;
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_fp16_cg1_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_fp16_cg1_param_1];
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::f16.collector::a::discard [%r1], [%r3], %rd2, %r2, %p1, 0;
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::f16.ashift.collector::a::discard [%r1], [%r3], %rd2, %r2, %p1, 0;
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::f16.ashift.collector::a::lastuse [%r1], [%r3], %rd2, %r2, %p1, 0;
@@ -63,15 +63,15 @@ define void @tcgen05_mma_fp16_cg2(ptr addrspace(6) %dtmem, ptr addrspace(6) %ate
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_fp16_cg2_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_fp16_cg2_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_fp16_cg2_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_fp16_cg2_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_fp16_cg2_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_fp16_cg2_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_fp16_cg2_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_fp16_cg2_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_fp16_cg2_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_fp16_cg2_param_4];
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::f16.collector::a::discard [%r1], %rd1, %rd2, %r2, %p1, 0;
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_fp16_cg2_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_fp16_cg2_param_1];
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::f16.collector::a::discard [%r1], [%r3], %rd2, %r2, %p1, 0;
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::f16.ashift.collector::a::discard [%r1], [%r3], %rd2, %r2, %p1, 0;
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::f16.ashift.collector::a::lastuse [%r1], [%r3], %rd2, %r2, %p1, 0;
@@ -114,16 +114,16 @@ define void @tcgen05_mma_sp_fp16_cg1(ptr addrspace(6) %dtmem, ptr addrspace(6) %
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_sp_fp16_cg1_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_sp_fp16_cg1_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_sp_fp16_cg1_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_sp_fp16_cg1_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_sp_fp16_cg1_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_sp_fp16_cg1_param_4];
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_sp_fp16_cg1_param_6];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_sp_fp16_cg1_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_sp_fp16_cg1_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_sp_fp16_cg1_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_sp_fp16_cg1_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_sp_fp16_cg1_param_6];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::f16.collector::a::discard [%r1], %rd1, %rd2, [%r3], %r2, %p1, 0;
-; CHECK-NEXT: ld.param.b32 %r4, [tcgen05_mma_sp_fp16_cg1_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r4, [tcgen05_mma_sp_fp16_cg1_param_1];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::f16.collector::a::discard [%r1], [%r4], %rd2, [%r3], %r2, %p1, 0;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::f16.ashift.collector::a::discard [%r1], [%r4], %rd2, [%r3], %r2, %p1, 0;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::f16.ashift.collector::a::lastuse [%r1], [%r4], %rd2, [%r3], %r2, %p1, 0;
@@ -165,16 +165,16 @@ define void @tcgen05_mma_sp_fp16_cg2(ptr addrspace(6) %dtmem, ptr addrspace(6) %
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_sp_fp16_cg2_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_sp_fp16_cg2_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_sp_fp16_cg2_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_sp_fp16_cg2_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_sp_fp16_cg2_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_sp_fp16_cg2_param_4];
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_sp_fp16_cg2_param_6];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_sp_fp16_cg2_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_sp_fp16_cg2_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_sp_fp16_cg2_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_sp_fp16_cg2_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_sp_fp16_cg2_param_6];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::f16.collector::a::discard [%r1], %rd1, %rd2, [%r3], %r2, %p1, 0;
-; CHECK-NEXT: ld.param.b32 %r4, [tcgen05_mma_sp_fp16_cg2_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r4, [tcgen05_mma_sp_fp16_cg2_param_1];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::f16.collector::a::discard [%r1], [%r4], %rd2, [%r3], %r2, %p1, 0;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::f16.ashift.collector::a::discard [%r1], [%r4], %rd2, [%r3], %r2, %p1, 0;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::f16.ashift.collector::a::lastuse [%r1], [%r4], %rd2, [%r3], %r2, %p1, 0;
@@ -217,15 +217,15 @@ define void @tcgen05_mma_tf32_cg1(ptr addrspace(6) %dtmem, ptr addrspace(6) %ate
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_tf32_cg1_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_tf32_cg1_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_tf32_cg1_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_tf32_cg1_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_tf32_cg1_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_tf32_cg1_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_tf32_cg1_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_tf32_cg1_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_tf32_cg1_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_tf32_cg1_param_4];
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::tf32.collector::a::discard [%r1], %rd1, %rd2, %r2, %p1, 0;
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_tf32_cg1_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_tf32_cg1_param_1];
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::tf32.collector::a::discard [%r1], [%r3], %rd2, %r2, %p1, 0;
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::tf32.ashift.collector::a::discard [%r1], [%r3], %rd2, %r2, %p1, 0;
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::tf32.ashift.collector::a::lastuse [%r1], [%r3], %rd2, %r2, %p1, 0;
@@ -267,15 +267,15 @@ define void @tcgen05_mma_tf32_cg2(ptr addrspace(6) %dtmem, ptr addrspace(6) %ate
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_tf32_cg2_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_tf32_cg2_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_tf32_cg2_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_tf32_cg2_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_tf32_cg2_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_tf32_cg2_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_tf32_cg2_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_tf32_cg2_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_tf32_cg2_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_tf32_cg2_param_4];
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::tf32.collector::a::discard [%r1], %rd1, %rd2, %r2, %p1, 0;
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_tf32_cg2_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_tf32_cg2_param_1];
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::tf32.collector::a::discard [%r1], [%r3], %rd2, %r2, %p1, 0;
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::tf32.ashift.collector::a::discard [%r1], [%r3], %rd2, %r2, %p1, 0;
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::tf32.ashift.collector::a::lastuse [%r1], [%r3], %rd2, %r2, %p1, 0;
@@ -318,16 +318,16 @@ define void @tcgen05_mma_sp_tf32_cg1(ptr addrspace(6) %dtmem, ptr addrspace(6) %
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_sp_tf32_cg1_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_sp_tf32_cg1_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_sp_tf32_cg1_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_sp_tf32_cg1_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_sp_tf32_cg1_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_sp_tf32_cg1_param_4];
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_sp_tf32_cg1_param_6];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_sp_tf32_cg1_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_sp_tf32_cg1_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_sp_tf32_cg1_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_sp_tf32_cg1_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_sp_tf32_cg1_param_6];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::tf32.collector::a::discard [%r1], %rd1, %rd2, [%r3], %r2, %p1, 0;
-; CHECK-NEXT: ld.param.b32 %r4, [tcgen05_mma_sp_tf32_cg1_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r4, [tcgen05_mma_sp_tf32_cg1_param_1];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::tf32.collector::a::discard [%r1], [%r4], %rd2, [%r3], %r2, %p1, 0;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::tf32.ashift.collector::a::discard [%r1], [%r4], %rd2, [%r3], %r2, %p1, 0;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::tf32.ashift.collector::a::lastuse [%r1], [%r4], %rd2, [%r3], %r2, %p1, 0;
@@ -369,16 +369,16 @@ define void @tcgen05_mma_sp_tf32_cg2(ptr addrspace(6) %dtmem, ptr addrspace(6) %
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_sp_tf32_cg2_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_sp_tf32_cg2_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_sp_tf32_cg2_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_sp_tf32_cg2_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_sp_tf32_cg2_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_sp_tf32_cg2_param_4];
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_sp_tf32_cg2_param_6];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_sp_tf32_cg2_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_sp_tf32_cg2_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_sp_tf32_cg2_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_sp_tf32_cg2_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_sp_tf32_cg2_param_6];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::tf32.collector::a::discard [%r1], %rd1, %rd2, [%r3], %r2, %p1, 0;
-; CHECK-NEXT: ld.param.b32 %r4, [tcgen05_mma_sp_tf32_cg2_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r4, [tcgen05_mma_sp_tf32_cg2_param_1];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::tf32.collector::a::discard [%r1], [%r4], %rd2, [%r3], %r2, %p1, 0;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::tf32.ashift.collector::a::discard [%r1], [%r4], %rd2, [%r3], %r2, %p1, 0;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::tf32.ashift.collector::a::lastuse [%r1], [%r4], %rd2, [%r3], %r2, %p1, 0;
@@ -421,16 +421,16 @@ define void @tcgen05_mma_fp16_shared_scale_d_disable_output_lane_cg1(ptr addrspa
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_fp16_shared_scale_d_disable_output_lane_cg1_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_fp16_shared_scale_d_disable_output_lane_cg1_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_fp16_shared_scale_d_disable_output_lane_cg1_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_fp16_shared_scale_d_disable_output_lane_cg1_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_fp16_shared_scale_d_disable_output_lane_cg1_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_fp16_shared_scale_d_disable_output_lane_cg1_param_4];
-; CHECK-NEXT: ld.param.v4.b32 {%r3, %r4, %r5, %r6}, [tcgen05_mma_fp16_shared_scale_d_disable_output_lane_cg1_param_6];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_fp16_shared_scale_d_disable_output_lane_cg1_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_fp16_shared_scale_d_disable_output_lane_cg1_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_fp16_shared_scale_d_disable_output_lane_cg1_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_fp16_shared_scale_d_disable_output_lane_cg1_param_4];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r3, %r4, %r5, %r6}, [tcgen05_mma_fp16_shared_scale_d_disable_output_lane_cg1_param_6];
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::f16.collector::a::discard [%r1], %rd1, %rd2, %r2, {%r3, %r4, %r5, %r6}, %p1, 0;
-; CHECK-NEXT: ld.param.b32 %r7, [tcgen05_mma_fp16_shared_scale_d_disable_output_lane_cg1_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r7, [tcgen05_mma_fp16_shared_scale_d_disable_output_lane_cg1_param_1];
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::f16.collector::a::discard [%r1], [%r7], %rd2, %r2, {%r3, %r4, %r5, %r6}, %p1, 0;
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::f16.ashift.collector::a::discard [%r1], [%r7], %rd2, %r2, {%r3, %r4, %r5, %r6}, %p1, 0;
; CHECK-NEXT: ret;
@@ -452,17 +452,17 @@ define void @tcgen05_mma_fp16_shared_scale_d_disable_output_lane_cg2(ptr addrspa
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_fp16_shared_scale_d_disable_output_lane_cg2_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_fp16_shared_scale_d_disable_output_lane_cg2_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_fp16_shared_scale_d_disable_output_lane_cg2_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_fp16_shared_scale_d_disable_output_lane_cg2_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_fp16_shared_scale_d_disable_output_lane_cg2_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_fp16_shared_scale_d_disable_output_lane_cg2_param_4];
-; CHECK-NEXT: ld.param.v4.b32 {%r3, %r4, %r5, %r6}, [tcgen05_mma_fp16_shared_scale_d_disable_output_lane_cg2_param_7+16];
-; CHECK-NEXT: ld.param.v4.b32 {%r7, %r8, %r9, %r10}, [tcgen05_mma_fp16_shared_scale_d_disable_output_lane_cg2_param_7];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_fp16_shared_scale_d_disable_output_lane_cg2_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_fp16_shared_scale_d_disable_output_lane_cg2_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_fp16_shared_scale_d_disable_output_lane_cg2_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_fp16_shared_scale_d_disable_output_lane_cg2_param_4];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r3, %r4, %r5, %r6}, [tcgen05_mma_fp16_shared_scale_d_disable_output_lane_cg2_param_7+16];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r7, %r8, %r9, %r10}, [tcgen05_mma_fp16_shared_scale_d_disable_output_lane_cg2_param_7];
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::f16.collector::a::discard [%r1], %rd1, %rd2, %r2, {%r7, %r8, %r9, %r10, %r3, %r4, %r5, %r6}, %p1, 0;
-; CHECK-NEXT: ld.param.b32 %r11, [tcgen05_mma_fp16_shared_scale_d_disable_output_lane_cg2_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r11, [tcgen05_mma_fp16_shared_scale_d_disable_output_lane_cg2_param_1];
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::f16.collector::a::discard [%r1], [%r11], %rd2, %r2, {%r7, %r8, %r9, %r10, %r3, %r4, %r5, %r6}, %p1, 0;
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::f16.ashift.collector::a::discard [%r1], [%r11], %rd2, %r2, {%r7, %r8, %r9, %r10, %r3, %r4, %r5, %r6}, %p1, 0;
; CHECK-NEXT: ret;
@@ -484,16 +484,16 @@ define void @tcgen05_mma_tf32_shared_scale_d_disable_output_lane_cg1(ptr addrspa
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_tf32_shared_scale_d_disable_output_lane_cg1_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_tf32_shared_scale_d_disable_output_lane_cg1_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_tf32_shared_scale_d_disable_output_lane_cg1_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_tf32_shared_scale_d_disable_output_lane_cg1_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_tf32_shared_scale_d_disable_output_lane_cg1_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_tf32_shared_scale_d_disable_output_lane_cg1_param_4];
-; CHECK-NEXT: ld.param.v4.b32 {%r3, %r4, %r5, %r6}, [tcgen05_mma_tf32_shared_scale_d_disable_output_lane_cg1_param_6];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_tf32_shared_scale_d_disable_output_lane_cg1_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_tf32_shared_scale_d_disable_output_lane_cg1_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_tf32_shared_scale_d_disable_output_lane_cg1_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_tf32_shared_scale_d_disable_output_lane_cg1_param_4];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r3, %r4, %r5, %r6}, [tcgen05_mma_tf32_shared_scale_d_disable_output_lane_cg1_param_6];
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::tf32.collector::a::discard [%r1], %rd1, %rd2, %r2, {%r3, %r4, %r5, %r6}, %p1, 0;
-; CHECK-NEXT: ld.param.b32 %r7, [tcgen05_mma_tf32_shared_scale_d_disable_output_lane_cg1_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r7, [tcgen05_mma_tf32_shared_scale_d_disable_output_lane_cg1_param_1];
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::tf32.collector::a::discard [%r1], [%r7], %rd2, %r2, {%r3, %r4, %r5, %r6}, %p1, 0;
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::tf32.ashift.collector::a::discard [%r1], [%r7], %rd2, %r2, {%r3, %r4, %r5, %r6}, %p1, 0;
; CHECK-NEXT: ret;
@@ -515,17 +515,17 @@ define void @tcgen05_mma_tf32_shared_scale_d_disable_output_lane_cg2(ptr addrspa
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_tf32_shared_scale_d_disable_output_lane_cg2_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_tf32_shared_scale_d_disable_output_lane_cg2_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_tf32_shared_scale_d_disable_output_lane_cg2_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_tf32_shared_scale_d_disable_output_lane_cg2_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_tf32_shared_scale_d_disable_output_lane_cg2_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_tf32_shared_scale_d_disable_output_lane_cg2_param_4];
-; CHECK-NEXT: ld.param.v4.b32 {%r3, %r4, %r5, %r6}, [tcgen05_mma_tf32_shared_scale_d_disable_output_lane_cg2_param_7+16];
-; CHECK-NEXT: ld.param.v4.b32 {%r7, %r8, %r9, %r10}, [tcgen05_mma_tf32_shared_scale_d_disable_output_lane_cg2_param_7];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_tf32_shared_scale_d_disable_output_lane_cg2_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_tf32_shared_scale_d_disable_output_lane_cg2_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_tf32_shared_scale_d_disable_output_lane_cg2_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_tf32_shared_scale_d_disable_output_lane_cg2_param_4];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r3, %r4, %r5, %r6}, [tcgen05_mma_tf32_shared_scale_d_disable_output_lane_cg2_param_7+16];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r7, %r8, %r9, %r10}, [tcgen05_mma_tf32_shared_scale_d_disable_output_lane_cg2_param_7];
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::tf32.collector::a::discard [%r1], %rd1, %rd2, %r2, {%r7, %r8, %r9, %r10, %r3, %r4, %r5, %r6}, %p1, 0;
-; CHECK-NEXT: ld.param.b32 %r11, [tcgen05_mma_tf32_shared_scale_d_disable_output_lane_cg2_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r11, [tcgen05_mma_tf32_shared_scale_d_disable_output_lane_cg2_param_1];
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::tf32.collector::a::discard [%r1], [%r11], %rd2, %r2, {%r7, %r8, %r9, %r10, %r3, %r4, %r5, %r6}, %p1, 0;
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::tf32.ashift.collector::a::discard [%r1], [%r11], %rd2, %r2, {%r7, %r8, %r9, %r10, %r3, %r4, %r5, %r6}, %p1, 0;
; CHECK-NEXT: ret;
diff --git a/llvm/test/CodeGen/NVPTX/tcgen05-mma-sp-collector-b.ll b/llvm/test/CodeGen/NVPTX/tcgen05-mma-sp-collector-b.ll
index 0f1a84829e9d0..85edfd006ab5b 100644
--- a/llvm/test/CodeGen/NVPTX/tcgen05-mma-sp-collector-b.ll
+++ b/llvm/test/CodeGen/NVPTX/tcgen05-mma-sp-collector-b.ll
@@ -15,16 +15,16 @@ define void @tcgen05_mma_sp_collector_b_f16_cta1(ptr addrspace(6) %dtmem, ptr ad
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_sp_collector_b_f16_cta1_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_sp_collector_b_f16_cta1_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_sp_collector_b_f16_cta1_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_sp_collector_b_f16_cta1_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_sp_collector_b_f16_cta1_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_sp_collector_b_f16_cta1_param_4];
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_sp_collector_b_f16_cta1_param_6];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_sp_collector_b_f16_cta1_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_sp_collector_b_f16_cta1_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_sp_collector_b_f16_cta1_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_sp_collector_b_f16_cta1_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_sp_collector_b_f16_cta1_param_6];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::f16.collector::a::discard.collector::b::lastuse [%r1], %rd1, %rd2, [%r3], %r2, %p1;
-; CHECK-NEXT: ld.param.b32 %r4, [tcgen05_mma_sp_collector_b_f16_cta1_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r4, [tcgen05_mma_sp_collector_b_f16_cta1_param_1];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::f16.collector::a::discard.collector::b::fill [%r1], %rd1, %rd2, [%r3], %r2, %p1;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::f16.collector::a::discard.collector::b::use [%r1], %rd1, %rd2, [%r3], %r2, %p1;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::f16.collector::a::discard.collector::b::lastuse [%r1], [%r4], %rd2, [%r3], %r2, %p1;
@@ -80,16 +80,16 @@ define void @tcgen05_mma_sp_collector_b_f16_cta2(ptr addrspace(6) %dtmem, ptr ad
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_sp_collector_b_f16_cta2_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_sp_collector_b_f16_cta2_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_sp_collector_b_f16_cta2_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_sp_collector_b_f16_cta2_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_sp_collector_b_f16_cta2_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_sp_collector_b_f16_cta2_param_4];
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_sp_collector_b_f16_cta2_param_6];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_sp_collector_b_f16_cta2_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_sp_collector_b_f16_cta2_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_sp_collector_b_f16_cta2_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_sp_collector_b_f16_cta2_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_sp_collector_b_f16_cta2_param_6];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::f16.collector::a::discard.collector::b::lastuse [%r1], %rd1, %rd2, [%r3], %r2, %p1;
-; CHECK-NEXT: ld.param.b32 %r4, [tcgen05_mma_sp_collector_b_f16_cta2_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r4, [tcgen05_mma_sp_collector_b_f16_cta2_param_1];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::f16.collector::a::discard.collector::b::lastuse [%r1], [%r4], %rd2, [%r3], %r2, %p1;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::f16.collector::a::lastuse.collector::b::fill [%r1], %rd1, %rd2, [%r3], %r2, %p1;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::f16.ashift.collector::a::discard.collector::b::lastuse [%r1], [%r4], %rd2, [%r3], %r2, %p1;
@@ -124,16 +124,16 @@ define void @tcgen05_mma_sp_collector_b_tf32_cta1(ptr addrspace(6) %dtmem, ptr a
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_sp_collector_b_tf32_cta1_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_sp_collector_b_tf32_cta1_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_sp_collector_b_tf32_cta1_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_sp_collector_b_tf32_cta1_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_sp_collector_b_tf32_cta1_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_sp_collector_b_tf32_cta1_param_4];
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_sp_collector_b_tf32_cta1_param_6];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_sp_collector_b_tf32_cta1_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_sp_collector_b_tf32_cta1_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_sp_collector_b_tf32_cta1_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_sp_collector_b_tf32_cta1_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_sp_collector_b_tf32_cta1_param_6];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::tf32.collector::a::discard.collector::b::lastuse [%r1], %rd1, %rd2, [%r3], %r2, %p1;
-; CHECK-NEXT: ld.param.b32 %r4, [tcgen05_mma_sp_collector_b_tf32_cta1_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r4, [tcgen05_mma_sp_collector_b_tf32_cta1_param_1];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::tf32.collector::a::discard.collector::b::fill [%r1], %rd1, %rd2, [%r3], %r2, %p1;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::tf32.collector::a::discard.collector::b::use [%r1], %rd1, %rd2, [%r3], %r2, %p1;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::tf32.collector::a::discard.collector::b::lastuse [%r1], [%r4], %rd2, [%r3], %r2, %p1;
@@ -183,16 +183,16 @@ define void @tcgen05_mma_sp_collector_b_f8f6f4_cta1(ptr addrspace(6) %dtmem, ptr
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_sp_collector_b_f8f6f4_cta1_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_sp_collector_b_f8f6f4_cta1_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_sp_collector_b_f8f6f4_cta1_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_sp_collector_b_f8f6f4_cta1_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_sp_collector_b_f8f6f4_cta1_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_sp_collector_b_f8f6f4_cta1_param_4];
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_sp_collector_b_f8f6f4_cta1_param_6];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_sp_collector_b_f8f6f4_cta1_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_sp_collector_b_f8f6f4_cta1_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_sp_collector_b_f8f6f4_cta1_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_sp_collector_b_f8f6f4_cta1_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_sp_collector_b_f8f6f4_cta1_param_6];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::f8f6f4.collector::a::discard.collector::b::lastuse [%r1], %rd1, %rd2, [%r3], %r2, %p1;
-; CHECK-NEXT: ld.param.b32 %r4, [tcgen05_mma_sp_collector_b_f8f6f4_cta1_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r4, [tcgen05_mma_sp_collector_b_f8f6f4_cta1_param_1];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::f8f6f4.collector::a::discard.collector::b::fill [%r1], %rd1, %rd2, [%r3], %r2, %p1;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::f8f6f4.collector::a::discard.collector::b::use [%r1], %rd1, %rd2, [%r3], %r2, %p1;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::f8f6f4.collector::a::discard.collector::b::lastuse [%r1], [%r4], %rd2, [%r3], %r2, %p1;
@@ -242,16 +242,16 @@ define void @tcgen05_mma_sp_collector_b_tf32_cta2(ptr addrspace(6) %dtmem, ptr a
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_sp_collector_b_tf32_cta2_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_sp_collector_b_tf32_cta2_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_sp_collector_b_tf32_cta2_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_sp_collector_b_tf32_cta2_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_sp_collector_b_tf32_cta2_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_sp_collector_b_tf32_cta2_param_4];
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_sp_collector_b_tf32_cta2_param_6];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_sp_collector_b_tf32_cta2_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_sp_collector_b_tf32_cta2_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_sp_collector_b_tf32_cta2_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_sp_collector_b_tf32_cta2_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_sp_collector_b_tf32_cta2_param_6];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::tf32.collector::a::discard.collector::b::lastuse [%r1], %rd1, %rd2, [%r3], %r2, %p1;
-; CHECK-NEXT: ld.param.b32 %r4, [tcgen05_mma_sp_collector_b_tf32_cta2_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r4, [tcgen05_mma_sp_collector_b_tf32_cta2_param_1];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::tf32.collector::a::discard.collector::b::lastuse [%r1], [%r4], %rd2, [%r3], %r2, %p1;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::tf32.ashift.collector::a::discard.collector::b::lastuse [%r1], [%r4], %rd2, [%r3], %r2, %p1;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::tf32.collector::a::lastuse.collector::b::fill [%r1], %rd1, %rd2, [%r3], %r2, %p1;
@@ -286,16 +286,16 @@ define void @tcgen05_mma_sp_collector_b_f8f6f4_cta2(ptr addrspace(6) %dtmem, ptr
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_sp_collector_b_f8f6f4_cta2_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_sp_collector_b_f8f6f4_cta2_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_sp_collector_b_f8f6f4_cta2_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_sp_collector_b_f8f6f4_cta2_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_sp_collector_b_f8f6f4_cta2_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_sp_collector_b_f8f6f4_cta2_param_4];
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_sp_collector_b_f8f6f4_cta2_param_6];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_sp_collector_b_f8f6f4_cta2_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_sp_collector_b_f8f6f4_cta2_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_sp_collector_b_f8f6f4_cta2_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_sp_collector_b_f8f6f4_cta2_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_sp_collector_b_f8f6f4_cta2_param_6];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::f8f6f4.collector::a::discard.collector::b::lastuse [%r1], %rd1, %rd2, [%r3], %r2, %p1;
-; CHECK-NEXT: ld.param.b32 %r4, [tcgen05_mma_sp_collector_b_f8f6f4_cta2_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r4, [tcgen05_mma_sp_collector_b_f8f6f4_cta2_param_1];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::f8f6f4.collector::a::discard.collector::b::fill [%r1], %rd1, %rd2, [%r3], %r2, %p1;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::f8f6f4.collector::a::discard.collector::b::use [%r1], %rd1, %rd2, [%r3], %r2, %p1;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::f8f6f4.collector::a::discard.collector::b::lastuse [%r1], [%r4], %rd2, [%r3], %r2, %p1;
@@ -345,16 +345,16 @@ define void @tcgen05_mma_sp_collector_b_scale_d_f16_cta1(ptr addrspace(6) %dtmem
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_sp_collector_b_scale_d_f16_cta1_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_sp_collector_b_scale_d_f16_cta1_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_sp_collector_b_scale_d_f16_cta1_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_sp_collector_b_scale_d_f16_cta1_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_sp_collector_b_scale_d_f16_cta1_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_sp_collector_b_scale_d_f16_cta1_param_4];
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_sp_collector_b_scale_d_f16_cta1_param_6];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_sp_collector_b_scale_d_f16_cta1_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_sp_collector_b_scale_d_f16_cta1_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_sp_collector_b_scale_d_f16_cta1_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_sp_collector_b_scale_d_f16_cta1_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_sp_collector_b_scale_d_f16_cta1_param_6];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::f16.collector::a::discard.collector::b::lastuse [%r1], %rd1, %rd2, [%r3], %r2, %p1, 0;
-; CHECK-NEXT: ld.param.b32 %r4, [tcgen05_mma_sp_collector_b_scale_d_f16_cta1_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r4, [tcgen05_mma_sp_collector_b_scale_d_f16_cta1_param_1];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::f16.collector::a::discard.collector::b::fill [%r1], %rd1, %rd2, [%r3], %r2, %p1, 0;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::f16.collector::a::lastuse.collector::b::lastuse [%r1], %rd1, %rd2, [%r3], %r2, %p1, 0;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::f16.collector::a::discard.collector::b::lastuse [%r1], [%r4], %rd2, [%r3], %r2, %p1, 0;
@@ -395,16 +395,16 @@ define void @tcgen05_mma_sp_collector_b_scale_d_f16_cta2(ptr addrspace(6) %dtmem
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_sp_collector_b_scale_d_f16_cta2_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_sp_collector_b_scale_d_f16_cta2_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_sp_collector_b_scale_d_f16_cta2_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_sp_collector_b_scale_d_f16_cta2_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_sp_collector_b_scale_d_f16_cta2_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_sp_collector_b_scale_d_f16_cta2_param_4];
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_sp_collector_b_scale_d_f16_cta2_param_6];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_sp_collector_b_scale_d_f16_cta2_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_sp_collector_b_scale_d_f16_cta2_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_sp_collector_b_scale_d_f16_cta2_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_sp_collector_b_scale_d_f16_cta2_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_sp_collector_b_scale_d_f16_cta2_param_6];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::f16.collector::a::discard.collector::b::lastuse [%r1], %rd1, %rd2, [%r3], %r2, %p1, 0;
-; CHECK-NEXT: ld.param.b32 %r4, [tcgen05_mma_sp_collector_b_scale_d_f16_cta2_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r4, [tcgen05_mma_sp_collector_b_scale_d_f16_cta2_param_1];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::f16.collector::a::discard.collector::b::lastuse [%r1], [%r4], %rd2, [%r3], %r2, %p1, 0;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::f16.ashift.collector::a::lastuse.collector::b::lastuse [%r1], [%r4], %rd2, [%r3], %r2, %p1, 0;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::f16.ashift.collector::a::lastuse [%r1], [%r4], %rd2, [%r3], %r2, %p1, 0;
@@ -436,16 +436,16 @@ define void @tcgen05_mma_sp_collector_b_scale_d_tf32_cta1(ptr addrspace(6) %dtme
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_sp_collector_b_scale_d_tf32_cta1_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_sp_collector_b_scale_d_tf32_cta1_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_sp_collector_b_scale_d_tf32_cta1_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_sp_collector_b_scale_d_tf32_cta1_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_sp_collector_b_scale_d_tf32_cta1_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_sp_collector_b_scale_d_tf32_cta1_param_4];
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_sp_collector_b_scale_d_tf32_cta1_param_6];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_sp_collector_b_scale_d_tf32_cta1_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_sp_collector_b_scale_d_tf32_cta1_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_sp_collector_b_scale_d_tf32_cta1_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_sp_collector_b_scale_d_tf32_cta1_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_sp_collector_b_scale_d_tf32_cta1_param_6];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::tf32.collector::a::discard.collector::b::lastuse [%r1], %rd1, %rd2, [%r3], %r2, %p1, 0;
-; CHECK-NEXT: ld.param.b32 %r4, [tcgen05_mma_sp_collector_b_scale_d_tf32_cta1_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r4, [tcgen05_mma_sp_collector_b_scale_d_tf32_cta1_param_1];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::tf32.collector::a::lastuse.collector::b::fill [%r1], %rd1, %rd2, [%r3], %r2, %p1, 0;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::tf32.collector::a::discard.collector::b::lastuse [%r1], [%r4], %rd2, [%r3], %r2, %p1, 0;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::tf32.ashift.collector::a::discard.collector::b::lastuse [%r1], [%r4], %rd2, [%r3], %r2, %p1, 0;
@@ -480,16 +480,16 @@ define void @tcgen05_mma_sp_collector_b_scale_d_tf32_cta2(ptr addrspace(6) %dtme
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_sp_collector_b_scale_d_tf32_cta2_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_sp_collector_b_scale_d_tf32_cta2_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_sp_collector_b_scale_d_tf32_cta2_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_sp_collector_b_scale_d_tf32_cta2_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_sp_collector_b_scale_d_tf32_cta2_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_sp_collector_b_scale_d_tf32_cta2_param_4];
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_sp_collector_b_scale_d_tf32_cta2_param_6];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_sp_collector_b_scale_d_tf32_cta2_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_sp_collector_b_scale_d_tf32_cta2_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_sp_collector_b_scale_d_tf32_cta2_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_sp_collector_b_scale_d_tf32_cta2_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_sp_collector_b_scale_d_tf32_cta2_param_6];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::tf32.collector::a::discard.collector::b::lastuse [%r1], %rd1, %rd2, [%r3], %r2, %p1, 0;
-; CHECK-NEXT: ld.param.b32 %r4, [tcgen05_mma_sp_collector_b_scale_d_tf32_cta2_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r4, [tcgen05_mma_sp_collector_b_scale_d_tf32_cta2_param_1];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::tf32.collector::a::discard.collector::b::lastuse [%r1], [%r4], %rd2, [%r3], %r2, %p1, 0;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::tf32.ashift.collector::a::lastuse.collector::b::lastuse [%r1], [%r4], %rd2, [%r3], %r2, %p1, 0;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::tf32.ashift.collector::a::lastuse [%r1], [%r4], %rd2, [%r3], %r2, %p1, 0;
@@ -521,18 +521,18 @@ define void @tcgen05_mma_sp_collector_b_block_scale_mxf8f6f4_cta1(ptr addrspace(
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_sp_collector_b_block_scale_mxf8f6f4_cta1_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_sp_collector_b_block_scale_mxf8f6f4_cta1_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_sp_collector_b_block_scale_mxf8f6f4_cta1_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_sp_collector_b_block_scale_mxf8f6f4_cta1_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_sp_collector_b_block_scale_mxf8f6f4_cta1_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_sp_collector_b_block_scale_mxf8f6f4_cta1_param_4];
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_sp_collector_b_block_scale_mxf8f6f4_cta1_param_6];
-; CHECK-NEXT: ld.param.b32 %r4, [tcgen05_mma_sp_collector_b_block_scale_mxf8f6f4_cta1_param_7];
-; CHECK-NEXT: ld.param.b32 %r5, [tcgen05_mma_sp_collector_b_block_scale_mxf8f6f4_cta1_param_8];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_sp_collector_b_block_scale_mxf8f6f4_cta1_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_sp_collector_b_block_scale_mxf8f6f4_cta1_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_sp_collector_b_block_scale_mxf8f6f4_cta1_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_sp_collector_b_block_scale_mxf8f6f4_cta1_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_sp_collector_b_block_scale_mxf8f6f4_cta1_param_6];
+; CHECK-NEXT: ld.param::func.b32 %r4, [tcgen05_mma_sp_collector_b_block_scale_mxf8f6f4_cta1_param_7];
+; CHECK-NEXT: ld.param::func.b32 %r5, [tcgen05_mma_sp_collector_b_block_scale_mxf8f6f4_cta1_param_8];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::mxf8f6f4.block_scale.collector::a::discard.collector::b::lastuse [%r1], %rd1, %rd2, [%r3], %r2, [%r4], [%r5], %p1;
-; CHECK-NEXT: ld.param.b32 %r6, [tcgen05_mma_sp_collector_b_block_scale_mxf8f6f4_cta1_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r6, [tcgen05_mma_sp_collector_b_block_scale_mxf8f6f4_cta1_param_1];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::mxf8f6f4.block_scale.collector::a::discard.collector::b::fill [%r1], %rd1, %rd2, [%r3], %r2, [%r4], [%r5], %p1;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::mxf8f6f4.block_scale.collector::a::discard.collector::b::use [%r1], %rd1, %rd2, [%r3], %r2, [%r4], [%r5], %p1;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::mxf8f6f4.block_scale.collector::a::lastuse.collector::b::lastuse [%r1], %rd1, %rd2, [%r3], %r2, [%r4], [%r5], %p1;
@@ -579,18 +579,18 @@ define void @tcgen05_mma_sp_collector_b_block_scale_mxf8f6f4_cta2(ptr addrspace(
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_sp_collector_b_block_scale_mxf8f6f4_cta2_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_sp_collector_b_block_scale_mxf8f6f4_cta2_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_sp_collector_b_block_scale_mxf8f6f4_cta2_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_sp_collector_b_block_scale_mxf8f6f4_cta2_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_sp_collector_b_block_scale_mxf8f6f4_cta2_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_sp_collector_b_block_scale_mxf8f6f4_cta2_param_4];
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_sp_collector_b_block_scale_mxf8f6f4_cta2_param_6];
-; CHECK-NEXT: ld.param.b32 %r4, [tcgen05_mma_sp_collector_b_block_scale_mxf8f6f4_cta2_param_7];
-; CHECK-NEXT: ld.param.b32 %r5, [tcgen05_mma_sp_collector_b_block_scale_mxf8f6f4_cta2_param_8];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_sp_collector_b_block_scale_mxf8f6f4_cta2_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_sp_collector_b_block_scale_mxf8f6f4_cta2_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_sp_collector_b_block_scale_mxf8f6f4_cta2_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_sp_collector_b_block_scale_mxf8f6f4_cta2_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_sp_collector_b_block_scale_mxf8f6f4_cta2_param_6];
+; CHECK-NEXT: ld.param::func.b32 %r4, [tcgen05_mma_sp_collector_b_block_scale_mxf8f6f4_cta2_param_7];
+; CHECK-NEXT: ld.param::func.b32 %r5, [tcgen05_mma_sp_collector_b_block_scale_mxf8f6f4_cta2_param_8];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::mxf8f6f4.block_scale.collector::a::discard.collector::b::lastuse [%r1], %rd1, %rd2, [%r3], %r2, [%r4], [%r5], %p1;
-; CHECK-NEXT: ld.param.b32 %r6, [tcgen05_mma_sp_collector_b_block_scale_mxf8f6f4_cta2_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r6, [tcgen05_mma_sp_collector_b_block_scale_mxf8f6f4_cta2_param_1];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::mxf8f6f4.block_scale.collector::a::lastuse.collector::b::lastuse [%r1], %rd1, %rd2, [%r3], %r2, [%r4], [%r5], %p1;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::mxf8f6f4.block_scale.collector::a::discard.collector::b::lastuse [%r1], [%r6], %rd2, [%r3], %r2, [%r4], [%r5], %p1;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::mxf8f6f4.block_scale.collector::a::fill.collector::b::use [%r1], [%r6], %rd2, [%r3], %r2, [%r4], [%r5], %p1;
@@ -625,18 +625,18 @@ define void @tcgen05_mma_sp_collector_b_block_scale_mxf8f6f4_block32_cta1(ptr ad
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_sp_collector_b_block_scale_mxf8f6f4_block32_cta1_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_sp_collector_b_block_scale_mxf8f6f4_block32_cta1_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_sp_collector_b_block_scale_mxf8f6f4_block32_cta1_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_sp_collector_b_block_scale_mxf8f6f4_block32_cta1_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_sp_collector_b_block_scale_mxf8f6f4_block32_cta1_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_sp_collector_b_block_scale_mxf8f6f4_block32_cta1_param_4];
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_sp_collector_b_block_scale_mxf8f6f4_block32_cta1_param_6];
-; CHECK-NEXT: ld.param.b32 %r4, [tcgen05_mma_sp_collector_b_block_scale_mxf8f6f4_block32_cta1_param_7];
-; CHECK-NEXT: ld.param.b32 %r5, [tcgen05_mma_sp_collector_b_block_scale_mxf8f6f4_block32_cta1_param_8];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_sp_collector_b_block_scale_mxf8f6f4_block32_cta1_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_sp_collector_b_block_scale_mxf8f6f4_block32_cta1_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_sp_collector_b_block_scale_mxf8f6f4_block32_cta1_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_sp_collector_b_block_scale_mxf8f6f4_block32_cta1_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_sp_collector_b_block_scale_mxf8f6f4_block32_cta1_param_6];
+; CHECK-NEXT: ld.param::func.b32 %r4, [tcgen05_mma_sp_collector_b_block_scale_mxf8f6f4_block32_cta1_param_7];
+; CHECK-NEXT: ld.param::func.b32 %r5, [tcgen05_mma_sp_collector_b_block_scale_mxf8f6f4_block32_cta1_param_8];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::mxf8f6f4.block_scale.block32.collector::a::discard.collector::b::lastuse [%r1], %rd1, %rd2, [%r3], %r2, [%r4], [%r5], %p1;
-; CHECK-NEXT: ld.param.b32 %r6, [tcgen05_mma_sp_collector_b_block_scale_mxf8f6f4_block32_cta1_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r6, [tcgen05_mma_sp_collector_b_block_scale_mxf8f6f4_block32_cta1_param_1];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::mxf8f6f4.block_scale.block32.collector::a::lastuse.collector::b::lastuse [%r1], %rd1, %rd2, [%r3], %r2, [%r4], [%r5], %p1;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::mxf8f6f4.block_scale.block32.collector::a::discard.collector::b::lastuse [%r1], [%r6], %rd2, [%r3], %r2, [%r4], [%r5], %p1;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::mxf8f6f4.block_scale.block32.collector::a::discard [%r1], [%r6], %rd2, [%r3], %r2, [%r4], [%r5], %p1;
@@ -668,18 +668,18 @@ define void @tcgen05_mma_sp_collector_b_block_scale_mxf8f6f4_block32_cta2(ptr ad
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_sp_collector_b_block_scale_mxf8f6f4_block32_cta2_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_sp_collector_b_block_scale_mxf8f6f4_block32_cta2_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_sp_collector_b_block_scale_mxf8f6f4_block32_cta2_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_sp_collector_b_block_scale_mxf8f6f4_block32_cta2_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_sp_collector_b_block_scale_mxf8f6f4_block32_cta2_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_sp_collector_b_block_scale_mxf8f6f4_block32_cta2_param_4];
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_sp_collector_b_block_scale_mxf8f6f4_block32_cta2_param_6];
-; CHECK-NEXT: ld.param.b32 %r4, [tcgen05_mma_sp_collector_b_block_scale_mxf8f6f4_block32_cta2_param_7];
-; CHECK-NEXT: ld.param.b32 %r5, [tcgen05_mma_sp_collector_b_block_scale_mxf8f6f4_block32_cta2_param_8];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_sp_collector_b_block_scale_mxf8f6f4_block32_cta2_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_sp_collector_b_block_scale_mxf8f6f4_block32_cta2_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_sp_collector_b_block_scale_mxf8f6f4_block32_cta2_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_sp_collector_b_block_scale_mxf8f6f4_block32_cta2_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_sp_collector_b_block_scale_mxf8f6f4_block32_cta2_param_6];
+; CHECK-NEXT: ld.param::func.b32 %r4, [tcgen05_mma_sp_collector_b_block_scale_mxf8f6f4_block32_cta2_param_7];
+; CHECK-NEXT: ld.param::func.b32 %r5, [tcgen05_mma_sp_collector_b_block_scale_mxf8f6f4_block32_cta2_param_8];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::mxf8f6f4.block_scale.block32.collector::a::discard.collector::b::lastuse [%r1], %rd1, %rd2, [%r3], %r2, [%r4], [%r5], %p1;
-; CHECK-NEXT: ld.param.b32 %r6, [tcgen05_mma_sp_collector_b_block_scale_mxf8f6f4_block32_cta2_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r6, [tcgen05_mma_sp_collector_b_block_scale_mxf8f6f4_block32_cta2_param_1];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::mxf8f6f4.block_scale.block32.collector::a::lastuse.collector::b::lastuse [%r1], %rd1, %rd2, [%r3], %r2, [%r4], [%r5], %p1;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::mxf8f6f4.block_scale.block32.collector::a::discard.collector::b::lastuse [%r1], [%r6], %rd2, [%r3], %r2, [%r4], [%r5], %p1;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::mxf8f6f4.block_scale.block32.collector::a::discard [%r1], [%r6], %rd2, [%r3], %r2, [%r4], [%r5], %p1;
diff --git a/llvm/test/CodeGen/NVPTX/tcgen05-mma-sp-disable-output-lane-collector-b.ll b/llvm/test/CodeGen/NVPTX/tcgen05-mma-sp-disable-output-lane-collector-b.ll
index 2e8b45dcafe40..482378e2793fe 100644
--- a/llvm/test/CodeGen/NVPTX/tcgen05-mma-sp-disable-output-lane-collector-b.ll
+++ b/llvm/test/CodeGen/NVPTX/tcgen05-mma-sp-disable-output-lane-collector-b.ll
@@ -16,17 +16,17 @@ define void @tcgen05_mma_sp_disable_output_lane_collector_b_f16_cta1(ptr addrspa
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_sp_disable_output_lane_collector_b_f16_cta1_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_sp_disable_output_lane_collector_b_f16_cta1_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_sp_disable_output_lane_collector_b_f16_cta1_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_sp_disable_output_lane_collector_b_f16_cta1_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_sp_disable_output_lane_collector_b_f16_cta1_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_sp_disable_output_lane_collector_b_f16_cta1_param_4];
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_sp_disable_output_lane_collector_b_f16_cta1_param_6];
-; CHECK-NEXT: ld.param.v4.b32 {%r4, %r5, %r6, %r7}, [tcgen05_mma_sp_disable_output_lane_collector_b_f16_cta1_param_7];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_sp_disable_output_lane_collector_b_f16_cta1_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_sp_disable_output_lane_collector_b_f16_cta1_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_sp_disable_output_lane_collector_b_f16_cta1_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_sp_disable_output_lane_collector_b_f16_cta1_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_sp_disable_output_lane_collector_b_f16_cta1_param_6];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r4, %r5, %r6, %r7}, [tcgen05_mma_sp_disable_output_lane_collector_b_f16_cta1_param_7];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::f16.collector::a::discard.collector::b::lastuse [%r1], %rd1, %rd2, [%r3], %r2, {%r4, %r5, %r6, %r7}, %p1;
-; CHECK-NEXT: ld.param.b32 %r8, [tcgen05_mma_sp_disable_output_lane_collector_b_f16_cta1_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r8, [tcgen05_mma_sp_disable_output_lane_collector_b_f16_cta1_param_1];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::f16.collector::a::discard.collector::b::fill [%r1], %rd1, %rd2, [%r3], %r2, {%r4, %r5, %r6, %r7}, %p1;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::f16.collector::a::discard.collector::b::use [%r1], %rd1, %rd2, [%r3], %r2, {%r4, %r5, %r6, %r7}, %p1;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::f16.collector::a::discard.collector::b::lastuse [%r1], [%r8], %rd2, [%r3], %r2, {%r4, %r5, %r6, %r7}, %p1;
@@ -79,18 +79,18 @@ define void @tcgen05_mma_sp_disable_output_lane_collector_b_f16_cta2(ptr addrspa
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_sp_disable_output_lane_collector_b_f16_cta2_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_sp_disable_output_lane_collector_b_f16_cta2_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_sp_disable_output_lane_collector_b_f16_cta2_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_sp_disable_output_lane_collector_b_f16_cta2_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_sp_disable_output_lane_collector_b_f16_cta2_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_sp_disable_output_lane_collector_b_f16_cta2_param_4];
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_sp_disable_output_lane_collector_b_f16_cta2_param_6];
-; CHECK-NEXT: ld.param.v4.b32 {%r4, %r5, %r6, %r7}, [tcgen05_mma_sp_disable_output_lane_collector_b_f16_cta2_param_7+16];
-; CHECK-NEXT: ld.param.v4.b32 {%r8, %r9, %r10, %r11}, [tcgen05_mma_sp_disable_output_lane_collector_b_f16_cta2_param_7];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_sp_disable_output_lane_collector_b_f16_cta2_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_sp_disable_output_lane_collector_b_f16_cta2_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_sp_disable_output_lane_collector_b_f16_cta2_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_sp_disable_output_lane_collector_b_f16_cta2_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_sp_disable_output_lane_collector_b_f16_cta2_param_6];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r4, %r5, %r6, %r7}, [tcgen05_mma_sp_disable_output_lane_collector_b_f16_cta2_param_7+16];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r8, %r9, %r10, %r11}, [tcgen05_mma_sp_disable_output_lane_collector_b_f16_cta2_param_7];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::f16.collector::a::discard.collector::b::lastuse [%r1], %rd1, %rd2, [%r3], %r2, {%r8, %r9, %r10, %r11, %r4, %r5, %r6, %r7}, %p1;
-; CHECK-NEXT: ld.param.b32 %r12, [tcgen05_mma_sp_disable_output_lane_collector_b_f16_cta2_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r12, [tcgen05_mma_sp_disable_output_lane_collector_b_f16_cta2_param_1];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::f16.collector::a::discard.collector::b::fill [%r1], [%r12], %rd2, [%r3], %r2, {%r8, %r9, %r10, %r11, %r4, %r5, %r6, %r7}, %p1;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::f16.ashift.collector::a::discard.collector::b::use [%r1], [%r12], %rd2, [%r3], %r2, {%r8, %r9, %r10, %r11, %r4, %r5, %r6, %r7}, %p1;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::f16.collector::a::lastuse.collector::b::use [%r1], %rd1, %rd2, [%r3], %r2, {%r8, %r9, %r10, %r11, %r4, %r5, %r6, %r7}, %p1;
@@ -125,17 +125,17 @@ define void @tcgen05_mma_sp_disable_output_lane_collector_b_tf32_cta1(ptr addrsp
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_sp_disable_output_lane_collector_b_tf32_cta1_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_sp_disable_output_lane_collector_b_tf32_cta1_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_sp_disable_output_lane_collector_b_tf32_cta1_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_sp_disable_output_lane_collector_b_tf32_cta1_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_sp_disable_output_lane_collector_b_tf32_cta1_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_sp_disable_output_lane_collector_b_tf32_cta1_param_4];
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_sp_disable_output_lane_collector_b_tf32_cta1_param_6];
-; CHECK-NEXT: ld.param.v4.b32 {%r4, %r5, %r6, %r7}, [tcgen05_mma_sp_disable_output_lane_collector_b_tf32_cta1_param_7];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_sp_disable_output_lane_collector_b_tf32_cta1_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_sp_disable_output_lane_collector_b_tf32_cta1_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_sp_disable_output_lane_collector_b_tf32_cta1_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_sp_disable_output_lane_collector_b_tf32_cta1_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_sp_disable_output_lane_collector_b_tf32_cta1_param_6];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r4, %r5, %r6, %r7}, [tcgen05_mma_sp_disable_output_lane_collector_b_tf32_cta1_param_7];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::tf32.collector::a::discard.collector::b::lastuse [%r1], %rd1, %rd2, [%r3], %r2, {%r4, %r5, %r6, %r7}, %p1;
-; CHECK-NEXT: ld.param.b32 %r8, [tcgen05_mma_sp_disable_output_lane_collector_b_tf32_cta1_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r8, [tcgen05_mma_sp_disable_output_lane_collector_b_tf32_cta1_param_1];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::tf32.collector::a::discard.collector::b::fill [%r1], [%r8], %rd2, [%r3], %r2, {%r4, %r5, %r6, %r7}, %p1;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::tf32.ashift.collector::a::discard.collector::b::use [%r1], [%r8], %rd2, [%r3], %r2, {%r4, %r5, %r6, %r7}, %p1;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::tf32.collector::a::use.collector::b::fill [%r1], %rd1, %rd2, [%r3], %r2, {%r4, %r5, %r6, %r7}, %p1;
@@ -170,18 +170,18 @@ define void @tcgen05_mma_sp_disable_output_lane_collector_b_tf32_cta2(ptr addrsp
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_sp_disable_output_lane_collector_b_tf32_cta2_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_sp_disable_output_lane_collector_b_tf32_cta2_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_sp_disable_output_lane_collector_b_tf32_cta2_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_sp_disable_output_lane_collector_b_tf32_cta2_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_sp_disable_output_lane_collector_b_tf32_cta2_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_sp_disable_output_lane_collector_b_tf32_cta2_param_4];
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_sp_disable_output_lane_collector_b_tf32_cta2_param_6];
-; CHECK-NEXT: ld.param.v4.b32 {%r4, %r5, %r6, %r7}, [tcgen05_mma_sp_disable_output_lane_collector_b_tf32_cta2_param_7+16];
-; CHECK-NEXT: ld.param.v4.b32 {%r8, %r9, %r10, %r11}, [tcgen05_mma_sp_disable_output_lane_collector_b_tf32_cta2_param_7];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_sp_disable_output_lane_collector_b_tf32_cta2_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_sp_disable_output_lane_collector_b_tf32_cta2_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_sp_disable_output_lane_collector_b_tf32_cta2_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_sp_disable_output_lane_collector_b_tf32_cta2_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_sp_disable_output_lane_collector_b_tf32_cta2_param_6];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r4, %r5, %r6, %r7}, [tcgen05_mma_sp_disable_output_lane_collector_b_tf32_cta2_param_7+16];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r8, %r9, %r10, %r11}, [tcgen05_mma_sp_disable_output_lane_collector_b_tf32_cta2_param_7];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::tf32.collector::a::discard.collector::b::fill [%r1], %rd1, %rd2, [%r3], %r2, {%r8, %r9, %r10, %r11, %r4, %r5, %r6, %r7}, %p1;
-; CHECK-NEXT: ld.param.b32 %r12, [tcgen05_mma_sp_disable_output_lane_collector_b_tf32_cta2_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r12, [tcgen05_mma_sp_disable_output_lane_collector_b_tf32_cta2_param_1];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::tf32.collector::a::discard.collector::b::use [%r1], [%r12], %rd2, [%r3], %r2, {%r8, %r9, %r10, %r11, %r4, %r5, %r6, %r7}, %p1;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::tf32.ashift.collector::a::lastuse.collector::b::lastuse [%r1], [%r12], %rd2, [%r3], %r2, {%r8, %r9, %r10, %r11, %r4, %r5, %r6, %r7}, %p1;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::tf32.ashift.collector::a::lastuse [%r1], [%r12], %rd2, [%r3], %r2, {%r8, %r9, %r10, %r11, %r4, %r5, %r6, %r7}, %p1;
@@ -213,17 +213,17 @@ define void @tcgen05_mma_sp_disable_output_lane_collector_b_f8f6f4_cta1(ptr addr
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_sp_disable_output_lane_collector_b_f8f6f4_cta1_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_sp_disable_output_lane_collector_b_f8f6f4_cta1_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_sp_disable_output_lane_collector_b_f8f6f4_cta1_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_sp_disable_output_lane_collector_b_f8f6f4_cta1_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_sp_disable_output_lane_collector_b_f8f6f4_cta1_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_sp_disable_output_lane_collector_b_f8f6f4_cta1_param_4];
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_sp_disable_output_lane_collector_b_f8f6f4_cta1_param_6];
-; CHECK-NEXT: ld.param.v4.b32 {%r4, %r5, %r6, %r7}, [tcgen05_mma_sp_disable_output_lane_collector_b_f8f6f4_cta1_param_7];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_sp_disable_output_lane_collector_b_f8f6f4_cta1_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_sp_disable_output_lane_collector_b_f8f6f4_cta1_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_sp_disable_output_lane_collector_b_f8f6f4_cta1_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_sp_disable_output_lane_collector_b_f8f6f4_cta1_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_sp_disable_output_lane_collector_b_f8f6f4_cta1_param_6];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r4, %r5, %r6, %r7}, [tcgen05_mma_sp_disable_output_lane_collector_b_f8f6f4_cta1_param_7];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::f8f6f4.collector::a::discard.collector::b::lastuse [%r1], %rd1, %rd2, [%r3], %r2, {%r4, %r5, %r6, %r7}, %p1;
-; CHECK-NEXT: ld.param.b32 %r8, [tcgen05_mma_sp_disable_output_lane_collector_b_f8f6f4_cta1_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r8, [tcgen05_mma_sp_disable_output_lane_collector_b_f8f6f4_cta1_param_1];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::f8f6f4.collector::a::discard.collector::b::fill [%r1], [%r8], %rd2, [%r3], %r2, {%r4, %r5, %r6, %r7}, %p1;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::f8f6f4.ashift.collector::a::discard.collector::b::use [%r1], [%r8], %rd2, [%r3], %r2, {%r4, %r5, %r6, %r7}, %p1;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::f8f6f4.collector::a::fill.collector::b::lastuse [%r1], %rd1, %rd2, [%r3], %r2, {%r4, %r5, %r6, %r7}, %p1;
@@ -258,18 +258,18 @@ define void @tcgen05_mma_sp_disable_output_lane_collector_b_f8f6f4_cta2(ptr addr
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_sp_disable_output_lane_collector_b_f8f6f4_cta2_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_sp_disable_output_lane_collector_b_f8f6f4_cta2_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_sp_disable_output_lane_collector_b_f8f6f4_cta2_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_sp_disable_output_lane_collector_b_f8f6f4_cta2_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_sp_disable_output_lane_collector_b_f8f6f4_cta2_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_sp_disable_output_lane_collector_b_f8f6f4_cta2_param_4];
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_sp_disable_output_lane_collector_b_f8f6f4_cta2_param_6];
-; CHECK-NEXT: ld.param.v4.b32 {%r4, %r5, %r6, %r7}, [tcgen05_mma_sp_disable_output_lane_collector_b_f8f6f4_cta2_param_7+16];
-; CHECK-NEXT: ld.param.v4.b32 {%r8, %r9, %r10, %r11}, [tcgen05_mma_sp_disable_output_lane_collector_b_f8f6f4_cta2_param_7];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_sp_disable_output_lane_collector_b_f8f6f4_cta2_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_sp_disable_output_lane_collector_b_f8f6f4_cta2_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_sp_disable_output_lane_collector_b_f8f6f4_cta2_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_sp_disable_output_lane_collector_b_f8f6f4_cta2_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_sp_disable_output_lane_collector_b_f8f6f4_cta2_param_6];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r4, %r5, %r6, %r7}, [tcgen05_mma_sp_disable_output_lane_collector_b_f8f6f4_cta2_param_7+16];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r8, %r9, %r10, %r11}, [tcgen05_mma_sp_disable_output_lane_collector_b_f8f6f4_cta2_param_7];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::f8f6f4.collector::a::discard.collector::b::use [%r1], %rd1, %rd2, [%r3], %r2, {%r8, %r9, %r10, %r11, %r4, %r5, %r6, %r7}, %p1;
-; CHECK-NEXT: ld.param.b32 %r12, [tcgen05_mma_sp_disable_output_lane_collector_b_f8f6f4_cta2_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r12, [tcgen05_mma_sp_disable_output_lane_collector_b_f8f6f4_cta2_param_1];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::f8f6f4.collector::a::discard.collector::b::fill [%r1], [%r12], %rd2, [%r3], %r2, {%r8, %r9, %r10, %r11, %r4, %r5, %r6, %r7}, %p1;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::f8f6f4.ashift.collector::a::lastuse.collector::b::use [%r1], [%r12], %rd2, [%r3], %r2, {%r8, %r9, %r10, %r11, %r4, %r5, %r6, %r7}, %p1;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::f8f6f4.ashift.collector::a::lastuse [%r1], [%r12], %rd2, [%r3], %r2, {%r8, %r9, %r10, %r11, %r4, %r5, %r6, %r7}, %p1;
@@ -301,17 +301,17 @@ define void @tcgen05_mma_sp_disable_output_lane_collector_b_f16_scale_d_cta1(ptr
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_sp_disable_output_lane_collector_b_f16_scale_d_cta1_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_sp_disable_output_lane_collector_b_f16_scale_d_cta1_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_sp_disable_output_lane_collector_b_f16_scale_d_cta1_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_sp_disable_output_lane_collector_b_f16_scale_d_cta1_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_sp_disable_output_lane_collector_b_f16_scale_d_cta1_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_sp_disable_output_lane_collector_b_f16_scale_d_cta1_param_4];
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_sp_disable_output_lane_collector_b_f16_scale_d_cta1_param_6];
-; CHECK-NEXT: ld.param.v4.b32 {%r4, %r5, %r6, %r7}, [tcgen05_mma_sp_disable_output_lane_collector_b_f16_scale_d_cta1_param_7];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_sp_disable_output_lane_collector_b_f16_scale_d_cta1_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_sp_disable_output_lane_collector_b_f16_scale_d_cta1_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_sp_disable_output_lane_collector_b_f16_scale_d_cta1_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_sp_disable_output_lane_collector_b_f16_scale_d_cta1_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_sp_disable_output_lane_collector_b_f16_scale_d_cta1_param_6];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r4, %r5, %r6, %r7}, [tcgen05_mma_sp_disable_output_lane_collector_b_f16_scale_d_cta1_param_7];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::f16.collector::a::discard.collector::b::lastuse [%r1], %rd1, %rd2, [%r3], %r2, {%r4, %r5, %r6, %r7}, %p1, 5;
-; CHECK-NEXT: ld.param.b32 %r8, [tcgen05_mma_sp_disable_output_lane_collector_b_f16_scale_d_cta1_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r8, [tcgen05_mma_sp_disable_output_lane_collector_b_f16_scale_d_cta1_param_1];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::f16.collector::a::discard.collector::b::fill [%r1], [%r8], %rd2, [%r3], %r2, {%r4, %r5, %r6, %r7}, %p1, 3;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::f16.ashift.collector::a::lastuse.collector::b::use [%r1], [%r8], %rd2, [%r3], %r2, {%r4, %r5, %r6, %r7}, %p1, 7;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::f16.ashift.collector::a::lastuse [%r1], [%r8], %rd2, [%r3], %r2, {%r4, %r5, %r6, %r7}, %p1, 7;
@@ -343,17 +343,17 @@ define void @tcgen05_mma_sp_disable_output_lane_collector_b_tf32_scale_d_cta1(pt
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_sp_disable_output_lane_collector_b_tf32_scale_d_cta1_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_sp_disable_output_lane_collector_b_tf32_scale_d_cta1_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_sp_disable_output_lane_collector_b_tf32_scale_d_cta1_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_sp_disable_output_lane_collector_b_tf32_scale_d_cta1_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_sp_disable_output_lane_collector_b_tf32_scale_d_cta1_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_sp_disable_output_lane_collector_b_tf32_scale_d_cta1_param_4];
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_sp_disable_output_lane_collector_b_tf32_scale_d_cta1_param_6];
-; CHECK-NEXT: ld.param.v4.b32 {%r4, %r5, %r6, %r7}, [tcgen05_mma_sp_disable_output_lane_collector_b_tf32_scale_d_cta1_param_7];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_sp_disable_output_lane_collector_b_tf32_scale_d_cta1_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_sp_disable_output_lane_collector_b_tf32_scale_d_cta1_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_sp_disable_output_lane_collector_b_tf32_scale_d_cta1_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_sp_disable_output_lane_collector_b_tf32_scale_d_cta1_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_sp_disable_output_lane_collector_b_tf32_scale_d_cta1_param_6];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r4, %r5, %r6, %r7}, [tcgen05_mma_sp_disable_output_lane_collector_b_tf32_scale_d_cta1_param_7];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::tf32.collector::a::discard.collector::b::fill [%r1], %rd1, %rd2, [%r3], %r2, {%r4, %r5, %r6, %r7}, %p1, 4;
-; CHECK-NEXT: ld.param.b32 %r8, [tcgen05_mma_sp_disable_output_lane_collector_b_tf32_scale_d_cta1_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r8, [tcgen05_mma_sp_disable_output_lane_collector_b_tf32_scale_d_cta1_param_1];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::tf32.collector::a::discard.collector::b::use [%r1], [%r8], %rd2, [%r3], %r2, {%r4, %r5, %r6, %r7}, %p1, 6;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::tf32.ashift.collector::a::lastuse.collector::b::lastuse [%r1], [%r8], %rd2, [%r3], %r2, {%r4, %r5, %r6, %r7}, %p1, 2;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::tf32.ashift.collector::a::lastuse [%r1], [%r8], %rd2, [%r3], %r2, {%r4, %r5, %r6, %r7}, %p1, 2;
@@ -385,18 +385,18 @@ define void @tcgen05_mma_sp_disable_output_lane_collector_b_f16_scale_d_cta2(ptr
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_sp_disable_output_lane_collector_b_f16_scale_d_cta2_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_sp_disable_output_lane_collector_b_f16_scale_d_cta2_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_sp_disable_output_lane_collector_b_f16_scale_d_cta2_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_sp_disable_output_lane_collector_b_f16_scale_d_cta2_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_sp_disable_output_lane_collector_b_f16_scale_d_cta2_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_sp_disable_output_lane_collector_b_f16_scale_d_cta2_param_4];
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_sp_disable_output_lane_collector_b_f16_scale_d_cta2_param_6];
-; CHECK-NEXT: ld.param.v4.b32 {%r4, %r5, %r6, %r7}, [tcgen05_mma_sp_disable_output_lane_collector_b_f16_scale_d_cta2_param_7+16];
-; CHECK-NEXT: ld.param.v4.b32 {%r8, %r9, %r10, %r11}, [tcgen05_mma_sp_disable_output_lane_collector_b_f16_scale_d_cta2_param_7];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_sp_disable_output_lane_collector_b_f16_scale_d_cta2_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_sp_disable_output_lane_collector_b_f16_scale_d_cta2_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_sp_disable_output_lane_collector_b_f16_scale_d_cta2_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_sp_disable_output_lane_collector_b_f16_scale_d_cta2_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_sp_disable_output_lane_collector_b_f16_scale_d_cta2_param_6];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r4, %r5, %r6, %r7}, [tcgen05_mma_sp_disable_output_lane_collector_b_f16_scale_d_cta2_param_7+16];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r8, %r9, %r10, %r11}, [tcgen05_mma_sp_disable_output_lane_collector_b_f16_scale_d_cta2_param_7];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::f16.collector::a::discard.collector::b::lastuse [%r1], %rd1, %rd2, [%r3], %r2, {%r8, %r9, %r10, %r11, %r4, %r5, %r6, %r7}, %p1, 5;
-; CHECK-NEXT: ld.param.b32 %r12, [tcgen05_mma_sp_disable_output_lane_collector_b_f16_scale_d_cta2_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r12, [tcgen05_mma_sp_disable_output_lane_collector_b_f16_scale_d_cta2_param_1];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::f16.collector::a::discard.collector::b::fill [%r1], [%r12], %rd2, [%r3], %r2, {%r8, %r9, %r10, %r11, %r4, %r5, %r6, %r7}, %p1, 3;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::f16.ashift.collector::a::lastuse.collector::b::use [%r1], [%r12], %rd2, [%r3], %r2, {%r8, %r9, %r10, %r11, %r4, %r5, %r6, %r7}, %p1, 7;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::f16.ashift.collector::a::lastuse [%r1], [%r12], %rd2, [%r3], %r2, {%r8, %r9, %r10, %r11, %r4, %r5, %r6, %r7}, %p1, 7;
@@ -428,18 +428,18 @@ define void @tcgen05_mma_sp_disable_output_lane_collector_b_tf32_scale_d_cta2(pt
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_sp_disable_output_lane_collector_b_tf32_scale_d_cta2_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_sp_disable_output_lane_collector_b_tf32_scale_d_cta2_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_sp_disable_output_lane_collector_b_tf32_scale_d_cta2_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_sp_disable_output_lane_collector_b_tf32_scale_d_cta2_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_sp_disable_output_lane_collector_b_tf32_scale_d_cta2_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_sp_disable_output_lane_collector_b_tf32_scale_d_cta2_param_4];
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_sp_disable_output_lane_collector_b_tf32_scale_d_cta2_param_6];
-; CHECK-NEXT: ld.param.v4.b32 {%r4, %r5, %r6, %r7}, [tcgen05_mma_sp_disable_output_lane_collector_b_tf32_scale_d_cta2_param_7+16];
-; CHECK-NEXT: ld.param.v4.b32 {%r8, %r9, %r10, %r11}, [tcgen05_mma_sp_disable_output_lane_collector_b_tf32_scale_d_cta2_param_7];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_sp_disable_output_lane_collector_b_tf32_scale_d_cta2_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_sp_disable_output_lane_collector_b_tf32_scale_d_cta2_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_sp_disable_output_lane_collector_b_tf32_scale_d_cta2_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_sp_disable_output_lane_collector_b_tf32_scale_d_cta2_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_sp_disable_output_lane_collector_b_tf32_scale_d_cta2_param_6];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r4, %r5, %r6, %r7}, [tcgen05_mma_sp_disable_output_lane_collector_b_tf32_scale_d_cta2_param_7+16];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r8, %r9, %r10, %r11}, [tcgen05_mma_sp_disable_output_lane_collector_b_tf32_scale_d_cta2_param_7];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::tf32.collector::a::discard.collector::b::fill [%r1], %rd1, %rd2, [%r3], %r2, {%r8, %r9, %r10, %r11, %r4, %r5, %r6, %r7}, %p1, 4;
-; CHECK-NEXT: ld.param.b32 %r12, [tcgen05_mma_sp_disable_output_lane_collector_b_tf32_scale_d_cta2_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r12, [tcgen05_mma_sp_disable_output_lane_collector_b_tf32_scale_d_cta2_param_1];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::tf32.collector::a::discard.collector::b::use [%r1], [%r12], %rd2, [%r3], %r2, {%r8, %r9, %r10, %r11, %r4, %r5, %r6, %r7}, %p1, 6;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::tf32.ashift.collector::a::lastuse.collector::b::lastuse [%r1], [%r12], %rd2, [%r3], %r2, {%r8, %r9, %r10, %r11, %r4, %r5, %r6, %r7}, %p1, 2;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::tf32.ashift.collector::a::lastuse [%r1], [%r12], %rd2, [%r3], %r2, {%r8, %r9, %r10, %r11, %r4, %r5, %r6, %r7}, %p1, 2;
diff --git a/llvm/test/CodeGen/NVPTX/tcgen05-mma-ws-i8.ll b/llvm/test/CodeGen/NVPTX/tcgen05-mma-ws-i8.ll
index 9ddc6039e9f72..fdd4ecc5fe9df 100644
--- a/llvm/test/CodeGen/NVPTX/tcgen05-mma-ws-i8.ll
+++ b/llvm/test/CodeGen/NVPTX/tcgen05-mma-ws-i8.ll
@@ -15,15 +15,15 @@ define void @tcgen05_mma_ws_i8(ptr addrspace(6) %dtmem, ptr addrspace(6) %atenso
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_ws_i8_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_ws_i8_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_ws_i8_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_ws_i8_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_ws_i8_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_ws_i8_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_ws_i8_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_ws_i8_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_ws_i8_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_ws_i8_param_4];
; CHECK-NEXT: tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::discard [%r1], %rd1, %rd2, %r2, %p1;
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_ws_i8_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_ws_i8_param_1];
; CHECK-NEXT: tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::discard [%r1], %rd1, %rd2, %r2, %p1;
; CHECK-NEXT: tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::discard [%r1], [%r3], %rd2, %r2, %p1;
; CHECK-NEXT: tcgen05.mma.ws.cta_group::1.kind::i8.collector::b0::discard [%r1], [%r3], %rd2, %r2, %p1;
@@ -95,16 +95,16 @@ define void @tcgen05_mma_ws_sp_i8(ptr addrspace(6) %dtmem, ptr addrspace(6) %ate
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_ws_sp_i8_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_ws_sp_i8_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_ws_sp_i8_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_ws_sp_i8_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_ws_sp_i8_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_ws_sp_i8_param_4];
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_ws_sp_i8_param_6];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_ws_sp_i8_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_ws_sp_i8_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_ws_sp_i8_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_ws_sp_i8_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_ws_sp_i8_param_6];
; CHECK-NEXT: tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b0::discard [%r1], %rd1, %rd2, [%r3], %r2, %p1;
-; CHECK-NEXT: ld.param.b32 %r4, [tcgen05_mma_ws_sp_i8_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r4, [tcgen05_mma_ws_sp_i8_param_1];
; CHECK-NEXT: tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b0::discard [%r1], %rd1, %rd2, [%r3], %r2, %p1;
; CHECK-NEXT: tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b0::discard [%r1], [%r4], %rd2, [%r3], %r2, %p1;
; CHECK-NEXT: tcgen05.mma.ws.sp.cta_group::1.kind::i8.collector::b0::discard [%r1], [%r4], %rd2, [%r3], %r2, %p1;
diff --git a/llvm/test/CodeGen/NVPTX/tcgen05-mma-ws.ll b/llvm/test/CodeGen/NVPTX/tcgen05-mma-ws.ll
index 8199eddb61241..292ced8056169 100644
--- a/llvm/test/CodeGen/NVPTX/tcgen05-mma-ws.ll
+++ b/llvm/test/CodeGen/NVPTX/tcgen05-mma-ws.ll
@@ -19,15 +19,15 @@ define void @tcgen05_mma_ws_fp16(ptr addrspace(6) %dtmem, ptr addrspace(6) %aten
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_ws_fp16_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_ws_fp16_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_ws_fp16_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_ws_fp16_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_ws_fp16_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_ws_fp16_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_ws_fp16_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_ws_fp16_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_ws_fp16_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_ws_fp16_param_4];
; CHECK-NEXT: tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::discard [%r1], %rd1, %rd2, %r2, %p1;
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_ws_fp16_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_ws_fp16_param_1];
; CHECK-NEXT: tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::discard [%r1], %rd1, %rd2, %r2, %p1;
; CHECK-NEXT: tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::discard [%r1], [%r3], %rd2, %r2, %p1;
; CHECK-NEXT: tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::discard [%r1], [%r3], %rd2, %r2, %p1;
@@ -99,16 +99,16 @@ define void @tcgen05_mma_ws_fp16_zero_col_mask(ptr addrspace(6) %dtmem, ptr addr
; CHECK-NEXT: .reg .b64 %rd<4>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_ws_fp16_zero_col_mask_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_ws_fp16_zero_col_mask_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_ws_fp16_zero_col_mask_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_ws_fp16_zero_col_mask_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_ws_fp16_zero_col_mask_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_ws_fp16_zero_col_mask_param_4];
-; CHECK-NEXT: ld.param.b64 %rd3, [tcgen05_mma_ws_fp16_zero_col_mask_param_6];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_ws_fp16_zero_col_mask_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_ws_fp16_zero_col_mask_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_ws_fp16_zero_col_mask_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_ws_fp16_zero_col_mask_param_4];
+; CHECK-NEXT: ld.param::func.b64 %rd3, [tcgen05_mma_ws_fp16_zero_col_mask_param_6];
; CHECK-NEXT: tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::discard [%r1], %rd1, %rd2, %r2, %p1, %rd3;
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_ws_fp16_zero_col_mask_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_ws_fp16_zero_col_mask_param_1];
; CHECK-NEXT: tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::discard [%r1], %rd1, %rd2, %r2, %p1, %rd3;
; CHECK-NEXT: tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::discard [%r1], [%r3], %rd2, %r2, %p1, %rd3;
; CHECK-NEXT: tcgen05.mma.ws.cta_group::1.kind::f16.collector::b0::discard [%r1], [%r3], %rd2, %r2, %p1, %rd3;
@@ -180,16 +180,16 @@ define void @tcgen05_mma_ws_sp_fp16(ptr addrspace(6) %dtmem, ptr addrspace(6) %a
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_ws_sp_fp16_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_ws_sp_fp16_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_ws_sp_fp16_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_ws_sp_fp16_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_ws_sp_fp16_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_ws_sp_fp16_param_4];
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_ws_sp_fp16_param_6];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_ws_sp_fp16_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_ws_sp_fp16_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_ws_sp_fp16_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_ws_sp_fp16_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_ws_sp_fp16_param_6];
; CHECK-NEXT: tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b0::discard [%r1], %rd1, %rd2, [%r3], %r2, %p1;
-; CHECK-NEXT: ld.param.b32 %r4, [tcgen05_mma_ws_sp_fp16_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r4, [tcgen05_mma_ws_sp_fp16_param_1];
; CHECK-NEXT: tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b0::discard [%r1], %rd1, %rd2, [%r3], %r2, %p1;
; CHECK-NEXT: tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b0::discard [%r1], [%r4], %rd2, [%r3], %r2, %p1;
; CHECK-NEXT: tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b0::discard [%r1], [%r4], %rd2, [%r3], %r2, %p1;
@@ -261,17 +261,17 @@ define void @tcgen05_mma_ws_sp_fp16_zero_col_mask(ptr addrspace(6) %dtmem, ptr a
; CHECK-NEXT: .reg .b64 %rd<4>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_ws_sp_fp16_zero_col_mask_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_ws_sp_fp16_zero_col_mask_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_ws_sp_fp16_zero_col_mask_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_ws_sp_fp16_zero_col_mask_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_ws_sp_fp16_zero_col_mask_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_ws_sp_fp16_zero_col_mask_param_4];
-; CHECK-NEXT: ld.param.b64 %rd3, [tcgen05_mma_ws_sp_fp16_zero_col_mask_param_6];
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_ws_sp_fp16_zero_col_mask_param_7];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_ws_sp_fp16_zero_col_mask_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_ws_sp_fp16_zero_col_mask_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_ws_sp_fp16_zero_col_mask_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_ws_sp_fp16_zero_col_mask_param_4];
+; CHECK-NEXT: ld.param::func.b64 %rd3, [tcgen05_mma_ws_sp_fp16_zero_col_mask_param_6];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_ws_sp_fp16_zero_col_mask_param_7];
; CHECK-NEXT: tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b0::discard [%r1], %rd1, %rd2, [%r3], %r2, %p1, %rd3;
-; CHECK-NEXT: ld.param.b32 %r4, [tcgen05_mma_ws_sp_fp16_zero_col_mask_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r4, [tcgen05_mma_ws_sp_fp16_zero_col_mask_param_1];
; CHECK-NEXT: tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b0::discard [%r1], %rd1, %rd2, [%r3], %r2, %p1, %rd3;
; CHECK-NEXT: tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b0::discard [%r1], [%r4], %rd2, [%r3], %r2, %p1, %rd3;
; CHECK-NEXT: tcgen05.mma.ws.sp.cta_group::1.kind::f16.collector::b0::discard [%r1], [%r4], %rd2, [%r3], %r2, %p1, %rd3;
@@ -343,15 +343,15 @@ define void @tcgen05_mma_ws_tf32(ptr addrspace(6) %dtmem, ptr addrspace(6) %aten
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_ws_tf32_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_ws_tf32_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_ws_tf32_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_ws_tf32_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_ws_tf32_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_ws_tf32_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_ws_tf32_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_ws_tf32_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_ws_tf32_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_ws_tf32_param_4];
; CHECK-NEXT: tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::discard [%r1], %rd1, %rd2, %r2, %p1;
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_ws_tf32_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_ws_tf32_param_1];
; CHECK-NEXT: tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::discard [%r1], %rd1, %rd2, %r2, %p1;
; CHECK-NEXT: tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::discard [%r1], [%r3], %rd2, %r2, %p1;
; CHECK-NEXT: tcgen05.mma.ws.cta_group::1.kind::tf32.collector::b0::discard [%r1], [%r3], %rd2, %r2, %p1;
@@ -423,15 +423,15 @@ define void @tcgen05_mma_ws_f8f6f4(ptr addrspace(6) %dtmem, ptr addrspace(6) %at
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_ws_f8f6f4_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_ws_f8f6f4_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_ws_f8f6f4_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_ws_f8f6f4_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_ws_f8f6f4_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_ws_f8f6f4_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_ws_f8f6f4_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_ws_f8f6f4_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_ws_f8f6f4_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_ws_f8f6f4_param_4];
; CHECK-NEXT: tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::discard [%r1], %rd1, %rd2, %r2, %p1;
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_ws_f8f6f4_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_ws_f8f6f4_param_1];
; CHECK-NEXT: tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::discard [%r1], %rd1, %rd2, %r2, %p1;
; CHECK-NEXT: tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::discard [%r1], [%r3], %rd2, %r2, %p1;
; CHECK-NEXT: tcgen05.mma.ws.cta_group::1.kind::f8f6f4.collector::b0::discard [%r1], [%r3], %rd2, %r2, %p1;
diff --git a/llvm/test/CodeGen/NVPTX/tcgen05-mma.ll b/llvm/test/CodeGen/NVPTX/tcgen05-mma.ll
index 25bda658ce26b..f4dcd9b26f250 100644
--- a/llvm/test/CodeGen/NVPTX/tcgen05-mma.ll
+++ b/llvm/test/CodeGen/NVPTX/tcgen05-mma.ll
@@ -19,15 +19,15 @@ define void @tcgen05_mma_fp16_cta1(ptr addrspace(6) %dtmem, ptr addrspace(6) %at
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_fp16_cta1_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_fp16_cta1_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_fp16_cta1_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_fp16_cta1_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_fp16_cta1_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_fp16_cta1_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_fp16_cta1_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_fp16_cta1_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_fp16_cta1_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_fp16_cta1_param_4];
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::f16.collector::a::discard [%r1], %rd1, %rd2, %r2, %p1;
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_fp16_cta1_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_fp16_cta1_param_1];
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::f16.collector::a::discard [%r1], [%r3], %rd2, %r2, %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::f16.ashift.collector::a::discard [%r1], [%r3], %rd2, %r2, %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::f16.collector::a::lastuse [%r1], %rd1, %rd2, %r2, %p1;
@@ -58,16 +58,16 @@ define void @tcgen05_mma_sp_fp16_cta1(ptr addrspace(6) %dtmem, ptr addrspace(6)
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_sp_fp16_cta1_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_sp_fp16_cta1_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_sp_fp16_cta1_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_sp_fp16_cta1_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_sp_fp16_cta1_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_sp_fp16_cta1_param_4];
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_sp_fp16_cta1_param_6];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_sp_fp16_cta1_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_sp_fp16_cta1_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_sp_fp16_cta1_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_sp_fp16_cta1_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_sp_fp16_cta1_param_6];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::f16.collector::a::discard [%r1], %rd1, %rd2, [%r3], %r2, %p1;
-; CHECK-NEXT: ld.param.b32 %r4, [tcgen05_mma_sp_fp16_cta1_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r4, [tcgen05_mma_sp_fp16_cta1_param_1];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::f16.collector::a::discard [%r1], [%r4], %rd2, [%r3], %r2, %p1;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::f16.ashift.collector::a::discard [%r1], [%r4], %rd2, [%r3], %r2, %p1;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::f16.collector::a::lastuse [%r1], %rd1, %rd2, [%r3], %r2, %p1;
@@ -98,15 +98,15 @@ define void @tcgen05_mma_tf32_cta1(ptr addrspace(6) %dtmem, ptr addrspace(6) %at
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_tf32_cta1_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_tf32_cta1_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_tf32_cta1_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_tf32_cta1_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_tf32_cta1_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_tf32_cta1_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_tf32_cta1_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_tf32_cta1_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_tf32_cta1_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_tf32_cta1_param_4];
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::tf32.collector::a::discard [%r1], %rd1, %rd2, %r2, %p1;
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_tf32_cta1_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_tf32_cta1_param_1];
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::tf32.collector::a::discard [%r1], [%r3], %rd2, %r2, %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::tf32.ashift.collector::a::discard [%r1], [%r3], %rd2, %r2, %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::tf32.collector::a::lastuse [%r1], %rd1, %rd2, %r2, %p1;
@@ -137,16 +137,16 @@ define void @tcgen05_mma_sp_tf32_cta1(ptr addrspace(6) %dtmem, ptr addrspace(6)
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_sp_tf32_cta1_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_sp_tf32_cta1_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_sp_tf32_cta1_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_sp_tf32_cta1_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_sp_tf32_cta1_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_sp_tf32_cta1_param_4];
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_sp_tf32_cta1_param_6];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_sp_tf32_cta1_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_sp_tf32_cta1_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_sp_tf32_cta1_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_sp_tf32_cta1_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_sp_tf32_cta1_param_6];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::tf32.collector::a::discard [%r1], %rd1, %rd2, [%r3], %r2, %p1;
-; CHECK-NEXT: ld.param.b32 %r4, [tcgen05_mma_sp_tf32_cta1_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r4, [tcgen05_mma_sp_tf32_cta1_param_1];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::tf32.collector::a::discard [%r1], [%r4], %rd2, [%r3], %r2, %p1;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::tf32.ashift.collector::a::discard [%r1], [%r4], %rd2, [%r3], %r2, %p1;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::tf32.collector::a::lastuse [%r1], %rd1, %rd2, [%r3], %r2, %p1;
@@ -177,15 +177,15 @@ define void @tcgen05_mma_f8f6f4_cta1(ptr addrspace(6) %dtmem, ptr addrspace(6) %
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_f8f6f4_cta1_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_f8f6f4_cta1_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_f8f6f4_cta1_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_f8f6f4_cta1_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_f8f6f4_cta1_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_f8f6f4_cta1_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_f8f6f4_cta1_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_f8f6f4_cta1_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_f8f6f4_cta1_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_f8f6f4_cta1_param_4];
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::f8f6f4.collector::a::discard [%r1], %rd1, %rd2, %r2, %p1;
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_f8f6f4_cta1_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_f8f6f4_cta1_param_1];
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::f8f6f4.collector::a::discard [%r1], [%r3], %rd2, %r2, %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::f8f6f4.ashift.collector::a::discard [%r1], [%r3], %rd2, %r2, %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::1.kind::f8f6f4.collector::a::lastuse [%r1], %rd1, %rd2, %r2, %p1;
@@ -216,16 +216,16 @@ define void @tcgen05_mma_sp_f8f6fr_cta1(ptr addrspace(6) %dtmem, ptr addrspace(6
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_sp_f8f6fr_cta1_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_sp_f8f6fr_cta1_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_sp_f8f6fr_cta1_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_sp_f8f6fr_cta1_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_sp_f8f6fr_cta1_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_sp_f8f6fr_cta1_param_4];
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_sp_f8f6fr_cta1_param_6];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_sp_f8f6fr_cta1_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_sp_f8f6fr_cta1_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_sp_f8f6fr_cta1_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_sp_f8f6fr_cta1_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_sp_f8f6fr_cta1_param_6];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::f8f6f4.collector::a::discard [%r1], %rd1, %rd2, [%r3], %r2, %p1;
-; CHECK-NEXT: ld.param.b32 %r4, [tcgen05_mma_sp_f8f6fr_cta1_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r4, [tcgen05_mma_sp_f8f6fr_cta1_param_1];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::f8f6f4.collector::a::discard [%r1], [%r4], %rd2, [%r3], %r2, %p1;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::f8f6f4.ashift.collector::a::discard [%r1], [%r4], %rd2, [%r3], %r2, %p1;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::1.kind::f8f6f4.collector::a::lastuse [%r1], %rd1, %rd2, [%r3], %r2, %p1;
@@ -256,15 +256,15 @@ define void @tcgen05_mma_fp16_cta2(ptr addrspace(6) %dtmem, ptr addrspace(6) %at
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_fp16_cta2_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_fp16_cta2_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_fp16_cta2_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_fp16_cta2_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_fp16_cta2_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_fp16_cta2_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_fp16_cta2_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_fp16_cta2_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_fp16_cta2_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_fp16_cta2_param_4];
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::f16.collector::a::discard [%r1], %rd1, %rd2, %r2, %p1;
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_fp16_cta2_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_fp16_cta2_param_1];
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::f16.collector::a::discard [%r1], [%r3], %rd2, %r2, %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::f16.ashift.collector::a::discard [%r1], [%r3], %rd2, %r2, %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::f16.collector::a::lastuse [%r1], %rd1, %rd2, %r2, %p1;
@@ -295,16 +295,16 @@ define void @tcgen05_mma_sp_fp16_cta2(ptr addrspace(6) %dtmem, ptr addrspace(6)
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_sp_fp16_cta2_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_sp_fp16_cta2_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_sp_fp16_cta2_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_sp_fp16_cta2_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_sp_fp16_cta2_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_sp_fp16_cta2_param_4];
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_sp_fp16_cta2_param_6];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_sp_fp16_cta2_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_sp_fp16_cta2_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_sp_fp16_cta2_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_sp_fp16_cta2_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_sp_fp16_cta2_param_6];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::f16.collector::a::discard [%r1], %rd1, %rd2, [%r3], %r2, %p1;
-; CHECK-NEXT: ld.param.b32 %r4, [tcgen05_mma_sp_fp16_cta2_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r4, [tcgen05_mma_sp_fp16_cta2_param_1];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::f16.collector::a::discard [%r1], [%r4], %rd2, [%r3], %r2, %p1;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::f16.ashift.collector::a::discard [%r1], [%r4], %rd2, [%r3], %r2, %p1;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::f16.collector::a::lastuse [%r1], %rd1, %rd2, [%r3], %r2, %p1;
@@ -335,15 +335,15 @@ define void @tcgen05_mma_tf32_cta2(ptr addrspace(6) %dtmem, ptr addrspace(6) %at
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_tf32_cta2_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_tf32_cta2_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_tf32_cta2_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_tf32_cta2_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_tf32_cta2_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_tf32_cta2_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_tf32_cta2_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_tf32_cta2_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_tf32_cta2_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_tf32_cta2_param_4];
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::tf32.collector::a::discard [%r1], %rd1, %rd2, %r2, %p1;
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_tf32_cta2_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_tf32_cta2_param_1];
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::tf32.collector::a::discard [%r1], [%r3], %rd2, %r2, %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::tf32.ashift.collector::a::discard [%r1], [%r3], %rd2, %r2, %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::tf32.collector::a::lastuse [%r1], %rd1, %rd2, %r2, %p1;
@@ -374,16 +374,16 @@ define void @tcgen05_mma_sp_tf32_cta2(ptr addrspace(6) %dtmem, ptr addrspace(6)
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_sp_tf32_cta2_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_sp_tf32_cta2_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_sp_tf32_cta2_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_sp_tf32_cta2_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_sp_tf32_cta2_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_sp_tf32_cta2_param_4];
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_sp_tf32_cta2_param_6];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_sp_tf32_cta2_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_sp_tf32_cta2_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_sp_tf32_cta2_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_sp_tf32_cta2_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_sp_tf32_cta2_param_6];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::tf32.collector::a::discard [%r1], %rd1, %rd2, [%r3], %r2, %p1;
-; CHECK-NEXT: ld.param.b32 %r4, [tcgen05_mma_sp_tf32_cta2_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r4, [tcgen05_mma_sp_tf32_cta2_param_1];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::tf32.collector::a::discard [%r1], [%r4], %rd2, [%r3], %r2, %p1;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::tf32.ashift.collector::a::discard [%r1], [%r4], %rd2, [%r3], %r2, %p1;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::tf32.collector::a::lastuse [%r1], %rd1, %rd2, [%r3], %r2, %p1;
@@ -414,15 +414,15 @@ define void @tcgen05_mma_f8f6f4_cta2(ptr addrspace(6) %dtmem, ptr addrspace(6) %
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_f8f6f4_cta2_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_f8f6f4_cta2_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_f8f6f4_cta2_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_f8f6f4_cta2_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_f8f6f4_cta2_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_f8f6f4_cta2_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_f8f6f4_cta2_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_f8f6f4_cta2_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_f8f6f4_cta2_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_f8f6f4_cta2_param_4];
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::f8f6f4.collector::a::discard [%r1], %rd1, %rd2, %r2, %p1;
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_f8f6f4_cta2_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_f8f6f4_cta2_param_1];
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::f8f6f4.collector::a::discard [%r1], [%r3], %rd2, %r2, %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::f8f6f4.ashift.collector::a::discard [%r1], [%r3], %rd2, %r2, %p1;
; CHECK-NEXT: tcgen05.mma.cta_group::2.kind::f8f6f4.collector::a::lastuse [%r1], %rd1, %rd2, %r2, %p1;
@@ -453,16 +453,16 @@ define void @tcgen05_mma_sp_f8f6fr_cta2(ptr addrspace(6) %dtmem, ptr addrspace(6
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b8 %rs1, [tcgen05_mma_sp_f8f6fr_cta2_param_5];
+; CHECK-NEXT: ld.param::func.b8 %rs1, [tcgen05_mma_sp_f8f6fr_cta2_param_5];
; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r1, [tcgen05_mma_sp_f8f6fr_cta2_param_0];
-; CHECK-NEXT: ld.param.b64 %rd1, [tcgen05_mma_sp_f8f6fr_cta2_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [tcgen05_mma_sp_f8f6fr_cta2_param_3];
-; CHECK-NEXT: ld.param.b32 %r2, [tcgen05_mma_sp_f8f6fr_cta2_param_4];
-; CHECK-NEXT: ld.param.b32 %r3, [tcgen05_mma_sp_f8f6fr_cta2_param_6];
+; CHECK-NEXT: ld.param::func.b32 %r1, [tcgen05_mma_sp_f8f6fr_cta2_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tcgen05_mma_sp_f8f6fr_cta2_param_2];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tcgen05_mma_sp_f8f6fr_cta2_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r2, [tcgen05_mma_sp_f8f6fr_cta2_param_4];
+; CHECK-NEXT: ld.param::func.b32 %r3, [tcgen05_mma_sp_f8f6fr_cta2_param_6];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::f8f6f4.collector::a::discard [%r1], %rd1, %rd2, [%r3], %r2, %p1;
-; CHECK-NEXT: ld.param.b32 %r4, [tcgen05_mma_sp_f8f6fr_cta2_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r4, [tcgen05_mma_sp_f8f6fr_cta2_param_1];
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::f8f6f4.collector::a::discard [%r1], [%r4], %rd2, [%r3], %r2, %p1;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::f8f6f4.ashift.collector::a::discard [%r1], [%r4], %rd2, [%r3], %r2, %p1;
; CHECK-NEXT: tcgen05.mma.sp.cta_group::2.kind::f8f6f4.collector::a::lastuse [%r1], %rd1, %rd2, [%r3], %r2, %p1;
diff --git a/llvm/test/CodeGen/NVPTX/tcgen05-shift.ll b/llvm/test/CodeGen/NVPTX/tcgen05-shift.ll
index 33483b58a62f9..4b13dadb0f3f4 100644
--- a/llvm/test/CodeGen/NVPTX/tcgen05-shift.ll
+++ b/llvm/test/CodeGen/NVPTX/tcgen05-shift.ll
@@ -15,7 +15,7 @@ define void @test_tcgen05_shift_cg1(ptr addrspace(6) %tmem_addr) {
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [test_tcgen05_shift_cg1_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_tcgen05_shift_cg1_param_0];
; CHECK-NEXT: tcgen05.shift.cta_group::1.down [%r1];
; CHECK-NEXT: ret;
call void @llvm.nvvm.tcgen05.shift.down.cg1(ptr addrspace(6) %tmem_addr)
@@ -29,7 +29,7 @@ define void @test_tcgen05_shift_cg2(ptr addrspace(6) %tmem_addr) {
; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [test_tcgen05_shift_cg2_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r1, [test_tcgen05_shift_cg2_param_0];
; CHECK-NEXT: tcgen05.shift.cta_group::2.down [%r1];
; CHECK-NEXT: ret;
call void @llvm.nvvm.tcgen05.shift.down.cg2(ptr addrspace(6) %tmem_addr)
diff --git a/llvm/test/CodeGen/NVPTX/tcgen05-st.ll b/llvm/test/CodeGen/NVPTX/tcgen05-st.ll
index 952e1cf39b6fc..cdf4ce443f654 100644
--- a/llvm/test/CodeGen/NVPTX/tcgen05-st.ll
+++ b/llvm/test/CodeGen/NVPTX/tcgen05-st.ll
@@ -17,79 +17,79 @@ define void @nvvm_tcgen05_st_16x64b(ptr addrspace(6) %taddr, <1 x i32> %stv1, <2
; CHECK-NEXT: .reg .b32 %r<257>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [nvvm_tcgen05_st_16x64b_param_0];
-; CHECK-NEXT: ld.param.b32 %r2, [nvvm_tcgen05_st_16x64b_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r1, [nvvm_tcgen05_st_16x64b_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r2, [nvvm_tcgen05_st_16x64b_param_1];
; CHECK-NEXT: tcgen05.st.sync.aligned.16x64b.x1.b32 [%r1], {%r2};
-; CHECK-NEXT: ld.param.v2.b32 {%r3, %r4}, [nvvm_tcgen05_st_16x64b_param_2];
+; CHECK-NEXT: ld.param::func.v2.b32 {%r3, %r4}, [nvvm_tcgen05_st_16x64b_param_2];
; CHECK-NEXT: tcgen05.st.sync.aligned.16x64b.x2.b32 [%r1], {%r3, %r4};
-; CHECK-NEXT: ld.param.v4.b32 {%r5, %r6, %r7, %r8}, [nvvm_tcgen05_st_16x64b_param_3];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r5, %r6, %r7, %r8}, [nvvm_tcgen05_st_16x64b_param_3];
; CHECK-NEXT: tcgen05.st.sync.aligned.16x64b.x4.b32 [%r1], {%r5, %r6, %r7, %r8};
-; CHECK-NEXT: ld.param.v4.b32 {%r9, %r10, %r11, %r12}, [nvvm_tcgen05_st_16x64b_param_4+16];
-; CHECK-NEXT: ld.param.v4.b32 {%r13, %r14, %r15, %r16}, [nvvm_tcgen05_st_16x64b_param_4];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r9, %r10, %r11, %r12}, [nvvm_tcgen05_st_16x64b_param_4+16];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r13, %r14, %r15, %r16}, [nvvm_tcgen05_st_16x64b_param_4];
; CHECK-NEXT: tcgen05.st.sync.aligned.16x64b.x8.b32 [%r1], {%r13, %r14, %r15, %r16, %r9, %r10, %r11, %r12};
-; CHECK-NEXT: ld.param.v4.b32 {%r17, %r18, %r19, %r20}, [nvvm_tcgen05_st_16x64b_param_5+48];
-; CHECK-NEXT: ld.param.v4.b32 {%r21, %r22, %r23, %r24}, [nvvm_tcgen05_st_16x64b_param_5+32];
-; CHECK-NEXT: ld.param.v4.b32 {%r25, %r26, %r27, %r28}, [nvvm_tcgen05_st_16x64b_param_5+16];
-; CHECK-NEXT: ld.param.v4.b32 {%r29, %r30, %r31, %r32}, [nvvm_tcgen05_st_16x64b_param_5];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r17, %r18, %r19, %r20}, [nvvm_tcgen05_st_16x64b_param_5+48];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r21, %r22, %r23, %r24}, [nvvm_tcgen05_st_16x64b_param_5+32];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r25, %r26, %r27, %r28}, [nvvm_tcgen05_st_16x64b_param_5+16];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r29, %r30, %r31, %r32}, [nvvm_tcgen05_st_16x64b_param_5];
; CHECK-NEXT: tcgen05.st.sync.aligned.16x64b.x16.b32 [%r1], {%r29, %r30, %r31, %r32, %r25, %r26, %r27, %r28, %r21, %r22, %r23, %r24, %r17, %r18, %r19, %r20};
-; CHECK-NEXT: ld.param.v4.b32 {%r33, %r34, %r35, %r36}, [nvvm_tcgen05_st_16x64b_param_6+112];
-; CHECK-NEXT: ld.param.v4.b32 {%r37, %r38, %r39, %r40}, [nvvm_tcgen05_st_16x64b_param_6+96];
-; CHECK-NEXT: ld.param.v4.b32 {%r41, %r42, %r43, %r44}, [nvvm_tcgen05_st_16x64b_param_6+80];
-; CHECK-NEXT: ld.param.v4.b32 {%r45, %r46, %r47, %r48}, [nvvm_tcgen05_st_16x64b_param_6+64];
-; CHECK-NEXT: ld.param.v4.b32 {%r49, %r50, %r51, %r52}, [nvvm_tcgen05_st_16x64b_param_6+48];
-; CHECK-NEXT: ld.param.v4.b32 {%r53, %r54, %r55, %r56}, [nvvm_tcgen05_st_16x64b_param_6+32];
-; CHECK-NEXT: ld.param.v4.b32 {%r57, %r58, %r59, %r60}, [nvvm_tcgen05_st_16x64b_param_6+16];
-; CHECK-NEXT: ld.param.v4.b32 {%r61, %r62, %r63, %r64}, [nvvm_tcgen05_st_16x64b_param_6];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r33, %r34, %r35, %r36}, [nvvm_tcgen05_st_16x64b_param_6+112];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r37, %r38, %r39, %r40}, [nvvm_tcgen05_st_16x64b_param_6+96];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r41, %r42, %r43, %r44}, [nvvm_tcgen05_st_16x64b_param_6+80];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r45, %r46, %r47, %r48}, [nvvm_tcgen05_st_16x64b_param_6+64];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r49, %r50, %r51, %r52}, [nvvm_tcgen05_st_16x64b_param_6+48];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r53, %r54, %r55, %r56}, [nvvm_tcgen05_st_16x64b_param_6+32];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r57, %r58, %r59, %r60}, [nvvm_tcgen05_st_16x64b_param_6+16];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r61, %r62, %r63, %r64}, [nvvm_tcgen05_st_16x64b_param_6];
; CHECK-NEXT: tcgen05.st.sync.aligned.16x64b.x32.b32 [%r1], {%r61, %r62, %r63, %r64, %r57, %r58, %r59, %r60, %r53, %r54, %r55, %r56, %r49, %r50, %r51, %r52, %r45, %r46, %r47, %r48, %r41, %r42, %r43, %r44, %r37, %r38, %r39, %r40, %r33, %r34, %r35, %r36};
-; CHECK-NEXT: ld.param.v4.b32 {%r65, %r66, %r67, %r68}, [nvvm_tcgen05_st_16x64b_param_7+240];
-; CHECK-NEXT: ld.param.v4.b32 {%r69, %r70, %r71, %r72}, [nvvm_tcgen05_st_16x64b_param_7+224];
-; CHECK-NEXT: ld.param.v4.b32 {%r73, %r74, %r75, %r76}, [nvvm_tcgen05_st_16x64b_param_7+208];
-; CHECK-NEXT: ld.param.v4.b32 {%r77, %r78, %r79, %r80}, [nvvm_tcgen05_st_16x64b_param_7+192];
-; CHECK-NEXT: ld.param.v4.b32 {%r81, %r82, %r83, %r84}, [nvvm_tcgen05_st_16x64b_param_7+176];
-; CHECK-NEXT: ld.param.v4.b32 {%r85, %r86, %r87, %r88}, [nvvm_tcgen05_st_16x64b_param_7+160];
-; CHECK-NEXT: ld.param.v4.b32 {%r89, %r90, %r91, %r92}, [nvvm_tcgen05_st_16x64b_param_7+144];
-; CHECK-NEXT: ld.param.v4.b32 {%r93, %r94, %r95, %r96}, [nvvm_tcgen05_st_16x64b_param_7+128];
-; CHECK-NEXT: ld.param.v4.b32 {%r97, %r98, %r99, %r100}, [nvvm_tcgen05_st_16x64b_param_7+112];
-; CHECK-NEXT: ld.param.v4.b32 {%r101, %r102, %r103, %r104}, [nvvm_tcgen05_st_16x64b_param_7+96];
-; CHECK-NEXT: ld.param.v4.b32 {%r105, %r106, %r107, %r108}, [nvvm_tcgen05_st_16x64b_param_7+80];
-; CHECK-NEXT: ld.param.v4.b32 {%r109, %r110, %r111, %r112}, [nvvm_tcgen05_st_16x64b_param_7+64];
-; CHECK-NEXT: ld.param.v4.b32 {%r113, %r114, %r115, %r116}, [nvvm_tcgen05_st_16x64b_param_7+48];
-; CHECK-NEXT: ld.param.v4.b32 {%r117, %r118, %r119, %r120}, [nvvm_tcgen05_st_16x64b_param_7+32];
-; CHECK-NEXT: ld.param.v4.b32 {%r121, %r122, %r123, %r124}, [nvvm_tcgen05_st_16x64b_param_7+16];
-; CHECK-NEXT: ld.param.v4.b32 {%r125, %r126, %r127, %r128}, [nvvm_tcgen05_st_16x64b_param_7];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r65, %r66, %r67, %r68}, [nvvm_tcgen05_st_16x64b_param_7+240];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r69, %r70, %r71, %r72}, [nvvm_tcgen05_st_16x64b_param_7+224];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r73, %r74, %r75, %r76}, [nvvm_tcgen05_st_16x64b_param_7+208];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r77, %r78, %r79, %r80}, [nvvm_tcgen05_st_16x64b_param_7+192];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r81, %r82, %r83, %r84}, [nvvm_tcgen05_st_16x64b_param_7+176];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r85, %r86, %r87, %r88}, [nvvm_tcgen05_st_16x64b_param_7+160];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r89, %r90, %r91, %r92}, [nvvm_tcgen05_st_16x64b_param_7+144];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r93, %r94, %r95, %r96}, [nvvm_tcgen05_st_16x64b_param_7+128];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r97, %r98, %r99, %r100}, [nvvm_tcgen05_st_16x64b_param_7+112];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r101, %r102, %r103, %r104}, [nvvm_tcgen05_st_16x64b_param_7+96];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r105, %r106, %r107, %r108}, [nvvm_tcgen05_st_16x64b_param_7+80];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r109, %r110, %r111, %r112}, [nvvm_tcgen05_st_16x64b_param_7+64];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r113, %r114, %r115, %r116}, [nvvm_tcgen05_st_16x64b_param_7+48];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r117, %r118, %r119, %r120}, [nvvm_tcgen05_st_16x64b_param_7+32];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r121, %r122, %r123, %r124}, [nvvm_tcgen05_st_16x64b_param_7+16];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r125, %r126, %r127, %r128}, [nvvm_tcgen05_st_16x64b_param_7];
; CHECK-NEXT: tcgen05.st.sync.aligned.16x64b.x64.b32 [%r1], {%r125, %r126, %r127, %r128, %r121, %r122, %r123, %r124, %r117, %r118, %r119, %r120, %r113, %r114, %r115, %r116, %r109, %r110, %r111, %r112, %r105, %r106, %r107, %r108, %r101, %r102, %r103, %r104, %r97, %r98, %r99, %r100, %r93, %r94, %r95, %r96, %r89, %r90, %r91, %r92, %r85, %r86, %r87, %r88, %r81, %r82, %r83, %r84, %r77, %r78, %r79, %r80, %r73, %r74, %r75, %r76, %r69, %r70, %r71, %r72, %r65, %r66, %r67, %r68};
-; CHECK-NEXT: ld.param.v4.b32 {%r129, %r130, %r131, %r132}, [nvvm_tcgen05_st_16x64b_param_8+496];
-; CHECK-NEXT: ld.param.v4.b32 {%r133, %r134, %r135, %r136}, [nvvm_tcgen05_st_16x64b_param_8+480];
-; CHECK-NEXT: ld.param.v4.b32 {%r137, %r138, %r139, %r140}, [nvvm_tcgen05_st_16x64b_param_8+464];
-; CHECK-NEXT: ld.param.v4.b32 {%r141, %r142, %r143, %r144}, [nvvm_tcgen05_st_16x64b_param_8+448];
-; CHECK-NEXT: ld.param.v4.b32 {%r145, %r146, %r147, %r148}, [nvvm_tcgen05_st_16x64b_param_8+432];
-; CHECK-NEXT: ld.param.v4.b32 {%r149, %r150, %r151, %r152}, [nvvm_tcgen05_st_16x64b_param_8+416];
-; CHECK-NEXT: ld.param.v4.b32 {%r153, %r154, %r155, %r156}, [nvvm_tcgen05_st_16x64b_param_8+400];
-; CHECK-NEXT: ld.param.v4.b32 {%r157, %r158, %r159, %r160}, [nvvm_tcgen05_st_16x64b_param_8+384];
-; CHECK-NEXT: ld.param.v4.b32 {%r161, %r162, %r163, %r164}, [nvvm_tcgen05_st_16x64b_param_8+368];
-; CHECK-NEXT: ld.param.v4.b32 {%r165, %r166, %r167, %r168}, [nvvm_tcgen05_st_16x64b_param_8+352];
-; CHECK-NEXT: ld.param.v4.b32 {%r169, %r170, %r171, %r172}, [nvvm_tcgen05_st_16x64b_param_8+336];
-; CHECK-NEXT: ld.param.v4.b32 {%r173, %r174, %r175, %r176}, [nvvm_tcgen05_st_16x64b_param_8+320];
-; CHECK-NEXT: ld.param.v4.b32 {%r177, %r178, %r179, %r180}, [nvvm_tcgen05_st_16x64b_param_8+304];
-; CHECK-NEXT: ld.param.v4.b32 {%r181, %r182, %r183, %r184}, [nvvm_tcgen05_st_16x64b_param_8+288];
-; CHECK-NEXT: ld.param.v4.b32 {%r185, %r186, %r187, %r188}, [nvvm_tcgen05_st_16x64b_param_8+272];
-; CHECK-NEXT: ld.param.v4.b32 {%r189, %r190, %r191, %r192}, [nvvm_tcgen05_st_16x64b_param_8+256];
-; CHECK-NEXT: ld.param.v4.b32 {%r193, %r194, %r195, %r196}, [nvvm_tcgen05_st_16x64b_param_8+240];
-; CHECK-NEXT: ld.param.v4.b32 {%r197, %r198, %r199, %r200}, [nvvm_tcgen05_st_16x64b_param_8+224];
-; CHECK-NEXT: ld.param.v4.b32 {%r201, %r202, %r203, %r204}, [nvvm_tcgen05_st_16x64b_param_8+208];
-; CHECK-NEXT: ld.param.v4.b32 {%r205, %r206, %r207, %r208}, [nvvm_tcgen05_st_16x64b_param_8+192];
-; CHECK-NEXT: ld.param.v4.b32 {%r209, %r210, %r211, %r212}, [nvvm_tcgen05_st_16x64b_param_8+176];
-; CHECK-NEXT: ld.param.v4.b32 {%r213, %r214, %r215, %r216}, [nvvm_tcgen05_st_16x64b_param_8+160];
-; CHECK-NEXT: ld.param.v4.b32 {%r217, %r218, %r219, %r220}, [nvvm_tcgen05_st_16x64b_param_8+144];
-; CHECK-NEXT: ld.param.v4.b32 {%r221, %r222, %r223, %r224}, [nvvm_tcgen05_st_16x64b_param_8+128];
-; CHECK-NEXT: ld.param.v4.b32 {%r225, %r226, %r227, %r228}, [nvvm_tcgen05_st_16x64b_param_8+112];
-; CHECK-NEXT: ld.param.v4.b32 {%r229, %r230, %r231, %r232}, [nvvm_tcgen05_st_16x64b_param_8+96];
-; CHECK-NEXT: ld.param.v4.b32 {%r233, %r234, %r235, %r236}, [nvvm_tcgen05_st_16x64b_param_8+80];
-; CHECK-NEXT: ld.param.v4.b32 {%r237, %r238, %r239, %r240}, [nvvm_tcgen05_st_16x64b_param_8+64];
-; CHECK-NEXT: ld.param.v4.b32 {%r241, %r242, %r243, %r244}, [nvvm_tcgen05_st_16x64b_param_8+48];
-; CHECK-NEXT: ld.param.v4.b32 {%r245, %r246, %r247, %r248}, [nvvm_tcgen05_st_16x64b_param_8+32];
-; CHECK-NEXT: ld.param.v4.b32 {%r249, %r250, %r251, %r252}, [nvvm_tcgen05_st_16x64b_param_8+16];
-; CHECK-NEXT: ld.param.v4.b32 {%r253, %r254, %r255, %r256}, [nvvm_tcgen05_st_16x64b_param_8];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r129, %r130, %r131, %r132}, [nvvm_tcgen05_st_16x64b_param_8+496];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r133, %r134, %r135, %r136}, [nvvm_tcgen05_st_16x64b_param_8+480];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r137, %r138, %r139, %r140}, [nvvm_tcgen05_st_16x64b_param_8+464];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r141, %r142, %r143, %r144}, [nvvm_tcgen05_st_16x64b_param_8+448];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r145, %r146, %r147, %r148}, [nvvm_tcgen05_st_16x64b_param_8+432];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r149, %r150, %r151, %r152}, [nvvm_tcgen05_st_16x64b_param_8+416];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r153, %r154, %r155, %r156}, [nvvm_tcgen05_st_16x64b_param_8+400];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r157, %r158, %r159, %r160}, [nvvm_tcgen05_st_16x64b_param_8+384];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r161, %r162, %r163, %r164}, [nvvm_tcgen05_st_16x64b_param_8+368];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r165, %r166, %r167, %r168}, [nvvm_tcgen05_st_16x64b_param_8+352];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r169, %r170, %r171, %r172}, [nvvm_tcgen05_st_16x64b_param_8+336];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r173, %r174, %r175, %r176}, [nvvm_tcgen05_st_16x64b_param_8+320];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r177, %r178, %r179, %r180}, [nvvm_tcgen05_st_16x64b_param_8+304];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r181, %r182, %r183, %r184}, [nvvm_tcgen05_st_16x64b_param_8+288];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r185, %r186, %r187, %r188}, [nvvm_tcgen05_st_16x64b_param_8+272];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r189, %r190, %r191, %r192}, [nvvm_tcgen05_st_16x64b_param_8+256];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r193, %r194, %r195, %r196}, [nvvm_tcgen05_st_16x64b_param_8+240];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r197, %r198, %r199, %r200}, [nvvm_tcgen05_st_16x64b_param_8+224];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r201, %r202, %r203, %r204}, [nvvm_tcgen05_st_16x64b_param_8+208];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r205, %r206, %r207, %r208}, [nvvm_tcgen05_st_16x64b_param_8+192];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r209, %r210, %r211, %r212}, [nvvm_tcgen05_st_16x64b_param_8+176];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r213, %r214, %r215, %r216}, [nvvm_tcgen05_st_16x64b_param_8+160];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r217, %r218, %r219, %r220}, [nvvm_tcgen05_st_16x64b_param_8+144];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r221, %r222, %r223, %r224}, [nvvm_tcgen05_st_16x64b_param_8+128];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r225, %r226, %r227, %r228}, [nvvm_tcgen05_st_16x64b_param_8+112];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r229, %r230, %r231, %r232}, [nvvm_tcgen05_st_16x64b_param_8+96];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r233, %r234, %r235, %r236}, [nvvm_tcgen05_st_16x64b_param_8+80];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r237, %r238, %r239, %r240}, [nvvm_tcgen05_st_16x64b_param_8+64];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r241, %r242, %r243, %r244}, [nvvm_tcgen05_st_16x64b_param_8+48];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r245, %r246, %r247, %r248}, [nvvm_tcgen05_st_16x64b_param_8+32];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r249, %r250, %r251, %r252}, [nvvm_tcgen05_st_16x64b_param_8+16];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r253, %r254, %r255, %r256}, [nvvm_tcgen05_st_16x64b_param_8];
; CHECK-NEXT: tcgen05.st.sync.aligned.16x64b.x128.b32 [%r1], {%r253, %r254, %r255, %r256, %r249, %r250, %r251, %r252, %r245, %r246, %r247, %r248, %r241, %r242, %r243, %r244, %r237, %r238, %r239, %r240, %r233, %r234, %r235, %r236, %r229, %r230, %r231, %r232, %r225, %r226, %r227, %r228, %r221, %r222, %r223, %r224, %r217, %r218, %r219, %r220, %r213, %r214, %r215, %r216, %r209, %r210, %r211, %r212, %r205, %r206, %r207, %r208, %r201, %r202, %r203, %r204, %r197, %r198, %r199, %r200, %r193, %r194, %r195, %r196, %r189, %r190, %r191, %r192, %r185, %r186, %r187, %r188, %r181, %r182, %r183, %r184, %r177, %r178, %r179, %r180, %r173, %r174, %r175, %r176, %r169, %r170, %r171, %r172, %r165, %r166, %r167, %r168, %r161, %r162, %r163, %r164, %r157, %r158, %r159, %r160, %r153, %r154, %r155, %r156, %r149, %r150, %r151, %r152, %r145, %r146, %r147, %r148, %r141, %r142, %r143, %r144, %r137, %r138, %r139, %r140, %r133, %r134, %r135, %r136, %r129, %r130, %r131, %r132};
; CHECK-NEXT: ret;
tail call void @llvm.nvvm.tcgen05.st.16x64b.x1(ptr addrspace(6) %taddr, <1 x i32> %stv1, i1 0)
@@ -117,79 +117,79 @@ define void @nvvm_tcgen05_st_16x64b_unpack(ptr addrspace(6) %taddr, <1 x i32> %s
; CHECK-NEXT: .reg .b32 %r<257>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [nvvm_tcgen05_st_16x64b_unpack_param_0];
-; CHECK-NEXT: ld.param.b32 %r2, [nvvm_tcgen05_st_16x64b_unpack_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r1, [nvvm_tcgen05_st_16x64b_unpack_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r2, [nvvm_tcgen05_st_16x64b_unpack_param_1];
; CHECK-NEXT: tcgen05.st.sync.aligned.16x64b.x1.unpack::16b.b32 [%r1], {%r2};
-; CHECK-NEXT: ld.param.v2.b32 {%r3, %r4}, [nvvm_tcgen05_st_16x64b_unpack_param_2];
+; CHECK-NEXT: ld.param::func.v2.b32 {%r3, %r4}, [nvvm_tcgen05_st_16x64b_unpack_param_2];
; CHECK-NEXT: tcgen05.st.sync.aligned.16x64b.x2.unpack::16b.b32 [%r1], {%r3, %r4};
-; CHECK-NEXT: ld.param.v4.b32 {%r5, %r6, %r7, %r8}, [nvvm_tcgen05_st_16x64b_unpack_param_3];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r5, %r6, %r7, %r8}, [nvvm_tcgen05_st_16x64b_unpack_param_3];
; CHECK-NEXT: tcgen05.st.sync.aligned.16x64b.x4.unpack::16b.b32 [%r1], {%r5, %r6, %r7, %r8};
-; CHECK-NEXT: ld.param.v4.b32 {%r9, %r10, %r11, %r12}, [nvvm_tcgen05_st_16x64b_unpack_param_4+16];
-; CHECK-NEXT: ld.param.v4.b32 {%r13, %r14, %r15, %r16}, [nvvm_tcgen05_st_16x64b_unpack_param_4];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r9, %r10, %r11, %r12}, [nvvm_tcgen05_st_16x64b_unpack_param_4+16];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r13, %r14, %r15, %r16}, [nvvm_tcgen05_st_16x64b_unpack_param_4];
; CHECK-NEXT: tcgen05.st.sync.aligned.16x64b.x8.unpack::16b.b32 [%r1], {%r13, %r14, %r15, %r16, %r9, %r10, %r11, %r12};
-; CHECK-NEXT: ld.param.v4.b32 {%r17, %r18, %r19, %r20}, [nvvm_tcgen05_st_16x64b_unpack_param_5+48];
-; CHECK-NEXT: ld.param.v4.b32 {%r21, %r22, %r23, %r24}, [nvvm_tcgen05_st_16x64b_unpack_param_5+32];
-; CHECK-NEXT: ld.param.v4.b32 {%r25, %r26, %r27, %r28}, [nvvm_tcgen05_st_16x64b_unpack_param_5+16];
-; CHECK-NEXT: ld.param.v4.b32 {%r29, %r30, %r31, %r32}, [nvvm_tcgen05_st_16x64b_unpack_param_5];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r17, %r18, %r19, %r20}, [nvvm_tcgen05_st_16x64b_unpack_param_5+48];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r21, %r22, %r23, %r24}, [nvvm_tcgen05_st_16x64b_unpack_param_5+32];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r25, %r26, %r27, %r28}, [nvvm_tcgen05_st_16x64b_unpack_param_5+16];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r29, %r30, %r31, %r32}, [nvvm_tcgen05_st_16x64b_unpack_param_5];
; CHECK-NEXT: tcgen05.st.sync.aligned.16x64b.x16.unpack::16b.b32 [%r1], {%r29, %r30, %r31, %r32, %r25, %r26, %r27, %r28, %r21, %r22, %r23, %r24, %r17, %r18, %r19, %r20};
-; CHECK-NEXT: ld.param.v4.b32 {%r33, %r34, %r35, %r36}, [nvvm_tcgen05_st_16x64b_unpack_param_6+112];
-; CHECK-NEXT: ld.param.v4.b32 {%r37, %r38, %r39, %r40}, [nvvm_tcgen05_st_16x64b_unpack_param_6+96];
-; CHECK-NEXT: ld.param.v4.b32 {%r41, %r42, %r43, %r44}, [nvvm_tcgen05_st_16x64b_unpack_param_6+80];
-; CHECK-NEXT: ld.param.v4.b32 {%r45, %r46, %r47, %r48}, [nvvm_tcgen05_st_16x64b_unpack_param_6+64];
-; CHECK-NEXT: ld.param.v4.b32 {%r49, %r50, %r51, %r52}, [nvvm_tcgen05_st_16x64b_unpack_param_6+48];
-; CHECK-NEXT: ld.param.v4.b32 {%r53, %r54, %r55, %r56}, [nvvm_tcgen05_st_16x64b_unpack_param_6+32];
-; CHECK-NEXT: ld.param.v4.b32 {%r57, %r58, %r59, %r60}, [nvvm_tcgen05_st_16x64b_unpack_param_6+16];
-; CHECK-NEXT: ld.param.v4.b32 {%r61, %r62, %r63, %r64}, [nvvm_tcgen05_st_16x64b_unpack_param_6];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r33, %r34, %r35, %r36}, [nvvm_tcgen05_st_16x64b_unpack_param_6+112];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r37, %r38, %r39, %r40}, [nvvm_tcgen05_st_16x64b_unpack_param_6+96];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r41, %r42, %r43, %r44}, [nvvm_tcgen05_st_16x64b_unpack_param_6+80];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r45, %r46, %r47, %r48}, [nvvm_tcgen05_st_16x64b_unpack_param_6+64];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r49, %r50, %r51, %r52}, [nvvm_tcgen05_st_16x64b_unpack_param_6+48];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r53, %r54, %r55, %r56}, [nvvm_tcgen05_st_16x64b_unpack_param_6+32];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r57, %r58, %r59, %r60}, [nvvm_tcgen05_st_16x64b_unpack_param_6+16];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r61, %r62, %r63, %r64}, [nvvm_tcgen05_st_16x64b_unpack_param_6];
; CHECK-NEXT: tcgen05.st.sync.aligned.16x64b.x32.unpack::16b.b32 [%r1], {%r61, %r62, %r63, %r64, %r57, %r58, %r59, %r60, %r53, %r54, %r55, %r56, %r49, %r50, %r51, %r52, %r45, %r46, %r47, %r48, %r41, %r42, %r43, %r44, %r37, %r38, %r39, %r40, %r33, %r34, %r35, %r36};
-; CHECK-NEXT: ld.param.v4.b32 {%r65, %r66, %r67, %r68}, [nvvm_tcgen05_st_16x64b_unpack_param_7+240];
-; CHECK-NEXT: ld.param.v4.b32 {%r69, %r70, %r71, %r72}, [nvvm_tcgen05_st_16x64b_unpack_param_7+224];
-; CHECK-NEXT: ld.param.v4.b32 {%r73, %r74, %r75, %r76}, [nvvm_tcgen05_st_16x64b_unpack_param_7+208];
-; CHECK-NEXT: ld.param.v4.b32 {%r77, %r78, %r79, %r80}, [nvvm_tcgen05_st_16x64b_unpack_param_7+192];
-; CHECK-NEXT: ld.param.v4.b32 {%r81, %r82, %r83, %r84}, [nvvm_tcgen05_st_16x64b_unpack_param_7+176];
-; CHECK-NEXT: ld.param.v4.b32 {%r85, %r86, %r87, %r88}, [nvvm_tcgen05_st_16x64b_unpack_param_7+160];
-; CHECK-NEXT: ld.param.v4.b32 {%r89, %r90, %r91, %r92}, [nvvm_tcgen05_st_16x64b_unpack_param_7+144];
-; CHECK-NEXT: ld.param.v4.b32 {%r93, %r94, %r95, %r96}, [nvvm_tcgen05_st_16x64b_unpack_param_7+128];
-; CHECK-NEXT: ld.param.v4.b32 {%r97, %r98, %r99, %r100}, [nvvm_tcgen05_st_16x64b_unpack_param_7+112];
-; CHECK-NEXT: ld.param.v4.b32 {%r101, %r102, %r103, %r104}, [nvvm_tcgen05_st_16x64b_unpack_param_7+96];
-; CHECK-NEXT: ld.param.v4.b32 {%r105, %r106, %r107, %r108}, [nvvm_tcgen05_st_16x64b_unpack_param_7+80];
-; CHECK-NEXT: ld.param.v4.b32 {%r109, %r110, %r111, %r112}, [nvvm_tcgen05_st_16x64b_unpack_param_7+64];
-; CHECK-NEXT: ld.param.v4.b32 {%r113, %r114, %r115, %r116}, [nvvm_tcgen05_st_16x64b_unpack_param_7+48];
-; CHECK-NEXT: ld.param.v4.b32 {%r117, %r118, %r119, %r120}, [nvvm_tcgen05_st_16x64b_unpack_param_7+32];
-; CHECK-NEXT: ld.param.v4.b32 {%r121, %r122, %r123, %r124}, [nvvm_tcgen05_st_16x64b_unpack_param_7+16];
-; CHECK-NEXT: ld.param.v4.b32 {%r125, %r126, %r127, %r128}, [nvvm_tcgen05_st_16x64b_unpack_param_7];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r65, %r66, %r67, %r68}, [nvvm_tcgen05_st_16x64b_unpack_param_7+240];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r69, %r70, %r71, %r72}, [nvvm_tcgen05_st_16x64b_unpack_param_7+224];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r73, %r74, %r75, %r76}, [nvvm_tcgen05_st_16x64b_unpack_param_7+208];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r77, %r78, %r79, %r80}, [nvvm_tcgen05_st_16x64b_unpack_param_7+192];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r81, %r82, %r83, %r84}, [nvvm_tcgen05_st_16x64b_unpack_param_7+176];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r85, %r86, %r87, %r88}, [nvvm_tcgen05_st_16x64b_unpack_param_7+160];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r89, %r90, %r91, %r92}, [nvvm_tcgen05_st_16x64b_unpack_param_7+144];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r93, %r94, %r95, %r96}, [nvvm_tcgen05_st_16x64b_unpack_param_7+128];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r97, %r98, %r99, %r100}, [nvvm_tcgen05_st_16x64b_unpack_param_7+112];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r101, %r102, %r103, %r104}, [nvvm_tcgen05_st_16x64b_unpack_param_7+96];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r105, %r106, %r107, %r108}, [nvvm_tcgen05_st_16x64b_unpack_param_7+80];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r109, %r110, %r111, %r112}, [nvvm_tcgen05_st_16x64b_unpack_param_7+64];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r113, %r114, %r115, %r116}, [nvvm_tcgen05_st_16x64b_unpack_param_7+48];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r117, %r118, %r119, %r120}, [nvvm_tcgen05_st_16x64b_unpack_param_7+32];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r121, %r122, %r123, %r124}, [nvvm_tcgen05_st_16x64b_unpack_param_7+16];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r125, %r126, %r127, %r128}, [nvvm_tcgen05_st_16x64b_unpack_param_7];
; CHECK-NEXT: tcgen05.st.sync.aligned.16x64b.x64.unpack::16b.b32 [%r1], {%r125, %r126, %r127, %r128, %r121, %r122, %r123, %r124, %r117, %r118, %r119, %r120, %r113, %r114, %r115, %r116, %r109, %r110, %r111, %r112, %r105, %r106, %r107, %r108, %r101, %r102, %r103, %r104, %r97, %r98, %r99, %r100, %r93, %r94, %r95, %r96, %r89, %r90, %r91, %r92, %r85, %r86, %r87, %r88, %r81, %r82, %r83, %r84, %r77, %r78, %r79, %r80, %r73, %r74, %r75, %r76, %r69, %r70, %r71, %r72, %r65, %r66, %r67, %r68};
-; CHECK-NEXT: ld.param.v4.b32 {%r129, %r130, %r131, %r132}, [nvvm_tcgen05_st_16x64b_unpack_param_8+496];
-; CHECK-NEXT: ld.param.v4.b32 {%r133, %r134, %r135, %r136}, [nvvm_tcgen05_st_16x64b_unpack_param_8+480];
-; CHECK-NEXT: ld.param.v4.b32 {%r137, %r138, %r139, %r140}, [nvvm_tcgen05_st_16x64b_unpack_param_8+464];
-; CHECK-NEXT: ld.param.v4.b32 {%r141, %r142, %r143, %r144}, [nvvm_tcgen05_st_16x64b_unpack_param_8+448];
-; CHECK-NEXT: ld.param.v4.b32 {%r145, %r146, %r147, %r148}, [nvvm_tcgen05_st_16x64b_unpack_param_8+432];
-; CHECK-NEXT: ld.param.v4.b32 {%r149, %r150, %r151, %r152}, [nvvm_tcgen05_st_16x64b_unpack_param_8+416];
-; CHECK-NEXT: ld.param.v4.b32 {%r153, %r154, %r155, %r156}, [nvvm_tcgen05_st_16x64b_unpack_param_8+400];
-; CHECK-NEXT: ld.param.v4.b32 {%r157, %r158, %r159, %r160}, [nvvm_tcgen05_st_16x64b_unpack_param_8+384];
-; CHECK-NEXT: ld.param.v4.b32 {%r161, %r162, %r163, %r164}, [nvvm_tcgen05_st_16x64b_unpack_param_8+368];
-; CHECK-NEXT: ld.param.v4.b32 {%r165, %r166, %r167, %r168}, [nvvm_tcgen05_st_16x64b_unpack_param_8+352];
-; CHECK-NEXT: ld.param.v4.b32 {%r169, %r170, %r171, %r172}, [nvvm_tcgen05_st_16x64b_unpack_param_8+336];
-; CHECK-NEXT: ld.param.v4.b32 {%r173, %r174, %r175, %r176}, [nvvm_tcgen05_st_16x64b_unpack_param_8+320];
-; CHECK-NEXT: ld.param.v4.b32 {%r177, %r178, %r179, %r180}, [nvvm_tcgen05_st_16x64b_unpack_param_8+304];
-; CHECK-NEXT: ld.param.v4.b32 {%r181, %r182, %r183, %r184}, [nvvm_tcgen05_st_16x64b_unpack_param_8+288];
-; CHECK-NEXT: ld.param.v4.b32 {%r185, %r186, %r187, %r188}, [nvvm_tcgen05_st_16x64b_unpack_param_8+272];
-; CHECK-NEXT: ld.param.v4.b32 {%r189, %r190, %r191, %r192}, [nvvm_tcgen05_st_16x64b_unpack_param_8+256];
-; CHECK-NEXT: ld.param.v4.b32 {%r193, %r194, %r195, %r196}, [nvvm_tcgen05_st_16x64b_unpack_param_8+240];
-; CHECK-NEXT: ld.param.v4.b32 {%r197, %r198, %r199, %r200}, [nvvm_tcgen05_st_16x64b_unpack_param_8+224];
-; CHECK-NEXT: ld.param.v4.b32 {%r201, %r202, %r203, %r204}, [nvvm_tcgen05_st_16x64b_unpack_param_8+208];
-; CHECK-NEXT: ld.param.v4.b32 {%r205, %r206, %r207, %r208}, [nvvm_tcgen05_st_16x64b_unpack_param_8+192];
-; CHECK-NEXT: ld.param.v4.b32 {%r209, %r210, %r211, %r212}, [nvvm_tcgen05_st_16x64b_unpack_param_8+176];
-; CHECK-NEXT: ld.param.v4.b32 {%r213, %r214, %r215, %r216}, [nvvm_tcgen05_st_16x64b_unpack_param_8+160];
-; CHECK-NEXT: ld.param.v4.b32 {%r217, %r218, %r219, %r220}, [nvvm_tcgen05_st_16x64b_unpack_param_8+144];
-; CHECK-NEXT: ld.param.v4.b32 {%r221, %r222, %r223, %r224}, [nvvm_tcgen05_st_16x64b_unpack_param_8+128];
-; CHECK-NEXT: ld.param.v4.b32 {%r225, %r226, %r227, %r228}, [nvvm_tcgen05_st_16x64b_unpack_param_8+112];
-; CHECK-NEXT: ld.param.v4.b32 {%r229, %r230, %r231, %r232}, [nvvm_tcgen05_st_16x64b_unpack_param_8+96];
-; CHECK-NEXT: ld.param.v4.b32 {%r233, %r234, %r235, %r236}, [nvvm_tcgen05_st_16x64b_unpack_param_8+80];
-; CHECK-NEXT: ld.param.v4.b32 {%r237, %r238, %r239, %r240}, [nvvm_tcgen05_st_16x64b_unpack_param_8+64];
-; CHECK-NEXT: ld.param.v4.b32 {%r241, %r242, %r243, %r244}, [nvvm_tcgen05_st_16x64b_unpack_param_8+48];
-; CHECK-NEXT: ld.param.v4.b32 {%r245, %r246, %r247, %r248}, [nvvm_tcgen05_st_16x64b_unpack_param_8+32];
-; CHECK-NEXT: ld.param.v4.b32 {%r249, %r250, %r251, %r252}, [nvvm_tcgen05_st_16x64b_unpack_param_8+16];
-; CHECK-NEXT: ld.param.v4.b32 {%r253, %r254, %r255, %r256}, [nvvm_tcgen05_st_16x64b_unpack_param_8];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r129, %r130, %r131, %r132}, [nvvm_tcgen05_st_16x64b_unpack_param_8+496];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r133, %r134, %r135, %r136}, [nvvm_tcgen05_st_16x64b_unpack_param_8+480];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r137, %r138, %r139, %r140}, [nvvm_tcgen05_st_16x64b_unpack_param_8+464];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r141, %r142, %r143, %r144}, [nvvm_tcgen05_st_16x64b_unpack_param_8+448];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r145, %r146, %r147, %r148}, [nvvm_tcgen05_st_16x64b_unpack_param_8+432];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r149, %r150, %r151, %r152}, [nvvm_tcgen05_st_16x64b_unpack_param_8+416];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r153, %r154, %r155, %r156}, [nvvm_tcgen05_st_16x64b_unpack_param_8+400];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r157, %r158, %r159, %r160}, [nvvm_tcgen05_st_16x64b_unpack_param_8+384];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r161, %r162, %r163, %r164}, [nvvm_tcgen05_st_16x64b_unpack_param_8+368];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r165, %r166, %r167, %r168}, [nvvm_tcgen05_st_16x64b_unpack_param_8+352];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r169, %r170, %r171, %r172}, [nvvm_tcgen05_st_16x64b_unpack_param_8+336];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r173, %r174, %r175, %r176}, [nvvm_tcgen05_st_16x64b_unpack_param_8+320];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r177, %r178, %r179, %r180}, [nvvm_tcgen05_st_16x64b_unpack_param_8+304];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r181, %r182, %r183, %r184}, [nvvm_tcgen05_st_16x64b_unpack_param_8+288];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r185, %r186, %r187, %r188}, [nvvm_tcgen05_st_16x64b_unpack_param_8+272];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r189, %r190, %r191, %r192}, [nvvm_tcgen05_st_16x64b_unpack_param_8+256];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r193, %r194, %r195, %r196}, [nvvm_tcgen05_st_16x64b_unpack_param_8+240];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r197, %r198, %r199, %r200}, [nvvm_tcgen05_st_16x64b_unpack_param_8+224];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r201, %r202, %r203, %r204}, [nvvm_tcgen05_st_16x64b_unpack_param_8+208];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r205, %r206, %r207, %r208}, [nvvm_tcgen05_st_16x64b_unpack_param_8+192];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r209, %r210, %r211, %r212}, [nvvm_tcgen05_st_16x64b_unpack_param_8+176];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r213, %r214, %r215, %r216}, [nvvm_tcgen05_st_16x64b_unpack_param_8+160];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r217, %r218, %r219, %r220}, [nvvm_tcgen05_st_16x64b_unpack_param_8+144];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r221, %r222, %r223, %r224}, [nvvm_tcgen05_st_16x64b_unpack_param_8+128];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r225, %r226, %r227, %r228}, [nvvm_tcgen05_st_16x64b_unpack_param_8+112];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r229, %r230, %r231, %r232}, [nvvm_tcgen05_st_16x64b_unpack_param_8+96];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r233, %r234, %r235, %r236}, [nvvm_tcgen05_st_16x64b_unpack_param_8+80];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r237, %r238, %r239, %r240}, [nvvm_tcgen05_st_16x64b_unpack_param_8+64];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r241, %r242, %r243, %r244}, [nvvm_tcgen05_st_16x64b_unpack_param_8+48];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r245, %r246, %r247, %r248}, [nvvm_tcgen05_st_16x64b_unpack_param_8+32];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r249, %r250, %r251, %r252}, [nvvm_tcgen05_st_16x64b_unpack_param_8+16];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r253, %r254, %r255, %r256}, [nvvm_tcgen05_st_16x64b_unpack_param_8];
; CHECK-NEXT: tcgen05.st.sync.aligned.16x64b.x128.unpack::16b.b32 [%r1], {%r253, %r254, %r255, %r256, %r249, %r250, %r251, %r252, %r245, %r246, %r247, %r248, %r241, %r242, %r243, %r244, %r237, %r238, %r239, %r240, %r233, %r234, %r235, %r236, %r229, %r230, %r231, %r232, %r225, %r226, %r227, %r228, %r221, %r222, %r223, %r224, %r217, %r218, %r219, %r220, %r213, %r214, %r215, %r216, %r209, %r210, %r211, %r212, %r205, %r206, %r207, %r208, %r201, %r202, %r203, %r204, %r197, %r198, %r199, %r200, %r193, %r194, %r195, %r196, %r189, %r190, %r191, %r192, %r185, %r186, %r187, %r188, %r181, %r182, %r183, %r184, %r177, %r178, %r179, %r180, %r173, %r174, %r175, %r176, %r169, %r170, %r171, %r172, %r165, %r166, %r167, %r168, %r161, %r162, %r163, %r164, %r157, %r158, %r159, %r160, %r153, %r154, %r155, %r156, %r149, %r150, %r151, %r152, %r145, %r146, %r147, %r148, %r141, %r142, %r143, %r144, %r137, %r138, %r139, %r140, %r133, %r134, %r135, %r136, %r129, %r130, %r131, %r132};
; CHECK-NEXT: ret;
tail call void @llvm.nvvm.tcgen05.st.16x64b.x1(ptr addrspace(6) %taddr, <1 x i32> %stv1, i1 1)
@@ -217,77 +217,77 @@ define void @nvvm_tcgen05_st_16x128b(ptr addrspace(6) %taddr, <1 x i32> %stv1, <
; CHECK-NEXT: .reg .b32 %r<256>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [nvvm_tcgen05_st_16x128b_param_0];
-; CHECK-NEXT: ld.param.v2.b32 {%r2, %r3}, [nvvm_tcgen05_st_16x128b_param_2];
+; CHECK-NEXT: ld.param::func.b32 %r1, [nvvm_tcgen05_st_16x128b_param_0];
+; CHECK-NEXT: ld.param::func.v2.b32 {%r2, %r3}, [nvvm_tcgen05_st_16x128b_param_2];
; CHECK-NEXT: tcgen05.st.sync.aligned.16x128b.x1.b32 [%r1], {%r2, %r3};
-; CHECK-NEXT: ld.param.v4.b32 {%r4, %r5, %r6, %r7}, [nvvm_tcgen05_st_16x128b_param_3];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r4, %r5, %r6, %r7}, [nvvm_tcgen05_st_16x128b_param_3];
; CHECK-NEXT: tcgen05.st.sync.aligned.16x128b.x2.b32 [%r1], {%r4, %r5, %r6, %r7};
-; CHECK-NEXT: ld.param.v4.b32 {%r8, %r9, %r10, %r11}, [nvvm_tcgen05_st_16x128b_param_4+16];
-; CHECK-NEXT: ld.param.v4.b32 {%r12, %r13, %r14, %r15}, [nvvm_tcgen05_st_16x128b_param_4];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r8, %r9, %r10, %r11}, [nvvm_tcgen05_st_16x128b_param_4+16];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r12, %r13, %r14, %r15}, [nvvm_tcgen05_st_16x128b_param_4];
; CHECK-NEXT: tcgen05.st.sync.aligned.16x128b.x4.b32 [%r1], {%r12, %r13, %r14, %r15, %r8, %r9, %r10, %r11};
-; CHECK-NEXT: ld.param.v4.b32 {%r16, %r17, %r18, %r19}, [nvvm_tcgen05_st_16x128b_param_5+48];
-; CHECK-NEXT: ld.param.v4.b32 {%r20, %r21, %r22, %r23}, [nvvm_tcgen05_st_16x128b_param_5+32];
-; CHECK-NEXT: ld.param.v4.b32 {%r24, %r25, %r26, %r27}, [nvvm_tcgen05_st_16x128b_param_5+16];
-; CHECK-NEXT: ld.param.v4.b32 {%r28, %r29, %r30, %r31}, [nvvm_tcgen05_st_16x128b_param_5];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r16, %r17, %r18, %r19}, [nvvm_tcgen05_st_16x128b_param_5+48];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r20, %r21, %r22, %r23}, [nvvm_tcgen05_st_16x128b_param_5+32];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r24, %r25, %r26, %r27}, [nvvm_tcgen05_st_16x128b_param_5+16];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r28, %r29, %r30, %r31}, [nvvm_tcgen05_st_16x128b_param_5];
; CHECK-NEXT: tcgen05.st.sync.aligned.16x128b.x8.b32 [%r1], {%r28, %r29, %r30, %r31, %r24, %r25, %r26, %r27, %r20, %r21, %r22, %r23, %r16, %r17, %r18, %r19};
-; CHECK-NEXT: ld.param.v4.b32 {%r32, %r33, %r34, %r35}, [nvvm_tcgen05_st_16x128b_param_6+112];
-; CHECK-NEXT: ld.param.v4.b32 {%r36, %r37, %r38, %r39}, [nvvm_tcgen05_st_16x128b_param_6+96];
-; CHECK-NEXT: ld.param.v4.b32 {%r40, %r41, %r42, %r43}, [nvvm_tcgen05_st_16x128b_param_6+80];
-; CHECK-NEXT: ld.param.v4.b32 {%r44, %r45, %r46, %r47}, [nvvm_tcgen05_st_16x128b_param_6+64];
-; CHECK-NEXT: ld.param.v4.b32 {%r48, %r49, %r50, %r51}, [nvvm_tcgen05_st_16x128b_param_6+48];
-; CHECK-NEXT: ld.param.v4.b32 {%r52, %r53, %r54, %r55}, [nvvm_tcgen05_st_16x128b_param_6+32];
-; CHECK-NEXT: ld.param.v4.b32 {%r56, %r57, %r58, %r59}, [nvvm_tcgen05_st_16x128b_param_6+16];
-; CHECK-NEXT: ld.param.v4.b32 {%r60, %r61, %r62, %r63}, [nvvm_tcgen05_st_16x128b_param_6];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r32, %r33, %r34, %r35}, [nvvm_tcgen05_st_16x128b_param_6+112];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r36, %r37, %r38, %r39}, [nvvm_tcgen05_st_16x128b_param_6+96];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r40, %r41, %r42, %r43}, [nvvm_tcgen05_st_16x128b_param_6+80];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r44, %r45, %r46, %r47}, [nvvm_tcgen05_st_16x128b_param_6+64];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r48, %r49, %r50, %r51}, [nvvm_tcgen05_st_16x128b_param_6+48];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r52, %r53, %r54, %r55}, [nvvm_tcgen05_st_16x128b_param_6+32];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r56, %r57, %r58, %r59}, [nvvm_tcgen05_st_16x128b_param_6+16];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r60, %r61, %r62, %r63}, [nvvm_tcgen05_st_16x128b_param_6];
; CHECK-NEXT: tcgen05.st.sync.aligned.16x128b.x16.b32 [%r1], {%r60, %r61, %r62, %r63, %r56, %r57, %r58, %r59, %r52, %r53, %r54, %r55, %r48, %r49, %r50, %r51, %r44, %r45, %r46, %r47, %r40, %r41, %r42, %r43, %r36, %r37, %r38, %r39, %r32, %r33, %r34, %r35};
-; CHECK-NEXT: ld.param.v4.b32 {%r64, %r65, %r66, %r67}, [nvvm_tcgen05_st_16x128b_param_7+240];
-; CHECK-NEXT: ld.param.v4.b32 {%r68, %r69, %r70, %r71}, [nvvm_tcgen05_st_16x128b_param_7+224];
-; CHECK-NEXT: ld.param.v4.b32 {%r72, %r73, %r74, %r75}, [nvvm_tcgen05_st_16x128b_param_7+208];
-; CHECK-NEXT: ld.param.v4.b32 {%r76, %r77, %r78, %r79}, [nvvm_tcgen05_st_16x128b_param_7+192];
-; CHECK-NEXT: ld.param.v4.b32 {%r80, %r81, %r82, %r83}, [nvvm_tcgen05_st_16x128b_param_7+176];
-; CHECK-NEXT: ld.param.v4.b32 {%r84, %r85, %r86, %r87}, [nvvm_tcgen05_st_16x128b_param_7+160];
-; CHECK-NEXT: ld.param.v4.b32 {%r88, %r89, %r90, %r91}, [nvvm_tcgen05_st_16x128b_param_7+144];
-; CHECK-NEXT: ld.param.v4.b32 {%r92, %r93, %r94, %r95}, [nvvm_tcgen05_st_16x128b_param_7+128];
-; CHECK-NEXT: ld.param.v4.b32 {%r96, %r97, %r98, %r99}, [nvvm_tcgen05_st_16x128b_param_7+112];
-; CHECK-NEXT: ld.param.v4.b32 {%r100, %r101, %r102, %r103}, [nvvm_tcgen05_st_16x128b_param_7+96];
-; CHECK-NEXT: ld.param.v4.b32 {%r104, %r105, %r106, %r107}, [nvvm_tcgen05_st_16x128b_param_7+80];
-; CHECK-NEXT: ld.param.v4.b32 {%r108, %r109, %r110, %r111}, [nvvm_tcgen05_st_16x128b_param_7+64];
-; CHECK-NEXT: ld.param.v4.b32 {%r112, %r113, %r114, %r115}, [nvvm_tcgen05_st_16x128b_param_7+48];
-; CHECK-NEXT: ld.param.v4.b32 {%r116, %r117, %r118, %r119}, [nvvm_tcgen05_st_16x128b_param_7+32];
-; CHECK-NEXT: ld.param.v4.b32 {%r120, %r121, %r122, %r123}, [nvvm_tcgen05_st_16x128b_param_7+16];
-; CHECK-NEXT: ld.param.v4.b32 {%r124, %r125, %r126, %r127}, [nvvm_tcgen05_st_16x128b_param_7];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r64, %r65, %r66, %r67}, [nvvm_tcgen05_st_16x128b_param_7+240];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r68, %r69, %r70, %r71}, [nvvm_tcgen05_st_16x128b_param_7+224];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r72, %r73, %r74, %r75}, [nvvm_tcgen05_st_16x128b_param_7+208];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r76, %r77, %r78, %r79}, [nvvm_tcgen05_st_16x128b_param_7+192];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r80, %r81, %r82, %r83}, [nvvm_tcgen05_st_16x128b_param_7+176];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r84, %r85, %r86, %r87}, [nvvm_tcgen05_st_16x128b_param_7+160];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r88, %r89, %r90, %r91}, [nvvm_tcgen05_st_16x128b_param_7+144];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r92, %r93, %r94, %r95}, [nvvm_tcgen05_st_16x128b_param_7+128];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r96, %r97, %r98, %r99}, [nvvm_tcgen05_st_16x128b_param_7+112];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r100, %r101, %r102, %r103}, [nvvm_tcgen05_st_16x128b_param_7+96];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r104, %r105, %r106, %r107}, [nvvm_tcgen05_st_16x128b_param_7+80];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r108, %r109, %r110, %r111}, [nvvm_tcgen05_st_16x128b_param_7+64];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r112, %r113, %r114, %r115}, [nvvm_tcgen05_st_16x128b_param_7+48];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r116, %r117, %r118, %r119}, [nvvm_tcgen05_st_16x128b_param_7+32];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r120, %r121, %r122, %r123}, [nvvm_tcgen05_st_16x128b_param_7+16];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r124, %r125, %r126, %r127}, [nvvm_tcgen05_st_16x128b_param_7];
; CHECK-NEXT: tcgen05.st.sync.aligned.16x128b.x32.b32 [%r1], {%r124, %r125, %r126, %r127, %r120, %r121, %r122, %r123, %r116, %r117, %r118, %r119, %r112, %r113, %r114, %r115, %r108, %r109, %r110, %r111, %r104, %r105, %r106, %r107, %r100, %r101, %r102, %r103, %r96, %r97, %r98, %r99, %r92, %r93, %r94, %r95, %r88, %r89, %r90, %r91, %r84, %r85, %r86, %r87, %r80, %r81, %r82, %r83, %r76, %r77, %r78, %r79, %r72, %r73, %r74, %r75, %r68, %r69, %r70, %r71, %r64, %r65, %r66, %r67};
-; CHECK-NEXT: ld.param.v4.b32 {%r128, %r129, %r130, %r131}, [nvvm_tcgen05_st_16x128b_param_8+496];
-; CHECK-NEXT: ld.param.v4.b32 {%r132, %r133, %r134, %r135}, [nvvm_tcgen05_st_16x128b_param_8+480];
-; CHECK-NEXT: ld.param.v4.b32 {%r136, %r137, %r138, %r139}, [nvvm_tcgen05_st_16x128b_param_8+464];
-; CHECK-NEXT: ld.param.v4.b32 {%r140, %r141, %r142, %r143}, [nvvm_tcgen05_st_16x128b_param_8+448];
-; CHECK-NEXT: ld.param.v4.b32 {%r144, %r145, %r146, %r147}, [nvvm_tcgen05_st_16x128b_param_8+432];
-; CHECK-NEXT: ld.param.v4.b32 {%r148, %r149, %r150, %r151}, [nvvm_tcgen05_st_16x128b_param_8+416];
-; CHECK-NEXT: ld.param.v4.b32 {%r152, %r153, %r154, %r155}, [nvvm_tcgen05_st_16x128b_param_8+400];
-; CHECK-NEXT: ld.param.v4.b32 {%r156, %r157, %r158, %r159}, [nvvm_tcgen05_st_16x128b_param_8+384];
-; CHECK-NEXT: ld.param.v4.b32 {%r160, %r161, %r162, %r163}, [nvvm_tcgen05_st_16x128b_param_8+368];
-; CHECK-NEXT: ld.param.v4.b32 {%r164, %r165, %r166, %r167}, [nvvm_tcgen05_st_16x128b_param_8+352];
-; CHECK-NEXT: ld.param.v4.b32 {%r168, %r169, %r170, %r171}, [nvvm_tcgen05_st_16x128b_param_8+336];
-; CHECK-NEXT: ld.param.v4.b32 {%r172, %r173, %r174, %r175}, [nvvm_tcgen05_st_16x128b_param_8+320];
-; CHECK-NEXT: ld.param.v4.b32 {%r176, %r177, %r178, %r179}, [nvvm_tcgen05_st_16x128b_param_8+304];
-; CHECK-NEXT: ld.param.v4.b32 {%r180, %r181, %r182, %r183}, [nvvm_tcgen05_st_16x128b_param_8+288];
-; CHECK-NEXT: ld.param.v4.b32 {%r184, %r185, %r186, %r187}, [nvvm_tcgen05_st_16x128b_param_8+272];
-; CHECK-NEXT: ld.param.v4.b32 {%r188, %r189, %r190, %r191}, [nvvm_tcgen05_st_16x128b_param_8+256];
-; CHECK-NEXT: ld.param.v4.b32 {%r192, %r193, %r194, %r195}, [nvvm_tcgen05_st_16x128b_param_8+240];
-; CHECK-NEXT: ld.param.v4.b32 {%r196, %r197, %r198, %r199}, [nvvm_tcgen05_st_16x128b_param_8+224];
-; CHECK-NEXT: ld.param.v4.b32 {%r200, %r201, %r202, %r203}, [nvvm_tcgen05_st_16x128b_param_8+208];
-; CHECK-NEXT: ld.param.v4.b32 {%r204, %r205, %r206, %r207}, [nvvm_tcgen05_st_16x128b_param_8+192];
-; CHECK-NEXT: ld.param.v4.b32 {%r208, %r209, %r210, %r211}, [nvvm_tcgen05_st_16x128b_param_8+176];
-; CHECK-NEXT: ld.param.v4.b32 {%r212, %r213, %r214, %r215}, [nvvm_tcgen05_st_16x128b_param_8+160];
-; CHECK-NEXT: ld.param.v4.b32 {%r216, %r217, %r218, %r219}, [nvvm_tcgen05_st_16x128b_param_8+144];
-; CHECK-NEXT: ld.param.v4.b32 {%r220, %r221, %r222, %r223}, [nvvm_tcgen05_st_16x128b_param_8+128];
-; CHECK-NEXT: ld.param.v4.b32 {%r224, %r225, %r226, %r227}, [nvvm_tcgen05_st_16x128b_param_8+112];
-; CHECK-NEXT: ld.param.v4.b32 {%r228, %r229, %r230, %r231}, [nvvm_tcgen05_st_16x128b_param_8+96];
-; CHECK-NEXT: ld.param.v4.b32 {%r232, %r233, %r234, %r235}, [nvvm_tcgen05_st_16x128b_param_8+80];
-; CHECK-NEXT: ld.param.v4.b32 {%r236, %r237, %r238, %r239}, [nvvm_tcgen05_st_16x128b_param_8+64];
-; CHECK-NEXT: ld.param.v4.b32 {%r240, %r241, %r242, %r243}, [nvvm_tcgen05_st_16x128b_param_8+48];
-; CHECK-NEXT: ld.param.v4.b32 {%r244, %r245, %r246, %r247}, [nvvm_tcgen05_st_16x128b_param_8+32];
-; CHECK-NEXT: ld.param.v4.b32 {%r248, %r249, %r250, %r251}, [nvvm_tcgen05_st_16x128b_param_8+16];
-; CHECK-NEXT: ld.param.v4.b32 {%r252, %r253, %r254, %r255}, [nvvm_tcgen05_st_16x128b_param_8];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r128, %r129, %r130, %r131}, [nvvm_tcgen05_st_16x128b_param_8+496];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r132, %r133, %r134, %r135}, [nvvm_tcgen05_st_16x128b_param_8+480];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r136, %r137, %r138, %r139}, [nvvm_tcgen05_st_16x128b_param_8+464];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r140, %r141, %r142, %r143}, [nvvm_tcgen05_st_16x128b_param_8+448];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r144, %r145, %r146, %r147}, [nvvm_tcgen05_st_16x128b_param_8+432];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r148, %r149, %r150, %r151}, [nvvm_tcgen05_st_16x128b_param_8+416];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r152, %r153, %r154, %r155}, [nvvm_tcgen05_st_16x128b_param_8+400];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r156, %r157, %r158, %r159}, [nvvm_tcgen05_st_16x128b_param_8+384];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r160, %r161, %r162, %r163}, [nvvm_tcgen05_st_16x128b_param_8+368];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r164, %r165, %r166, %r167}, [nvvm_tcgen05_st_16x128b_param_8+352];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r168, %r169, %r170, %r171}, [nvvm_tcgen05_st_16x128b_param_8+336];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r172, %r173, %r174, %r175}, [nvvm_tcgen05_st_16x128b_param_8+320];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r176, %r177, %r178, %r179}, [nvvm_tcgen05_st_16x128b_param_8+304];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r180, %r181, %r182, %r183}, [nvvm_tcgen05_st_16x128b_param_8+288];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r184, %r185, %r186, %r187}, [nvvm_tcgen05_st_16x128b_param_8+272];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r188, %r189, %r190, %r191}, [nvvm_tcgen05_st_16x128b_param_8+256];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r192, %r193, %r194, %r195}, [nvvm_tcgen05_st_16x128b_param_8+240];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r196, %r197, %r198, %r199}, [nvvm_tcgen05_st_16x128b_param_8+224];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r200, %r201, %r202, %r203}, [nvvm_tcgen05_st_16x128b_param_8+208];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r204, %r205, %r206, %r207}, [nvvm_tcgen05_st_16x128b_param_8+192];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r208, %r209, %r210, %r211}, [nvvm_tcgen05_st_16x128b_param_8+176];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r212, %r213, %r214, %r215}, [nvvm_tcgen05_st_16x128b_param_8+160];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r216, %r217, %r218, %r219}, [nvvm_tcgen05_st_16x128b_param_8+144];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r220, %r221, %r222, %r223}, [nvvm_tcgen05_st_16x128b_param_8+128];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r224, %r225, %r226, %r227}, [nvvm_tcgen05_st_16x128b_param_8+112];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r228, %r229, %r230, %r231}, [nvvm_tcgen05_st_16x128b_param_8+96];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r232, %r233, %r234, %r235}, [nvvm_tcgen05_st_16x128b_param_8+80];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r236, %r237, %r238, %r239}, [nvvm_tcgen05_st_16x128b_param_8+64];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r240, %r241, %r242, %r243}, [nvvm_tcgen05_st_16x128b_param_8+48];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r244, %r245, %r246, %r247}, [nvvm_tcgen05_st_16x128b_param_8+32];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r248, %r249, %r250, %r251}, [nvvm_tcgen05_st_16x128b_param_8+16];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r252, %r253, %r254, %r255}, [nvvm_tcgen05_st_16x128b_param_8];
; CHECK-NEXT: tcgen05.st.sync.aligned.16x128b.x64.b32 [%r1], {%r252, %r253, %r254, %r255, %r248, %r249, %r250, %r251, %r244, %r245, %r246, %r247, %r240, %r241, %r242, %r243, %r236, %r237, %r238, %r239, %r232, %r233, %r234, %r235, %r228, %r229, %r230, %r231, %r224, %r225, %r226, %r227, %r220, %r221, %r222, %r223, %r216, %r217, %r218, %r219, %r212, %r213, %r214, %r215, %r208, %r209, %r210, %r211, %r204, %r205, %r206, %r207, %r200, %r201, %r202, %r203, %r196, %r197, %r198, %r199, %r192, %r193, %r194, %r195, %r188, %r189, %r190, %r191, %r184, %r185, %r186, %r187, %r180, %r181, %r182, %r183, %r176, %r177, %r178, %r179, %r172, %r173, %r174, %r175, %r168, %r169, %r170, %r171, %r164, %r165, %r166, %r167, %r160, %r161, %r162, %r163, %r156, %r157, %r158, %r159, %r152, %r153, %r154, %r155, %r148, %r149, %r150, %r151, %r144, %r145, %r146, %r147, %r140, %r141, %r142, %r143, %r136, %r137, %r138, %r139, %r132, %r133, %r134, %r135, %r128, %r129, %r130, %r131};
; CHECK-NEXT: ret;
tail call void @llvm.nvvm.tcgen05.st.16x128b.x1(ptr addrspace(6) %taddr, <2 x i32> %stv2, i1 0)
@@ -313,77 +313,77 @@ define void @nvvm_tcgen05_st_16x128b_unpack(ptr addrspace(6) %taddr, <1 x i32> %
; CHECK-NEXT: .reg .b32 %r<256>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [nvvm_tcgen05_st_16x128b_unpack_param_0];
-; CHECK-NEXT: ld.param.v2.b32 {%r2, %r3}, [nvvm_tcgen05_st_16x128b_unpack_param_2];
+; CHECK-NEXT: ld.param::func.b32 %r1, [nvvm_tcgen05_st_16x128b_unpack_param_0];
+; CHECK-NEXT: ld.param::func.v2.b32 {%r2, %r3}, [nvvm_tcgen05_st_16x128b_unpack_param_2];
; CHECK-NEXT: tcgen05.st.sync.aligned.16x128b.x1.unpack::16b.b32 [%r1], {%r2, %r3};
-; CHECK-NEXT: ld.param.v4.b32 {%r4, %r5, %r6, %r7}, [nvvm_tcgen05_st_16x128b_unpack_param_3];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r4, %r5, %r6, %r7}, [nvvm_tcgen05_st_16x128b_unpack_param_3];
; CHECK-NEXT: tcgen05.st.sync.aligned.16x128b.x2.unpack::16b.b32 [%r1], {%r4, %r5, %r6, %r7};
-; CHECK-NEXT: ld.param.v4.b32 {%r8, %r9, %r10, %r11}, [nvvm_tcgen05_st_16x128b_unpack_param_4+16];
-; CHECK-NEXT: ld.param.v4.b32 {%r12, %r13, %r14, %r15}, [nvvm_tcgen05_st_16x128b_unpack_param_4];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r8, %r9, %r10, %r11}, [nvvm_tcgen05_st_16x128b_unpack_param_4+16];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r12, %r13, %r14, %r15}, [nvvm_tcgen05_st_16x128b_unpack_param_4];
; CHECK-NEXT: tcgen05.st.sync.aligned.16x128b.x4.unpack::16b.b32 [%r1], {%r12, %r13, %r14, %r15, %r8, %r9, %r10, %r11};
-; CHECK-NEXT: ld.param.v4.b32 {%r16, %r17, %r18, %r19}, [nvvm_tcgen05_st_16x128b_unpack_param_5+48];
-; CHECK-NEXT: ld.param.v4.b32 {%r20, %r21, %r22, %r23}, [nvvm_tcgen05_st_16x128b_unpack_param_5+32];
-; CHECK-NEXT: ld.param.v4.b32 {%r24, %r25, %r26, %r27}, [nvvm_tcgen05_st_16x128b_unpack_param_5+16];
-; CHECK-NEXT: ld.param.v4.b32 {%r28, %r29, %r30, %r31}, [nvvm_tcgen05_st_16x128b_unpack_param_5];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r16, %r17, %r18, %r19}, [nvvm_tcgen05_st_16x128b_unpack_param_5+48];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r20, %r21, %r22, %r23}, [nvvm_tcgen05_st_16x128b_unpack_param_5+32];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r24, %r25, %r26, %r27}, [nvvm_tcgen05_st_16x128b_unpack_param_5+16];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r28, %r29, %r30, %r31}, [nvvm_tcgen05_st_16x128b_unpack_param_5];
; CHECK-NEXT: tcgen05.st.sync.aligned.16x128b.x8.unpack::16b.b32 [%r1], {%r28, %r29, %r30, %r31, %r24, %r25, %r26, %r27, %r20, %r21, %r22, %r23, %r16, %r17, %r18, %r19};
-; CHECK-NEXT: ld.param.v4.b32 {%r32, %r33, %r34, %r35}, [nvvm_tcgen05_st_16x128b_unpack_param_6+112];
-; CHECK-NEXT: ld.param.v4.b32 {%r36, %r37, %r38, %r39}, [nvvm_tcgen05_st_16x128b_unpack_param_6+96];
-; CHECK-NEXT: ld.param.v4.b32 {%r40, %r41, %r42, %r43}, [nvvm_tcgen05_st_16x128b_unpack_param_6+80];
-; CHECK-NEXT: ld.param.v4.b32 {%r44, %r45, %r46, %r47}, [nvvm_tcgen05_st_16x128b_unpack_param_6+64];
-; CHECK-NEXT: ld.param.v4.b32 {%r48, %r49, %r50, %r51}, [nvvm_tcgen05_st_16x128b_unpack_param_6+48];
-; CHECK-NEXT: ld.param.v4.b32 {%r52, %r53, %r54, %r55}, [nvvm_tcgen05_st_16x128b_unpack_param_6+32];
-; CHECK-NEXT: ld.param.v4.b32 {%r56, %r57, %r58, %r59}, [nvvm_tcgen05_st_16x128b_unpack_param_6+16];
-; CHECK-NEXT: ld.param.v4.b32 {%r60, %r61, %r62, %r63}, [nvvm_tcgen05_st_16x128b_unpack_param_6];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r32, %r33, %r34, %r35}, [nvvm_tcgen05_st_16x128b_unpack_param_6+112];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r36, %r37, %r38, %r39}, [nvvm_tcgen05_st_16x128b_unpack_param_6+96];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r40, %r41, %r42, %r43}, [nvvm_tcgen05_st_16x128b_unpack_param_6+80];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r44, %r45, %r46, %r47}, [nvvm_tcgen05_st_16x128b_unpack_param_6+64];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r48, %r49, %r50, %r51}, [nvvm_tcgen05_st_16x128b_unpack_param_6+48];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r52, %r53, %r54, %r55}, [nvvm_tcgen05_st_16x128b_unpack_param_6+32];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r56, %r57, %r58, %r59}, [nvvm_tcgen05_st_16x128b_unpack_param_6+16];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r60, %r61, %r62, %r63}, [nvvm_tcgen05_st_16x128b_unpack_param_6];
; CHECK-NEXT: tcgen05.st.sync.aligned.16x128b.x16.unpack::16b.b32 [%r1], {%r60, %r61, %r62, %r63, %r56, %r57, %r58, %r59, %r52, %r53, %r54, %r55, %r48, %r49, %r50, %r51, %r44, %r45, %r46, %r47, %r40, %r41, %r42, %r43, %r36, %r37, %r38, %r39, %r32, %r33, %r34, %r35};
-; CHECK-NEXT: ld.param.v4.b32 {%r64, %r65, %r66, %r67}, [nvvm_tcgen05_st_16x128b_unpack_param_7+240];
-; CHECK-NEXT: ld.param.v4.b32 {%r68, %r69, %r70, %r71}, [nvvm_tcgen05_st_16x128b_unpack_param_7+224];
-; CHECK-NEXT: ld.param.v4.b32 {%r72, %r73, %r74, %r75}, [nvvm_tcgen05_st_16x128b_unpack_param_7+208];
-; CHECK-NEXT: ld.param.v4.b32 {%r76, %r77, %r78, %r79}, [nvvm_tcgen05_st_16x128b_unpack_param_7+192];
-; CHECK-NEXT: ld.param.v4.b32 {%r80, %r81, %r82, %r83}, [nvvm_tcgen05_st_16x128b_unpack_param_7+176];
-; CHECK-NEXT: ld.param.v4.b32 {%r84, %r85, %r86, %r87}, [nvvm_tcgen05_st_16x128b_unpack_param_7+160];
-; CHECK-NEXT: ld.param.v4.b32 {%r88, %r89, %r90, %r91}, [nvvm_tcgen05_st_16x128b_unpack_param_7+144];
-; CHECK-NEXT: ld.param.v4.b32 {%r92, %r93, %r94, %r95}, [nvvm_tcgen05_st_16x128b_unpack_param_7+128];
-; CHECK-NEXT: ld.param.v4.b32 {%r96, %r97, %r98, %r99}, [nvvm_tcgen05_st_16x128b_unpack_param_7+112];
-; CHECK-NEXT: ld.param.v4.b32 {%r100, %r101, %r102, %r103}, [nvvm_tcgen05_st_16x128b_unpack_param_7+96];
-; CHECK-NEXT: ld.param.v4.b32 {%r104, %r105, %r106, %r107}, [nvvm_tcgen05_st_16x128b_unpack_param_7+80];
-; CHECK-NEXT: ld.param.v4.b32 {%r108, %r109, %r110, %r111}, [nvvm_tcgen05_st_16x128b_unpack_param_7+64];
-; CHECK-NEXT: ld.param.v4.b32 {%r112, %r113, %r114, %r115}, [nvvm_tcgen05_st_16x128b_unpack_param_7+48];
-; CHECK-NEXT: ld.param.v4.b32 {%r116, %r117, %r118, %r119}, [nvvm_tcgen05_st_16x128b_unpack_param_7+32];
-; CHECK-NEXT: ld.param.v4.b32 {%r120, %r121, %r122, %r123}, [nvvm_tcgen05_st_16x128b_unpack_param_7+16];
-; CHECK-NEXT: ld.param.v4.b32 {%r124, %r125, %r126, %r127}, [nvvm_tcgen05_st_16x128b_unpack_param_7];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r64, %r65, %r66, %r67}, [nvvm_tcgen05_st_16x128b_unpack_param_7+240];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r68, %r69, %r70, %r71}, [nvvm_tcgen05_st_16x128b_unpack_param_7+224];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r72, %r73, %r74, %r75}, [nvvm_tcgen05_st_16x128b_unpack_param_7+208];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r76, %r77, %r78, %r79}, [nvvm_tcgen05_st_16x128b_unpack_param_7+192];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r80, %r81, %r82, %r83}, [nvvm_tcgen05_st_16x128b_unpack_param_7+176];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r84, %r85, %r86, %r87}, [nvvm_tcgen05_st_16x128b_unpack_param_7+160];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r88, %r89, %r90, %r91}, [nvvm_tcgen05_st_16x128b_unpack_param_7+144];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r92, %r93, %r94, %r95}, [nvvm_tcgen05_st_16x128b_unpack_param_7+128];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r96, %r97, %r98, %r99}, [nvvm_tcgen05_st_16x128b_unpack_param_7+112];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r100, %r101, %r102, %r103}, [nvvm_tcgen05_st_16x128b_unpack_param_7+96];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r104, %r105, %r106, %r107}, [nvvm_tcgen05_st_16x128b_unpack_param_7+80];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r108, %r109, %r110, %r111}, [nvvm_tcgen05_st_16x128b_unpack_param_7+64];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r112, %r113, %r114, %r115}, [nvvm_tcgen05_st_16x128b_unpack_param_7+48];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r116, %r117, %r118, %r119}, [nvvm_tcgen05_st_16x128b_unpack_param_7+32];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r120, %r121, %r122, %r123}, [nvvm_tcgen05_st_16x128b_unpack_param_7+16];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r124, %r125, %r126, %r127}, [nvvm_tcgen05_st_16x128b_unpack_param_7];
; CHECK-NEXT: tcgen05.st.sync.aligned.16x128b.x32.unpack::16b.b32 [%r1], {%r124, %r125, %r126, %r127, %r120, %r121, %r122, %r123, %r116, %r117, %r118, %r119, %r112, %r113, %r114, %r115, %r108, %r109, %r110, %r111, %r104, %r105, %r106, %r107, %r100, %r101, %r102, %r103, %r96, %r97, %r98, %r99, %r92, %r93, %r94, %r95, %r88, %r89, %r90, %r91, %r84, %r85, %r86, %r87, %r80, %r81, %r82, %r83, %r76, %r77, %r78, %r79, %r72, %r73, %r74, %r75, %r68, %r69, %r70, %r71, %r64, %r65, %r66, %r67};
-; CHECK-NEXT: ld.param.v4.b32 {%r128, %r129, %r130, %r131}, [nvvm_tcgen05_st_16x128b_unpack_param_8+496];
-; CHECK-NEXT: ld.param.v4.b32 {%r132, %r133, %r134, %r135}, [nvvm_tcgen05_st_16x128b_unpack_param_8+480];
-; CHECK-NEXT: ld.param.v4.b32 {%r136, %r137, %r138, %r139}, [nvvm_tcgen05_st_16x128b_unpack_param_8+464];
-; CHECK-NEXT: ld.param.v4.b32 {%r140, %r141, %r142, %r143}, [nvvm_tcgen05_st_16x128b_unpack_param_8+448];
-; CHECK-NEXT: ld.param.v4.b32 {%r144, %r145, %r146, %r147}, [nvvm_tcgen05_st_16x128b_unpack_param_8+432];
-; CHECK-NEXT: ld.param.v4.b32 {%r148, %r149, %r150, %r151}, [nvvm_tcgen05_st_16x128b_unpack_param_8+416];
-; CHECK-NEXT: ld.param.v4.b32 {%r152, %r153, %r154, %r155}, [nvvm_tcgen05_st_16x128b_unpack_param_8+400];
-; CHECK-NEXT: ld.param.v4.b32 {%r156, %r157, %r158, %r159}, [nvvm_tcgen05_st_16x128b_unpack_param_8+384];
-; CHECK-NEXT: ld.param.v4.b32 {%r160, %r161, %r162, %r163}, [nvvm_tcgen05_st_16x128b_unpack_param_8+368];
-; CHECK-NEXT: ld.param.v4.b32 {%r164, %r165, %r166, %r167}, [nvvm_tcgen05_st_16x128b_unpack_param_8+352];
-; CHECK-NEXT: ld.param.v4.b32 {%r168, %r169, %r170, %r171}, [nvvm_tcgen05_st_16x128b_unpack_param_8+336];
-; CHECK-NEXT: ld.param.v4.b32 {%r172, %r173, %r174, %r175}, [nvvm_tcgen05_st_16x128b_unpack_param_8+320];
-; CHECK-NEXT: ld.param.v4.b32 {%r176, %r177, %r178, %r179}, [nvvm_tcgen05_st_16x128b_unpack_param_8+304];
-; CHECK-NEXT: ld.param.v4.b32 {%r180, %r181, %r182, %r183}, [nvvm_tcgen05_st_16x128b_unpack_param_8+288];
-; CHECK-NEXT: ld.param.v4.b32 {%r184, %r185, %r186, %r187}, [nvvm_tcgen05_st_16x128b_unpack_param_8+272];
-; CHECK-NEXT: ld.param.v4.b32 {%r188, %r189, %r190, %r191}, [nvvm_tcgen05_st_16x128b_unpack_param_8+256];
-; CHECK-NEXT: ld.param.v4.b32 {%r192, %r193, %r194, %r195}, [nvvm_tcgen05_st_16x128b_unpack_param_8+240];
-; CHECK-NEXT: ld.param.v4.b32 {%r196, %r197, %r198, %r199}, [nvvm_tcgen05_st_16x128b_unpack_param_8+224];
-; CHECK-NEXT: ld.param.v4.b32 {%r200, %r201, %r202, %r203}, [nvvm_tcgen05_st_16x128b_unpack_param_8+208];
-; CHECK-NEXT: ld.param.v4.b32 {%r204, %r205, %r206, %r207}, [nvvm_tcgen05_st_16x128b_unpack_param_8+192];
-; CHECK-NEXT: ld.param.v4.b32 {%r208, %r209, %r210, %r211}, [nvvm_tcgen05_st_16x128b_unpack_param_8+176];
-; CHECK-NEXT: ld.param.v4.b32 {%r212, %r213, %r214, %r215}, [nvvm_tcgen05_st_16x128b_unpack_param_8+160];
-; CHECK-NEXT: ld.param.v4.b32 {%r216, %r217, %r218, %r219}, [nvvm_tcgen05_st_16x128b_unpack_param_8+144];
-; CHECK-NEXT: ld.param.v4.b32 {%r220, %r221, %r222, %r223}, [nvvm_tcgen05_st_16x128b_unpack_param_8+128];
-; CHECK-NEXT: ld.param.v4.b32 {%r224, %r225, %r226, %r227}, [nvvm_tcgen05_st_16x128b_unpack_param_8+112];
-; CHECK-NEXT: ld.param.v4.b32 {%r228, %r229, %r230, %r231}, [nvvm_tcgen05_st_16x128b_unpack_param_8+96];
-; CHECK-NEXT: ld.param.v4.b32 {%r232, %r233, %r234, %r235}, [nvvm_tcgen05_st_16x128b_unpack_param_8+80];
-; CHECK-NEXT: ld.param.v4.b32 {%r236, %r237, %r238, %r239}, [nvvm_tcgen05_st_16x128b_unpack_param_8+64];
-; CHECK-NEXT: ld.param.v4.b32 {%r240, %r241, %r242, %r243}, [nvvm_tcgen05_st_16x128b_unpack_param_8+48];
-; CHECK-NEXT: ld.param.v4.b32 {%r244, %r245, %r246, %r247}, [nvvm_tcgen05_st_16x128b_unpack_param_8+32];
-; CHECK-NEXT: ld.param.v4.b32 {%r248, %r249, %r250, %r251}, [nvvm_tcgen05_st_16x128b_unpack_param_8+16];
-; CHECK-NEXT: ld.param.v4.b32 {%r252, %r253, %r254, %r255}, [nvvm_tcgen05_st_16x128b_unpack_param_8];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r128, %r129, %r130, %r131}, [nvvm_tcgen05_st_16x128b_unpack_param_8+496];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r132, %r133, %r134, %r135}, [nvvm_tcgen05_st_16x128b_unpack_param_8+480];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r136, %r137, %r138, %r139}, [nvvm_tcgen05_st_16x128b_unpack_param_8+464];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r140, %r141, %r142, %r143}, [nvvm_tcgen05_st_16x128b_unpack_param_8+448];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r144, %r145, %r146, %r147}, [nvvm_tcgen05_st_16x128b_unpack_param_8+432];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r148, %r149, %r150, %r151}, [nvvm_tcgen05_st_16x128b_unpack_param_8+416];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r152, %r153, %r154, %r155}, [nvvm_tcgen05_st_16x128b_unpack_param_8+400];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r156, %r157, %r158, %r159}, [nvvm_tcgen05_st_16x128b_unpack_param_8+384];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r160, %r161, %r162, %r163}, [nvvm_tcgen05_st_16x128b_unpack_param_8+368];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r164, %r165, %r166, %r167}, [nvvm_tcgen05_st_16x128b_unpack_param_8+352];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r168, %r169, %r170, %r171}, [nvvm_tcgen05_st_16x128b_unpack_param_8+336];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r172, %r173, %r174, %r175}, [nvvm_tcgen05_st_16x128b_unpack_param_8+320];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r176, %r177, %r178, %r179}, [nvvm_tcgen05_st_16x128b_unpack_param_8+304];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r180, %r181, %r182, %r183}, [nvvm_tcgen05_st_16x128b_unpack_param_8+288];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r184, %r185, %r186, %r187}, [nvvm_tcgen05_st_16x128b_unpack_param_8+272];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r188, %r189, %r190, %r191}, [nvvm_tcgen05_st_16x128b_unpack_param_8+256];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r192, %r193, %r194, %r195}, [nvvm_tcgen05_st_16x128b_unpack_param_8+240];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r196, %r197, %r198, %r199}, [nvvm_tcgen05_st_16x128b_unpack_param_8+224];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r200, %r201, %r202, %r203}, [nvvm_tcgen05_st_16x128b_unpack_param_8+208];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r204, %r205, %r206, %r207}, [nvvm_tcgen05_st_16x128b_unpack_param_8+192];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r208, %r209, %r210, %r211}, [nvvm_tcgen05_st_16x128b_unpack_param_8+176];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r212, %r213, %r214, %r215}, [nvvm_tcgen05_st_16x128b_unpack_param_8+160];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r216, %r217, %r218, %r219}, [nvvm_tcgen05_st_16x128b_unpack_param_8+144];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r220, %r221, %r222, %r223}, [nvvm_tcgen05_st_16x128b_unpack_param_8+128];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r224, %r225, %r226, %r227}, [nvvm_tcgen05_st_16x128b_unpack_param_8+112];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r228, %r229, %r230, %r231}, [nvvm_tcgen05_st_16x128b_unpack_param_8+96];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r232, %r233, %r234, %r235}, [nvvm_tcgen05_st_16x128b_unpack_param_8+80];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r236, %r237, %r238, %r239}, [nvvm_tcgen05_st_16x128b_unpack_param_8+64];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r240, %r241, %r242, %r243}, [nvvm_tcgen05_st_16x128b_unpack_param_8+48];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r244, %r245, %r246, %r247}, [nvvm_tcgen05_st_16x128b_unpack_param_8+32];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r248, %r249, %r250, %r251}, [nvvm_tcgen05_st_16x128b_unpack_param_8+16];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r252, %r253, %r254, %r255}, [nvvm_tcgen05_st_16x128b_unpack_param_8];
; CHECK-NEXT: tcgen05.st.sync.aligned.16x128b.x64.unpack::16b.b32 [%r1], {%r252, %r253, %r254, %r255, %r248, %r249, %r250, %r251, %r244, %r245, %r246, %r247, %r240, %r241, %r242, %r243, %r236, %r237, %r238, %r239, %r232, %r233, %r234, %r235, %r228, %r229, %r230, %r231, %r224, %r225, %r226, %r227, %r220, %r221, %r222, %r223, %r216, %r217, %r218, %r219, %r212, %r213, %r214, %r215, %r208, %r209, %r210, %r211, %r204, %r205, %r206, %r207, %r200, %r201, %r202, %r203, %r196, %r197, %r198, %r199, %r192, %r193, %r194, %r195, %r188, %r189, %r190, %r191, %r184, %r185, %r186, %r187, %r180, %r181, %r182, %r183, %r176, %r177, %r178, %r179, %r172, %r173, %r174, %r175, %r168, %r169, %r170, %r171, %r164, %r165, %r166, %r167, %r160, %r161, %r162, %r163, %r156, %r157, %r158, %r159, %r152, %r153, %r154, %r155, %r148, %r149, %r150, %r151, %r144, %r145, %r146, %r147, %r140, %r141, %r142, %r143, %r136, %r137, %r138, %r139, %r132, %r133, %r134, %r135, %r128, %r129, %r130, %r131};
; CHECK-NEXT: ret;
tail call void @llvm.nvvm.tcgen05.st.16x128b.x1(ptr addrspace(6) %taddr, <2 x i32> %stv2, i1 1)
@@ -409,75 +409,75 @@ define void @nvvm_tcgen05_st_16x256b(ptr addrspace(6) %taddr, <1 x i32> %stv1, <
; CHECK-NEXT: .reg .b32 %r<254>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [nvvm_tcgen05_st_16x256b_param_0];
-; CHECK-NEXT: ld.param.v4.b32 {%r2, %r3, %r4, %r5}, [nvvm_tcgen05_st_16x256b_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r1, [nvvm_tcgen05_st_16x256b_param_0];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r2, %r3, %r4, %r5}, [nvvm_tcgen05_st_16x256b_param_3];
; CHECK-NEXT: tcgen05.st.sync.aligned.16x256b.x1.b32 [%r1], {%r2, %r3, %r4, %r5};
-; CHECK-NEXT: ld.param.v4.b32 {%r6, %r7, %r8, %r9}, [nvvm_tcgen05_st_16x256b_param_4+16];
-; CHECK-NEXT: ld.param.v4.b32 {%r10, %r11, %r12, %r13}, [nvvm_tcgen05_st_16x256b_param_4];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r6, %r7, %r8, %r9}, [nvvm_tcgen05_st_16x256b_param_4+16];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r10, %r11, %r12, %r13}, [nvvm_tcgen05_st_16x256b_param_4];
; CHECK-NEXT: tcgen05.st.sync.aligned.16x256b.x2.b32 [%r1], {%r10, %r11, %r12, %r13, %r6, %r7, %r8, %r9};
-; CHECK-NEXT: ld.param.v4.b32 {%r14, %r15, %r16, %r17}, [nvvm_tcgen05_st_16x256b_param_5+48];
-; CHECK-NEXT: ld.param.v4.b32 {%r18, %r19, %r20, %r21}, [nvvm_tcgen05_st_16x256b_param_5+32];
-; CHECK-NEXT: ld.param.v4.b32 {%r22, %r23, %r24, %r25}, [nvvm_tcgen05_st_16x256b_param_5+16];
-; CHECK-NEXT: ld.param.v4.b32 {%r26, %r27, %r28, %r29}, [nvvm_tcgen05_st_16x256b_param_5];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r14, %r15, %r16, %r17}, [nvvm_tcgen05_st_16x256b_param_5+48];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r18, %r19, %r20, %r21}, [nvvm_tcgen05_st_16x256b_param_5+32];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r22, %r23, %r24, %r25}, [nvvm_tcgen05_st_16x256b_param_5+16];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r26, %r27, %r28, %r29}, [nvvm_tcgen05_st_16x256b_param_5];
; CHECK-NEXT: tcgen05.st.sync.aligned.16x256b.x4.b32 [%r1], {%r26, %r27, %r28, %r29, %r22, %r23, %r24, %r25, %r18, %r19, %r20, %r21, %r14, %r15, %r16, %r17};
-; CHECK-NEXT: ld.param.v4.b32 {%r30, %r31, %r32, %r33}, [nvvm_tcgen05_st_16x256b_param_6+112];
-; CHECK-NEXT: ld.param.v4.b32 {%r34, %r35, %r36, %r37}, [nvvm_tcgen05_st_16x256b_param_6+96];
-; CHECK-NEXT: ld.param.v4.b32 {%r38, %r39, %r40, %r41}, [nvvm_tcgen05_st_16x256b_param_6+80];
-; CHECK-NEXT: ld.param.v4.b32 {%r42, %r43, %r44, %r45}, [nvvm_tcgen05_st_16x256b_param_6+64];
-; CHECK-NEXT: ld.param.v4.b32 {%r46, %r47, %r48, %r49}, [nvvm_tcgen05_st_16x256b_param_6+48];
-; CHECK-NEXT: ld.param.v4.b32 {%r50, %r51, %r52, %r53}, [nvvm_tcgen05_st_16x256b_param_6+32];
-; CHECK-NEXT: ld.param.v4.b32 {%r54, %r55, %r56, %r57}, [nvvm_tcgen05_st_16x256b_param_6+16];
-; CHECK-NEXT: ld.param.v4.b32 {%r58, %r59, %r60, %r61}, [nvvm_tcgen05_st_16x256b_param_6];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r30, %r31, %r32, %r33}, [nvvm_tcgen05_st_16x256b_param_6+112];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r34, %r35, %r36, %r37}, [nvvm_tcgen05_st_16x256b_param_6+96];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r38, %r39, %r40, %r41}, [nvvm_tcgen05_st_16x256b_param_6+80];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r42, %r43, %r44, %r45}, [nvvm_tcgen05_st_16x256b_param_6+64];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r46, %r47, %r48, %r49}, [nvvm_tcgen05_st_16x256b_param_6+48];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r50, %r51, %r52, %r53}, [nvvm_tcgen05_st_16x256b_param_6+32];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r54, %r55, %r56, %r57}, [nvvm_tcgen05_st_16x256b_param_6+16];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r58, %r59, %r60, %r61}, [nvvm_tcgen05_st_16x256b_param_6];
; CHECK-NEXT: tcgen05.st.sync.aligned.16x256b.x8.b32 [%r1], {%r58, %r59, %r60, %r61, %r54, %r55, %r56, %r57, %r50, %r51, %r52, %r53, %r46, %r47, %r48, %r49, %r42, %r43, %r44, %r45, %r38, %r39, %r40, %r41, %r34, %r35, %r36, %r37, %r30, %r31, %r32, %r33};
-; CHECK-NEXT: ld.param.v4.b32 {%r62, %r63, %r64, %r65}, [nvvm_tcgen05_st_16x256b_param_7+240];
-; CHECK-NEXT: ld.param.v4.b32 {%r66, %r67, %r68, %r69}, [nvvm_tcgen05_st_16x256b_param_7+224];
-; CHECK-NEXT: ld.param.v4.b32 {%r70, %r71, %r72, %r73}, [nvvm_tcgen05_st_16x256b_param_7+208];
-; CHECK-NEXT: ld.param.v4.b32 {%r74, %r75, %r76, %r77}, [nvvm_tcgen05_st_16x256b_param_7+192];
-; CHECK-NEXT: ld.param.v4.b32 {%r78, %r79, %r80, %r81}, [nvvm_tcgen05_st_16x256b_param_7+176];
-; CHECK-NEXT: ld.param.v4.b32 {%r82, %r83, %r84, %r85}, [nvvm_tcgen05_st_16x256b_param_7+160];
-; CHECK-NEXT: ld.param.v4.b32 {%r86, %r87, %r88, %r89}, [nvvm_tcgen05_st_16x256b_param_7+144];
-; CHECK-NEXT: ld.param.v4.b32 {%r90, %r91, %r92, %r93}, [nvvm_tcgen05_st_16x256b_param_7+128];
-; CHECK-NEXT: ld.param.v4.b32 {%r94, %r95, %r96, %r97}, [nvvm_tcgen05_st_16x256b_param_7+112];
-; CHECK-NEXT: ld.param.v4.b32 {%r98, %r99, %r100, %r101}, [nvvm_tcgen05_st_16x256b_param_7+96];
-; CHECK-NEXT: ld.param.v4.b32 {%r102, %r103, %r104, %r105}, [nvvm_tcgen05_st_16x256b_param_7+80];
-; CHECK-NEXT: ld.param.v4.b32 {%r106, %r107, %r108, %r109}, [nvvm_tcgen05_st_16x256b_param_7+64];
-; CHECK-NEXT: ld.param.v4.b32 {%r110, %r111, %r112, %r113}, [nvvm_tcgen05_st_16x256b_param_7+48];
-; CHECK-NEXT: ld.param.v4.b32 {%r114, %r115, %r116, %r117}, [nvvm_tcgen05_st_16x256b_param_7+32];
-; CHECK-NEXT: ld.param.v4.b32 {%r118, %r119, %r120, %r121}, [nvvm_tcgen05_st_16x256b_param_7+16];
-; CHECK-NEXT: ld.param.v4.b32 {%r122, %r123, %r124, %r125}, [nvvm_tcgen05_st_16x256b_param_7];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r62, %r63, %r64, %r65}, [nvvm_tcgen05_st_16x256b_param_7+240];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r66, %r67, %r68, %r69}, [nvvm_tcgen05_st_16x256b_param_7+224];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r70, %r71, %r72, %r73}, [nvvm_tcgen05_st_16x256b_param_7+208];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r74, %r75, %r76, %r77}, [nvvm_tcgen05_st_16x256b_param_7+192];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r78, %r79, %r80, %r81}, [nvvm_tcgen05_st_16x256b_param_7+176];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r82, %r83, %r84, %r85}, [nvvm_tcgen05_st_16x256b_param_7+160];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r86, %r87, %r88, %r89}, [nvvm_tcgen05_st_16x256b_param_7+144];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r90, %r91, %r92, %r93}, [nvvm_tcgen05_st_16x256b_param_7+128];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r94, %r95, %r96, %r97}, [nvvm_tcgen05_st_16x256b_param_7+112];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r98, %r99, %r100, %r101}, [nvvm_tcgen05_st_16x256b_param_7+96];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r102, %r103, %r104, %r105}, [nvvm_tcgen05_st_16x256b_param_7+80];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r106, %r107, %r108, %r109}, [nvvm_tcgen05_st_16x256b_param_7+64];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r110, %r111, %r112, %r113}, [nvvm_tcgen05_st_16x256b_param_7+48];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r114, %r115, %r116, %r117}, [nvvm_tcgen05_st_16x256b_param_7+32];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r118, %r119, %r120, %r121}, [nvvm_tcgen05_st_16x256b_param_7+16];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r122, %r123, %r124, %r125}, [nvvm_tcgen05_st_16x256b_param_7];
; CHECK-NEXT: tcgen05.st.sync.aligned.16x256b.x16.b32 [%r1], {%r122, %r123, %r124, %r125, %r118, %r119, %r120, %r121, %r114, %r115, %r116, %r117, %r110, %r111, %r112, %r113, %r106, %r107, %r108, %r109, %r102, %r103, %r104, %r105, %r98, %r99, %r100, %r101, %r94, %r95, %r96, %r97, %r90, %r91, %r92, %r93, %r86, %r87, %r88, %r89, %r82, %r83, %r84, %r85, %r78, %r79, %r80, %r81, %r74, %r75, %r76, %r77, %r70, %r71, %r72, %r73, %r66, %r67, %r68, %r69, %r62, %r63, %r64, %r65};
-; CHECK-NEXT: ld.param.v4.b32 {%r126, %r127, %r128, %r129}, [nvvm_tcgen05_st_16x256b_param_8+496];
-; CHECK-NEXT: ld.param.v4.b32 {%r130, %r131, %r132, %r133}, [nvvm_tcgen05_st_16x256b_param_8+480];
-; CHECK-NEXT: ld.param.v4.b32 {%r134, %r135, %r136, %r137}, [nvvm_tcgen05_st_16x256b_param_8+464];
-; CHECK-NEXT: ld.param.v4.b32 {%r138, %r139, %r140, %r141}, [nvvm_tcgen05_st_16x256b_param_8+448];
-; CHECK-NEXT: ld.param.v4.b32 {%r142, %r143, %r144, %r145}, [nvvm_tcgen05_st_16x256b_param_8+432];
-; CHECK-NEXT: ld.param.v4.b32 {%r146, %r147, %r148, %r149}, [nvvm_tcgen05_st_16x256b_param_8+416];
-; CHECK-NEXT: ld.param.v4.b32 {%r150, %r151, %r152, %r153}, [nvvm_tcgen05_st_16x256b_param_8+400];
-; CHECK-NEXT: ld.param.v4.b32 {%r154, %r155, %r156, %r157}, [nvvm_tcgen05_st_16x256b_param_8+384];
-; CHECK-NEXT: ld.param.v4.b32 {%r158, %r159, %r160, %r161}, [nvvm_tcgen05_st_16x256b_param_8+368];
-; CHECK-NEXT: ld.param.v4.b32 {%r162, %r163, %r164, %r165}, [nvvm_tcgen05_st_16x256b_param_8+352];
-; CHECK-NEXT: ld.param.v4.b32 {%r166, %r167, %r168, %r169}, [nvvm_tcgen05_st_16x256b_param_8+336];
-; CHECK-NEXT: ld.param.v4.b32 {%r170, %r171, %r172, %r173}, [nvvm_tcgen05_st_16x256b_param_8+320];
-; CHECK-NEXT: ld.param.v4.b32 {%r174, %r175, %r176, %r177}, [nvvm_tcgen05_st_16x256b_param_8+304];
-; CHECK-NEXT: ld.param.v4.b32 {%r178, %r179, %r180, %r181}, [nvvm_tcgen05_st_16x256b_param_8+288];
-; CHECK-NEXT: ld.param.v4.b32 {%r182, %r183, %r184, %r185}, [nvvm_tcgen05_st_16x256b_param_8+272];
-; CHECK-NEXT: ld.param.v4.b32 {%r186, %r187, %r188, %r189}, [nvvm_tcgen05_st_16x256b_param_8+256];
-; CHECK-NEXT: ld.param.v4.b32 {%r190, %r191, %r192, %r193}, [nvvm_tcgen05_st_16x256b_param_8+240];
-; CHECK-NEXT: ld.param.v4.b32 {%r194, %r195, %r196, %r197}, [nvvm_tcgen05_st_16x256b_param_8+224];
-; CHECK-NEXT: ld.param.v4.b32 {%r198, %r199, %r200, %r201}, [nvvm_tcgen05_st_16x256b_param_8+208];
-; CHECK-NEXT: ld.param.v4.b32 {%r202, %r203, %r204, %r205}, [nvvm_tcgen05_st_16x256b_param_8+192];
-; CHECK-NEXT: ld.param.v4.b32 {%r206, %r207, %r208, %r209}, [nvvm_tcgen05_st_16x256b_param_8+176];
-; CHECK-NEXT: ld.param.v4.b32 {%r210, %r211, %r212, %r213}, [nvvm_tcgen05_st_16x256b_param_8+160];
-; CHECK-NEXT: ld.param.v4.b32 {%r214, %r215, %r216, %r217}, [nvvm_tcgen05_st_16x256b_param_8+144];
-; CHECK-NEXT: ld.param.v4.b32 {%r218, %r219, %r220, %r221}, [nvvm_tcgen05_st_16x256b_param_8+128];
-; CHECK-NEXT: ld.param.v4.b32 {%r222, %r223, %r224, %r225}, [nvvm_tcgen05_st_16x256b_param_8+112];
-; CHECK-NEXT: ld.param.v4.b32 {%r226, %r227, %r228, %r229}, [nvvm_tcgen05_st_16x256b_param_8+96];
-; CHECK-NEXT: ld.param.v4.b32 {%r230, %r231, %r232, %r233}, [nvvm_tcgen05_st_16x256b_param_8+80];
-; CHECK-NEXT: ld.param.v4.b32 {%r234, %r235, %r236, %r237}, [nvvm_tcgen05_st_16x256b_param_8+64];
-; CHECK-NEXT: ld.param.v4.b32 {%r238, %r239, %r240, %r241}, [nvvm_tcgen05_st_16x256b_param_8+48];
-; CHECK-NEXT: ld.param.v4.b32 {%r242, %r243, %r244, %r245}, [nvvm_tcgen05_st_16x256b_param_8+32];
-; CHECK-NEXT: ld.param.v4.b32 {%r246, %r247, %r248, %r249}, [nvvm_tcgen05_st_16x256b_param_8+16];
-; CHECK-NEXT: ld.param.v4.b32 {%r250, %r251, %r252, %r253}, [nvvm_tcgen05_st_16x256b_param_8];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r126, %r127, %r128, %r129}, [nvvm_tcgen05_st_16x256b_param_8+496];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r130, %r131, %r132, %r133}, [nvvm_tcgen05_st_16x256b_param_8+480];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r134, %r135, %r136, %r137}, [nvvm_tcgen05_st_16x256b_param_8+464];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r138, %r139, %r140, %r141}, [nvvm_tcgen05_st_16x256b_param_8+448];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r142, %r143, %r144, %r145}, [nvvm_tcgen05_st_16x256b_param_8+432];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r146, %r147, %r148, %r149}, [nvvm_tcgen05_st_16x256b_param_8+416];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r150, %r151, %r152, %r153}, [nvvm_tcgen05_st_16x256b_param_8+400];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r154, %r155, %r156, %r157}, [nvvm_tcgen05_st_16x256b_param_8+384];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r158, %r159, %r160, %r161}, [nvvm_tcgen05_st_16x256b_param_8+368];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r162, %r163, %r164, %r165}, [nvvm_tcgen05_st_16x256b_param_8+352];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r166, %r167, %r168, %r169}, [nvvm_tcgen05_st_16x256b_param_8+336];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r170, %r171, %r172, %r173}, [nvvm_tcgen05_st_16x256b_param_8+320];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r174, %r175, %r176, %r177}, [nvvm_tcgen05_st_16x256b_param_8+304];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r178, %r179, %r180, %r181}, [nvvm_tcgen05_st_16x256b_param_8+288];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r182, %r183, %r184, %r185}, [nvvm_tcgen05_st_16x256b_param_8+272];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r186, %r187, %r188, %r189}, [nvvm_tcgen05_st_16x256b_param_8+256];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r190, %r191, %r192, %r193}, [nvvm_tcgen05_st_16x256b_param_8+240];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r194, %r195, %r196, %r197}, [nvvm_tcgen05_st_16x256b_param_8+224];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r198, %r199, %r200, %r201}, [nvvm_tcgen05_st_16x256b_param_8+208];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r202, %r203, %r204, %r205}, [nvvm_tcgen05_st_16x256b_param_8+192];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r206, %r207, %r208, %r209}, [nvvm_tcgen05_st_16x256b_param_8+176];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r210, %r211, %r212, %r213}, [nvvm_tcgen05_st_16x256b_param_8+160];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r214, %r215, %r216, %r217}, [nvvm_tcgen05_st_16x256b_param_8+144];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r218, %r219, %r220, %r221}, [nvvm_tcgen05_st_16x256b_param_8+128];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r222, %r223, %r224, %r225}, [nvvm_tcgen05_st_16x256b_param_8+112];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r226, %r227, %r228, %r229}, [nvvm_tcgen05_st_16x256b_param_8+96];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r230, %r231, %r232, %r233}, [nvvm_tcgen05_st_16x256b_param_8+80];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r234, %r235, %r236, %r237}, [nvvm_tcgen05_st_16x256b_param_8+64];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r238, %r239, %r240, %r241}, [nvvm_tcgen05_st_16x256b_param_8+48];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r242, %r243, %r244, %r245}, [nvvm_tcgen05_st_16x256b_param_8+32];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r246, %r247, %r248, %r249}, [nvvm_tcgen05_st_16x256b_param_8+16];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r250, %r251, %r252, %r253}, [nvvm_tcgen05_st_16x256b_param_8];
; CHECK-NEXT: tcgen05.st.sync.aligned.16x256b.x32.b32 [%r1], {%r250, %r251, %r252, %r253, %r246, %r247, %r248, %r249, %r242, %r243, %r244, %r245, %r238, %r239, %r240, %r241, %r234, %r235, %r236, %r237, %r230, %r231, %r232, %r233, %r226, %r227, %r228, %r229, %r222, %r223, %r224, %r225, %r218, %r219, %r220, %r221, %r214, %r215, %r216, %r217, %r210, %r211, %r212, %r213, %r206, %r207, %r208, %r209, %r202, %r203, %r204, %r205, %r198, %r199, %r200, %r201, %r194, %r195, %r196, %r197, %r190, %r191, %r192, %r193, %r186, %r187, %r188, %r189, %r182, %r183, %r184, %r185, %r178, %r179, %r180, %r181, %r174, %r175, %r176, %r177, %r170, %r171, %r172, %r173, %r166, %r167, %r168, %r169, %r162, %r163, %r164, %r165, %r158, %r159, %r160, %r161, %r154, %r155, %r156, %r157, %r150, %r151, %r152, %r153, %r146, %r147, %r148, %r149, %r142, %r143, %r144, %r145, %r138, %r139, %r140, %r141, %r134, %r135, %r136, %r137, %r130, %r131, %r132, %r133, %r126, %r127, %r128, %r129};
; CHECK-NEXT: ret;
tail call void @llvm.nvvm.tcgen05.st.16x256b.x1(ptr addrspace(6) %taddr, <4 x i32> %stv4, i1 0)
@@ -501,75 +501,75 @@ define void @nvvm_tcgen05_st_16x256b_unpack(ptr addrspace(6) %taddr, <1 x i32> %
; CHECK-NEXT: .reg .b32 %r<254>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [nvvm_tcgen05_st_16x256b_unpack_param_0];
-; CHECK-NEXT: ld.param.v4.b32 {%r2, %r3, %r4, %r5}, [nvvm_tcgen05_st_16x256b_unpack_param_3];
+; CHECK-NEXT: ld.param::func.b32 %r1, [nvvm_tcgen05_st_16x256b_unpack_param_0];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r2, %r3, %r4, %r5}, [nvvm_tcgen05_st_16x256b_unpack_param_3];
; CHECK-NEXT: tcgen05.st.sync.aligned.16x256b.x1.unpack::16b.b32 [%r1], {%r2, %r3, %r4, %r5};
-; CHECK-NEXT: ld.param.v4.b32 {%r6, %r7, %r8, %r9}, [nvvm_tcgen05_st_16x256b_unpack_param_4+16];
-; CHECK-NEXT: ld.param.v4.b32 {%r10, %r11, %r12, %r13}, [nvvm_tcgen05_st_16x256b_unpack_param_4];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r6, %r7, %r8, %r9}, [nvvm_tcgen05_st_16x256b_unpack_param_4+16];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r10, %r11, %r12, %r13}, [nvvm_tcgen05_st_16x256b_unpack_param_4];
; CHECK-NEXT: tcgen05.st.sync.aligned.16x256b.x2.unpack::16b.b32 [%r1], {%r10, %r11, %r12, %r13, %r6, %r7, %r8, %r9};
-; CHECK-NEXT: ld.param.v4.b32 {%r14, %r15, %r16, %r17}, [nvvm_tcgen05_st_16x256b_unpack_param_5+48];
-; CHECK-NEXT: ld.param.v4.b32 {%r18, %r19, %r20, %r21}, [nvvm_tcgen05_st_16x256b_unpack_param_5+32];
-; CHECK-NEXT: ld.param.v4.b32 {%r22, %r23, %r24, %r25}, [nvvm_tcgen05_st_16x256b_unpack_param_5+16];
-; CHECK-NEXT: ld.param.v4.b32 {%r26, %r27, %r28, %r29}, [nvvm_tcgen05_st_16x256b_unpack_param_5];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r14, %r15, %r16, %r17}, [nvvm_tcgen05_st_16x256b_unpack_param_5+48];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r18, %r19, %r20, %r21}, [nvvm_tcgen05_st_16x256b_unpack_param_5+32];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r22, %r23, %r24, %r25}, [nvvm_tcgen05_st_16x256b_unpack_param_5+16];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r26, %r27, %r28, %r29}, [nvvm_tcgen05_st_16x256b_unpack_param_5];
; CHECK-NEXT: tcgen05.st.sync.aligned.16x256b.x4.unpack::16b.b32 [%r1], {%r26, %r27, %r28, %r29, %r22, %r23, %r24, %r25, %r18, %r19, %r20, %r21, %r14, %r15, %r16, %r17};
-; CHECK-NEXT: ld.param.v4.b32 {%r30, %r31, %r32, %r33}, [nvvm_tcgen05_st_16x256b_unpack_param_6+112];
-; CHECK-NEXT: ld.param.v4.b32 {%r34, %r35, %r36, %r37}, [nvvm_tcgen05_st_16x256b_unpack_param_6+96];
-; CHECK-NEXT: ld.param.v4.b32 {%r38, %r39, %r40, %r41}, [nvvm_tcgen05_st_16x256b_unpack_param_6+80];
-; CHECK-NEXT: ld.param.v4.b32 {%r42, %r43, %r44, %r45}, [nvvm_tcgen05_st_16x256b_unpack_param_6+64];
-; CHECK-NEXT: ld.param.v4.b32 {%r46, %r47, %r48, %r49}, [nvvm_tcgen05_st_16x256b_unpack_param_6+48];
-; CHECK-NEXT: ld.param.v4.b32 {%r50, %r51, %r52, %r53}, [nvvm_tcgen05_st_16x256b_unpack_param_6+32];
-; CHECK-NEXT: ld.param.v4.b32 {%r54, %r55, %r56, %r57}, [nvvm_tcgen05_st_16x256b_unpack_param_6+16];
-; CHECK-NEXT: ld.param.v4.b32 {%r58, %r59, %r60, %r61}, [nvvm_tcgen05_st_16x256b_unpack_param_6];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r30, %r31, %r32, %r33}, [nvvm_tcgen05_st_16x256b_unpack_param_6+112];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r34, %r35, %r36, %r37}, [nvvm_tcgen05_st_16x256b_unpack_param_6+96];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r38, %r39, %r40, %r41}, [nvvm_tcgen05_st_16x256b_unpack_param_6+80];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r42, %r43, %r44, %r45}, [nvvm_tcgen05_st_16x256b_unpack_param_6+64];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r46, %r47, %r48, %r49}, [nvvm_tcgen05_st_16x256b_unpack_param_6+48];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r50, %r51, %r52, %r53}, [nvvm_tcgen05_st_16x256b_unpack_param_6+32];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r54, %r55, %r56, %r57}, [nvvm_tcgen05_st_16x256b_unpack_param_6+16];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r58, %r59, %r60, %r61}, [nvvm_tcgen05_st_16x256b_unpack_param_6];
; CHECK-NEXT: tcgen05.st.sync.aligned.16x256b.x8.unpack::16b.b32 [%r1], {%r58, %r59, %r60, %r61, %r54, %r55, %r56, %r57, %r50, %r51, %r52, %r53, %r46, %r47, %r48, %r49, %r42, %r43, %r44, %r45, %r38, %r39, %r40, %r41, %r34, %r35, %r36, %r37, %r30, %r31, %r32, %r33};
-; CHECK-NEXT: ld.param.v4.b32 {%r62, %r63, %r64, %r65}, [nvvm_tcgen05_st_16x256b_unpack_param_7+240];
-; CHECK-NEXT: ld.param.v4.b32 {%r66, %r67, %r68, %r69}, [nvvm_tcgen05_st_16x256b_unpack_param_7+224];
-; CHECK-NEXT: ld.param.v4.b32 {%r70, %r71, %r72, %r73}, [nvvm_tcgen05_st_16x256b_unpack_param_7+208];
-; CHECK-NEXT: ld.param.v4.b32 {%r74, %r75, %r76, %r77}, [nvvm_tcgen05_st_16x256b_unpack_param_7+192];
-; CHECK-NEXT: ld.param.v4.b32 {%r78, %r79, %r80, %r81}, [nvvm_tcgen05_st_16x256b_unpack_param_7+176];
-; CHECK-NEXT: ld.param.v4.b32 {%r82, %r83, %r84, %r85}, [nvvm_tcgen05_st_16x256b_unpack_param_7+160];
-; CHECK-NEXT: ld.param.v4.b32 {%r86, %r87, %r88, %r89}, [nvvm_tcgen05_st_16x256b_unpack_param_7+144];
-; CHECK-NEXT: ld.param.v4.b32 {%r90, %r91, %r92, %r93}, [nvvm_tcgen05_st_16x256b_unpack_param_7+128];
-; CHECK-NEXT: ld.param.v4.b32 {%r94, %r95, %r96, %r97}, [nvvm_tcgen05_st_16x256b_unpack_param_7+112];
-; CHECK-NEXT: ld.param.v4.b32 {%r98, %r99, %r100, %r101}, [nvvm_tcgen05_st_16x256b_unpack_param_7+96];
-; CHECK-NEXT: ld.param.v4.b32 {%r102, %r103, %r104, %r105}, [nvvm_tcgen05_st_16x256b_unpack_param_7+80];
-; CHECK-NEXT: ld.param.v4.b32 {%r106, %r107, %r108, %r109}, [nvvm_tcgen05_st_16x256b_unpack_param_7+64];
-; CHECK-NEXT: ld.param.v4.b32 {%r110, %r111, %r112, %r113}, [nvvm_tcgen05_st_16x256b_unpack_param_7+48];
-; CHECK-NEXT: ld.param.v4.b32 {%r114, %r115, %r116, %r117}, [nvvm_tcgen05_st_16x256b_unpack_param_7+32];
-; CHECK-NEXT: ld.param.v4.b32 {%r118, %r119, %r120, %r121}, [nvvm_tcgen05_st_16x256b_unpack_param_7+16];
-; CHECK-NEXT: ld.param.v4.b32 {%r122, %r123, %r124, %r125}, [nvvm_tcgen05_st_16x256b_unpack_param_7];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r62, %r63, %r64, %r65}, [nvvm_tcgen05_st_16x256b_unpack_param_7+240];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r66, %r67, %r68, %r69}, [nvvm_tcgen05_st_16x256b_unpack_param_7+224];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r70, %r71, %r72, %r73}, [nvvm_tcgen05_st_16x256b_unpack_param_7+208];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r74, %r75, %r76, %r77}, [nvvm_tcgen05_st_16x256b_unpack_param_7+192];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r78, %r79, %r80, %r81}, [nvvm_tcgen05_st_16x256b_unpack_param_7+176];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r82, %r83, %r84, %r85}, [nvvm_tcgen05_st_16x256b_unpack_param_7+160];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r86, %r87, %r88, %r89}, [nvvm_tcgen05_st_16x256b_unpack_param_7+144];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r90, %r91, %r92, %r93}, [nvvm_tcgen05_st_16x256b_unpack_param_7+128];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r94, %r95, %r96, %r97}, [nvvm_tcgen05_st_16x256b_unpack_param_7+112];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r98, %r99, %r100, %r101}, [nvvm_tcgen05_st_16x256b_unpack_param_7+96];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r102, %r103, %r104, %r105}, [nvvm_tcgen05_st_16x256b_unpack_param_7+80];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r106, %r107, %r108, %r109}, [nvvm_tcgen05_st_16x256b_unpack_param_7+64];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r110, %r111, %r112, %r113}, [nvvm_tcgen05_st_16x256b_unpack_param_7+48];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r114, %r115, %r116, %r117}, [nvvm_tcgen05_st_16x256b_unpack_param_7+32];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r118, %r119, %r120, %r121}, [nvvm_tcgen05_st_16x256b_unpack_param_7+16];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r122, %r123, %r124, %r125}, [nvvm_tcgen05_st_16x256b_unpack_param_7];
; CHECK-NEXT: tcgen05.st.sync.aligned.16x256b.x16.unpack::16b.b32 [%r1], {%r122, %r123, %r124, %r125, %r118, %r119, %r120, %r121, %r114, %r115, %r116, %r117, %r110, %r111, %r112, %r113, %r106, %r107, %r108, %r109, %r102, %r103, %r104, %r105, %r98, %r99, %r100, %r101, %r94, %r95, %r96, %r97, %r90, %r91, %r92, %r93, %r86, %r87, %r88, %r89, %r82, %r83, %r84, %r85, %r78, %r79, %r80, %r81, %r74, %r75, %r76, %r77, %r70, %r71, %r72, %r73, %r66, %r67, %r68, %r69, %r62, %r63, %r64, %r65};
-; CHECK-NEXT: ld.param.v4.b32 {%r126, %r127, %r128, %r129}, [nvvm_tcgen05_st_16x256b_unpack_param_8+496];
-; CHECK-NEXT: ld.param.v4.b32 {%r130, %r131, %r132, %r133}, [nvvm_tcgen05_st_16x256b_unpack_param_8+480];
-; CHECK-NEXT: ld.param.v4.b32 {%r134, %r135, %r136, %r137}, [nvvm_tcgen05_st_16x256b_unpack_param_8+464];
-; CHECK-NEXT: ld.param.v4.b32 {%r138, %r139, %r140, %r141}, [nvvm_tcgen05_st_16x256b_unpack_param_8+448];
-; CHECK-NEXT: ld.param.v4.b32 {%r142, %r143, %r144, %r145}, [nvvm_tcgen05_st_16x256b_unpack_param_8+432];
-; CHECK-NEXT: ld.param.v4.b32 {%r146, %r147, %r148, %r149}, [nvvm_tcgen05_st_16x256b_unpack_param_8+416];
-; CHECK-NEXT: ld.param.v4.b32 {%r150, %r151, %r152, %r153}, [nvvm_tcgen05_st_16x256b_unpack_param_8+400];
-; CHECK-NEXT: ld.param.v4.b32 {%r154, %r155, %r156, %r157}, [nvvm_tcgen05_st_16x256b_unpack_param_8+384];
-; CHECK-NEXT: ld.param.v4.b32 {%r158, %r159, %r160, %r161}, [nvvm_tcgen05_st_16x256b_unpack_param_8+368];
-; CHECK-NEXT: ld.param.v4.b32 {%r162, %r163, %r164, %r165}, [nvvm_tcgen05_st_16x256b_unpack_param_8+352];
-; CHECK-NEXT: ld.param.v4.b32 {%r166, %r167, %r168, %r169}, [nvvm_tcgen05_st_16x256b_unpack_param_8+336];
-; CHECK-NEXT: ld.param.v4.b32 {%r170, %r171, %r172, %r173}, [nvvm_tcgen05_st_16x256b_unpack_param_8+320];
-; CHECK-NEXT: ld.param.v4.b32 {%r174, %r175, %r176, %r177}, [nvvm_tcgen05_st_16x256b_unpack_param_8+304];
-; CHECK-NEXT: ld.param.v4.b32 {%r178, %r179, %r180, %r181}, [nvvm_tcgen05_st_16x256b_unpack_param_8+288];
-; CHECK-NEXT: ld.param.v4.b32 {%r182, %r183, %r184, %r185}, [nvvm_tcgen05_st_16x256b_unpack_param_8+272];
-; CHECK-NEXT: ld.param.v4.b32 {%r186, %r187, %r188, %r189}, [nvvm_tcgen05_st_16x256b_unpack_param_8+256];
-; CHECK-NEXT: ld.param.v4.b32 {%r190, %r191, %r192, %r193}, [nvvm_tcgen05_st_16x256b_unpack_param_8+240];
-; CHECK-NEXT: ld.param.v4.b32 {%r194, %r195, %r196, %r197}, [nvvm_tcgen05_st_16x256b_unpack_param_8+224];
-; CHECK-NEXT: ld.param.v4.b32 {%r198, %r199, %r200, %r201}, [nvvm_tcgen05_st_16x256b_unpack_param_8+208];
-; CHECK-NEXT: ld.param.v4.b32 {%r202, %r203, %r204, %r205}, [nvvm_tcgen05_st_16x256b_unpack_param_8+192];
-; CHECK-NEXT: ld.param.v4.b32 {%r206, %r207, %r208, %r209}, [nvvm_tcgen05_st_16x256b_unpack_param_8+176];
-; CHECK-NEXT: ld.param.v4.b32 {%r210, %r211, %r212, %r213}, [nvvm_tcgen05_st_16x256b_unpack_param_8+160];
-; CHECK-NEXT: ld.param.v4.b32 {%r214, %r215, %r216, %r217}, [nvvm_tcgen05_st_16x256b_unpack_param_8+144];
-; CHECK-NEXT: ld.param.v4.b32 {%r218, %r219, %r220, %r221}, [nvvm_tcgen05_st_16x256b_unpack_param_8+128];
-; CHECK-NEXT: ld.param.v4.b32 {%r222, %r223, %r224, %r225}, [nvvm_tcgen05_st_16x256b_unpack_param_8+112];
-; CHECK-NEXT: ld.param.v4.b32 {%r226, %r227, %r228, %r229}, [nvvm_tcgen05_st_16x256b_unpack_param_8+96];
-; CHECK-NEXT: ld.param.v4.b32 {%r230, %r231, %r232, %r233}, [nvvm_tcgen05_st_16x256b_unpack_param_8+80];
-; CHECK-NEXT: ld.param.v4.b32 {%r234, %r235, %r236, %r237}, [nvvm_tcgen05_st_16x256b_unpack_param_8+64];
-; CHECK-NEXT: ld.param.v4.b32 {%r238, %r239, %r240, %r241}, [nvvm_tcgen05_st_16x256b_unpack_param_8+48];
-; CHECK-NEXT: ld.param.v4.b32 {%r242, %r243, %r244, %r245}, [nvvm_tcgen05_st_16x256b_unpack_param_8+32];
-; CHECK-NEXT: ld.param.v4.b32 {%r246, %r247, %r248, %r249}, [nvvm_tcgen05_st_16x256b_unpack_param_8+16];
-; CHECK-NEXT: ld.param.v4.b32 {%r250, %r251, %r252, %r253}, [nvvm_tcgen05_st_16x256b_unpack_param_8];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r126, %r127, %r128, %r129}, [nvvm_tcgen05_st_16x256b_unpack_param_8+496];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r130, %r131, %r132, %r133}, [nvvm_tcgen05_st_16x256b_unpack_param_8+480];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r134, %r135, %r136, %r137}, [nvvm_tcgen05_st_16x256b_unpack_param_8+464];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r138, %r139, %r140, %r141}, [nvvm_tcgen05_st_16x256b_unpack_param_8+448];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r142, %r143, %r144, %r145}, [nvvm_tcgen05_st_16x256b_unpack_param_8+432];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r146, %r147, %r148, %r149}, [nvvm_tcgen05_st_16x256b_unpack_param_8+416];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r150, %r151, %r152, %r153}, [nvvm_tcgen05_st_16x256b_unpack_param_8+400];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r154, %r155, %r156, %r157}, [nvvm_tcgen05_st_16x256b_unpack_param_8+384];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r158, %r159, %r160, %r161}, [nvvm_tcgen05_st_16x256b_unpack_param_8+368];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r162, %r163, %r164, %r165}, [nvvm_tcgen05_st_16x256b_unpack_param_8+352];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r166, %r167, %r168, %r169}, [nvvm_tcgen05_st_16x256b_unpack_param_8+336];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r170, %r171, %r172, %r173}, [nvvm_tcgen05_st_16x256b_unpack_param_8+320];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r174, %r175, %r176, %r177}, [nvvm_tcgen05_st_16x256b_unpack_param_8+304];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r178, %r179, %r180, %r181}, [nvvm_tcgen05_st_16x256b_unpack_param_8+288];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r182, %r183, %r184, %r185}, [nvvm_tcgen05_st_16x256b_unpack_param_8+272];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r186, %r187, %r188, %r189}, [nvvm_tcgen05_st_16x256b_unpack_param_8+256];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r190, %r191, %r192, %r193}, [nvvm_tcgen05_st_16x256b_unpack_param_8+240];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r194, %r195, %r196, %r197}, [nvvm_tcgen05_st_16x256b_unpack_param_8+224];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r198, %r199, %r200, %r201}, [nvvm_tcgen05_st_16x256b_unpack_param_8+208];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r202, %r203, %r204, %r205}, [nvvm_tcgen05_st_16x256b_unpack_param_8+192];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r206, %r207, %r208, %r209}, [nvvm_tcgen05_st_16x256b_unpack_param_8+176];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r210, %r211, %r212, %r213}, [nvvm_tcgen05_st_16x256b_unpack_param_8+160];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r214, %r215, %r216, %r217}, [nvvm_tcgen05_st_16x256b_unpack_param_8+144];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r218, %r219, %r220, %r221}, [nvvm_tcgen05_st_16x256b_unpack_param_8+128];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r222, %r223, %r224, %r225}, [nvvm_tcgen05_st_16x256b_unpack_param_8+112];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r226, %r227, %r228, %r229}, [nvvm_tcgen05_st_16x256b_unpack_param_8+96];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r230, %r231, %r232, %r233}, [nvvm_tcgen05_st_16x256b_unpack_param_8+80];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r234, %r235, %r236, %r237}, [nvvm_tcgen05_st_16x256b_unpack_param_8+64];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r238, %r239, %r240, %r241}, [nvvm_tcgen05_st_16x256b_unpack_param_8+48];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r242, %r243, %r244, %r245}, [nvvm_tcgen05_st_16x256b_unpack_param_8+32];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r246, %r247, %r248, %r249}, [nvvm_tcgen05_st_16x256b_unpack_param_8+16];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r250, %r251, %r252, %r253}, [nvvm_tcgen05_st_16x256b_unpack_param_8];
; CHECK-NEXT: tcgen05.st.sync.aligned.16x256b.x32.unpack::16b.b32 [%r1], {%r250, %r251, %r252, %r253, %r246, %r247, %r248, %r249, %r242, %r243, %r244, %r245, %r238, %r239, %r240, %r241, %r234, %r235, %r236, %r237, %r230, %r231, %r232, %r233, %r226, %r227, %r228, %r229, %r222, %r223, %r224, %r225, %r218, %r219, %r220, %r221, %r214, %r215, %r216, %r217, %r210, %r211, %r212, %r213, %r206, %r207, %r208, %r209, %r202, %r203, %r204, %r205, %r198, %r199, %r200, %r201, %r194, %r195, %r196, %r197, %r190, %r191, %r192, %r193, %r186, %r187, %r188, %r189, %r182, %r183, %r184, %r185, %r178, %r179, %r180, %r181, %r174, %r175, %r176, %r177, %r170, %r171, %r172, %r173, %r166, %r167, %r168, %r169, %r162, %r163, %r164, %r165, %r158, %r159, %r160, %r161, %r154, %r155, %r156, %r157, %r150, %r151, %r152, %r153, %r146, %r147, %r148, %r149, %r142, %r143, %r144, %r145, %r138, %r139, %r140, %r141, %r134, %r135, %r136, %r137, %r130, %r131, %r132, %r133, %r126, %r127, %r128, %r129};
; CHECK-NEXT: ret;
tail call void @llvm.nvvm.tcgen05.st.16x256b.x1(ptr addrspace(6) %taddr, <4 x i32> %stv4, i1 1)
@@ -593,79 +593,79 @@ define void @nvvm_tcgen05_st_32x32b(ptr addrspace(6) %taddr, <1 x i32> %stv1, <2
; CHECK-NEXT: .reg .b32 %r<257>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [nvvm_tcgen05_st_32x32b_param_0];
-; CHECK-NEXT: ld.param.b32 %r2, [nvvm_tcgen05_st_32x32b_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r1, [nvvm_tcgen05_st_32x32b_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r2, [nvvm_tcgen05_st_32x32b_param_1];
; CHECK-NEXT: tcgen05.st.sync.aligned.32x32b.x1.b32 [%r1], {%r2};
-; CHECK-NEXT: ld.param.v2.b32 {%r3, %r4}, [nvvm_tcgen05_st_32x32b_param_2];
+; CHECK-NEXT: ld.param::func.v2.b32 {%r3, %r4}, [nvvm_tcgen05_st_32x32b_param_2];
; CHECK-NEXT: tcgen05.st.sync.aligned.32x32b.x2.b32 [%r1], {%r3, %r4};
-; CHECK-NEXT: ld.param.v4.b32 {%r5, %r6, %r7, %r8}, [nvvm_tcgen05_st_32x32b_param_3];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r5, %r6, %r7, %r8}, [nvvm_tcgen05_st_32x32b_param_3];
; CHECK-NEXT: tcgen05.st.sync.aligned.32x32b.x4.b32 [%r1], {%r5, %r6, %r7, %r8};
-; CHECK-NEXT: ld.param.v4.b32 {%r9, %r10, %r11, %r12}, [nvvm_tcgen05_st_32x32b_param_4+16];
-; CHECK-NEXT: ld.param.v4.b32 {%r13, %r14, %r15, %r16}, [nvvm_tcgen05_st_32x32b_param_4];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r9, %r10, %r11, %r12}, [nvvm_tcgen05_st_32x32b_param_4+16];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r13, %r14, %r15, %r16}, [nvvm_tcgen05_st_32x32b_param_4];
; CHECK-NEXT: tcgen05.st.sync.aligned.32x32b.x8.b32 [%r1], {%r13, %r14, %r15, %r16, %r9, %r10, %r11, %r12};
-; CHECK-NEXT: ld.param.v4.b32 {%r17, %r18, %r19, %r20}, [nvvm_tcgen05_st_32x32b_param_5+48];
-; CHECK-NEXT: ld.param.v4.b32 {%r21, %r22, %r23, %r24}, [nvvm_tcgen05_st_32x32b_param_5+32];
-; CHECK-NEXT: ld.param.v4.b32 {%r25, %r26, %r27, %r28}, [nvvm_tcgen05_st_32x32b_param_5+16];
-; CHECK-NEXT: ld.param.v4.b32 {%r29, %r30, %r31, %r32}, [nvvm_tcgen05_st_32x32b_param_5];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r17, %r18, %r19, %r20}, [nvvm_tcgen05_st_32x32b_param_5+48];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r21, %r22, %r23, %r24}, [nvvm_tcgen05_st_32x32b_param_5+32];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r25, %r26, %r27, %r28}, [nvvm_tcgen05_st_32x32b_param_5+16];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r29, %r30, %r31, %r32}, [nvvm_tcgen05_st_32x32b_param_5];
; CHECK-NEXT: tcgen05.st.sync.aligned.32x32b.x16.b32 [%r1], {%r29, %r30, %r31, %r32, %r25, %r26, %r27, %r28, %r21, %r22, %r23, %r24, %r17, %r18, %r19, %r20};
-; CHECK-NEXT: ld.param.v4.b32 {%r33, %r34, %r35, %r36}, [nvvm_tcgen05_st_32x32b_param_6+112];
-; CHECK-NEXT: ld.param.v4.b32 {%r37, %r38, %r39, %r40}, [nvvm_tcgen05_st_32x32b_param_6+96];
-; CHECK-NEXT: ld.param.v4.b32 {%r41, %r42, %r43, %r44}, [nvvm_tcgen05_st_32x32b_param_6+80];
-; CHECK-NEXT: ld.param.v4.b32 {%r45, %r46, %r47, %r48}, [nvvm_tcgen05_st_32x32b_param_6+64];
-; CHECK-NEXT: ld.param.v4.b32 {%r49, %r50, %r51, %r52}, [nvvm_tcgen05_st_32x32b_param_6+48];
-; CHECK-NEXT: ld.param.v4.b32 {%r53, %r54, %r55, %r56}, [nvvm_tcgen05_st_32x32b_param_6+32];
-; CHECK-NEXT: ld.param.v4.b32 {%r57, %r58, %r59, %r60}, [nvvm_tcgen05_st_32x32b_param_6+16];
-; CHECK-NEXT: ld.param.v4.b32 {%r61, %r62, %r63, %r64}, [nvvm_tcgen05_st_32x32b_param_6];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r33, %r34, %r35, %r36}, [nvvm_tcgen05_st_32x32b_param_6+112];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r37, %r38, %r39, %r40}, [nvvm_tcgen05_st_32x32b_param_6+96];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r41, %r42, %r43, %r44}, [nvvm_tcgen05_st_32x32b_param_6+80];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r45, %r46, %r47, %r48}, [nvvm_tcgen05_st_32x32b_param_6+64];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r49, %r50, %r51, %r52}, [nvvm_tcgen05_st_32x32b_param_6+48];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r53, %r54, %r55, %r56}, [nvvm_tcgen05_st_32x32b_param_6+32];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r57, %r58, %r59, %r60}, [nvvm_tcgen05_st_32x32b_param_6+16];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r61, %r62, %r63, %r64}, [nvvm_tcgen05_st_32x32b_param_6];
; CHECK-NEXT: tcgen05.st.sync.aligned.32x32b.x32.b32 [%r1], {%r61, %r62, %r63, %r64, %r57, %r58, %r59, %r60, %r53, %r54, %r55, %r56, %r49, %r50, %r51, %r52, %r45, %r46, %r47, %r48, %r41, %r42, %r43, %r44, %r37, %r38, %r39, %r40, %r33, %r34, %r35, %r36};
-; CHECK-NEXT: ld.param.v4.b32 {%r65, %r66, %r67, %r68}, [nvvm_tcgen05_st_32x32b_param_7+240];
-; CHECK-NEXT: ld.param.v4.b32 {%r69, %r70, %r71, %r72}, [nvvm_tcgen05_st_32x32b_param_7+224];
-; CHECK-NEXT: ld.param.v4.b32 {%r73, %r74, %r75, %r76}, [nvvm_tcgen05_st_32x32b_param_7+208];
-; CHECK-NEXT: ld.param.v4.b32 {%r77, %r78, %r79, %r80}, [nvvm_tcgen05_st_32x32b_param_7+192];
-; CHECK-NEXT: ld.param.v4.b32 {%r81, %r82, %r83, %r84}, [nvvm_tcgen05_st_32x32b_param_7+176];
-; CHECK-NEXT: ld.param.v4.b32 {%r85, %r86, %r87, %r88}, [nvvm_tcgen05_st_32x32b_param_7+160];
-; CHECK-NEXT: ld.param.v4.b32 {%r89, %r90, %r91, %r92}, [nvvm_tcgen05_st_32x32b_param_7+144];
-; CHECK-NEXT: ld.param.v4.b32 {%r93, %r94, %r95, %r96}, [nvvm_tcgen05_st_32x32b_param_7+128];
-; CHECK-NEXT: ld.param.v4.b32 {%r97, %r98, %r99, %r100}, [nvvm_tcgen05_st_32x32b_param_7+112];
-; CHECK-NEXT: ld.param.v4.b32 {%r101, %r102, %r103, %r104}, [nvvm_tcgen05_st_32x32b_param_7+96];
-; CHECK-NEXT: ld.param.v4.b32 {%r105, %r106, %r107, %r108}, [nvvm_tcgen05_st_32x32b_param_7+80];
-; CHECK-NEXT: ld.param.v4.b32 {%r109, %r110, %r111, %r112}, [nvvm_tcgen05_st_32x32b_param_7+64];
-; CHECK-NEXT: ld.param.v4.b32 {%r113, %r114, %r115, %r116}, [nvvm_tcgen05_st_32x32b_param_7+48];
-; CHECK-NEXT: ld.param.v4.b32 {%r117, %r118, %r119, %r120}, [nvvm_tcgen05_st_32x32b_param_7+32];
-; CHECK-NEXT: ld.param.v4.b32 {%r121, %r122, %r123, %r124}, [nvvm_tcgen05_st_32x32b_param_7+16];
-; CHECK-NEXT: ld.param.v4.b32 {%r125, %r126, %r127, %r128}, [nvvm_tcgen05_st_32x32b_param_7];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r65, %r66, %r67, %r68}, [nvvm_tcgen05_st_32x32b_param_7+240];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r69, %r70, %r71, %r72}, [nvvm_tcgen05_st_32x32b_param_7+224];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r73, %r74, %r75, %r76}, [nvvm_tcgen05_st_32x32b_param_7+208];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r77, %r78, %r79, %r80}, [nvvm_tcgen05_st_32x32b_param_7+192];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r81, %r82, %r83, %r84}, [nvvm_tcgen05_st_32x32b_param_7+176];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r85, %r86, %r87, %r88}, [nvvm_tcgen05_st_32x32b_param_7+160];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r89, %r90, %r91, %r92}, [nvvm_tcgen05_st_32x32b_param_7+144];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r93, %r94, %r95, %r96}, [nvvm_tcgen05_st_32x32b_param_7+128];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r97, %r98, %r99, %r100}, [nvvm_tcgen05_st_32x32b_param_7+112];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r101, %r102, %r103, %r104}, [nvvm_tcgen05_st_32x32b_param_7+96];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r105, %r106, %r107, %r108}, [nvvm_tcgen05_st_32x32b_param_7+80];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r109, %r110, %r111, %r112}, [nvvm_tcgen05_st_32x32b_param_7+64];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r113, %r114, %r115, %r116}, [nvvm_tcgen05_st_32x32b_param_7+48];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r117, %r118, %r119, %r120}, [nvvm_tcgen05_st_32x32b_param_7+32];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r121, %r122, %r123, %r124}, [nvvm_tcgen05_st_32x32b_param_7+16];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r125, %r126, %r127, %r128}, [nvvm_tcgen05_st_32x32b_param_7];
; CHECK-NEXT: tcgen05.st.sync.aligned.32x32b.x64.b32 [%r1], {%r125, %r126, %r127, %r128, %r121, %r122, %r123, %r124, %r117, %r118, %r119, %r120, %r113, %r114, %r115, %r116, %r109, %r110, %r111, %r112, %r105, %r106, %r107, %r108, %r101, %r102, %r103, %r104, %r97, %r98, %r99, %r100, %r93, %r94, %r95, %r96, %r89, %r90, %r91, %r92, %r85, %r86, %r87, %r88, %r81, %r82, %r83, %r84, %r77, %r78, %r79, %r80, %r73, %r74, %r75, %r76, %r69, %r70, %r71, %r72, %r65, %r66, %r67, %r68};
-; CHECK-NEXT: ld.param.v4.b32 {%r129, %r130, %r131, %r132}, [nvvm_tcgen05_st_32x32b_param_8+496];
-; CHECK-NEXT: ld.param.v4.b32 {%r133, %r134, %r135, %r136}, [nvvm_tcgen05_st_32x32b_param_8+480];
-; CHECK-NEXT: ld.param.v4.b32 {%r137, %r138, %r139, %r140}, [nvvm_tcgen05_st_32x32b_param_8+464];
-; CHECK-NEXT: ld.param.v4.b32 {%r141, %r142, %r143, %r144}, [nvvm_tcgen05_st_32x32b_param_8+448];
-; CHECK-NEXT: ld.param.v4.b32 {%r145, %r146, %r147, %r148}, [nvvm_tcgen05_st_32x32b_param_8+432];
-; CHECK-NEXT: ld.param.v4.b32 {%r149, %r150, %r151, %r152}, [nvvm_tcgen05_st_32x32b_param_8+416];
-; CHECK-NEXT: ld.param.v4.b32 {%r153, %r154, %r155, %r156}, [nvvm_tcgen05_st_32x32b_param_8+400];
-; CHECK-NEXT: ld.param.v4.b32 {%r157, %r158, %r159, %r160}, [nvvm_tcgen05_st_32x32b_param_8+384];
-; CHECK-NEXT: ld.param.v4.b32 {%r161, %r162, %r163, %r164}, [nvvm_tcgen05_st_32x32b_param_8+368];
-; CHECK-NEXT: ld.param.v4.b32 {%r165, %r166, %r167, %r168}, [nvvm_tcgen05_st_32x32b_param_8+352];
-; CHECK-NEXT: ld.param.v4.b32 {%r169, %r170, %r171, %r172}, [nvvm_tcgen05_st_32x32b_param_8+336];
-; CHECK-NEXT: ld.param.v4.b32 {%r173, %r174, %r175, %r176}, [nvvm_tcgen05_st_32x32b_param_8+320];
-; CHECK-NEXT: ld.param.v4.b32 {%r177, %r178, %r179, %r180}, [nvvm_tcgen05_st_32x32b_param_8+304];
-; CHECK-NEXT: ld.param.v4.b32 {%r181, %r182, %r183, %r184}, [nvvm_tcgen05_st_32x32b_param_8+288];
-; CHECK-NEXT: ld.param.v4.b32 {%r185, %r186, %r187, %r188}, [nvvm_tcgen05_st_32x32b_param_8+272];
-; CHECK-NEXT: ld.param.v4.b32 {%r189, %r190, %r191, %r192}, [nvvm_tcgen05_st_32x32b_param_8+256];
-; CHECK-NEXT: ld.param.v4.b32 {%r193, %r194, %r195, %r196}, [nvvm_tcgen05_st_32x32b_param_8+240];
-; CHECK-NEXT: ld.param.v4.b32 {%r197, %r198, %r199, %r200}, [nvvm_tcgen05_st_32x32b_param_8+224];
-; CHECK-NEXT: ld.param.v4.b32 {%r201, %r202, %r203, %r204}, [nvvm_tcgen05_st_32x32b_param_8+208];
-; CHECK-NEXT: ld.param.v4.b32 {%r205, %r206, %r207, %r208}, [nvvm_tcgen05_st_32x32b_param_8+192];
-; CHECK-NEXT: ld.param.v4.b32 {%r209, %r210, %r211, %r212}, [nvvm_tcgen05_st_32x32b_param_8+176];
-; CHECK-NEXT: ld.param.v4.b32 {%r213, %r214, %r215, %r216}, [nvvm_tcgen05_st_32x32b_param_8+160];
-; CHECK-NEXT: ld.param.v4.b32 {%r217, %r218, %r219, %r220}, [nvvm_tcgen05_st_32x32b_param_8+144];
-; CHECK-NEXT: ld.param.v4.b32 {%r221, %r222, %r223, %r224}, [nvvm_tcgen05_st_32x32b_param_8+128];
-; CHECK-NEXT: ld.param.v4.b32 {%r225, %r226, %r227, %r228}, [nvvm_tcgen05_st_32x32b_param_8+112];
-; CHECK-NEXT: ld.param.v4.b32 {%r229, %r230, %r231, %r232}, [nvvm_tcgen05_st_32x32b_param_8+96];
-; CHECK-NEXT: ld.param.v4.b32 {%r233, %r234, %r235, %r236}, [nvvm_tcgen05_st_32x32b_param_8+80];
-; CHECK-NEXT: ld.param.v4.b32 {%r237, %r238, %r239, %r240}, [nvvm_tcgen05_st_32x32b_param_8+64];
-; CHECK-NEXT: ld.param.v4.b32 {%r241, %r242, %r243, %r244}, [nvvm_tcgen05_st_32x32b_param_8+48];
-; CHECK-NEXT: ld.param.v4.b32 {%r245, %r246, %r247, %r248}, [nvvm_tcgen05_st_32x32b_param_8+32];
-; CHECK-NEXT: ld.param.v4.b32 {%r249, %r250, %r251, %r252}, [nvvm_tcgen05_st_32x32b_param_8+16];
-; CHECK-NEXT: ld.param.v4.b32 {%r253, %r254, %r255, %r256}, [nvvm_tcgen05_st_32x32b_param_8];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r129, %r130, %r131, %r132}, [nvvm_tcgen05_st_32x32b_param_8+496];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r133, %r134, %r135, %r136}, [nvvm_tcgen05_st_32x32b_param_8+480];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r137, %r138, %r139, %r140}, [nvvm_tcgen05_st_32x32b_param_8+464];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r141, %r142, %r143, %r144}, [nvvm_tcgen05_st_32x32b_param_8+448];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r145, %r146, %r147, %r148}, [nvvm_tcgen05_st_32x32b_param_8+432];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r149, %r150, %r151, %r152}, [nvvm_tcgen05_st_32x32b_param_8+416];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r153, %r154, %r155, %r156}, [nvvm_tcgen05_st_32x32b_param_8+400];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r157, %r158, %r159, %r160}, [nvvm_tcgen05_st_32x32b_param_8+384];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r161, %r162, %r163, %r164}, [nvvm_tcgen05_st_32x32b_param_8+368];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r165, %r166, %r167, %r168}, [nvvm_tcgen05_st_32x32b_param_8+352];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r169, %r170, %r171, %r172}, [nvvm_tcgen05_st_32x32b_param_8+336];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r173, %r174, %r175, %r176}, [nvvm_tcgen05_st_32x32b_param_8+320];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r177, %r178, %r179, %r180}, [nvvm_tcgen05_st_32x32b_param_8+304];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r181, %r182, %r183, %r184}, [nvvm_tcgen05_st_32x32b_param_8+288];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r185, %r186, %r187, %r188}, [nvvm_tcgen05_st_32x32b_param_8+272];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r189, %r190, %r191, %r192}, [nvvm_tcgen05_st_32x32b_param_8+256];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r193, %r194, %r195, %r196}, [nvvm_tcgen05_st_32x32b_param_8+240];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r197, %r198, %r199, %r200}, [nvvm_tcgen05_st_32x32b_param_8+224];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r201, %r202, %r203, %r204}, [nvvm_tcgen05_st_32x32b_param_8+208];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r205, %r206, %r207, %r208}, [nvvm_tcgen05_st_32x32b_param_8+192];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r209, %r210, %r211, %r212}, [nvvm_tcgen05_st_32x32b_param_8+176];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r213, %r214, %r215, %r216}, [nvvm_tcgen05_st_32x32b_param_8+160];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r217, %r218, %r219, %r220}, [nvvm_tcgen05_st_32x32b_param_8+144];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r221, %r222, %r223, %r224}, [nvvm_tcgen05_st_32x32b_param_8+128];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r225, %r226, %r227, %r228}, [nvvm_tcgen05_st_32x32b_param_8+112];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r229, %r230, %r231, %r232}, [nvvm_tcgen05_st_32x32b_param_8+96];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r233, %r234, %r235, %r236}, [nvvm_tcgen05_st_32x32b_param_8+80];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r237, %r238, %r239, %r240}, [nvvm_tcgen05_st_32x32b_param_8+64];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r241, %r242, %r243, %r244}, [nvvm_tcgen05_st_32x32b_param_8+48];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r245, %r246, %r247, %r248}, [nvvm_tcgen05_st_32x32b_param_8+32];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r249, %r250, %r251, %r252}, [nvvm_tcgen05_st_32x32b_param_8+16];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r253, %r254, %r255, %r256}, [nvvm_tcgen05_st_32x32b_param_8];
; CHECK-NEXT: tcgen05.st.sync.aligned.32x32b.x128.b32 [%r1], {%r253, %r254, %r255, %r256, %r249, %r250, %r251, %r252, %r245, %r246, %r247, %r248, %r241, %r242, %r243, %r244, %r237, %r238, %r239, %r240, %r233, %r234, %r235, %r236, %r229, %r230, %r231, %r232, %r225, %r226, %r227, %r228, %r221, %r222, %r223, %r224, %r217, %r218, %r219, %r220, %r213, %r214, %r215, %r216, %r209, %r210, %r211, %r212, %r205, %r206, %r207, %r208, %r201, %r202, %r203, %r204, %r197, %r198, %r199, %r200, %r193, %r194, %r195, %r196, %r189, %r190, %r191, %r192, %r185, %r186, %r187, %r188, %r181, %r182, %r183, %r184, %r177, %r178, %r179, %r180, %r173, %r174, %r175, %r176, %r169, %r170, %r171, %r172, %r165, %r166, %r167, %r168, %r161, %r162, %r163, %r164, %r157, %r158, %r159, %r160, %r153, %r154, %r155, %r156, %r149, %r150, %r151, %r152, %r145, %r146, %r147, %r148, %r141, %r142, %r143, %r144, %r137, %r138, %r139, %r140, %r133, %r134, %r135, %r136, %r129, %r130, %r131, %r132};
; CHECK-NEXT: ret;
tail call void @llvm.nvvm.tcgen05.st.32x32b.x1(ptr addrspace(6) %taddr, <1 x i32> %stv1, i1 0)
@@ -693,79 +693,79 @@ define void @nvvm_tcgen05_st_32x32b_unpack(ptr addrspace(6) %taddr, <1 x i32> %s
; CHECK-NEXT: .reg .b32 %r<257>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [nvvm_tcgen05_st_32x32b_unpack_param_0];
-; CHECK-NEXT: ld.param.b32 %r2, [nvvm_tcgen05_st_32x32b_unpack_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r1, [nvvm_tcgen05_st_32x32b_unpack_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r2, [nvvm_tcgen05_st_32x32b_unpack_param_1];
; CHECK-NEXT: tcgen05.st.sync.aligned.32x32b.x1.unpack::16b.b32 [%r1], {%r2};
-; CHECK-NEXT: ld.param.v2.b32 {%r3, %r4}, [nvvm_tcgen05_st_32x32b_unpack_param_2];
+; CHECK-NEXT: ld.param::func.v2.b32 {%r3, %r4}, [nvvm_tcgen05_st_32x32b_unpack_param_2];
; CHECK-NEXT: tcgen05.st.sync.aligned.32x32b.x2.unpack::16b.b32 [%r1], {%r3, %r4};
-; CHECK-NEXT: ld.param.v4.b32 {%r5, %r6, %r7, %r8}, [nvvm_tcgen05_st_32x32b_unpack_param_3];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r5, %r6, %r7, %r8}, [nvvm_tcgen05_st_32x32b_unpack_param_3];
; CHECK-NEXT: tcgen05.st.sync.aligned.32x32b.x4.unpack::16b.b32 [%r1], {%r5, %r6, %r7, %r8};
-; CHECK-NEXT: ld.param.v4.b32 {%r9, %r10, %r11, %r12}, [nvvm_tcgen05_st_32x32b_unpack_param_4+16];
-; CHECK-NEXT: ld.param.v4.b32 {%r13, %r14, %r15, %r16}, [nvvm_tcgen05_st_32x32b_unpack_param_4];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r9, %r10, %r11, %r12}, [nvvm_tcgen05_st_32x32b_unpack_param_4+16];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r13, %r14, %r15, %r16}, [nvvm_tcgen05_st_32x32b_unpack_param_4];
; CHECK-NEXT: tcgen05.st.sync.aligned.32x32b.x8.unpack::16b.b32 [%r1], {%r13, %r14, %r15, %r16, %r9, %r10, %r11, %r12};
-; CHECK-NEXT: ld.param.v4.b32 {%r17, %r18, %r19, %r20}, [nvvm_tcgen05_st_32x32b_unpack_param_5+48];
-; CHECK-NEXT: ld.param.v4.b32 {%r21, %r22, %r23, %r24}, [nvvm_tcgen05_st_32x32b_unpack_param_5+32];
-; CHECK-NEXT: ld.param.v4.b32 {%r25, %r26, %r27, %r28}, [nvvm_tcgen05_st_32x32b_unpack_param_5+16];
-; CHECK-NEXT: ld.param.v4.b32 {%r29, %r30, %r31, %r32}, [nvvm_tcgen05_st_32x32b_unpack_param_5];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r17, %r18, %r19, %r20}, [nvvm_tcgen05_st_32x32b_unpack_param_5+48];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r21, %r22, %r23, %r24}, [nvvm_tcgen05_st_32x32b_unpack_param_5+32];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r25, %r26, %r27, %r28}, [nvvm_tcgen05_st_32x32b_unpack_param_5+16];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r29, %r30, %r31, %r32}, [nvvm_tcgen05_st_32x32b_unpack_param_5];
; CHECK-NEXT: tcgen05.st.sync.aligned.32x32b.x16.unpack::16b.b32 [%r1], {%r29, %r30, %r31, %r32, %r25, %r26, %r27, %r28, %r21, %r22, %r23, %r24, %r17, %r18, %r19, %r20};
-; CHECK-NEXT: ld.param.v4.b32 {%r33, %r34, %r35, %r36}, [nvvm_tcgen05_st_32x32b_unpack_param_6+112];
-; CHECK-NEXT: ld.param.v4.b32 {%r37, %r38, %r39, %r40}, [nvvm_tcgen05_st_32x32b_unpack_param_6+96];
-; CHECK-NEXT: ld.param.v4.b32 {%r41, %r42, %r43, %r44}, [nvvm_tcgen05_st_32x32b_unpack_param_6+80];
-; CHECK-NEXT: ld.param.v4.b32 {%r45, %r46, %r47, %r48}, [nvvm_tcgen05_st_32x32b_unpack_param_6+64];
-; CHECK-NEXT: ld.param.v4.b32 {%r49, %r50, %r51, %r52}, [nvvm_tcgen05_st_32x32b_unpack_param_6+48];
-; CHECK-NEXT: ld.param.v4.b32 {%r53, %r54, %r55, %r56}, [nvvm_tcgen05_st_32x32b_unpack_param_6+32];
-; CHECK-NEXT: ld.param.v4.b32 {%r57, %r58, %r59, %r60}, [nvvm_tcgen05_st_32x32b_unpack_param_6+16];
-; CHECK-NEXT: ld.param.v4.b32 {%r61, %r62, %r63, %r64}, [nvvm_tcgen05_st_32x32b_unpack_param_6];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r33, %r34, %r35, %r36}, [nvvm_tcgen05_st_32x32b_unpack_param_6+112];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r37, %r38, %r39, %r40}, [nvvm_tcgen05_st_32x32b_unpack_param_6+96];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r41, %r42, %r43, %r44}, [nvvm_tcgen05_st_32x32b_unpack_param_6+80];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r45, %r46, %r47, %r48}, [nvvm_tcgen05_st_32x32b_unpack_param_6+64];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r49, %r50, %r51, %r52}, [nvvm_tcgen05_st_32x32b_unpack_param_6+48];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r53, %r54, %r55, %r56}, [nvvm_tcgen05_st_32x32b_unpack_param_6+32];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r57, %r58, %r59, %r60}, [nvvm_tcgen05_st_32x32b_unpack_param_6+16];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r61, %r62, %r63, %r64}, [nvvm_tcgen05_st_32x32b_unpack_param_6];
; CHECK-NEXT: tcgen05.st.sync.aligned.32x32b.x32.unpack::16b.b32 [%r1], {%r61, %r62, %r63, %r64, %r57, %r58, %r59, %r60, %r53, %r54, %r55, %r56, %r49, %r50, %r51, %r52, %r45, %r46, %r47, %r48, %r41, %r42, %r43, %r44, %r37, %r38, %r39, %r40, %r33, %r34, %r35, %r36};
-; CHECK-NEXT: ld.param.v4.b32 {%r65, %r66, %r67, %r68}, [nvvm_tcgen05_st_32x32b_unpack_param_7+240];
-; CHECK-NEXT: ld.param.v4.b32 {%r69, %r70, %r71, %r72}, [nvvm_tcgen05_st_32x32b_unpack_param_7+224];
-; CHECK-NEXT: ld.param.v4.b32 {%r73, %r74, %r75, %r76}, [nvvm_tcgen05_st_32x32b_unpack_param_7+208];
-; CHECK-NEXT: ld.param.v4.b32 {%r77, %r78, %r79, %r80}, [nvvm_tcgen05_st_32x32b_unpack_param_7+192];
-; CHECK-NEXT: ld.param.v4.b32 {%r81, %r82, %r83, %r84}, [nvvm_tcgen05_st_32x32b_unpack_param_7+176];
-; CHECK-NEXT: ld.param.v4.b32 {%r85, %r86, %r87, %r88}, [nvvm_tcgen05_st_32x32b_unpack_param_7+160];
-; CHECK-NEXT: ld.param.v4.b32 {%r89, %r90, %r91, %r92}, [nvvm_tcgen05_st_32x32b_unpack_param_7+144];
-; CHECK-NEXT: ld.param.v4.b32 {%r93, %r94, %r95, %r96}, [nvvm_tcgen05_st_32x32b_unpack_param_7+128];
-; CHECK-NEXT: ld.param.v4.b32 {%r97, %r98, %r99, %r100}, [nvvm_tcgen05_st_32x32b_unpack_param_7+112];
-; CHECK-NEXT: ld.param.v4.b32 {%r101, %r102, %r103, %r104}, [nvvm_tcgen05_st_32x32b_unpack_param_7+96];
-; CHECK-NEXT: ld.param.v4.b32 {%r105, %r106, %r107, %r108}, [nvvm_tcgen05_st_32x32b_unpack_param_7+80];
-; CHECK-NEXT: ld.param.v4.b32 {%r109, %r110, %r111, %r112}, [nvvm_tcgen05_st_32x32b_unpack_param_7+64];
-; CHECK-NEXT: ld.param.v4.b32 {%r113, %r114, %r115, %r116}, [nvvm_tcgen05_st_32x32b_unpack_param_7+48];
-; CHECK-NEXT: ld.param.v4.b32 {%r117, %r118, %r119, %r120}, [nvvm_tcgen05_st_32x32b_unpack_param_7+32];
-; CHECK-NEXT: ld.param.v4.b32 {%r121, %r122, %r123, %r124}, [nvvm_tcgen05_st_32x32b_unpack_param_7+16];
-; CHECK-NEXT: ld.param.v4.b32 {%r125, %r126, %r127, %r128}, [nvvm_tcgen05_st_32x32b_unpack_param_7];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r65, %r66, %r67, %r68}, [nvvm_tcgen05_st_32x32b_unpack_param_7+240];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r69, %r70, %r71, %r72}, [nvvm_tcgen05_st_32x32b_unpack_param_7+224];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r73, %r74, %r75, %r76}, [nvvm_tcgen05_st_32x32b_unpack_param_7+208];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r77, %r78, %r79, %r80}, [nvvm_tcgen05_st_32x32b_unpack_param_7+192];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r81, %r82, %r83, %r84}, [nvvm_tcgen05_st_32x32b_unpack_param_7+176];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r85, %r86, %r87, %r88}, [nvvm_tcgen05_st_32x32b_unpack_param_7+160];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r89, %r90, %r91, %r92}, [nvvm_tcgen05_st_32x32b_unpack_param_7+144];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r93, %r94, %r95, %r96}, [nvvm_tcgen05_st_32x32b_unpack_param_7+128];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r97, %r98, %r99, %r100}, [nvvm_tcgen05_st_32x32b_unpack_param_7+112];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r101, %r102, %r103, %r104}, [nvvm_tcgen05_st_32x32b_unpack_param_7+96];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r105, %r106, %r107, %r108}, [nvvm_tcgen05_st_32x32b_unpack_param_7+80];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r109, %r110, %r111, %r112}, [nvvm_tcgen05_st_32x32b_unpack_param_7+64];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r113, %r114, %r115, %r116}, [nvvm_tcgen05_st_32x32b_unpack_param_7+48];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r117, %r118, %r119, %r120}, [nvvm_tcgen05_st_32x32b_unpack_param_7+32];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r121, %r122, %r123, %r124}, [nvvm_tcgen05_st_32x32b_unpack_param_7+16];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r125, %r126, %r127, %r128}, [nvvm_tcgen05_st_32x32b_unpack_param_7];
; CHECK-NEXT: tcgen05.st.sync.aligned.32x32b.x64.unpack::16b.b32 [%r1], {%r125, %r126, %r127, %r128, %r121, %r122, %r123, %r124, %r117, %r118, %r119, %r120, %r113, %r114, %r115, %r116, %r109, %r110, %r111, %r112, %r105, %r106, %r107, %r108, %r101, %r102, %r103, %r104, %r97, %r98, %r99, %r100, %r93, %r94, %r95, %r96, %r89, %r90, %r91, %r92, %r85, %r86, %r87, %r88, %r81, %r82, %r83, %r84, %r77, %r78, %r79, %r80, %r73, %r74, %r75, %r76, %r69, %r70, %r71, %r72, %r65, %r66, %r67, %r68};
-; CHECK-NEXT: ld.param.v4.b32 {%r129, %r130, %r131, %r132}, [nvvm_tcgen05_st_32x32b_unpack_param_8+496];
-; CHECK-NEXT: ld.param.v4.b32 {%r133, %r134, %r135, %r136}, [nvvm_tcgen05_st_32x32b_unpack_param_8+480];
-; CHECK-NEXT: ld.param.v4.b32 {%r137, %r138, %r139, %r140}, [nvvm_tcgen05_st_32x32b_unpack_param_8+464];
-; CHECK-NEXT: ld.param.v4.b32 {%r141, %r142, %r143, %r144}, [nvvm_tcgen05_st_32x32b_unpack_param_8+448];
-; CHECK-NEXT: ld.param.v4.b32 {%r145, %r146, %r147, %r148}, [nvvm_tcgen05_st_32x32b_unpack_param_8+432];
-; CHECK-NEXT: ld.param.v4.b32 {%r149, %r150, %r151, %r152}, [nvvm_tcgen05_st_32x32b_unpack_param_8+416];
-; CHECK-NEXT: ld.param.v4.b32 {%r153, %r154, %r155, %r156}, [nvvm_tcgen05_st_32x32b_unpack_param_8+400];
-; CHECK-NEXT: ld.param.v4.b32 {%r157, %r158, %r159, %r160}, [nvvm_tcgen05_st_32x32b_unpack_param_8+384];
-; CHECK-NEXT: ld.param.v4.b32 {%r161, %r162, %r163, %r164}, [nvvm_tcgen05_st_32x32b_unpack_param_8+368];
-; CHECK-NEXT: ld.param.v4.b32 {%r165, %r166, %r167, %r168}, [nvvm_tcgen05_st_32x32b_unpack_param_8+352];
-; CHECK-NEXT: ld.param.v4.b32 {%r169, %r170, %r171, %r172}, [nvvm_tcgen05_st_32x32b_unpack_param_8+336];
-; CHECK-NEXT: ld.param.v4.b32 {%r173, %r174, %r175, %r176}, [nvvm_tcgen05_st_32x32b_unpack_param_8+320];
-; CHECK-NEXT: ld.param.v4.b32 {%r177, %r178, %r179, %r180}, [nvvm_tcgen05_st_32x32b_unpack_param_8+304];
-; CHECK-NEXT: ld.param.v4.b32 {%r181, %r182, %r183, %r184}, [nvvm_tcgen05_st_32x32b_unpack_param_8+288];
-; CHECK-NEXT: ld.param.v4.b32 {%r185, %r186, %r187, %r188}, [nvvm_tcgen05_st_32x32b_unpack_param_8+272];
-; CHECK-NEXT: ld.param.v4.b32 {%r189, %r190, %r191, %r192}, [nvvm_tcgen05_st_32x32b_unpack_param_8+256];
-; CHECK-NEXT: ld.param.v4.b32 {%r193, %r194, %r195, %r196}, [nvvm_tcgen05_st_32x32b_unpack_param_8+240];
-; CHECK-NEXT: ld.param.v4.b32 {%r197, %r198, %r199, %r200}, [nvvm_tcgen05_st_32x32b_unpack_param_8+224];
-; CHECK-NEXT: ld.param.v4.b32 {%r201, %r202, %r203, %r204}, [nvvm_tcgen05_st_32x32b_unpack_param_8+208];
-; CHECK-NEXT: ld.param.v4.b32 {%r205, %r206, %r207, %r208}, [nvvm_tcgen05_st_32x32b_unpack_param_8+192];
-; CHECK-NEXT: ld.param.v4.b32 {%r209, %r210, %r211, %r212}, [nvvm_tcgen05_st_32x32b_unpack_param_8+176];
-; CHECK-NEXT: ld.param.v4.b32 {%r213, %r214, %r215, %r216}, [nvvm_tcgen05_st_32x32b_unpack_param_8+160];
-; CHECK-NEXT: ld.param.v4.b32 {%r217, %r218, %r219, %r220}, [nvvm_tcgen05_st_32x32b_unpack_param_8+144];
-; CHECK-NEXT: ld.param.v4.b32 {%r221, %r222, %r223, %r224}, [nvvm_tcgen05_st_32x32b_unpack_param_8+128];
-; CHECK-NEXT: ld.param.v4.b32 {%r225, %r226, %r227, %r228}, [nvvm_tcgen05_st_32x32b_unpack_param_8+112];
-; CHECK-NEXT: ld.param.v4.b32 {%r229, %r230, %r231, %r232}, [nvvm_tcgen05_st_32x32b_unpack_param_8+96];
-; CHECK-NEXT: ld.param.v4.b32 {%r233, %r234, %r235, %r236}, [nvvm_tcgen05_st_32x32b_unpack_param_8+80];
-; CHECK-NEXT: ld.param.v4.b32 {%r237, %r238, %r239, %r240}, [nvvm_tcgen05_st_32x32b_unpack_param_8+64];
-; CHECK-NEXT: ld.param.v4.b32 {%r241, %r242, %r243, %r244}, [nvvm_tcgen05_st_32x32b_unpack_param_8+48];
-; CHECK-NEXT: ld.param.v4.b32 {%r245, %r246, %r247, %r248}, [nvvm_tcgen05_st_32x32b_unpack_param_8+32];
-; CHECK-NEXT: ld.param.v4.b32 {%r249, %r250, %r251, %r252}, [nvvm_tcgen05_st_32x32b_unpack_param_8+16];
-; CHECK-NEXT: ld.param.v4.b32 {%r253, %r254, %r255, %r256}, [nvvm_tcgen05_st_32x32b_unpack_param_8];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r129, %r130, %r131, %r132}, [nvvm_tcgen05_st_32x32b_unpack_param_8+496];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r133, %r134, %r135, %r136}, [nvvm_tcgen05_st_32x32b_unpack_param_8+480];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r137, %r138, %r139, %r140}, [nvvm_tcgen05_st_32x32b_unpack_param_8+464];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r141, %r142, %r143, %r144}, [nvvm_tcgen05_st_32x32b_unpack_param_8+448];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r145, %r146, %r147, %r148}, [nvvm_tcgen05_st_32x32b_unpack_param_8+432];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r149, %r150, %r151, %r152}, [nvvm_tcgen05_st_32x32b_unpack_param_8+416];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r153, %r154, %r155, %r156}, [nvvm_tcgen05_st_32x32b_unpack_param_8+400];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r157, %r158, %r159, %r160}, [nvvm_tcgen05_st_32x32b_unpack_param_8+384];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r161, %r162, %r163, %r164}, [nvvm_tcgen05_st_32x32b_unpack_param_8+368];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r165, %r166, %r167, %r168}, [nvvm_tcgen05_st_32x32b_unpack_param_8+352];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r169, %r170, %r171, %r172}, [nvvm_tcgen05_st_32x32b_unpack_param_8+336];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r173, %r174, %r175, %r176}, [nvvm_tcgen05_st_32x32b_unpack_param_8+320];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r177, %r178, %r179, %r180}, [nvvm_tcgen05_st_32x32b_unpack_param_8+304];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r181, %r182, %r183, %r184}, [nvvm_tcgen05_st_32x32b_unpack_param_8+288];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r185, %r186, %r187, %r188}, [nvvm_tcgen05_st_32x32b_unpack_param_8+272];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r189, %r190, %r191, %r192}, [nvvm_tcgen05_st_32x32b_unpack_param_8+256];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r193, %r194, %r195, %r196}, [nvvm_tcgen05_st_32x32b_unpack_param_8+240];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r197, %r198, %r199, %r200}, [nvvm_tcgen05_st_32x32b_unpack_param_8+224];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r201, %r202, %r203, %r204}, [nvvm_tcgen05_st_32x32b_unpack_param_8+208];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r205, %r206, %r207, %r208}, [nvvm_tcgen05_st_32x32b_unpack_param_8+192];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r209, %r210, %r211, %r212}, [nvvm_tcgen05_st_32x32b_unpack_param_8+176];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r213, %r214, %r215, %r216}, [nvvm_tcgen05_st_32x32b_unpack_param_8+160];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r217, %r218, %r219, %r220}, [nvvm_tcgen05_st_32x32b_unpack_param_8+144];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r221, %r222, %r223, %r224}, [nvvm_tcgen05_st_32x32b_unpack_param_8+128];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r225, %r226, %r227, %r228}, [nvvm_tcgen05_st_32x32b_unpack_param_8+112];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r229, %r230, %r231, %r232}, [nvvm_tcgen05_st_32x32b_unpack_param_8+96];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r233, %r234, %r235, %r236}, [nvvm_tcgen05_st_32x32b_unpack_param_8+80];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r237, %r238, %r239, %r240}, [nvvm_tcgen05_st_32x32b_unpack_param_8+64];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r241, %r242, %r243, %r244}, [nvvm_tcgen05_st_32x32b_unpack_param_8+48];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r245, %r246, %r247, %r248}, [nvvm_tcgen05_st_32x32b_unpack_param_8+32];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r249, %r250, %r251, %r252}, [nvvm_tcgen05_st_32x32b_unpack_param_8+16];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r253, %r254, %r255, %r256}, [nvvm_tcgen05_st_32x32b_unpack_param_8];
; CHECK-NEXT: tcgen05.st.sync.aligned.32x32b.x128.unpack::16b.b32 [%r1], {%r253, %r254, %r255, %r256, %r249, %r250, %r251, %r252, %r245, %r246, %r247, %r248, %r241, %r242, %r243, %r244, %r237, %r238, %r239, %r240, %r233, %r234, %r235, %r236, %r229, %r230, %r231, %r232, %r225, %r226, %r227, %r228, %r221, %r222, %r223, %r224, %r217, %r218, %r219, %r220, %r213, %r214, %r215, %r216, %r209, %r210, %r211, %r212, %r205, %r206, %r207, %r208, %r201, %r202, %r203, %r204, %r197, %r198, %r199, %r200, %r193, %r194, %r195, %r196, %r189, %r190, %r191, %r192, %r185, %r186, %r187, %r188, %r181, %r182, %r183, %r184, %r177, %r178, %r179, %r180, %r173, %r174, %r175, %r176, %r169, %r170, %r171, %r172, %r165, %r166, %r167, %r168, %r161, %r162, %r163, %r164, %r157, %r158, %r159, %r160, %r153, %r154, %r155, %r156, %r149, %r150, %r151, %r152, %r145, %r146, %r147, %r148, %r141, %r142, %r143, %r144, %r137, %r138, %r139, %r140, %r133, %r134, %r135, %r136, %r129, %r130, %r131, %r132};
; CHECK-NEXT: ret;
tail call void @llvm.nvvm.tcgen05.st.32x32b.x1(ptr addrspace(6) %taddr, <1 x i32> %stv1, i1 1)
@@ -793,79 +793,79 @@ define void @nvvm_tcgen05_st_16x32bx2(ptr addrspace(6) %taddr, <1 x i32> %stv1,
; CHECK-NEXT: .reg .b32 %r<257>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [nvvm_tcgen05_st_16x32bx2_param_0];
-; CHECK-NEXT: ld.param.b32 %r2, [nvvm_tcgen05_st_16x32bx2_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r1, [nvvm_tcgen05_st_16x32bx2_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r2, [nvvm_tcgen05_st_16x32bx2_param_1];
; CHECK-NEXT: tcgen05.st.sync.aligned.16x32bx2.x1.b32 [%r1], 2, {%r2};
-; CHECK-NEXT: ld.param.v2.b32 {%r3, %r4}, [nvvm_tcgen05_st_16x32bx2_param_2];
+; CHECK-NEXT: ld.param::func.v2.b32 {%r3, %r4}, [nvvm_tcgen05_st_16x32bx2_param_2];
; CHECK-NEXT: tcgen05.st.sync.aligned.16x32bx2.x2.b32 [%r1], 2, {%r3, %r4};
-; CHECK-NEXT: ld.param.v4.b32 {%r5, %r6, %r7, %r8}, [nvvm_tcgen05_st_16x32bx2_param_3];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r5, %r6, %r7, %r8}, [nvvm_tcgen05_st_16x32bx2_param_3];
; CHECK-NEXT: tcgen05.st.sync.aligned.16x32bx2.x4.b32 [%r1], 2, {%r5, %r6, %r7, %r8};
-; CHECK-NEXT: ld.param.v4.b32 {%r9, %r10, %r11, %r12}, [nvvm_tcgen05_st_16x32bx2_param_4+16];
-; CHECK-NEXT: ld.param.v4.b32 {%r13, %r14, %r15, %r16}, [nvvm_tcgen05_st_16x32bx2_param_4];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r9, %r10, %r11, %r12}, [nvvm_tcgen05_st_16x32bx2_param_4+16];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r13, %r14, %r15, %r16}, [nvvm_tcgen05_st_16x32bx2_param_4];
; CHECK-NEXT: tcgen05.st.sync.aligned.16x32bx2.x8.b32 [%r1], 2, {%r13, %r14, %r15, %r16, %r9, %r10, %r11, %r12};
-; CHECK-NEXT: ld.param.v4.b32 {%r17, %r18, %r19, %r20}, [nvvm_tcgen05_st_16x32bx2_param_5+48];
-; CHECK-NEXT: ld.param.v4.b32 {%r21, %r22, %r23, %r24}, [nvvm_tcgen05_st_16x32bx2_param_5+32];
-; CHECK-NEXT: ld.param.v4.b32 {%r25, %r26, %r27, %r28}, [nvvm_tcgen05_st_16x32bx2_param_5+16];
-; CHECK-NEXT: ld.param.v4.b32 {%r29, %r30, %r31, %r32}, [nvvm_tcgen05_st_16x32bx2_param_5];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r17, %r18, %r19, %r20}, [nvvm_tcgen05_st_16x32bx2_param_5+48];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r21, %r22, %r23, %r24}, [nvvm_tcgen05_st_16x32bx2_param_5+32];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r25, %r26, %r27, %r28}, [nvvm_tcgen05_st_16x32bx2_param_5+16];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r29, %r30, %r31, %r32}, [nvvm_tcgen05_st_16x32bx2_param_5];
; CHECK-NEXT: tcgen05.st.sync.aligned.16x32bx2.x16.b32 [%r1], 2, {%r29, %r30, %r31, %r32, %r25, %r26, %r27, %r28, %r21, %r22, %r23, %r24, %r17, %r18, %r19, %r20};
-; CHECK-NEXT: ld.param.v4.b32 {%r33, %r34, %r35, %r36}, [nvvm_tcgen05_st_16x32bx2_param_6+112];
-; CHECK-NEXT: ld.param.v4.b32 {%r37, %r38, %r39, %r40}, [nvvm_tcgen05_st_16x32bx2_param_6+96];
-; CHECK-NEXT: ld.param.v4.b32 {%r41, %r42, %r43, %r44}, [nvvm_tcgen05_st_16x32bx2_param_6+80];
-; CHECK-NEXT: ld.param.v4.b32 {%r45, %r46, %r47, %r48}, [nvvm_tcgen05_st_16x32bx2_param_6+64];
-; CHECK-NEXT: ld.param.v4.b32 {%r49, %r50, %r51, %r52}, [nvvm_tcgen05_st_16x32bx2_param_6+48];
-; CHECK-NEXT: ld.param.v4.b32 {%r53, %r54, %r55, %r56}, [nvvm_tcgen05_st_16x32bx2_param_6+32];
-; CHECK-NEXT: ld.param.v4.b32 {%r57, %r58, %r59, %r60}, [nvvm_tcgen05_st_16x32bx2_param_6+16];
-; CHECK-NEXT: ld.param.v4.b32 {%r61, %r62, %r63, %r64}, [nvvm_tcgen05_st_16x32bx2_param_6];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r33, %r34, %r35, %r36}, [nvvm_tcgen05_st_16x32bx2_param_6+112];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r37, %r38, %r39, %r40}, [nvvm_tcgen05_st_16x32bx2_param_6+96];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r41, %r42, %r43, %r44}, [nvvm_tcgen05_st_16x32bx2_param_6+80];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r45, %r46, %r47, %r48}, [nvvm_tcgen05_st_16x32bx2_param_6+64];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r49, %r50, %r51, %r52}, [nvvm_tcgen05_st_16x32bx2_param_6+48];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r53, %r54, %r55, %r56}, [nvvm_tcgen05_st_16x32bx2_param_6+32];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r57, %r58, %r59, %r60}, [nvvm_tcgen05_st_16x32bx2_param_6+16];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r61, %r62, %r63, %r64}, [nvvm_tcgen05_st_16x32bx2_param_6];
; CHECK-NEXT: tcgen05.st.sync.aligned.16x32bx2.x32.b32 [%r1], 2, {%r61, %r62, %r63, %r64, %r57, %r58, %r59, %r60, %r53, %r54, %r55, %r56, %r49, %r50, %r51, %r52, %r45, %r46, %r47, %r48, %r41, %r42, %r43, %r44, %r37, %r38, %r39, %r40, %r33, %r34, %r35, %r36};
-; CHECK-NEXT: ld.param.v4.b32 {%r65, %r66, %r67, %r68}, [nvvm_tcgen05_st_16x32bx2_param_7+240];
-; CHECK-NEXT: ld.param.v4.b32 {%r69, %r70, %r71, %r72}, [nvvm_tcgen05_st_16x32bx2_param_7+224];
-; CHECK-NEXT: ld.param.v4.b32 {%r73, %r74, %r75, %r76}, [nvvm_tcgen05_st_16x32bx2_param_7+208];
-; CHECK-NEXT: ld.param.v4.b32 {%r77, %r78, %r79, %r80}, [nvvm_tcgen05_st_16x32bx2_param_7+192];
-; CHECK-NEXT: ld.param.v4.b32 {%r81, %r82, %r83, %r84}, [nvvm_tcgen05_st_16x32bx2_param_7+176];
-; CHECK-NEXT: ld.param.v4.b32 {%r85, %r86, %r87, %r88}, [nvvm_tcgen05_st_16x32bx2_param_7+160];
-; CHECK-NEXT: ld.param.v4.b32 {%r89, %r90, %r91, %r92}, [nvvm_tcgen05_st_16x32bx2_param_7+144];
-; CHECK-NEXT: ld.param.v4.b32 {%r93, %r94, %r95, %r96}, [nvvm_tcgen05_st_16x32bx2_param_7+128];
-; CHECK-NEXT: ld.param.v4.b32 {%r97, %r98, %r99, %r100}, [nvvm_tcgen05_st_16x32bx2_param_7+112];
-; CHECK-NEXT: ld.param.v4.b32 {%r101, %r102, %r103, %r104}, [nvvm_tcgen05_st_16x32bx2_param_7+96];
-; CHECK-NEXT: ld.param.v4.b32 {%r105, %r106, %r107, %r108}, [nvvm_tcgen05_st_16x32bx2_param_7+80];
-; CHECK-NEXT: ld.param.v4.b32 {%r109, %r110, %r111, %r112}, [nvvm_tcgen05_st_16x32bx2_param_7+64];
-; CHECK-NEXT: ld.param.v4.b32 {%r113, %r114, %r115, %r116}, [nvvm_tcgen05_st_16x32bx2_param_7+48];
-; CHECK-NEXT: ld.param.v4.b32 {%r117, %r118, %r119, %r120}, [nvvm_tcgen05_st_16x32bx2_param_7+32];
-; CHECK-NEXT: ld.param.v4.b32 {%r121, %r122, %r123, %r124}, [nvvm_tcgen05_st_16x32bx2_param_7+16];
-; CHECK-NEXT: ld.param.v4.b32 {%r125, %r126, %r127, %r128}, [nvvm_tcgen05_st_16x32bx2_param_7];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r65, %r66, %r67, %r68}, [nvvm_tcgen05_st_16x32bx2_param_7+240];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r69, %r70, %r71, %r72}, [nvvm_tcgen05_st_16x32bx2_param_7+224];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r73, %r74, %r75, %r76}, [nvvm_tcgen05_st_16x32bx2_param_7+208];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r77, %r78, %r79, %r80}, [nvvm_tcgen05_st_16x32bx2_param_7+192];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r81, %r82, %r83, %r84}, [nvvm_tcgen05_st_16x32bx2_param_7+176];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r85, %r86, %r87, %r88}, [nvvm_tcgen05_st_16x32bx2_param_7+160];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r89, %r90, %r91, %r92}, [nvvm_tcgen05_st_16x32bx2_param_7+144];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r93, %r94, %r95, %r96}, [nvvm_tcgen05_st_16x32bx2_param_7+128];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r97, %r98, %r99, %r100}, [nvvm_tcgen05_st_16x32bx2_param_7+112];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r101, %r102, %r103, %r104}, [nvvm_tcgen05_st_16x32bx2_param_7+96];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r105, %r106, %r107, %r108}, [nvvm_tcgen05_st_16x32bx2_param_7+80];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r109, %r110, %r111, %r112}, [nvvm_tcgen05_st_16x32bx2_param_7+64];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r113, %r114, %r115, %r116}, [nvvm_tcgen05_st_16x32bx2_param_7+48];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r117, %r118, %r119, %r120}, [nvvm_tcgen05_st_16x32bx2_param_7+32];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r121, %r122, %r123, %r124}, [nvvm_tcgen05_st_16x32bx2_param_7+16];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r125, %r126, %r127, %r128}, [nvvm_tcgen05_st_16x32bx2_param_7];
; CHECK-NEXT: tcgen05.st.sync.aligned.16x32bx2.x64.b32 [%r1], 2, {%r125, %r126, %r127, %r128, %r121, %r122, %r123, %r124, %r117, %r118, %r119, %r120, %r113, %r114, %r115, %r116, %r109, %r110, %r111, %r112, %r105, %r106, %r107, %r108, %r101, %r102, %r103, %r104, %r97, %r98, %r99, %r100, %r93, %r94, %r95, %r96, %r89, %r90, %r91, %r92, %r85, %r86, %r87, %r88, %r81, %r82, %r83, %r84, %r77, %r78, %r79, %r80, %r73, %r74, %r75, %r76, %r69, %r70, %r71, %r72, %r65, %r66, %r67, %r68};
-; CHECK-NEXT: ld.param.v4.b32 {%r129, %r130, %r131, %r132}, [nvvm_tcgen05_st_16x32bx2_param_8+496];
-; CHECK-NEXT: ld.param.v4.b32 {%r133, %r134, %r135, %r136}, [nvvm_tcgen05_st_16x32bx2_param_8+480];
-; CHECK-NEXT: ld.param.v4.b32 {%r137, %r138, %r139, %r140}, [nvvm_tcgen05_st_16x32bx2_param_8+464];
-; CHECK-NEXT: ld.param.v4.b32 {%r141, %r142, %r143, %r144}, [nvvm_tcgen05_st_16x32bx2_param_8+448];
-; CHECK-NEXT: ld.param.v4.b32 {%r145, %r146, %r147, %r148}, [nvvm_tcgen05_st_16x32bx2_param_8+432];
-; CHECK-NEXT: ld.param.v4.b32 {%r149, %r150, %r151, %r152}, [nvvm_tcgen05_st_16x32bx2_param_8+416];
-; CHECK-NEXT: ld.param.v4.b32 {%r153, %r154, %r155, %r156}, [nvvm_tcgen05_st_16x32bx2_param_8+400];
-; CHECK-NEXT: ld.param.v4.b32 {%r157, %r158, %r159, %r160}, [nvvm_tcgen05_st_16x32bx2_param_8+384];
-; CHECK-NEXT: ld.param.v4.b32 {%r161, %r162, %r163, %r164}, [nvvm_tcgen05_st_16x32bx2_param_8+368];
-; CHECK-NEXT: ld.param.v4.b32 {%r165, %r166, %r167, %r168}, [nvvm_tcgen05_st_16x32bx2_param_8+352];
-; CHECK-NEXT: ld.param.v4.b32 {%r169, %r170, %r171, %r172}, [nvvm_tcgen05_st_16x32bx2_param_8+336];
-; CHECK-NEXT: ld.param.v4.b32 {%r173, %r174, %r175, %r176}, [nvvm_tcgen05_st_16x32bx2_param_8+320];
-; CHECK-NEXT: ld.param.v4.b32 {%r177, %r178, %r179, %r180}, [nvvm_tcgen05_st_16x32bx2_param_8+304];
-; CHECK-NEXT: ld.param.v4.b32 {%r181, %r182, %r183, %r184}, [nvvm_tcgen05_st_16x32bx2_param_8+288];
-; CHECK-NEXT: ld.param.v4.b32 {%r185, %r186, %r187, %r188}, [nvvm_tcgen05_st_16x32bx2_param_8+272];
-; CHECK-NEXT: ld.param.v4.b32 {%r189, %r190, %r191, %r192}, [nvvm_tcgen05_st_16x32bx2_param_8+256];
-; CHECK-NEXT: ld.param.v4.b32 {%r193, %r194, %r195, %r196}, [nvvm_tcgen05_st_16x32bx2_param_8+240];
-; CHECK-NEXT: ld.param.v4.b32 {%r197, %r198, %r199, %r200}, [nvvm_tcgen05_st_16x32bx2_param_8+224];
-; CHECK-NEXT: ld.param.v4.b32 {%r201, %r202, %r203, %r204}, [nvvm_tcgen05_st_16x32bx2_param_8+208];
-; CHECK-NEXT: ld.param.v4.b32 {%r205, %r206, %r207, %r208}, [nvvm_tcgen05_st_16x32bx2_param_8+192];
-; CHECK-NEXT: ld.param.v4.b32 {%r209, %r210, %r211, %r212}, [nvvm_tcgen05_st_16x32bx2_param_8+176];
-; CHECK-NEXT: ld.param.v4.b32 {%r213, %r214, %r215, %r216}, [nvvm_tcgen05_st_16x32bx2_param_8+160];
-; CHECK-NEXT: ld.param.v4.b32 {%r217, %r218, %r219, %r220}, [nvvm_tcgen05_st_16x32bx2_param_8+144];
-; CHECK-NEXT: ld.param.v4.b32 {%r221, %r222, %r223, %r224}, [nvvm_tcgen05_st_16x32bx2_param_8+128];
-; CHECK-NEXT: ld.param.v4.b32 {%r225, %r226, %r227, %r228}, [nvvm_tcgen05_st_16x32bx2_param_8+112];
-; CHECK-NEXT: ld.param.v4.b32 {%r229, %r230, %r231, %r232}, [nvvm_tcgen05_st_16x32bx2_param_8+96];
-; CHECK-NEXT: ld.param.v4.b32 {%r233, %r234, %r235, %r236}, [nvvm_tcgen05_st_16x32bx2_param_8+80];
-; CHECK-NEXT: ld.param.v4.b32 {%r237, %r238, %r239, %r240}, [nvvm_tcgen05_st_16x32bx2_param_8+64];
-; CHECK-NEXT: ld.param.v4.b32 {%r241, %r242, %r243, %r244}, [nvvm_tcgen05_st_16x32bx2_param_8+48];
-; CHECK-NEXT: ld.param.v4.b32 {%r245, %r246, %r247, %r248}, [nvvm_tcgen05_st_16x32bx2_param_8+32];
-; CHECK-NEXT: ld.param.v4.b32 {%r249, %r250, %r251, %r252}, [nvvm_tcgen05_st_16x32bx2_param_8+16];
-; CHECK-NEXT: ld.param.v4.b32 {%r253, %r254, %r255, %r256}, [nvvm_tcgen05_st_16x32bx2_param_8];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r129, %r130, %r131, %r132}, [nvvm_tcgen05_st_16x32bx2_param_8+496];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r133, %r134, %r135, %r136}, [nvvm_tcgen05_st_16x32bx2_param_8+480];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r137, %r138, %r139, %r140}, [nvvm_tcgen05_st_16x32bx2_param_8+464];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r141, %r142, %r143, %r144}, [nvvm_tcgen05_st_16x32bx2_param_8+448];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r145, %r146, %r147, %r148}, [nvvm_tcgen05_st_16x32bx2_param_8+432];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r149, %r150, %r151, %r152}, [nvvm_tcgen05_st_16x32bx2_param_8+416];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r153, %r154, %r155, %r156}, [nvvm_tcgen05_st_16x32bx2_param_8+400];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r157, %r158, %r159, %r160}, [nvvm_tcgen05_st_16x32bx2_param_8+384];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r161, %r162, %r163, %r164}, [nvvm_tcgen05_st_16x32bx2_param_8+368];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r165, %r166, %r167, %r168}, [nvvm_tcgen05_st_16x32bx2_param_8+352];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r169, %r170, %r171, %r172}, [nvvm_tcgen05_st_16x32bx2_param_8+336];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r173, %r174, %r175, %r176}, [nvvm_tcgen05_st_16x32bx2_param_8+320];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r177, %r178, %r179, %r180}, [nvvm_tcgen05_st_16x32bx2_param_8+304];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r181, %r182, %r183, %r184}, [nvvm_tcgen05_st_16x32bx2_param_8+288];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r185, %r186, %r187, %r188}, [nvvm_tcgen05_st_16x32bx2_param_8+272];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r189, %r190, %r191, %r192}, [nvvm_tcgen05_st_16x32bx2_param_8+256];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r193, %r194, %r195, %r196}, [nvvm_tcgen05_st_16x32bx2_param_8+240];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r197, %r198, %r199, %r200}, [nvvm_tcgen05_st_16x32bx2_param_8+224];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r201, %r202, %r203, %r204}, [nvvm_tcgen05_st_16x32bx2_param_8+208];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r205, %r206, %r207, %r208}, [nvvm_tcgen05_st_16x32bx2_param_8+192];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r209, %r210, %r211, %r212}, [nvvm_tcgen05_st_16x32bx2_param_8+176];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r213, %r214, %r215, %r216}, [nvvm_tcgen05_st_16x32bx2_param_8+160];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r217, %r218, %r219, %r220}, [nvvm_tcgen05_st_16x32bx2_param_8+144];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r221, %r222, %r223, %r224}, [nvvm_tcgen05_st_16x32bx2_param_8+128];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r225, %r226, %r227, %r228}, [nvvm_tcgen05_st_16x32bx2_param_8+112];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r229, %r230, %r231, %r232}, [nvvm_tcgen05_st_16x32bx2_param_8+96];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r233, %r234, %r235, %r236}, [nvvm_tcgen05_st_16x32bx2_param_8+80];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r237, %r238, %r239, %r240}, [nvvm_tcgen05_st_16x32bx2_param_8+64];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r241, %r242, %r243, %r244}, [nvvm_tcgen05_st_16x32bx2_param_8+48];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r245, %r246, %r247, %r248}, [nvvm_tcgen05_st_16x32bx2_param_8+32];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r249, %r250, %r251, %r252}, [nvvm_tcgen05_st_16x32bx2_param_8+16];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r253, %r254, %r255, %r256}, [nvvm_tcgen05_st_16x32bx2_param_8];
; CHECK-NEXT: tcgen05.st.sync.aligned.16x32bx2.x128.b32 [%r1], 2, {%r253, %r254, %r255, %r256, %r249, %r250, %r251, %r252, %r245, %r246, %r247, %r248, %r241, %r242, %r243, %r244, %r237, %r238, %r239, %r240, %r233, %r234, %r235, %r236, %r229, %r230, %r231, %r232, %r225, %r226, %r227, %r228, %r221, %r222, %r223, %r224, %r217, %r218, %r219, %r220, %r213, %r214, %r215, %r216, %r209, %r210, %r211, %r212, %r205, %r206, %r207, %r208, %r201, %r202, %r203, %r204, %r197, %r198, %r199, %r200, %r193, %r194, %r195, %r196, %r189, %r190, %r191, %r192, %r185, %r186, %r187, %r188, %r181, %r182, %r183, %r184, %r177, %r178, %r179, %r180, %r173, %r174, %r175, %r176, %r169, %r170, %r171, %r172, %r165, %r166, %r167, %r168, %r161, %r162, %r163, %r164, %r157, %r158, %r159, %r160, %r153, %r154, %r155, %r156, %r149, %r150, %r151, %r152, %r145, %r146, %r147, %r148, %r141, %r142, %r143, %r144, %r137, %r138, %r139, %r140, %r133, %r134, %r135, %r136, %r129, %r130, %r131, %r132};
; CHECK-NEXT: ret;
tail call void @llvm.nvvm.tcgen05.st.16x32bx2.x1(ptr addrspace(6) %taddr, i64 2, <1 x i32> %stv1, i1 0)
@@ -893,79 +893,79 @@ define void @nvvm_tcgen05_st_16x32bx2_unpack(ptr addrspace(6) %taddr, <1 x i32>
; CHECK-NEXT: .reg .b32 %r<257>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [nvvm_tcgen05_st_16x32bx2_unpack_param_0];
-; CHECK-NEXT: ld.param.b32 %r2, [nvvm_tcgen05_st_16x32bx2_unpack_param_1];
+; CHECK-NEXT: ld.param::func.b32 %r1, [nvvm_tcgen05_st_16x32bx2_unpack_param_0];
+; CHECK-NEXT: ld.param::func.b32 %r2, [nvvm_tcgen05_st_16x32bx2_unpack_param_1];
; CHECK-NEXT: tcgen05.st.sync.aligned.16x32bx2.x1.unpack::16b.b32 [%r1], 2, {%r2};
-; CHECK-NEXT: ld.param.v2.b32 {%r3, %r4}, [nvvm_tcgen05_st_16x32bx2_unpack_param_2];
+; CHECK-NEXT: ld.param::func.v2.b32 {%r3, %r4}, [nvvm_tcgen05_st_16x32bx2_unpack_param_2];
; CHECK-NEXT: tcgen05.st.sync.aligned.16x32bx2.x2.unpack::16b.b32 [%r1], 2, {%r3, %r4};
-; CHECK-NEXT: ld.param.v4.b32 {%r5, %r6, %r7, %r8}, [nvvm_tcgen05_st_16x32bx2_unpack_param_3];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r5, %r6, %r7, %r8}, [nvvm_tcgen05_st_16x32bx2_unpack_param_3];
; CHECK-NEXT: tcgen05.st.sync.aligned.16x32bx2.x4.unpack::16b.b32 [%r1], 2, {%r5, %r6, %r7, %r8};
-; CHECK-NEXT: ld.param.v4.b32 {%r9, %r10, %r11, %r12}, [nvvm_tcgen05_st_16x32bx2_unpack_param_4+16];
-; CHECK-NEXT: ld.param.v4.b32 {%r13, %r14, %r15, %r16}, [nvvm_tcgen05_st_16x32bx2_unpack_param_4];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r9, %r10, %r11, %r12}, [nvvm_tcgen05_st_16x32bx2_unpack_param_4+16];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r13, %r14, %r15, %r16}, [nvvm_tcgen05_st_16x32bx2_unpack_param_4];
; CHECK-NEXT: tcgen05.st.sync.aligned.16x32bx2.x8.unpack::16b.b32 [%r1], 2, {%r13, %r14, %r15, %r16, %r9, %r10, %r11, %r12};
-; CHECK-NEXT: ld.param.v4.b32 {%r17, %r18, %r19, %r20}, [nvvm_tcgen05_st_16x32bx2_unpack_param_5+48];
-; CHECK-NEXT: ld.param.v4.b32 {%r21, %r22, %r23, %r24}, [nvvm_tcgen05_st_16x32bx2_unpack_param_5+32];
-; CHECK-NEXT: ld.param.v4.b32 {%r25, %r26, %r27, %r28}, [nvvm_tcgen05_st_16x32bx2_unpack_param_5+16];
-; CHECK-NEXT: ld.param.v4.b32 {%r29, %r30, %r31, %r32}, [nvvm_tcgen05_st_16x32bx2_unpack_param_5];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r17, %r18, %r19, %r20}, [nvvm_tcgen05_st_16x32bx2_unpack_param_5+48];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r21, %r22, %r23, %r24}, [nvvm_tcgen05_st_16x32bx2_unpack_param_5+32];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r25, %r26, %r27, %r28}, [nvvm_tcgen05_st_16x32bx2_unpack_param_5+16];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r29, %r30, %r31, %r32}, [nvvm_tcgen05_st_16x32bx2_unpack_param_5];
; CHECK-NEXT: tcgen05.st.sync.aligned.16x32bx2.x16.unpack::16b.b32 [%r1], 2, {%r29, %r30, %r31, %r32, %r25, %r26, %r27, %r28, %r21, %r22, %r23, %r24, %r17, %r18, %r19, %r20};
-; CHECK-NEXT: ld.param.v4.b32 {%r33, %r34, %r35, %r36}, [nvvm_tcgen05_st_16x32bx2_unpack_param_6+112];
-; CHECK-NEXT: ld.param.v4.b32 {%r37, %r38, %r39, %r40}, [nvvm_tcgen05_st_16x32bx2_unpack_param_6+96];
-; CHECK-NEXT: ld.param.v4.b32 {%r41, %r42, %r43, %r44}, [nvvm_tcgen05_st_16x32bx2_unpack_param_6+80];
-; CHECK-NEXT: ld.param.v4.b32 {%r45, %r46, %r47, %r48}, [nvvm_tcgen05_st_16x32bx2_unpack_param_6+64];
-; CHECK-NEXT: ld.param.v4.b32 {%r49, %r50, %r51, %r52}, [nvvm_tcgen05_st_16x32bx2_unpack_param_6+48];
-; CHECK-NEXT: ld.param.v4.b32 {%r53, %r54, %r55, %r56}, [nvvm_tcgen05_st_16x32bx2_unpack_param_6+32];
-; CHECK-NEXT: ld.param.v4.b32 {%r57, %r58, %r59, %r60}, [nvvm_tcgen05_st_16x32bx2_unpack_param_6+16];
-; CHECK-NEXT: ld.param.v4.b32 {%r61, %r62, %r63, %r64}, [nvvm_tcgen05_st_16x32bx2_unpack_param_6];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r33, %r34, %r35, %r36}, [nvvm_tcgen05_st_16x32bx2_unpack_param_6+112];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r37, %r38, %r39, %r40}, [nvvm_tcgen05_st_16x32bx2_unpack_param_6+96];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r41, %r42, %r43, %r44}, [nvvm_tcgen05_st_16x32bx2_unpack_param_6+80];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r45, %r46, %r47, %r48}, [nvvm_tcgen05_st_16x32bx2_unpack_param_6+64];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r49, %r50, %r51, %r52}, [nvvm_tcgen05_st_16x32bx2_unpack_param_6+48];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r53, %r54, %r55, %r56}, [nvvm_tcgen05_st_16x32bx2_unpack_param_6+32];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r57, %r58, %r59, %r60}, [nvvm_tcgen05_st_16x32bx2_unpack_param_6+16];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r61, %r62, %r63, %r64}, [nvvm_tcgen05_st_16x32bx2_unpack_param_6];
; CHECK-NEXT: tcgen05.st.sync.aligned.16x32bx2.x32.unpack::16b.b32 [%r1], 2, {%r61, %r62, %r63, %r64, %r57, %r58, %r59, %r60, %r53, %r54, %r55, %r56, %r49, %r50, %r51, %r52, %r45, %r46, %r47, %r48, %r41, %r42, %r43, %r44, %r37, %r38, %r39, %r40, %r33, %r34, %r35, %r36};
-; CHECK-NEXT: ld.param.v4.b32 {%r65, %r66, %r67, %r68}, [nvvm_tcgen05_st_16x32bx2_unpack_param_7+240];
-; CHECK-NEXT: ld.param.v4.b32 {%r69, %r70, %r71, %r72}, [nvvm_tcgen05_st_16x32bx2_unpack_param_7+224];
-; CHECK-NEXT: ld.param.v4.b32 {%r73, %r74, %r75, %r76}, [nvvm_tcgen05_st_16x32bx2_unpack_param_7+208];
-; CHECK-NEXT: ld.param.v4.b32 {%r77, %r78, %r79, %r80}, [nvvm_tcgen05_st_16x32bx2_unpack_param_7+192];
-; CHECK-NEXT: ld.param.v4.b32 {%r81, %r82, %r83, %r84}, [nvvm_tcgen05_st_16x32bx2_unpack_param_7+176];
-; CHECK-NEXT: ld.param.v4.b32 {%r85, %r86, %r87, %r88}, [nvvm_tcgen05_st_16x32bx2_unpack_param_7+160];
-; CHECK-NEXT: ld.param.v4.b32 {%r89, %r90, %r91, %r92}, [nvvm_tcgen05_st_16x32bx2_unpack_param_7+144];
-; CHECK-NEXT: ld.param.v4.b32 {%r93, %r94, %r95, %r96}, [nvvm_tcgen05_st_16x32bx2_unpack_param_7+128];
-; CHECK-NEXT: ld.param.v4.b32 {%r97, %r98, %r99, %r100}, [nvvm_tcgen05_st_16x32bx2_unpack_param_7+112];
-; CHECK-NEXT: ld.param.v4.b32 {%r101, %r102, %r103, %r104}, [nvvm_tcgen05_st_16x32bx2_unpack_param_7+96];
-; CHECK-NEXT: ld.param.v4.b32 {%r105, %r106, %r107, %r108}, [nvvm_tcgen05_st_16x32bx2_unpack_param_7+80];
-; CHECK-NEXT: ld.param.v4.b32 {%r109, %r110, %r111, %r112}, [nvvm_tcgen05_st_16x32bx2_unpack_param_7+64];
-; CHECK-NEXT: ld.param.v4.b32 {%r113, %r114, %r115, %r116}, [nvvm_tcgen05_st_16x32bx2_unpack_param_7+48];
-; CHECK-NEXT: ld.param.v4.b32 {%r117, %r118, %r119, %r120}, [nvvm_tcgen05_st_16x32bx2_unpack_param_7+32];
-; CHECK-NEXT: ld.param.v4.b32 {%r121, %r122, %r123, %r124}, [nvvm_tcgen05_st_16x32bx2_unpack_param_7+16];
-; CHECK-NEXT: ld.param.v4.b32 {%r125, %r126, %r127, %r128}, [nvvm_tcgen05_st_16x32bx2_unpack_param_7];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r65, %r66, %r67, %r68}, [nvvm_tcgen05_st_16x32bx2_unpack_param_7+240];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r69, %r70, %r71, %r72}, [nvvm_tcgen05_st_16x32bx2_unpack_param_7+224];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r73, %r74, %r75, %r76}, [nvvm_tcgen05_st_16x32bx2_unpack_param_7+208];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r77, %r78, %r79, %r80}, [nvvm_tcgen05_st_16x32bx2_unpack_param_7+192];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r81, %r82, %r83, %r84}, [nvvm_tcgen05_st_16x32bx2_unpack_param_7+176];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r85, %r86, %r87, %r88}, [nvvm_tcgen05_st_16x32bx2_unpack_param_7+160];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r89, %r90, %r91, %r92}, [nvvm_tcgen05_st_16x32bx2_unpack_param_7+144];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r93, %r94, %r95, %r96}, [nvvm_tcgen05_st_16x32bx2_unpack_param_7+128];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r97, %r98, %r99, %r100}, [nvvm_tcgen05_st_16x32bx2_unpack_param_7+112];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r101, %r102, %r103, %r104}, [nvvm_tcgen05_st_16x32bx2_unpack_param_7+96];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r105, %r106, %r107, %r108}, [nvvm_tcgen05_st_16x32bx2_unpack_param_7+80];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r109, %r110, %r111, %r112}, [nvvm_tcgen05_st_16x32bx2_unpack_param_7+64];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r113, %r114, %r115, %r116}, [nvvm_tcgen05_st_16x32bx2_unpack_param_7+48];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r117, %r118, %r119, %r120}, [nvvm_tcgen05_st_16x32bx2_unpack_param_7+32];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r121, %r122, %r123, %r124}, [nvvm_tcgen05_st_16x32bx2_unpack_param_7+16];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r125, %r126, %r127, %r128}, [nvvm_tcgen05_st_16x32bx2_unpack_param_7];
; CHECK-NEXT: tcgen05.st.sync.aligned.16x32bx2.x64.unpack::16b.b32 [%r1], 2, {%r125, %r126, %r127, %r128, %r121, %r122, %r123, %r124, %r117, %r118, %r119, %r120, %r113, %r114, %r115, %r116, %r109, %r110, %r111, %r112, %r105, %r106, %r107, %r108, %r101, %r102, %r103, %r104, %r97, %r98, %r99, %r100, %r93, %r94, %r95, %r96, %r89, %r90, %r91, %r92, %r85, %r86, %r87, %r88, %r81, %r82, %r83, %r84, %r77, %r78, %r79, %r80, %r73, %r74, %r75, %r76, %r69, %r70, %r71, %r72, %r65, %r66, %r67, %r68};
-; CHECK-NEXT: ld.param.v4.b32 {%r129, %r130, %r131, %r132}, [nvvm_tcgen05_st_16x32bx2_unpack_param_8+496];
-; CHECK-NEXT: ld.param.v4.b32 {%r133, %r134, %r135, %r136}, [nvvm_tcgen05_st_16x32bx2_unpack_param_8+480];
-; CHECK-NEXT: ld.param.v4.b32 {%r137, %r138, %r139, %r140}, [nvvm_tcgen05_st_16x32bx2_unpack_param_8+464];
-; CHECK-NEXT: ld.param.v4.b32 {%r141, %r142, %r143, %r144}, [nvvm_tcgen05_st_16x32bx2_unpack_param_8+448];
-; CHECK-NEXT: ld.param.v4.b32 {%r145, %r146, %r147, %r148}, [nvvm_tcgen05_st_16x32bx2_unpack_param_8+432];
-; CHECK-NEXT: ld.param.v4.b32 {%r149, %r150, %r151, %r152}, [nvvm_tcgen05_st_16x32bx2_unpack_param_8+416];
-; CHECK-NEXT: ld.param.v4.b32 {%r153, %r154, %r155, %r156}, [nvvm_tcgen05_st_16x32bx2_unpack_param_8+400];
-; CHECK-NEXT: ld.param.v4.b32 {%r157, %r158, %r159, %r160}, [nvvm_tcgen05_st_16x32bx2_unpack_param_8+384];
-; CHECK-NEXT: ld.param.v4.b32 {%r161, %r162, %r163, %r164}, [nvvm_tcgen05_st_16x32bx2_unpack_param_8+368];
-; CHECK-NEXT: ld.param.v4.b32 {%r165, %r166, %r167, %r168}, [nvvm_tcgen05_st_16x32bx2_unpack_param_8+352];
-; CHECK-NEXT: ld.param.v4.b32 {%r169, %r170, %r171, %r172}, [nvvm_tcgen05_st_16x32bx2_unpack_param_8+336];
-; CHECK-NEXT: ld.param.v4.b32 {%r173, %r174, %r175, %r176}, [nvvm_tcgen05_st_16x32bx2_unpack_param_8+320];
-; CHECK-NEXT: ld.param.v4.b32 {%r177, %r178, %r179, %r180}, [nvvm_tcgen05_st_16x32bx2_unpack_param_8+304];
-; CHECK-NEXT: ld.param.v4.b32 {%r181, %r182, %r183, %r184}, [nvvm_tcgen05_st_16x32bx2_unpack_param_8+288];
-; CHECK-NEXT: ld.param.v4.b32 {%r185, %r186, %r187, %r188}, [nvvm_tcgen05_st_16x32bx2_unpack_param_8+272];
-; CHECK-NEXT: ld.param.v4.b32 {%r189, %r190, %r191, %r192}, [nvvm_tcgen05_st_16x32bx2_unpack_param_8+256];
-; CHECK-NEXT: ld.param.v4.b32 {%r193, %r194, %r195, %r196}, [nvvm_tcgen05_st_16x32bx2_unpack_param_8+240];
-; CHECK-NEXT: ld.param.v4.b32 {%r197, %r198, %r199, %r200}, [nvvm_tcgen05_st_16x32bx2_unpack_param_8+224];
-; CHECK-NEXT: ld.param.v4.b32 {%r201, %r202, %r203, %r204}, [nvvm_tcgen05_st_16x32bx2_unpack_param_8+208];
-; CHECK-NEXT: ld.param.v4.b32 {%r205, %r206, %r207, %r208}, [nvvm_tcgen05_st_16x32bx2_unpack_param_8+192];
-; CHECK-NEXT: ld.param.v4.b32 {%r209, %r210, %r211, %r212}, [nvvm_tcgen05_st_16x32bx2_unpack_param_8+176];
-; CHECK-NEXT: ld.param.v4.b32 {%r213, %r214, %r215, %r216}, [nvvm_tcgen05_st_16x32bx2_unpack_param_8+160];
-; CHECK-NEXT: ld.param.v4.b32 {%r217, %r218, %r219, %r220}, [nvvm_tcgen05_st_16x32bx2_unpack_param_8+144];
-; CHECK-NEXT: ld.param.v4.b32 {%r221, %r222, %r223, %r224}, [nvvm_tcgen05_st_16x32bx2_unpack_param_8+128];
-; CHECK-NEXT: ld.param.v4.b32 {%r225, %r226, %r227, %r228}, [nvvm_tcgen05_st_16x32bx2_unpack_param_8+112];
-; CHECK-NEXT: ld.param.v4.b32 {%r229, %r230, %r231, %r232}, [nvvm_tcgen05_st_16x32bx2_unpack_param_8+96];
-; CHECK-NEXT: ld.param.v4.b32 {%r233, %r234, %r235, %r236}, [nvvm_tcgen05_st_16x32bx2_unpack_param_8+80];
-; CHECK-NEXT: ld.param.v4.b32 {%r237, %r238, %r239, %r240}, [nvvm_tcgen05_st_16x32bx2_unpack_param_8+64];
-; CHECK-NEXT: ld.param.v4.b32 {%r241, %r242, %r243, %r244}, [nvvm_tcgen05_st_16x32bx2_unpack_param_8+48];
-; CHECK-NEXT: ld.param.v4.b32 {%r245, %r246, %r247, %r248}, [nvvm_tcgen05_st_16x32bx2_unpack_param_8+32];
-; CHECK-NEXT: ld.param.v4.b32 {%r249, %r250, %r251, %r252}, [nvvm_tcgen05_st_16x32bx2_unpack_param_8+16];
-; CHECK-NEXT: ld.param.v4.b32 {%r253, %r254, %r255, %r256}, [nvvm_tcgen05_st_16x32bx2_unpack_param_8];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r129, %r130, %r131, %r132}, [nvvm_tcgen05_st_16x32bx2_unpack_param_8+496];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r133, %r134, %r135, %r136}, [nvvm_tcgen05_st_16x32bx2_unpack_param_8+480];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r137, %r138, %r139, %r140}, [nvvm_tcgen05_st_16x32bx2_unpack_param_8+464];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r141, %r142, %r143, %r144}, [nvvm_tcgen05_st_16x32bx2_unpack_param_8+448];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r145, %r146, %r147, %r148}, [nvvm_tcgen05_st_16x32bx2_unpack_param_8+432];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r149, %r150, %r151, %r152}, [nvvm_tcgen05_st_16x32bx2_unpack_param_8+416];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r153, %r154, %r155, %r156}, [nvvm_tcgen05_st_16x32bx2_unpack_param_8+400];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r157, %r158, %r159, %r160}, [nvvm_tcgen05_st_16x32bx2_unpack_param_8+384];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r161, %r162, %r163, %r164}, [nvvm_tcgen05_st_16x32bx2_unpack_param_8+368];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r165, %r166, %r167, %r168}, [nvvm_tcgen05_st_16x32bx2_unpack_param_8+352];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r169, %r170, %r171, %r172}, [nvvm_tcgen05_st_16x32bx2_unpack_param_8+336];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r173, %r174, %r175, %r176}, [nvvm_tcgen05_st_16x32bx2_unpack_param_8+320];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r177, %r178, %r179, %r180}, [nvvm_tcgen05_st_16x32bx2_unpack_param_8+304];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r181, %r182, %r183, %r184}, [nvvm_tcgen05_st_16x32bx2_unpack_param_8+288];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r185, %r186, %r187, %r188}, [nvvm_tcgen05_st_16x32bx2_unpack_param_8+272];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r189, %r190, %r191, %r192}, [nvvm_tcgen05_st_16x32bx2_unpack_param_8+256];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r193, %r194, %r195, %r196}, [nvvm_tcgen05_st_16x32bx2_unpack_param_8+240];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r197, %r198, %r199, %r200}, [nvvm_tcgen05_st_16x32bx2_unpack_param_8+224];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r201, %r202, %r203, %r204}, [nvvm_tcgen05_st_16x32bx2_unpack_param_8+208];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r205, %r206, %r207, %r208}, [nvvm_tcgen05_st_16x32bx2_unpack_param_8+192];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r209, %r210, %r211, %r212}, [nvvm_tcgen05_st_16x32bx2_unpack_param_8+176];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r213, %r214, %r215, %r216}, [nvvm_tcgen05_st_16x32bx2_unpack_param_8+160];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r217, %r218, %r219, %r220}, [nvvm_tcgen05_st_16x32bx2_unpack_param_8+144];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r221, %r222, %r223, %r224}, [nvvm_tcgen05_st_16x32bx2_unpack_param_8+128];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r225, %r226, %r227, %r228}, [nvvm_tcgen05_st_16x32bx2_unpack_param_8+112];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r229, %r230, %r231, %r232}, [nvvm_tcgen05_st_16x32bx2_unpack_param_8+96];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r233, %r234, %r235, %r236}, [nvvm_tcgen05_st_16x32bx2_unpack_param_8+80];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r237, %r238, %r239, %r240}, [nvvm_tcgen05_st_16x32bx2_unpack_param_8+64];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r241, %r242, %r243, %r244}, [nvvm_tcgen05_st_16x32bx2_unpack_param_8+48];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r245, %r246, %r247, %r248}, [nvvm_tcgen05_st_16x32bx2_unpack_param_8+32];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r249, %r250, %r251, %r252}, [nvvm_tcgen05_st_16x32bx2_unpack_param_8+16];
+; CHECK-NEXT: ld.param::func.v4.b32 {%r253, %r254, %r255, %r256}, [nvvm_tcgen05_st_16x32bx2_unpack_param_8];
; CHECK-NEXT: tcgen05.st.sync.aligned.16x32bx2.x128.unpack::16b.b32 [%r1], 2, {%r253, %r254, %r255, %r256, %r249, %r250, %r251, %r252, %r245, %r246, %r247, %r248, %r241, %r242, %r243, %r244, %r237, %r238, %r239, %r240, %r233, %r234, %r235, %r236, %r229, %r230, %r231, %r232, %r225, %r226, %r227, %r228, %r221, %r222, %r223, %r224, %r217, %r218, %r219, %r220, %r213, %r214, %r215, %r216, %r209, %r210, %r211, %r212, %r205, %r206, %r207, %r208, %r201, %r202, %r203, %r204, %r197, %r198, %r199, %r200, %r193, %r194, %r195, %r196, %r189, %r190, %r191, %r192, %r185, %r186, %r187, %r188, %r181, %r182, %r183, %r184, %r177, %r178, %r179, %r180, %r173, %r174, %r175, %r176, %r169, %r170, %r171, %r172, %r165, %r166, %r167, %r168, %r161, %r162, %r163, %r164, %r157, %r158, %r159, %r160, %r153, %r154, %r155, %r156, %r149, %r150, %r151, %r152, %r145, %r146, %r147, %r148, %r141, %r142, %r143, %r144, %r137, %r138, %r139, %r140, %r133, %r134, %r135, %r136, %r129, %r130, %r131, %r132};
; CHECK-NEXT: ret;
tail call void @llvm.nvvm.tcgen05.st.16x32bx2.x1(ptr addrspace(6) %taddr, i64 2, <1 x i32> %stv1, i1 1)
diff --git a/llvm/test/CodeGen/NVPTX/tensormap_replace_sm_100a.ll b/llvm/test/CodeGen/NVPTX/tensormap_replace_sm_100a.ll
index 10e74d14c9421..4e4d17fb667ab 100644
--- a/llvm/test/CodeGen/NVPTX/tensormap_replace_sm_100a.ll
+++ b/llvm/test/CodeGen/NVPTX/tensormap_replace_sm_100a.ll
@@ -8,9 +8,9 @@ define void @tensormap_replace_swizzle_atomicity(ptr addrspace(1) %global_addr,
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [tensormap_replace_swizzle_atomicity_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tensormap_replace_swizzle_atomicity_param_0];
; CHECK-NEXT: tensormap.replace.tile.swizzle_atomicity.global.b1024.b32 [%rd1], 0;
-; CHECK-NEXT: ld.param.b64 %rd2, [tensormap_replace_swizzle_atomicity_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tensormap_replace_swizzle_atomicity_param_1];
; CHECK-NEXT: tensormap.replace.tile.swizzle_atomicity.shared::cta.b1024.b32 [%rd2], 0;
; CHECK-NEXT: tensormap.replace.tile.swizzle_atomicity.global.b1024.b32 [%rd1], 1;
; CHECK-NEXT: tensormap.replace.tile.swizzle_atomicity.shared::cta.b1024.b32 [%rd2], 1;
@@ -27,7 +27,7 @@ define void @tensormap_replace_swizzle_atomicity(ptr addrspace(1) %global_addr,
call void @llvm.nvvm.tensormap.replace.swizzle.atomicity.p1(ptr addrspace(1) %global_addr, /* swizzle_atomicity=32B + 8B flip */ i32 2)
call void @llvm.nvvm.tensormap.replace.swizzle.atomicity.p3(ptr addrspace(3) %shared_addr, /* swizzle_atomicity=32B + 8B flip */ i32 2)
-
+
call void @llvm.nvvm.tensormap.replace.swizzle.atomicity.p1(ptr addrspace(1) %global_addr, /* swizzle_atomicity=64B */ i32 3)
call void @llvm.nvvm.tensormap.replace.swizzle.atomicity.p3(ptr addrspace(3) %shared_addr, /* swizzle_atomicity=64B */ i32 3)
ret void
@@ -39,9 +39,9 @@ define void @tensormap_replace_elemtype(ptr addrspace(1) %global_addr, ptr addrs
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [tensormap_replace_elemtype_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tensormap_replace_elemtype_param_0];
; CHECK-NEXT: tensormap.replace.tile.elemtype.global.b1024.b32 [%rd1], 13;
-; CHECK-NEXT: ld.param.b64 %rd2, [tensormap_replace_elemtype_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tensormap_replace_elemtype_param_1];
; CHECK-NEXT: tensormap.replace.tile.elemtype.shared::cta.b1024.b32 [%rd2], 13;
; CHECK-NEXT: tensormap.replace.tile.elemtype.global.b1024.b32 [%rd1], 14;
; CHECK-NEXT: tensormap.replace.tile.elemtype.shared::cta.b1024.b32 [%rd2], 14;
diff --git a/llvm/test/CodeGen/NVPTX/tensormap_replace_sm_103a.ll b/llvm/test/CodeGen/NVPTX/tensormap_replace_sm_103a.ll
index 931fe70a60182..136e0e302f0bd 100644
--- a/llvm/test/CodeGen/NVPTX/tensormap_replace_sm_103a.ll
+++ b/llvm/test/CodeGen/NVPTX/tensormap_replace_sm_103a.ll
@@ -8,9 +8,9 @@ define void @tensormap_replace_swizzle_mode(ptr addrspace(1) %global_addr, ptr a
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd1, [tensormap_replace_swizzle_mode_param_0];
+; CHECK-NEXT: ld.param::func.b64 %rd1, [tensormap_replace_swizzle_mode_param_0];
; CHECK-NEXT: tensormap.replace.tile.swizzle_mode.global.b1024.b32 [%rd1], 4;
-; CHECK-NEXT: ld.param.b64 %rd2, [tensormap_replace_swizzle_mode_param_1];
+; CHECK-NEXT: ld.param::func.b64 %rd2, [tensormap_replace_swizzle_mode_param_1];
; CHECK-NEXT: tensormap.replace.tile.swizzle_mode.shared::cta.b1024.b32 [%rd2], 4;
; CHECK-NEXT: ret;
call void @llvm.nvvm.tensormap.replace.swizzle.mode.p1(ptr addrspace(1) %global_addr, /* swizzle_mode=96B swizzling */ i32 4)
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