[llvm] 57a9c4f - [AMDGPU] VOP1 bf16 instructions read high 16 bit of an inline (#215688)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Aug 11 17:00:18 PDT 2026
Author: Stanislav Mekhanoshin
Date: 2026-08-11T17:00:12-07:00
New Revision: 57a9c4f939e52211dbb2c7dbc0f6091bdb48916d
URL: https://github.com/llvm/llvm-project/commit/57a9c4f939e52211dbb2c7dbc0f6091bdb48916d
DIFF: https://github.com/llvm/llvm-project/commit/57a9c4f939e52211dbb2c7dbc0f6091bdb48916d.diff
LOG: [AMDGPU] VOP1 bf16 instructions read high 16 bit of an inline (#215688)
VOP1 cannot be used in this case and VOP3 shall use OPSEL.
Added:
Modified:
llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cos.bf16.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.bf16.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.log.bf16.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.bf16.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.bf16.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sin.bf16.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sqrt.bf16.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tanh.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
index 04a9ed487d655..7401ff8456cae 100644
--- a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
+++ b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
@@ -710,6 +710,26 @@ bool SIFoldOperandsImpl::updateOperand(FoldCandidate &Fold) const {
if (!TII->isOperandLegal(*MI, OpNo, &New))
return false;
+ if (ST->hasBF16InlineConstFromUpperFP32() &&
+ OpNo ==
+ AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::src0)) {
+ unsigned Opcode = MI->getOpcode();
+ uint8_t OpType = TII->get(Opcode).operands()[OpNo].OperandType;
+ if ((OpType == AMDGPU::OPERAND_REG_IMM_BF16 ||
+ OpType == AMDGPU::OPERAND_REG_INLINE_C_BF16) &&
+ TII->isInlineConstant(*ImmVal, OpType)) {
+ // We can fold it, but we need to set OPSEL
+ int Mod0 =
+ AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0_modifiers);
+ if (Mod0 == -1)
+ return false;
+ MachineOperand &ModOp = MI->getOperand(Mod0);
+ if (ModOp.getImm())
+ return false;
+ ModOp.setImm(SISrcMods::OP_SEL_0);
+ }
+ }
+
Old.ChangeToImmediate(*ImmVal);
return true;
}
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 1e7037a8bfe46..48b97ec2a04ec 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -4912,6 +4912,14 @@ bool SIInstrInfo::isImmOperandLegal(const MCInstrDesc &InstDesc, unsigned OpNo,
OpNo == (unsigned)AMDGPU::getNamedOperandIdx(InstDesc.getOpcode(),
AMDGPU::OpName::src2))
return false;
+
+ if (ST.hasBF16InlineConstFromUpperFP32() && isVOP1(Opc)) {
+ if ((OpInfo.OperandType == AMDGPU::OPERAND_REG_IMM_BF16 ||
+ OpInfo.OperandType == AMDGPU::OPERAND_REG_INLINE_C_BF16) &&
+ isInlineConstant(ImmVal, OpInfo.OperandType))
+ return false;
+ }
+
return RI.opCanUseInlineConstant(OpInfo.OperandType);
}
@@ -5007,8 +5015,7 @@ bool SIInstrInfo::canShrink(const MachineInstr &MI,
hasModifiersSet(MI, AMDGPU::OpName::src1_modifiers)))
return false;
- // We don't need to check src0, all input types are legal, so just make sure
- // src0 isn't using any modifiers.
+ // Make sure src0 isn't using any modifiers.
if (hasModifiersSet(MI, AMDGPU::OpName::src0_modifiers))
return false;
@@ -5016,6 +5023,15 @@ bool SIInstrInfo::canShrink(const MachineInstr &MI,
if (!hasVALU32BitEncoding(MI.getOpcode()))
return false;
+ const MachineOperand *Src0 = getNamedOperand(MI, AMDGPU::OpName::src0);
+ if (Src0 && Src0->isImm()) {
+ unsigned Op32 = AMDGPU::getVOPe32(MI.getOpcode());
+ if (!isImmOperandLegal(
+ get(Op32), AMDGPU::getNamedOperandIdx(Op32, AMDGPU::OpName::src0),
+ *Src0))
+ return false;
+ }
+
// Check output modifiers
return !hasModifiersSet(MI, AMDGPU::OpName::omod) &&
!hasModifiersSet(MI, AMDGPU::OpName::clamp) &&
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cos.bf16.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cos.bf16.ll
index 06ceb1c0999ca..76d66b15ee646 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cos.bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cos.bf16.ll
@@ -47,7 +47,7 @@ define amdgpu_kernel void @cos_bf16_constant_4(ptr addrspace(1) %out) #1 {
; FAKE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
-; FAKE16-NEXT: v_cos_bf16_e32 v0, 4.0
+; FAKE16-NEXT: v_cos_bf16_e64 v0, 4.0 op_sel:[1,0]
; FAKE16-NEXT: v_mov_b32_e32 v1, 0
; FAKE16-NEXT: s_wait_kmcnt 0x0
; FAKE16-NEXT: global_store_b16 v1, v0, s[0:1]
@@ -60,7 +60,7 @@ define amdgpu_kernel void @cos_bf16_constant_4(ptr addrspace(1) %out) #1 {
; REAL16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; REAL16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
-; REAL16-NEXT: v_cos_bf16_e32 v0.l, 4.0
+; REAL16-NEXT: v_cos_bf16_e64 v0.l, 4.0 op_sel:[1,0]
; REAL16-NEXT: v_mov_b32_e32 v1, 0
; REAL16-NEXT: s_wait_kmcnt 0x0
; REAL16-NEXT: global_store_b16 v1, v0, s[0:1]
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.bf16.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.bf16.ll
index 02fdd994a925b..a7363bb521156 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.bf16.ll
@@ -45,7 +45,7 @@ define amdgpu_kernel void @exp_bf16_constant_4(ptr addrspace(1) %out) #1 {
; FAKE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
-; FAKE16-NEXT: v_exp_bf16_e32 v0, 4.0
+; FAKE16-NEXT: v_exp_bf16_e64 v0, 4.0 op_sel:[1,0]
; FAKE16-NEXT: v_mov_b32_e32 v1, 0
; FAKE16-NEXT: s_wait_kmcnt 0x0
; FAKE16-NEXT: global_store_b16 v1, v0, s[0:1]
@@ -58,7 +58,7 @@ define amdgpu_kernel void @exp_bf16_constant_4(ptr addrspace(1) %out) #1 {
; REAL16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; REAL16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
-; REAL16-NEXT: v_exp_bf16_e32 v0.l, 4.0
+; REAL16-NEXT: v_exp_bf16_e64 v0.l, 4.0 op_sel:[1,0]
; REAL16-NEXT: v_mov_b32_e32 v1, 0
; REAL16-NEXT: s_wait_kmcnt 0x0
; REAL16-NEXT: global_store_b16 v1, v0, s[0:1]
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.log.bf16.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.log.bf16.ll
index e21279058014d..b4ae8443763c7 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.log.bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.log.bf16.ll
@@ -45,7 +45,7 @@ define amdgpu_kernel void @log_bf16_constant_4(ptr addrspace(1) %out) #1 {
; FAKE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
-; FAKE16-NEXT: v_log_bf16_e32 v0, 4.0
+; FAKE16-NEXT: v_log_bf16_e64 v0, 4.0 op_sel:[1,0]
; FAKE16-NEXT: v_mov_b32_e32 v1, 0
; FAKE16-NEXT: s_wait_kmcnt 0x0
; FAKE16-NEXT: global_store_b16 v1, v0, s[0:1]
@@ -58,7 +58,7 @@ define amdgpu_kernel void @log_bf16_constant_4(ptr addrspace(1) %out) #1 {
; REAL16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; REAL16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
-; REAL16-NEXT: v_log_bf16_e32 v0.l, 4.0
+; REAL16-NEXT: v_log_bf16_e64 v0.l, 4.0 op_sel:[1,0]
; REAL16-NEXT: v_mov_b32_e32 v1, 0
; REAL16-NEXT: s_wait_kmcnt 0x0
; REAL16-NEXT: global_store_b16 v1, v0, s[0:1]
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.bf16.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.bf16.ll
index 96b29e14af7be..36b238ca185aa 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.bf16.ll
@@ -168,7 +168,7 @@ define amdgpu_kernel void @rcp_bf16_constant_4(ptr addrspace(1) %out) #1 {
; GI-TRUE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GI-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GI-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 nv
-; GI-TRUE16-NEXT: v_rcp_bf16_e32 v0.l, 4.0
+; GI-TRUE16-NEXT: v_rcp_bf16_e64 v0.l, 4.0 op_sel:[1,0]
; GI-TRUE16-NEXT: v_mov_b32_e32 v1, 0
; GI-TRUE16-NEXT: s_wait_kmcnt 0x0
; GI-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
@@ -181,7 +181,7 @@ define amdgpu_kernel void @rcp_bf16_constant_4(ptr addrspace(1) %out) #1 {
; GI-FAKE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GI-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GI-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 nv
-; GI-FAKE16-NEXT: v_rcp_bf16_e32 v0, 4.0
+; GI-FAKE16-NEXT: v_rcp_bf16_e64 v0, 4.0 op_sel:[1,0]
; GI-FAKE16-NEXT: v_mov_b32_e32 v1, 0
; GI-FAKE16-NEXT: s_wait_kmcnt 0x0
; GI-FAKE16-NEXT: global_store_b16 v1, v0, s[0:1]
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.bf16.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.bf16.ll
index 574867bd54611..f630b20c7ee46 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.bf16.ll
@@ -71,7 +71,7 @@ define amdgpu_kernel void @rsq_bf16_constant_4(ptr addrspace(1) %out) #1 {
; SDAG-REAL16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; SDAG-REAL16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 nv
-; SDAG-REAL16-NEXT: v_rsq_bf16_e32 v0.l, 4.0
+; SDAG-REAL16-NEXT: v_rsq_bf16_e64 v0.l, 4.0 op_sel:[1,0]
; SDAG-REAL16-NEXT: v_mov_b32_e32 v1, 0
; SDAG-REAL16-NEXT: s_wait_kmcnt 0x0
; SDAG-REAL16-NEXT: global_store_b16 v1, v0, s[0:1]
@@ -84,7 +84,7 @@ define amdgpu_kernel void @rsq_bf16_constant_4(ptr addrspace(1) %out) #1 {
; SDAG-FAKE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; SDAG-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 nv
-; SDAG-FAKE16-NEXT: v_rsq_bf16_e32 v0, 4.0
+; SDAG-FAKE16-NEXT: v_rsq_bf16_e64 v0, 4.0 op_sel:[1,0]
; SDAG-FAKE16-NEXT: v_mov_b32_e32 v1, 0
; SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
; SDAG-FAKE16-NEXT: global_store_b16 v1, v0, s[0:1]
@@ -97,7 +97,7 @@ define amdgpu_kernel void @rsq_bf16_constant_4(ptr addrspace(1) %out) #1 {
; GISEL-REAL16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GISEL-REAL16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 nv
-; GISEL-REAL16-NEXT: v_rsq_bf16_e32 v0.l, 4.0
+; GISEL-REAL16-NEXT: v_rsq_bf16_e64 v0.l, 4.0 op_sel:[1,0]
; GISEL-REAL16-NEXT: v_mov_b32_e32 v1, 0
; GISEL-REAL16-NEXT: s_wait_kmcnt 0x0
; GISEL-REAL16-NEXT: global_store_b16 v1, v0, s[0:1]
@@ -110,7 +110,7 @@ define amdgpu_kernel void @rsq_bf16_constant_4(ptr addrspace(1) %out) #1 {
; GISEL-FAKE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GISEL-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 nv
-; GISEL-FAKE16-NEXT: v_rsq_bf16_e32 v0, 4.0
+; GISEL-FAKE16-NEXT: v_rsq_bf16_e64 v0, 4.0 op_sel:[1,0]
; GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, 0
; GISEL-FAKE16-NEXT: s_wait_kmcnt 0x0
; GISEL-FAKE16-NEXT: global_store_b16 v1, v0, s[0:1]
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sin.bf16.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sin.bf16.ll
index e329978679b5c..c82301ab3405b 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sin.bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sin.bf16.ll
@@ -47,7 +47,7 @@ define amdgpu_kernel void @sin_bf16_constant_4(ptr addrspace(1) %out) #1 {
; FAKE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
-; FAKE16-NEXT: v_sin_bf16_e32 v0, 4.0
+; FAKE16-NEXT: v_sin_bf16_e64 v0, 4.0 op_sel:[1,0]
; FAKE16-NEXT: v_mov_b32_e32 v1, 0
; FAKE16-NEXT: s_wait_kmcnt 0x0
; FAKE16-NEXT: global_store_b16 v1, v0, s[0:1]
@@ -60,7 +60,7 @@ define amdgpu_kernel void @sin_bf16_constant_4(ptr addrspace(1) %out) #1 {
; REAL16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; REAL16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
-; REAL16-NEXT: v_sin_bf16_e32 v0.l, 4.0
+; REAL16-NEXT: v_sin_bf16_e64 v0.l, 4.0 op_sel:[1,0]
; REAL16-NEXT: v_mov_b32_e32 v1, 0
; REAL16-NEXT: s_wait_kmcnt 0x0
; REAL16-NEXT: global_store_b16 v1, v0, s[0:1]
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sqrt.bf16.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sqrt.bf16.ll
index a345990b1299c..3c1f756270d1f 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sqrt.bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sqrt.bf16.ll
@@ -45,7 +45,7 @@ define amdgpu_kernel void @sqrt_bf16_constant_4(ptr addrspace(1) %out) #1 {
; FAKE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
-; FAKE16-NEXT: v_sqrt_bf16_e32 v0, 4.0
+; FAKE16-NEXT: v_sqrt_bf16_e64 v0, 4.0 op_sel:[1,0]
; FAKE16-NEXT: v_mov_b32_e32 v1, 0
; FAKE16-NEXT: s_wait_kmcnt 0x0
; FAKE16-NEXT: global_store_b16 v1, v0, s[0:1]
@@ -58,7 +58,7 @@ define amdgpu_kernel void @sqrt_bf16_constant_4(ptr addrspace(1) %out) #1 {
; REAL16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; REAL16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
-; REAL16-NEXT: v_sqrt_bf16_e32 v0.l, 4.0
+; REAL16-NEXT: v_sqrt_bf16_e64 v0.l, 4.0 op_sel:[1,0]
; REAL16-NEXT: v_mov_b32_e32 v1, 0
; REAL16-NEXT: s_wait_kmcnt 0x0
; REAL16-NEXT: global_store_b16 v1, v0, s[0:1]
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tanh.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tanh.ll
index 38c5f49c9c7ac..44a3fa77889b8 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tanh.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.tanh.ll
@@ -1099,7 +1099,7 @@ define amdgpu_ps bfloat @tanh_bf16_constant_4.0() {
; GFX1250-SDAG-REAL16-NEXT: v_nop
; GFX1250-SDAG-REAL16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-SDAG-REAL16-NEXT: v_tanh_bf16_e32 v0.l, 4.0
+; GFX1250-SDAG-REAL16-NEXT: v_tanh_bf16_e64 v0.l, 4.0 op_sel:[1,0]
; GFX1250-SDAG-REAL16-NEXT: ; return to shader part epilog
;
; GFX1250-SDAG-FAKE16-LABEL: tanh_bf16_constant_4.0:
@@ -1108,7 +1108,7 @@ define amdgpu_ps bfloat @tanh_bf16_constant_4.0() {
; GFX1250-SDAG-FAKE16-NEXT: v_nop
; GFX1250-SDAG-FAKE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-SDAG-FAKE16-NEXT: v_tanh_bf16_e32 v0, 4.0
+; GFX1250-SDAG-FAKE16-NEXT: v_tanh_bf16_e64 v0, 4.0 op_sel:[1,0]
; GFX1250-SDAG-FAKE16-NEXT: ; return to shader part epilog
;
; GFX1250-GISEL-REAL16-LABEL: tanh_bf16_constant_4.0:
@@ -1117,7 +1117,7 @@ define amdgpu_ps bfloat @tanh_bf16_constant_4.0() {
; GFX1250-GISEL-REAL16-NEXT: v_nop
; GFX1250-GISEL-REAL16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-GISEL-REAL16-NEXT: v_tanh_bf16_e32 v0.l, 4.0
+; GFX1250-GISEL-REAL16-NEXT: v_tanh_bf16_e64 v0.l, 4.0 op_sel:[1,0]
; GFX1250-GISEL-REAL16-NEXT: ; return to shader part epilog
;
; GFX1250-GISEL-FAKE16-LABEL: tanh_bf16_constant_4.0:
@@ -1126,27 +1126,27 @@ define amdgpu_ps bfloat @tanh_bf16_constant_4.0() {
; GFX1250-GISEL-FAKE16-NEXT: v_nop
; GFX1250-GISEL-FAKE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-GISEL-FAKE16-NEXT: v_tanh_bf16_e32 v0, 4.0
+; GFX1250-GISEL-FAKE16-NEXT: v_tanh_bf16_e64 v0, 4.0 op_sel:[1,0]
; GFX1250-GISEL-FAKE16-NEXT: ; return to shader part epilog
;
; GFX13-SDAG-REAL16-LABEL: tanh_bf16_constant_4.0:
; GFX13-SDAG-REAL16: ; %bb.0:
-; GFX13-SDAG-REAL16-NEXT: v_tanh_bf16_e32 v0.l, 4.0
+; GFX13-SDAG-REAL16-NEXT: v_tanh_bf16_e64 v0.l, 4.0 op_sel:[1,0]
; GFX13-SDAG-REAL16-NEXT: ; return to shader part epilog
;
; GFX13-SDAG-FAKE16-LABEL: tanh_bf16_constant_4.0:
; GFX13-SDAG-FAKE16: ; %bb.0:
-; GFX13-SDAG-FAKE16-NEXT: v_tanh_bf16_e32 v0, 4.0
+; GFX13-SDAG-FAKE16-NEXT: v_tanh_bf16_e64 v0, 4.0 op_sel:[1,0]
; GFX13-SDAG-FAKE16-NEXT: ; return to shader part epilog
;
; GFX13-GISEL-REAL16-LABEL: tanh_bf16_constant_4.0:
; GFX13-GISEL-REAL16: ; %bb.0:
-; GFX13-GISEL-REAL16-NEXT: v_tanh_bf16_e32 v0.l, 4.0
+; GFX13-GISEL-REAL16-NEXT: v_tanh_bf16_e64 v0.l, 4.0 op_sel:[1,0]
; GFX13-GISEL-REAL16-NEXT: ; return to shader part epilog
;
; GFX13-GISEL-FAKE16-LABEL: tanh_bf16_constant_4.0:
; GFX13-GISEL-FAKE16: ; %bb.0:
-; GFX13-GISEL-FAKE16-NEXT: v_tanh_bf16_e32 v0, 4.0
+; GFX13-GISEL-FAKE16-NEXT: v_tanh_bf16_e64 v0, 4.0 op_sel:[1,0]
; GFX13-GISEL-FAKE16-NEXT: ; return to shader part epilog
%tanh = call bfloat @llvm.amdgcn.tanh.bf16(bfloat 4.0)
ret bfloat %tanh
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